xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/regSTC.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regSTC.h
//  Description: TSP STC/PCR Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_STC_H_
#define _REG_STC_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

typedef struct _REG_STC_64
{
    REG32       STC_L;
    REG32       STC_H;
} REG_STC_64;

typedef struct _REG_STC_ENG_Ctrl // STC (Bank:0x300E)
{
    // reg_pcr64_0_riu @ tsp0 bank h'7 ~ h'A
    // reg_pcr64_1_riu @ tsp1 bank h'10 ~ h'13
    REG_STC_64  CFG_STC_00_17[6];                                               // reg_pcr64_2_riu ~ reg_pcr64_7_riu

    REG16       CFG_STC_18;                                                     // reserved

    // @NOTE: STC0_CONFIG & STC1_CONFIG is controlled by TSP HW ,
    //        no need riu fields...
    REG32       CFG_STC_19_1A;
        #define CFG_STC_19_1A_REG_SET_BASE_STC                                  0x00000001
        #define CFG_STC_19_1A_REG_STC_ENABLE                                    0x00000002
        #define CFG_STC_19_1A_REG_STC_LD                                        0x00000004

} REG_STC_ENG_Ctrl;

// PCR (Bank:0x300E)
// [Eng    , Offset]
// HW PCR0 , h'20 ~ h'27
// HW PCR1 , h'28 ~ h'2F
// HW PCR2 , h'30 ~ h'38
// HW PCR3 , h'38 ~ h'3f
// HW PCR4 , h'40 ~ h'48
// HW PCR5 , h'48 ~ h'4F
// HW PCR6 , h'50 ~ h'58
// HW PCR7 , h'58 ~ h'5F
typedef struct _REG_PCR_ENG_Ctrl
{
    REG16       CFG_PCR_00;
        #define CFG_PCR_00_REG_PCR_SRC_MASK                                     0x000F
        #define CFG_PCR_00_REG_PCR_SRC_SHIFT                                    0
        #define CFG_PCR_00_REG_TEI_SKIP_PKT_PCR                                 0x0010
        #define CFG_PCR_00_REG_PCR_RESET                                        0x0020
        #define CFG_PCR_00_REG_PCR_READ                                         0x0040
        #define CFG_PCR_00_REG_DSS_ENABLE                                       0x0080
        #define CFG_PCR_00_REG_SKIP_PVR_RUSH_DATA                               0x0100
        #define CFG_PCR_00_REG_PCR_CONFIG_MASK                                  0xFE00
        #define CFG_PCR_00_REG_PCR_CONFIG_SHIFT                                 9

    REG32       CFG_PCR_01_02;                                                  // reg_pidflt_pcr
        #define CFG_PCR_01_02_REG_PIDFLT_PCR_PID_MASK                           0x00001FFF
        #define CFG_PCR_01_02_REG_PIDFLT_PCR_PID_SHIFT                          0
        #define CFG_PCR_01_02_REG_PIDFLT_PCR_ENPCR                              0x00008000
        #define CFG_PCR_01_02_REG_PIDFLT_PCR_SOURCE_MASK                        0x003F0000
        #define CFG_PCR_01_02_REG_PIDFLT_PCR_SOURCE_SHIFT                       16

    REG32       CFG_PCR_03_04;                                                  // reg_pcr_valid ([31:0])

    REG16       CFG_PCR_05;                                                     // reg_pcr_valid ([32]) , reg_pcr_valid_ext
        #define CFG_PCR_05_REG_PCR_VALID_BIT32_MASK                             0x0001
        #define CFG_PCR_05_REG_PCR_VALID_EXT_MASK                               0x03FE
        #define CFG_PCR_05_REG_PCR_VALID_EXT_SHIFT                              1

    REG32       CFG_PCR_06_07;                                                  // reserved

} REG_PCR_ENG_Ctrl;

#endif // _REG_STC_H_