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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regSPS_SPD.h 98 // Description: TSP SPS / SPD Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_SPS_SPD_H_ 103 #define _REG_SPS_SPD_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_SPS_ENG_Ctrl // SPS (Bank:0x170D) 148 { 149 REG16 CFG_SPS_00_03[0x4 - 0x0]; // reg_ctr_iv_sps_init_pvr 150 151 REG16 CFG_SPS_04; // reg_ctr_iv_sps_max_pvr 152 #define CFG_SPS_04_CTR_IV_SPS_MAX_1K 0x0001 153 #define CFG_SPS_04_CTR_IV_SPS_MAX_2K 0x0002 154 #define CFG_SPS_04_CTR_IV_SPS_MAX_4K 0x0004 155 #define CFG_SPS_04_CTR_IV_SPS_MAX_8K 0x0008 156 #define CFG_SPS_04_CTR_IV_SPS_MAX_16K 0x0010 157 #define CFG_SPS_04_CTR_IV_SPS_MAX_32K 0x0020 158 #define CFG_SPS_04_CTR_IV_SPS_MAX_64K 0x0040 159 #define CFG_SPS_04_CTR_IV_SPS_MAX_128K 0x0080 160 161 REG16 CFG_SPS_05; 162 #define CFG_SPS_05_REG_CTR_MODE_SPS_PVR 0x0001 163 #define CFG_SPS_05_REG_UPDATE_CTR_MODE_COUNTER_IV_SPS_PVR 0x0002 164 #define CFG_SPS_05_REG_LOAD_INIT_COUNTER_SPS 0x0004 165 #define CFG_SPS_05_REG_SPS_ONEWAY_CTR_MODE 0x4000 166 #define CFG_SPS_05_REG_SPS_ONEWAY_IV_MAX 0x8000 167 168 REG16 CFG_SPS_06_09[0xA - 0x6]; // reg_ctr_iv_sps_update_vld_pvr 169 170 REG16 CFG_SPS_0A_0D[0xE - 0xA]; // reg_for_debug 171 172 REG32 CFG_SPS_0E_0F; // reserved 173 174 } REG_SPS_ENG_Ctrl; 175 176 typedef struct _REG_SPD_ENG_Ctrl // SPD (Bank:0x170C) 177 { 178 REG16 CFG_SPD_00_03[0x4 - 0x0]; // reg_ctr_iv_spd_init_filein 179 180 REG16 CFG_SPD_04; // reg_ctr_iv_spd_max_filein 181 #define CFG_SPD_04_CTR_IV_SPD_MAX_1K 0x0001 182 #define CFG_SPD_04_CTR_IV_SPD_MAX_2K 0x0002 183 #define CFG_SPD_04_CTR_IV_SPD_MAX_4K 0x0004 184 #define CFG_SPD_04_CTR_IV_SPD_MAX_8K 0x0008 185 #define CFG_SPD_04_CTR_IV_SPD_MAX_16K 0x0010 186 #define CFG_SPD_04_CTR_IV_SPD_MAX_32K 0x0020 187 #define CFG_SPD_04_CTR_IV_SPD_MAX_64K 0x0040 188 #define CFG_SPD_04_CTR_IV_SPD_MAX_128K 0x0080 189 190 REG16 CFG_SPD_05; 191 #define CFG_SPD_05_REG_CTR_MODE_SPD_FILEIN 0x0001 192 #define CFG_SPD_05_REG_UPDATE_CTR_MODE_COUNTER_IV_SPD_FILEIN 0x0002 193 #define CFG_SPD_05_REG_LOAD_INIT_COUNTER_SPD 0x0004 194 #define CFG_SPD_05_REG_SPD_ONEWAY_CTR_MODE 0x4000 195 #define CFG_SPD_05_REG_SPD_ONEWAY_IV_MAX 0x8000 196 197 REG16 CFG_SPD_06_09[0xA - 0x6]; // reg_ctr_iv_spd_update_vld_filein 198 199 REG16 CFG_SPD_0A_0F[0x10 - 0xA]; // reserved 200 201 } REG_SPD_ENG_Ctrl; 202 203 #endif // _REG_SPS_SPD_H_ 204