xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/regSPS_SPD.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regSPS_SPD.h
//  Description: TSP SPS / SPD Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_SPS_SPD_H_
#define _REG_SPS_SPD_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

typedef struct _REG_SPS_ENG_Ctrl // SPS (Bank:0x170D)
{
    REG16       CFG_SPS_00_03[0x4 - 0x0];                                       // reg_ctr_iv_sps_init_pvr

    REG16       CFG_SPS_04;                                                     // reg_ctr_iv_sps_max_pvr
        #define CFG_SPS_04_CTR_IV_SPS_MAX_1K                                    0x0001
        #define CFG_SPS_04_CTR_IV_SPS_MAX_2K                                    0x0002
        #define CFG_SPS_04_CTR_IV_SPS_MAX_4K                                    0x0004
        #define CFG_SPS_04_CTR_IV_SPS_MAX_8K                                    0x0008
        #define CFG_SPS_04_CTR_IV_SPS_MAX_16K                                   0x0010
        #define CFG_SPS_04_CTR_IV_SPS_MAX_32K                                   0x0020
        #define CFG_SPS_04_CTR_IV_SPS_MAX_64K                                   0x0040
        #define CFG_SPS_04_CTR_IV_SPS_MAX_128K                                  0x0080

    REG16       CFG_SPS_05;
        #define CFG_SPS_05_REG_CTR_MODE_SPS_PVR                                 0x0001
        #define CFG_SPS_05_REG_UPDATE_CTR_MODE_COUNTER_IV_SPS_PVR               0x0002
        #define CFG_SPS_05_REG_LOAD_INIT_COUNTER_SPS                            0x0004
        #define CFG_SPS_05_REG_SPS_ONEWAY_CTR_MODE                              0x4000
        #define CFG_SPS_05_REG_SPS_ONEWAY_IV_MAX                                0x8000

    REG16       CFG_SPS_06_09[0xA - 0x6];                                       // reg_ctr_iv_sps_update_vld_pvr

    REG16       CFG_SPS_0A_0D[0xE - 0xA];                                       // reg_for_debug

    REG32       CFG_SPS_0E_0F;                                                  // reserved

} REG_SPS_ENG_Ctrl;

typedef struct _REG_SPD_ENG_Ctrl // SPD (Bank:0x170C)
{
    REG16       CFG_SPD_00_03[0x4 - 0x0];                                       // reg_ctr_iv_spd_init_filein

    REG16       CFG_SPD_04;                                                     // reg_ctr_iv_spd_max_filein
        #define CFG_SPD_04_CTR_IV_SPD_MAX_1K                                    0x0001
        #define CFG_SPD_04_CTR_IV_SPD_MAX_2K                                    0x0002
        #define CFG_SPD_04_CTR_IV_SPD_MAX_4K                                    0x0004
        #define CFG_SPD_04_CTR_IV_SPD_MAX_8K                                    0x0008
        #define CFG_SPD_04_CTR_IV_SPD_MAX_16K                                   0x0010
        #define CFG_SPD_04_CTR_IV_SPD_MAX_32K                                   0x0020
        #define CFG_SPD_04_CTR_IV_SPD_MAX_64K                                   0x0040
        #define CFG_SPD_04_CTR_IV_SPD_MAX_128K                                  0x0080

    REG16       CFG_SPD_05;
        #define CFG_SPD_05_REG_CTR_MODE_SPD_FILEIN                              0x0001
        #define CFG_SPD_05_REG_UPDATE_CTR_MODE_COUNTER_IV_SPD_FILEIN            0x0002
        #define CFG_SPD_05_REG_LOAD_INIT_COUNTER_SPD                            0x0004
        #define CFG_SPD_05_REG_SPD_ONEWAY_CTR_MODE                              0x4000
        #define CFG_SPD_05_REG_SPD_ONEWAY_IV_MAX                                0x8000

    REG16       CFG_SPD_06_09[0xA - 0x6];                                       // reg_ctr_iv_spd_update_vld_filein

    REG16       CFG_SPD_0A_0F[0x10 - 0xA];                                      // reserved

} REG_SPD_ENG_Ctrl;

#endif // _REG_SPS_SPD_H_