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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regPVR.h 98 // Description: TSP PVR Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_PVR_H_ 103 #define _REG_PVR_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_PVR_ENG_Ctrl // PVR 1~8 (Bank:0x300A ~ 0x300D) , PVR 9~10 (Bank:0x162B) 148 { 149 REG16 CFG_PVR_00; 150 #define CFG_PVR_00_REG_PVR_PINGPONG_EN 0x0001 151 #define CFG_PVR_00_REG_PVR_STR2MI_EN 0x0002 152 #define CFG_PVR_00_REG_PVR_STR2MI_RST_WADR 0x0004 153 #define CFG_PVR_00_REG_PVR_STR2MI_PAUSE 0x0008 154 #define CFG_PVR_00_REG_PVR_PKT192_EN 0x0010 155 #define CFG_PVR_00_REG_PVR_DMA_FLUSH_EN 0x0020 156 #define CFG_PVR_00_REG_PVR_BURST_LEN_MASK 0x00C0 157 #define CFG_PVR_00_REG_PVR_BURST_LEN_SHIFT 6 158 #define CFG_PVR_00_REG_PVR_LPCR1_WLD 0x0100 159 #define CFG_PVR_00_REG_PVR_ALIGN_EN 0x0200 160 #define CFG_PVR_00_REG_PVR_STR2MI_DSWAP 0x0400 161 #define CFG_PVR_00_REG_PVR_STR2MI_BT_ORDER 0x0800 162 #define CFG_PVR_00_REG_REC_DATA_INV_EN 0x1000 163 #define CFG_PVR_00_REG_REC_ALL_OLD 0x4000 164 #define CFG_PVR_00_REG_PVR_LPCR1_RLD 0x8000 165 166 REG32 CFG_PVR_01_02; // reg_pvr_str2mi_head 167 168 REG32 CFG_PVR_03_04; // reg_pvr_str2mi_mid 169 170 REG32 CFG_PVR_05_06; // reg_pvr_str2mi_tail 171 172 REG32 CFG_PVR_07_08; // reg_pvr_str2mi_head2 173 174 REG32 CFG_PVR_09_0A; // reg_pvr_str2mi_mid2 175 176 REG32 CFG_PVR_0B_0C; // reg_pvr_str2mi_tail2 177 178 REG16 CFG_PVR_0D; 179 #define CFG_PVR_0D_REG_STR2MI_WP_LD 0x0001 180 #define CFG_PVR_0D_REG_STR2MI_90K_27M_SEL 0x0002 181 #define CFG_PVR_0D_REG_PVR_TIMESTAMP_SRC_SEL 0x0004 182 #define CFG_PVR_0D_REG_SPS_PVR_FIFO_SRC_SEL 0x0008 183 #define CFG_PVR_0D_REG_BYTE_ENABLE_TIE_1_SPS 0x0010 184 #define CFG_PVR_0D_REG_CLR_PVR_OVERFLOW 0x0020 185 #define CFG_PVR_0D_REG_FORCE_SYNC_EN 0x0040 186 #define CFG_PVR_0D_REG_RECORD_AT_SYNC_DIS 0x0080 187 #define CFG_PVR_0D_REG_MIU_HIGHPRI 0x0100 188 #define CFG_PVR_0D_REG_PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN 0x0200 189 #define CFG_PVR_0D_REG_FLUSH_PVR_DATA 0x0400 190 #define CFG_PVR_0D_REG_FLUSH_DATA_PVR_STATUS 0x0800 191 #define CFG_PVR_0D_REG_PVR_DMAW_PROTECT_EN 0x1000 192 #define CFG_PVR_0D_REG_ONEWAY_REC_CA_UPPER_PATH 0x2000 193 #define CFG_PVR_0D_REG_MIU_HIGHPRI_THOLD_MASK 0xC000 194 #define CFG_PVR_0D_REG_MIU_HIGHPRI_THOLD_SHIFT 14 195 196 REG32 CFG_PVR_0E_0F; // reg_pvr_pkt_meet_size 197 198 REG16 CFG_PVR_10; 199 #define CFG_PVR_10_REG_PVR_STR2MI_CNT_CLEAR 0x0001 200 #define CFG_PVR_10_REG_PVR_CNT_INT_MODE 0x0002 201 #define CFG_PVR_10_REG_PVR_SYNC_INT_MODE 0x0004 202 #define CFG_PVR_10_REG_REC_CA_UPPER_PATH 0x0008 203 #define CFG_PVR_10_REG_INPUT_SRC_MASK 0x00F0 204 #define CFG_PVR_10_REG_INPUT_SRC_SHIFT 4 205 #define CFG_PVR_10_REG_PVR_MEET_SIZE_CNT_R_MASK 0xFF00 206 #define CFG_PVR_10_REG_PVR_MEET_SIZE_CNT_R_SHIFT 8 207 208 REG32 CFG_PVR_11_12; // reserved 209 210 REG32 CFG_PVR_13_14; // reg_pvr_str2mi_wadr_r 211 212 REG32 CFG_PVR_15_16; // reg_pvr_lpcr1_buf 213 214 REG32 CFG_PVR_17_18; // reg_pvr_lpcr1 215 216 REG16 CFG_PVR_19; // reg_pvr_fifo_status 217 218 REG16 CFG_PVR_1A; 219 #define CFG_PVR_1A_REG_PVR_EVER_OVERFLOW 0x0001 220 #define CFG_PVR_1A_REG_CHANGE_PRIVILEGE_SYNC_BYTE_ENABLE_PVR 0x0002 221 #define CFG_PVR_1A_REG_CLR_PVR_NO_HIT_DMAW 0x0004 222 #define CFG_PVR_1A_REG_SYNC_BYTE_PRIVILEGE_PVR_MASK 0xFF00 223 #define CFG_PVR_1A_REG_SYNC_BYTE_PRIVILEGE_PVR_SHIFT 8 224 225 REG16 CFG_PVR_1B; 226 #define CFG_PVR_1B_REG_PKT_192_SPS_EN 0x0001 227 #define CFG_PVR_1B_REG_LOAD_SPS_KEY 0x0002 228 #define CFG_PVR_1B_REG_AES_DOUT_BT_ORDER 0x0004 229 #define CFG_PVR_1B_REG_AES_DIN_BT_ORDER 0x0008 230 #define CFG_PVR_1B_REG_ONEWAY_PKT192_SPS_EN 0x0010 231 232 REG32 CFG_PVR_1C_1D; // reg_pvr_dmaw_lbnd 233 234 REG32 CFG_PVR_1E_1F; // reg_pvr_dmaw_ubnd 235 236 REG16 CFG_PVR_20; 237 #define CFG_PVR_20_REG_START_READ_BYPASS_EN 0x0001 238 #define CFG_PVR_20_REG_CLR_PIDFLT_BYTE_CNT 0x0002 239 #define CFG_PVR_20_REG_PVR_ERR_RM_EN 0x0004 240 #define CFG_PVR_20_REG_MASK_SCR_PVR_EN 0x0008 241 #define CFG_PVR_20_REG_DIS_NULL_PKT 0x0010 242 #define CFG_PVR_20_REG_TEI_SKIP_PKT 0x0020 243 #define CFG_PVR_20_REG_RECORD_TS 0x0040 244 #define CFG_PVR_20_REG_RECORD_ALL 0x0080 245 #define CFG_PVR_20_REG_SKIP_PVR_RUSH_DATA 0x0100 246 #define CFG_PVR_20_REG_ALT_TS_SIZE 0x0200 247 #define CFG_PVR_20_REG_PVR_BLOCK_DISABLE 0x0400 248 #define CFG_PVR_20_REG_PVR_PES_DIRECTV_130_MODE 0x0800 249 #define CFG_PVR_20_REG_PVR_PES_DIRECTV_134_MODE 0x1000 250 #define CFG_PVR_20_REG_SUPPORT_DIRECTV_ALIGN_MODE 0x2000 //K7U not support 251 #define CFG_PVR_20_REG_RESET_FILTER 0x4000 252 #define CFG_PVR_20_REG_ONEWAY_PVR 0x8000 253 254 REG16 CFG_PVR_21; 255 #define CFG_PVR_21_REG_PKT_SIZE_MASK 0x00FF 256 #define CFG_PVR_21_REG_PKT_SIZE_SHIFT 0 257 258 REG32 CFG_PVR_22_23; // reg_pause_time 259 260 REG32 CFG_PVR_24_25; // reg_pvr_gap 261 262 REG16 CFG_PVR_26; 263 #define CFG_PVR_26_REG_RESET_FIRST_SYNC_PVR 0x0001 264 #define CFG_PVR_26_REG_MINUS_BASE_TIME_PVR 0x0002 265 #define CFG_PVR_26_REG_BYPASS_TIMESTAMP_SEL 0x0004 266 #define CFG_PVR_26_REG_PVR_GAP_LD 0x0008 267 #define CFG_PVR_26_REG_RESET_TIMESTAMP_SEL 0x0010 268 269 REG16 CFG_PVR_27; // reg_config_by_tee_pvr 270 #define CFG_PVR_27_REG_CHK_PRIVILEGE_FLAG 0x0001 271 #define CFG_PVR_27_REG_CHK_TEE_FILEIN 0x0002 272 273 REG16 CFG_PVR_28; 274 #define CFG_PVR_28_REG_PVR_MCM_DISABLE 0x0001 275 #define CFG_PVR_28_REG_RESET_TOP 0x0002 276 277 REG16 CFG_PVR_29; 278 #define CFG_PVR_29_REG_PVR_INT_EN_MASK 0x00FF 279 #define CFG_PVR_29_REG_PVR_INT_EN_PVR_MEET_TAIL 0x0001 280 #define CFG_PVR_29_REG_PVR_INT_EN_PVR_MEET_MID 0x0002 281 #define CFG_PVR_29_REG_PVR_INT_STATUS_MASK 0xFF00 282 #define CFG_PVR_29_INT_STATUS_PVR_MEET_TAIL 0x0100 283 #define CFG_PVR_29_INT_STATUS_PVR_MEET_MID 0x0200 284 285 REG16 CFG_PVR_2A_3E[0x3F - 0x2A]; // reserved 286 287 REG16 CFG_PVR_3F; 288 #define CFG_PVR_3F_REG_CLK_GATING_TSP_PVR 0x0001 289 #define CFG_PVR_3F_REG_CLK_GATING_MIU_PVR 0x0002 290 291 } REG_PVR_ENG_Ctrl; 292 293 #endif // _REG_PVR_H_ 294