xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/regPVR.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regPVR.h
//  Description: TSP PVR Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_PVR_H_
#define _REG_PVR_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

typedef struct _REG_PVR_ENG_Ctrl // PVR 1~8 (Bank:0x300A ~ 0x300D) , PVR 9~10 (Bank:0x162B)
{
    REG16       CFG_PVR_00;
        #define CFG_PVR_00_REG_PVR_PINGPONG_EN                                  0x0001
        #define CFG_PVR_00_REG_PVR_STR2MI_EN                                    0x0002
        #define CFG_PVR_00_REG_PVR_STR2MI_RST_WADR                              0x0004
        #define CFG_PVR_00_REG_PVR_STR2MI_PAUSE                                 0x0008
        #define CFG_PVR_00_REG_PVR_PKT192_EN                                    0x0010
        #define CFG_PVR_00_REG_PVR_DMA_FLUSH_EN                                 0x0020
        #define CFG_PVR_00_REG_PVR_BURST_LEN_MASK                               0x00C0
        #define CFG_PVR_00_REG_PVR_BURST_LEN_SHIFT                              6
        #define CFG_PVR_00_REG_PVR_LPCR1_WLD                                    0x0100
        #define CFG_PVR_00_REG_PVR_ALIGN_EN                                     0x0200
        #define CFG_PVR_00_REG_PVR_STR2MI_DSWAP                                 0x0400
        #define CFG_PVR_00_REG_PVR_STR2MI_BT_ORDER                              0x0800
        #define CFG_PVR_00_REG_REC_DATA_INV_EN                                  0x1000
        #define CFG_PVR_00_REG_REC_ALL_OLD                                      0x4000
        #define CFG_PVR_00_REG_PVR_LPCR1_RLD                                    0x8000

    REG32       CFG_PVR_01_02;                                                  // reg_pvr_str2mi_head

    REG32       CFG_PVR_03_04;                                                  // reg_pvr_str2mi_mid

    REG32       CFG_PVR_05_06;                                                  // reg_pvr_str2mi_tail

    REG32       CFG_PVR_07_08;                                                  // reg_pvr_str2mi_head2

    REG32       CFG_PVR_09_0A;                                                  // reg_pvr_str2mi_mid2

    REG32       CFG_PVR_0B_0C;                                                  // reg_pvr_str2mi_tail2

    REG16       CFG_PVR_0D;
        #define CFG_PVR_0D_REG_STR2MI_WP_LD                                     0x0001
        #define CFG_PVR_0D_REG_STR2MI_90K_27M_SEL                               0x0002
        #define CFG_PVR_0D_REG_PVR_TIMESTAMP_SRC_SEL                            0x0004
        #define CFG_PVR_0D_REG_SPS_PVR_FIFO_SRC_SEL                             0x0008
        #define CFG_PVR_0D_REG_BYTE_ENABLE_TIE_1_SPS                            0x0010
        #define CFG_PVR_0D_REG_CLR_PVR_OVERFLOW                                 0x0020
        #define CFG_PVR_0D_REG_FORCE_SYNC_EN                                    0x0040
        #define CFG_PVR_0D_REG_RECORD_AT_SYNC_DIS                               0x0080
        #define CFG_PVR_0D_REG_MIU_HIGHPRI                                      0x0100
        #define CFG_PVR_0D_REG_PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN             0x0200
        #define CFG_PVR_0D_REG_FLUSH_PVR_DATA                                   0x0400
        #define CFG_PVR_0D_REG_FLUSH_DATA_PVR_STATUS                            0x0800
        #define CFG_PVR_0D_REG_PVR_DMAW_PROTECT_EN                              0x1000
        #define CFG_PVR_0D_REG_ONEWAY_REC_CA_UPPER_PATH                         0x2000
        #define CFG_PVR_0D_REG_MIU_HIGHPRI_THOLD_MASK                           0xC000
        #define CFG_PVR_0D_REG_MIU_HIGHPRI_THOLD_SHIFT                          14

    REG32       CFG_PVR_0E_0F;                                                  // reg_pvr_pkt_meet_size

    REG16       CFG_PVR_10;
        #define CFG_PVR_10_REG_PVR_STR2MI_CNT_CLEAR                             0x0001
        #define CFG_PVR_10_REG_PVR_CNT_INT_MODE                                 0x0002
        #define CFG_PVR_10_REG_PVR_SYNC_INT_MODE                                0x0004
        #define CFG_PVR_10_REG_REC_CA_UPPER_PATH                                0x0008
        #define CFG_PVR_10_REG_INPUT_SRC_MASK                                   0x00F0
        #define CFG_PVR_10_REG_INPUT_SRC_SHIFT                                  4
        #define CFG_PVR_10_REG_PVR_MEET_SIZE_CNT_R_MASK                         0xFF00
        #define CFG_PVR_10_REG_PVR_MEET_SIZE_CNT_R_SHIFT                        8

    REG32       CFG_PVR_11_12;                                                  // reserved

    REG32       CFG_PVR_13_14;                                                  // reg_pvr_str2mi_wadr_r

    REG32       CFG_PVR_15_16;                                                  // reg_pvr_lpcr1_buf

    REG32       CFG_PVR_17_18;                                                  // reg_pvr_lpcr1

    REG16       CFG_PVR_19;                                                     // reg_pvr_fifo_status

    REG16       CFG_PVR_1A;
        #define CFG_PVR_1A_REG_PVR_EVER_OVERFLOW                                0x0001
        #define CFG_PVR_1A_REG_CHANGE_PRIVILEGE_SYNC_BYTE_ENABLE_PVR            0x0002
        #define CFG_PVR_1A_REG_CLR_PVR_NO_HIT_DMAW                              0x0004
        #define CFG_PVR_1A_REG_SYNC_BYTE_PRIVILEGE_PVR_MASK                     0xFF00
        #define CFG_PVR_1A_REG_SYNC_BYTE_PRIVILEGE_PVR_SHIFT                    8

    REG16       CFG_PVR_1B;
        #define CFG_PVR_1B_REG_PKT_192_SPS_EN                                   0x0001
        #define CFG_PVR_1B_REG_LOAD_SPS_KEY                                     0x0002
        #define CFG_PVR_1B_REG_AES_DOUT_BT_ORDER                                0x0004
        #define CFG_PVR_1B_REG_AES_DIN_BT_ORDER                                 0x0008
        #define CFG_PVR_1B_REG_ONEWAY_PKT192_SPS_EN                             0x0010

    REG32       CFG_PVR_1C_1D;                                                  // reg_pvr_dmaw_lbnd

    REG32       CFG_PVR_1E_1F;                                                  // reg_pvr_dmaw_ubnd

    REG16       CFG_PVR_20;
        #define CFG_PVR_20_REG_START_READ_BYPASS_EN                             0x0001
        #define CFG_PVR_20_REG_CLR_PIDFLT_BYTE_CNT                              0x0002
        #define CFG_PVR_20_REG_PVR_ERR_RM_EN                                    0x0004
        #define CFG_PVR_20_REG_MASK_SCR_PVR_EN                                  0x0008
        #define CFG_PVR_20_REG_DIS_NULL_PKT                                     0x0010
        #define CFG_PVR_20_REG_TEI_SKIP_PKT                                     0x0020
        #define CFG_PVR_20_REG_RECORD_TS                                        0x0040
        #define CFG_PVR_20_REG_RECORD_ALL                                       0x0080
        #define CFG_PVR_20_REG_SKIP_PVR_RUSH_DATA                               0x0100
        #define CFG_PVR_20_REG_ALT_TS_SIZE                                      0x0200
        #define CFG_PVR_20_REG_PVR_BLOCK_DISABLE                                0x0400
        #define CFG_PVR_20_REG_PVR_PES_DIRECTV_130_MODE                         0x0800
        #define CFG_PVR_20_REG_PVR_PES_DIRECTV_134_MODE                         0x1000
        #define CFG_PVR_20_REG_SUPPORT_DIRECTV_ALIGN_MODE                       0x2000  //K7U not support
        #define CFG_PVR_20_REG_RESET_FILTER                                     0x4000
        #define CFG_PVR_20_REG_ONEWAY_PVR                                       0x8000

    REG16       CFG_PVR_21;
        #define CFG_PVR_21_REG_PKT_SIZE_MASK                                    0x00FF
        #define CFG_PVR_21_REG_PKT_SIZE_SHIFT                                   0

    REG32       CFG_PVR_22_23;                                                  // reg_pause_time

    REG32       CFG_PVR_24_25;                                                  // reg_pvr_gap

    REG16       CFG_PVR_26;
        #define CFG_PVR_26_REG_RESET_FIRST_SYNC_PVR                             0x0001
        #define CFG_PVR_26_REG_MINUS_BASE_TIME_PVR                              0x0002
        #define CFG_PVR_26_REG_BYPASS_TIMESTAMP_SEL                             0x0004
        #define CFG_PVR_26_REG_PVR_GAP_LD                                       0x0008
        #define CFG_PVR_26_REG_RESET_TIMESTAMP_SEL                              0x0010

    REG16       CFG_PVR_27;                                                     // reg_config_by_tee_pvr
        #define CFG_PVR_27_REG_CHK_PRIVILEGE_FLAG                               0x0001
        #define CFG_PVR_27_REG_CHK_TEE_FILEIN                                   0x0002

    REG16       CFG_PVR_28;
        #define CFG_PVR_28_REG_PVR_MCM_DISABLE                                  0x0001
        #define CFG_PVR_28_REG_RESET_TOP                                        0x0002

    REG16       CFG_PVR_29;
        #define CFG_PVR_29_REG_PVR_INT_EN_MASK                                  0x00FF
        #define CFG_PVR_29_REG_PVR_INT_EN_PVR_MEET_TAIL                         0x0001
        #define CFG_PVR_29_REG_PVR_INT_EN_PVR_MEET_MID                          0x0002
        #define CFG_PVR_29_REG_PVR_INT_STATUS_MASK                              0xFF00
        #define CFG_PVR_29_INT_STATUS_PVR_MEET_TAIL                             0x0100
        #define CFG_PVR_29_INT_STATUS_PVR_MEET_MID                              0x0200

    REG16       CFG_PVR_2A_3E[0x3F - 0x2A];                                     // reserved

    REG16       CFG_PVR_3F;
        #define CFG_PVR_3F_REG_CLK_GATING_TSP_PVR                               0x0001
        #define CFG_PVR_3F_REG_CLK_GATING_MIU_PVR                               0x0002

} REG_PVR_ENG_Ctrl;

#endif // _REG_PVR_H_