xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/regFILE.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regFILE.h
//  Description: TSP File-in Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_FILE_H_
#define _REG_FILE_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

typedef struct _REG_FILE_ENG_Ctrl // FILE (Bank:0x1611 , 0x1627)
{
    REG16       CFG_FILE_00;
        #define CFG_FILE_00_REG_TSP_FILE_IN                                     0x0001
        #define CFG_FILE_00_REG_MEM_TS_DATA_ENDIAN                              0x0002
        #define CFG_FILE_00_REG_TSP_FILE_SEGMENT                                0x0004
        #define CFG_FILE_00_REG_FILEIN_RADDR_READ                               0x0008
        #define CFG_FILE_00_REG_MEM_TS_W_ORDER                                  0x0010
        #define CFG_FILE_00_REG_DIS_MIU_RQ                                      0x0020
        #define CFG_FILE_00_REG_RST_TS_FIN                                      0x0040
        #define CFG_FILE_00_REG_RST_FILEIN_TSIF                                 0x0080
        #define CFG_FILE_00_REG_RST_CMDQ_FILEIN                                 0x0100
        #define CFG_FILE_00_REG_WB_RST_FILEIN                                   0x0200
        #define CFG_FILE_00_REG_RST_WB_DMA_FILEIN                               0x0400
        #define CFG_FILE_00_REG_FILE2MI_PRI                                     0x0800
        #define CFG_FILE_00_REG_RST_READ_DMA                                    0x1000
        #define CFG_FILE_00_REG_LPCR2_LOAD                                      0x2000
        #define CFG_FILE_00_REG_WB_FSM_RESET                                    0x4000

    REG16       CFG_FILE_01;
        #define CFG_FILE_01_REG_TIMER_EN                                        0x0002
        #define CFG_FILE_01_REG_PKT192_EN                                       0x0004
        #define CFG_FILE_01_REG_PKT192_BLK_DISABLE                              0x0008
        #define CFG_FILE_01_REG_LPCR2_WLD                                       0x0010
        #define CFG_FILE_01_REG_TS_DATA_PORT_SEL                                0x0020
        #define CFG_FILE_01_REG_LPCR_FREG_27M_90K                               0x0040
        #define CFG_FILE_01_REG_TSP_FILEIN_ABORT                                0x0080
        #define CFG_FILE_01_REG_DISABLE_FILEIN_ADDR_LEN_BY_TEE                  0x0100
        #define CFG_FILE_01_REG_PS_MODE_BLOCK                                   0x0200
        #define CFG_FILE_01_REG_TSIF_PAUSE                                      0x0400
        #define CFG_FILE_01_REG_DISABLE_STREAM_ID_CHK_FOR_NAGRA_DONGLE          0x0800
        #define CFG_FILE_01_REG_FILTER_STREAM_ID_0_TO_1F_FOR_NAGRA_DONGLE       0x1000
        #define CFG_FILE_01_REG_INCR_PERFORMANCE_ENABLE                         0x2000

    REG32       CFG_FILE_02_03;                                                 // reg_tsp_filein_raddr_tsif

    REG32       CFG_FILE_04_05;                                                 // reg_tsp_filein_rnum_tsif

    REG16       CFG_FILE_06;                                                    // reg_tsp_filein_ctrl_tsif
        #define CFG_FILE_06_REG_FILEIN_RSTART                                   0x0001
        #define CFG_FILE_06_REG_FILEIN_DONE                                     0x0002
        #define CFG_FILE_06_REG_FILEIN_INIT_TRUST                               0x0004
        #define CFG_FILE_06_REG_FILEIN_ABORT                                    0x0010

    REG16       CFG_FILE_07;
        #define CFG_FILE_07_CMD_WR_CNT_TSIF1_MASK                               0x001F
        #define CFG_FILE_07_CMD_WR_CNT_TSIF1_SHIFT                              0
        #define CFG_FILE_07_CMD_FIFO_FULL_TSIF1                                 0x0040
        #define CFG_FILE_07_CMD_FIFO_EMPTY_TSIF1                                0x0080
        #define CFG_FILE_07_CMD_WR_LEVEL_TSIF1_MASK                             0x0300
        #define CFG_FILE_07_CMD_WR_LEVEL_TSIF1_SHIFT                            8

    REG16       CFG_FILE_08;
        #define CFG_FILE_08_REG_CHK_PKT_SIZE_MASK                               0x00FF
        #define CFG_FILE_08_REG_CHK_PKT_SIZE_SHIFT                              0
        #define CFG_FILE_08_REG_MATCH_CNT_THRESHOLD_MASK                        0x0F00
        #define CFG_FILE_08_REG_MATCH_CNT_THRESHOLD_SHIFT                       8
        #define CFG_FILE_08_REG_MATCH_CNT_INIT_VALUE_MASK                       0xF000
        #define CFG_FILE_08_REG_MATCH_CNT_INIT_VALUE_SHIFT                      12

    REG16       CFG_FILE_09;                                                    // reg_tsp_file_timer

    REG16       CFG_FILE_0A;
        #define CFG_FILE_0A_REG_FIX_192_TIMER_0_EN                              0x0001
        #define CFG_FILE_0A_REG_INIT_TIMESTAMP                                  0x0002
        #define CFG_FILE_0A_REG_FIXED_TIMESTAMP_RING_BACK_EN                    0x0004
        #define CFG_FILE_0A_REG_FIX_LPCR_RING_BACK_EN                           0x0008
        #define CFG_FILE_0A_REG_MATCH_CNT_FILEIN_EN                             0x0010
        #define CFG_FILE_0A_REG_INIT_STAMP_RSTART_EN                            0x0020
        #define CFG_FILE_0A_REG_CHK_PRIVILEGE_SYNC_BYTE_EN                      0x0040
        #define CFG_FILE_0A_REG_INIT_TRUST_SYNC_CNT_VALUE_MASK                  0xFF00
        #define CFG_FILE_0A_REG_INIT_TRUST_SYNC_CNT_VALUE_SHIFT                 8

    REG32       CFG_FILE_0B_0C;                                                 // reg_init_timestamp_vld

    REG16       CFG_FILE_0D;
        #define CFG_FILE_0D_REG_SYNC_BYTE_PRIVILEGE_MASK                        0x00FF
        #define CFG_FILE_0D_REG_SYNC_BYTE_PRIVILEGE_SHIFT                       0
        #define CFG_FILE_0D_REG_REPLACE_PRIVILEGE_SYNC_BYTE_MASK                0xFF00
        #define CFG_FILE_0D_REG_REPLACE_PRIVILEGE_SYNC_BYTE_SHIFT               8

    REG16       CFG_FILE_0E;
        #define CFG_FILE_0E_REG_RVU_PSI_EN                                      0x0001
        #define CFG_FILE_0E_REG_RVU_TEI_EN                                      0x0002
        #define CFG_FILE_0E_REG_RVU_ERR_CLR                                     0x0004
        #define CFG_FILE_0E_REG_RVU_EN                                          0x0008
        #define CFG_FILE_0E_REG_RVU_TIMESTAMP_EN                                0x0010
        #define CFG_FILE_0E_REG_RVU_ERR_EVER                                    0x0020
        #define CFG_FILE_0E_REG_HD_0000_TO_SECTION                              0x0040
        #define CFG_FILE_0E_REG_HD_1100_TO_SECTION                              0x0080
        #define CFG_FILE_0E_REG_HD_10X0_11X0_TO_SECTION                         0x0100
        #define CFG_FILE_0E_REG_PAYLOAD_128_MODE                                0x0200
        #define CFG_FILE_0E_REG_SUPPORT_NB                                      0x0400
        #define CFG_FILE_0E_REG_FIND_RVU_SYNC_PID                               0x0800

    REG16       CFG_FILE_0F;
        #define CFG_FILE_0F_REG_TSIF_SPD_RST                                    0x0001
        #define CFG_FILE_0F_REG_SPD_TSIF_BYPASS                                 0x0002
        #define CFG_FILE_0F_REG_LOAD_SPD_KEY                                    0x0004

    REG32       CFG_FILE_10_11;                                                 // reg_lpcr_buf

    REG32       CFG_FILE_12_13;                                                 // reg_lpcr_tsif

    REG32       CFG_FILE_14_15;                                                 // reg_timestamp

    REG32       CFG_FILE_16_17;                                                 // reg_tsp2mi_raddr_tsif
        #define CFG_FILE_16_17_REG_TSP2MI_RADDR_TSIF_MASK                       0x0FFFFFFF

    REG16       CFG_FILE_18;
        #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F0_MASK                  0x00FF
        #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F0_SHIFT                 0
        #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F1_MASK                  0xFF00
        #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F1_SHIFT                 8

    REG16       CFG_FILE_19_1F[0x20 - 0x19];                                    // reserved

} REG_FILE_ENG_Ctrl;

#endif // _REG_FILE_H_