1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halTSP.h 20 // @brief TSP HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_TSP_H__ 24 #define __HAL_TSP_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM TSP_PVRENG_NUM 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 //VQ define 36 #define VQ_NUM TSP_TSIF_NUM 37 #define VQ_PACKET_UNIT_LEN 208 38 39 #define TSP_TSIF0 0x00 40 #define TSP_TSIF1 0x01 41 #define TSP_TSIF2 0x02 42 #define TSP_TSIF3 0x03 43 #define TSP_TSIF4 0x04 44 #define TSP_TSIF5 0x05 45 #define TSP_TSIF6 0x06 46 47 //FQ define 48 #define TSP_FQ_NUM 11 // exclude FQ #7 49 #define TSP_FQ_MUX_START_ID 8 50 51 52 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 53 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 54 //######################################################################### 55 //#### Software Capability Macro Start 56 //######################################################################### 57 58 #define TSP_CA_RESERVED_FLT_NUM 1 59 #define TSP_RECFLT_NUM 1 60 #define TSP_PIDFLT_REC_NUM (TSP_PIDFLT_NUM - TSP_PCRFLT_NUM) // 0~767 (0 for CA) 61 // 777 for Err 62 // 776 for REC 63 // 768 ~ 775 for PCR0 ~ PCR7 64 65 #if HW_PCRFLT_ENABLE 66 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 67 #else 68 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 69 #endif 70 71 //######################################################################### 72 //#### Software Capability Macro End 73 //######################################################################### 74 75 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 76 #define TSP_CAFLT_START_ID 0 77 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) // 1 78 79 // section FLT ID 80 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID // 1 81 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID // 1 82 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 83 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 84 85 // PID 86 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID // 1 87 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 88 89 // PCR 90 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID // 192 91 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 92 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) // 196 93 94 // REC 95 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID // 196 96 97 //-------------------------------------------------------------------------------------------------- 98 // Driver Compiler Option 99 //-------------------------------------------------------------------------------------------------- 100 101 102 //-------------------------------------------------------------------------------------------------- 103 // PVR Hardware Abstraction Layer 104 //-------------------------------------------------------------------------------------------------- 105 106 // HW characteristic 107 108 typedef enum _PVRENG_SEQ 109 { 110 E_TSP_PVR_PVRENG_START = 0, 111 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 112 E_TSP_PVR_PVRENG_1, 113 E_TSP_PVR_PVRENG_2, 114 E_TSP_PVR_PVRENG_3, 115 E_TSP_PVR_PVRENG_4, 116 E_TSP_PVR_PVRENG_5, 117 E_TSP_PVR_PVRENG_6, 118 E_TSP_PVR_PVRENG_7, 119 E_TSP_PVR_PVRENG_8, 120 E_TSP_PVR_PVRENG_9, 121 E_TSP_PVR_PVRENG_END, 122 123 E_TSP_PVR_ENG_INVALID, 124 } PVRENG_SEQ; 125 126 typedef enum _FILEENG_SEQ 127 { 128 E_FILEENG_TSIF0 = TSP_TSIF0, 129 E_FILEENG_TSIF1 = TSP_TSIF1, 130 E_FILEENG_TSIF2 = TSP_TSIF2, 131 E_FILEENG_TSIF3 = TSP_TSIF3, 132 E_FILEENG_TSIF4 = TSP_TSIF4, 133 E_FILEENG_TSIF5 = TSP_TSIF5, 134 E_FILEENG_TSIF6 = TSP_TSIF6, 135 E_FILEENG_INVALID, 136 137 } FILEENG_SEQ; 138 139 // Destination type 140 typedef enum _TSP_DST_SEQ 141 { 142 E_TSP_DST_FIFO_VIDEO, 143 E_TSP_DST_FIFO_VIDEO3D, 144 E_TSP_DST_FIFO_VIDEO3, 145 E_TSP_DST_FIFO_VIDEO4, 146 E_TSP_DST_FIFO_VIDEO5, 147 E_TSP_DST_FIFO_VIDEO6, 148 E_TSP_DST_FIFO_VIDEO7, 149 E_TSP_DST_FIFO_VIDEO8, 150 151 E_TSP_DST_FIFO_AUDIO, 152 E_TSP_DST_FIFO_AUDIO2, 153 E_TSP_DST_FIFO_AUDIO3, 154 E_TSP_DST_FIFO_AUDIO4, 155 E_TSP_DST_FIFO_AUDIO5, 156 E_TSP_DST_FIFO_AUDIO6, 157 158 E_TSP_DST_INVALID, 159 } TSP_DST_SEQ; 160 161 typedef enum _TSP_SRC_SEQ 162 { 163 E_TSP_SRC_PKTDMX0 = 1, 164 E_TSP_SRC_PKTDMX1, 165 E_TSP_SRC_PKTDMX2, 166 E_TSP_SRC_PKTDMX3, 167 E_TSP_SRC_PKTDMX4, 168 E_TSP_SRC_PKTDMX5, 169 E_TSP_SRC_PKTDMX6, 170 E_TSP_SRC_MMFI0, 171 E_TSP_SRC_MMFI1, 172 173 E_TSP_SRC_INVALID, 174 } TSP_SRC_SEQ; 175 176 typedef enum _TSIF_CFG 177 { 178 // @NOTE should be Exclusive usage 179 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 180 E_TSP_TSIF_CFG_EN = 0x0001, 181 E_TSP_TSIF_CFG_PARA = 0x0002, 182 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 183 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 184 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 185 E_TSP_TSIF_CFG_3WIRE = 0x0010 186 } TSP_TSIF_CFG; 187 188 // for stream input source 189 typedef enum _HAL_TS_PAD 190 { 191 E_TSP_TS_PAD_EXT0, 192 E_TSP_TS_PAD_EXT1, 193 E_TSP_TS_PAD_EXT2, 194 E_TSP_TS_PAD_EXT3, 195 E_TSP_TS_PAD_EXT4, 196 E_TSP_TS_PAD_EXT5, 197 E_TSP_TS_PAD_EXT6, 198 E_TSP_TS_PAD_EXT7, 199 E_TSP_TS_PAD_INTER0, 200 E_TSP_TS_PAD_INTER1, 201 E_TSP_TS_PAD_TSOUT0, 202 E_TSP_TS_PAD_TSOUT1, 203 E_TSP_TS_PAD_TSIOOUT0, 204 E_TSP_TS_PAD_INVALID, 205 } TSP_TS_PAD; 206 207 // for ts pad mode 208 typedef enum _HAL_TS_PAD_MUX_MODE 209 { 210 E_TSP_TS_PAD_MUX_PARALLEL, // in 211 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 212 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 213 E_TSP_TS_PAD_MUX_TSO, // out 214 E_TSP_TS_PAD_MUX_S2P, // out 215 E_TSP_TS_PAD_MUX_S2P1, // out 216 E_TSP_TS_PAD_MUX_DEMOD, // out 217 218 E_TSP_TS_PAD_MUX_INVALID 219 } TSP_TS_PAD_MUX_MODE; 220 221 // for pkt converter mode 222 typedef enum _HAL_TS_PKT_CONVERTER_MODE 223 { 224 E_TSP_PKT_CONVERTER_188Mode = 0, 225 E_TSP_PKT_CONVERTER_CIMode = 1, 226 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 227 E_TSP_PKT_CONVERTER_ATSMode = 3, 228 E_TSP_PKT_CONVERTER_MxLMode = 4, 229 E_TSP_PKT_CONVERTER_NagraDongleMode = 5, 230 E_TSP_PKT_CONVERTER_Invalid, 231 } TSP_TS_PKT_CONVERTER_MODE; 232 233 typedef enum _HAL_TS_MXL_PKT_MODE 234 { 235 E_TSP_TS_MXL_PKT_192 = 4, 236 E_TSP_TS_MXL_PKT_196 = 8, 237 E_TSP_TS_MXL_PKT_200 = 12, 238 E_TSP_TS_MXL_PKT_INVALID, 239 } TSP_TS_MXL_PKT_MODE; 240 241 typedef enum _HAL_TSP_CLK_TYPE 242 { 243 E_TSP_HAL_TSP_CLK, 244 E_TSP_HAL_STC_CLK, 245 E_TSP_HAL_INVALID 246 } EN_TSP_HAL_CLK_TYPE; 247 248 typedef struct _HAL_TSP_CLK_STATUS 249 { 250 MS_BOOL bEnable; 251 MS_BOOL bInvert; 252 MS_U8 u8ClkSrc; 253 } ST_TSP_HAL_CLK_STATUS; 254 255 typedef enum _PCR_SRC 256 { 257 /* register setting for kaiser pcr 258 0: tsif0 259 1: tsif1 260 2: tsif2 261 3: tsif3 262 4: tsif4 263 5: tsif5 264 6: tsif6 265 a: MM file in 1 266 b: MM file in 2 267 c: FIQ in 1 268 d: FIQ in 2 269 */ 270 E_TSP_PCR_SRC_TSIF0 = 0, 271 E_TSP_PCR_SRC_TSIF1, 272 E_TSP_PCR_SRC_TSIF2, 273 E_TSP_PCR_SRC_TSIF3, 274 E_TSP_PCR_SRC_TSIF4, 275 E_TSP_PCR_SRC_TSIF5, 276 E_TSP_PCR_SRC_TSIF6, 277 278 E_TSP_PCR_SRC_MMFI0 = 0xA, 279 E_TSP_PCR_SRC_MMFI1, 280 E_TSP_PCR_SRC_FIQ0, 281 E_TSP_PCR_SRC_FIQ1, 282 E_TSP_PCR_SRC_INVALID, 283 } TSP_PCR_SRC; 284 285 typedef enum _HAL_TSP_TSIF // for HW TSIF 286 { 287 E_TSP_HAL_TSIF_0 , 288 E_TSP_HAL_TSIF_1 , 289 E_TSP_HAL_TSIF_2 , 290 E_TSP_HAL_TSIF_3 , 291 E_TSP_HAL_TSIF_4 , 292 E_TSP_HAL_TSIF_5 , 293 E_TSP_HAL_TSIF_6 , 294 295 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 296 E_TSP_HAL_TSIF_PVR0 , 297 E_TSP_HAL_TSIF_PVR1 , 298 E_TSP_HAL_TSIF_PVR2 , 299 E_TSP_HAL_TSIF_PVR3 , 300 E_TSP_HAL_TSIF_INVALID , 301 } TSP_HAL_TSIF; 302 303 304 typedef enum _TSP_HAL_FileState 305 { 306 /// Command Queue is Idle 307 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 308 /// Command Queue is Busy 309 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 310 /// Command Queue is Paused. 311 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 312 313 E_TSP_HAL_FILE_STATE_INVALID, 314 }TSP_HAL_FileState; 315 316 typedef enum 317 { 318 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 319 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 320 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 321 322 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 323 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 324 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 325 326 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 327 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 328 329 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 330 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 331 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 332 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 333 334 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 335 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 336 337 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 338 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 339 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 340 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 341 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 342 343 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 344 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 345 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 346 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 347 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 348 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 349 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 350 351 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 352 353 //27 is reserved, and can not be used 354 355 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 356 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 357 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 358 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 359 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 360 361 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 362 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 363 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 364 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 365 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 366 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 367 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 368 E_TSP_HAL_CAP_FIQ_NUM = 40, 369 E_TSP_HAL_CAP_TYPE_NULL, 370 } TSP_HAL_CAP_TYPE; 371 372 // @F_TODO remove unused enum member 373 typedef enum 374 { 375 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PCRFLT_END_ID - TSP_PIDFLT_START_ID), 376 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 377 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 378 379 E_TSP_HAL_CAP_VAL_RECENG_NUM = PVR_NUM, 380 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 381 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 382 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 383 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 384 385 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 6, //MMFI0 filters 386 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 6, //MMFI1 filters 387 388 E_TSP_HAL_CAP_VAL_TSIF_NUM = TSP_TSIF_NUM, 389 E_TSP_HAL_CAP_VAL_DEMOD_NUM = STC_ENG_NUM, //internal demod // [ToDo] STC number... by MM problem Jason-YH.Sun 390 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 391 E_TSP_HAL_CAP_VAL_VQ_NUM = VQ_NUM, 392 393 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 394 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 395 396 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 397 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 398 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 399 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 400 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 401 402 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 403 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 404 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 405 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 406 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 407 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 408 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 409 410 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 411 412 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 8, 413 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 6, 414 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 415 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 416 417 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x8000, // 32KB 418 419 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 420 } TSP_HAL_CAP_VAL; 421 422 /// TSP TEI Remove Error Packet Infomation 423 typedef enum 424 { 425 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 426 E_TSP_HAL_TEI_REMOVE_AUDIO2_PKT, ///< TEI Remoce Audio2 Packet 427 E_TSP_HAL_TEI_REMOVE_AUDIO3_PKT, ///< TEI Remoce Audio3 Packet 428 E_TSP_HAL_TEI_REMOVE_AUDIO4_PKT, ///< TEI Remoce Audio4 Packet 429 E_TSP_HAL_TEI_REMOVE_AUDIO5_PKT, ///< TEI Remoce Audio5 Packet 430 E_TSP_HAL_TEI_REMOVE_AUDIO6_PKT, ///< TEI Remoce Audio6 Packet 431 432 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT, ///< TEI Remoce Video Packet 433 E_TSP_HAL_TEI_REMOVE_VIDEO2_PKT, ///< TEI Remoce Video2 Packet 434 E_TSP_HAL_TEI_REMOVE_VIDEO3_PKT, ///< TEI Remoce Video3 Packet 435 E_TSP_HAL_TEI_REMOVE_VIDEO4_PKT, ///< TEI Remoce Video4 Packet 436 E_TSP_HAL_TEI_REMOVE_VIDEO5_PKT, ///< TEI Remoce Video5 Packet 437 E_TSP_HAL_TEI_REMOVE_VIDEO6_PKT, ///< TEI Remoce Video6 Packet 438 E_TSP_HAL_TEI_REMOVE_VIDEO7_PKT, ///< TEI Remoce Video7 Packet 439 E_TSP_HAL_TEI_REMOVE_VIDEO8_PKT ///< TEI Remoce Video8 Packet 440 441 }TSP_HAL_TEI_RmPktType; 442 443 // TSP TimeStamp Clk Select 444 typedef enum 445 { 446 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 447 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 448 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 449 450 } TSP_HAL_TimeStamp_Clk; 451 452 /// TSP Packet Converter Input Mode 453 typedef enum 454 { 455 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 456 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 457 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 458 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 459 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 460 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 461 E_TSP_HAL_PKT_MODE_MXL_200, ///< MXL mode (200 bytes) 462 E_TSP_HAL_PKT_MODE_ND, ///< Nagra Dongle mode (192 bytes) 463 464 E_TSP_HAL_PKT_MODE_INVALID 465 }TSP_HAL_PKT_MODE; 466 467 //---------------------------------- 468 /// DMX debug table information structure 469 //---------------------------------- 470 471 typedef enum 472 { 473 E_TSP_HAL_FLOW_LIVE0, 474 E_TSP_HAL_FLOW_LIVE1, 475 E_TSP_HAL_FLOW_LIVE2, 476 E_TSP_HAL_FLOW_LIVE3, 477 E_TSP_HAL_FLOW_LIVE4, 478 E_TSP_HAL_FLOW_LIVE5, 479 E_TSP_HAL_FLOW_LIVE6, 480 481 E_TSP_HAL_FLOW_FILE0, 482 E_TSP_HAL_FLOW_FILE1, 483 E_TSP_HAL_FLOW_FILE2, 484 E_TSP_HAL_FLOW_FILE3, 485 E_TSP_HAL_FLOW_FILE4, 486 E_TSP_HAL_FLOW_FILE5, 487 E_TSP_HAL_FLOW_FILE6, 488 489 E_TSP_HAL_FLOW_MMFI0, 490 E_TSP_HAL_FLOW_MMFI1, 491 492 E_TSP_HAL_FLOW_INVALID, 493 494 } TSP_HAL_FLOW; 495 496 typedef enum 497 { 498 E_TSP_HAL_GATING_PATH0 = 0, 499 E_TSP_HAL_GATING_PATH1, 500 E_TSP_HAL_GATING_PATH2, 501 E_TSP_HAL_GATING_PATH3, 502 E_TSP_HAL_GATING_PATH4, 503 E_TSP_HAL_GATING_PATH5, 504 E_TSP_HAL_GATING_PATH6, 505 E_TSP_HAL_GATING_TSP_ENG, 506 E_TSP_HAL_GATING_FIQ, //global 507 E_TSP_HAL_GATING_PVR1, 508 E_TSP_HAL_GATING_PVR2, 509 E_TSP_HAL_GATING_PVR3, 510 E_TSP_HAL_GATING_PVR4, 511 E_TSP_HAL_GATING_PVR5, 512 E_TSP_HAL_GATING_PVR6, 513 E_TSP_HAL_GATING_PVR7, 514 E_TSP_HAL_GATING_PVR8, 515 516 E_TSP_HAL_MIU_CLK_GATING_PATH0, 517 E_TSP_HAL_MIU_CLK_GATING_PATH1, 518 E_TSP_HAL_MIU_CLK_GATING_PATH2, 519 E_TSP_HAL_MIU_CLK_GATING_PATH3, 520 E_TSP_HAL_MIU_CLK_GATING_PATH4, 521 E_TSP_HAL_MIU_CLK_GATING_PATH5, 522 E_TSP_HAL_MIU_CLK_GATING_PATH6, 523 E_TSP_HAL_MIU_CLK_GATING_TSP_ENG, 524 E_TSP_HAL_MIU_CLK_GATING_FIQ, 525 E_TSP_HAL_MIU_CLK_GATING_PVR1, 526 E_TSP_HAL_MIU_CLK_GATING_PVR2, 527 E_TSP_HAL_MIU_CLK_GATING_PVR3, 528 E_TSP_HAL_MIU_CLK_GATING_PVR4, 529 E_TSP_HAL_MIU_CLK_GATING_PVR5, 530 E_TSP_HAL_MIU_CLK_GATING_PVR6, 531 E_TSP_HAL_MIU_CLK_GATING_PVR7, 532 E_TSP_HAL_MIU_CLK_GATING_PVR8, 533 E_TSP_HAL_MIU_CLK_GATING_MMFI0, 534 E_TSP_HAL_MIU_CLK_GATING_MMFI1, 535 536 E_TSP_HAL_GATING_FIQ0, 537 E_TSP_HAL_GATING_FIQ1, 538 E_TSP_HAL_GATING_FIQ2, 539 E_TSP_HAL_GATING_FIQ3, 540 E_TSP_HAL_GATING_FIQ4, 541 E_TSP_HAL_GATING_FIQ5, 542 E_TSP_HAL_GATING_FIQ6, 543 544 E_TSP_HAL_MIU_CLK_GATING_FIQ0, 545 E_TSP_HAL_MIU_CLK_GATING_FIQ1, 546 E_TSP_HAL_MIU_CLK_GATING_FIQ2, 547 E_TSP_HAL_MIU_CLK_GATING_FIQ3, 548 E_TSP_HAL_MIU_CLK_GATING_FIQ4, 549 E_TSP_HAL_MIU_CLK_GATING_FIQ5, 550 E_TSP_HAL_MIU_CLK_GATING_FIQ6, 551 552 E_TSP_HAL_GATING_INVALID, 553 554 } TSP_HAL_GATING; 555 556 typedef enum 557 { 558 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0, 559 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER1, 560 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER2, 561 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER3, 562 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER4, 563 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER5, 564 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER6, 565 566 E_TSP_HAL_RESET_CTRL_FIQ0, 567 E_TSP_HAL_RESET_CTRL_FIQ1, 568 E_TSP_HAL_RESET_CTRL_FIQ2, 569 E_TSP_HAL_RESET_CTRL_FIQ3, 570 E_TSP_HAL_RESET_CTRL_FIQ4, 571 E_TSP_HAL_RESET_CTRL_FIQ5, 572 E_TSP_HAL_RESET_CTRL_FIQ6, 573 574 E_TSP_HAL_RESET_CTRL_VQ_TX0, 575 E_TSP_HAL_RESET_CTRL_VQ_TX1, 576 E_TSP_HAL_RESET_CTRL_VQ_TX2, 577 E_TSP_HAL_RESET_CTRL_VQ_TX3, 578 E_TSP_HAL_RESET_CTRL_VQ_TX4, 579 E_TSP_HAL_RESET_CTRL_VQ_TX5, 580 E_TSP_HAL_RESET_CTRL_VQ_TX6, 581 E_TSP_HAL_RESET_CTRL_VQ_RX, 582 E_TSP_HAL_RESET_CTRL_VQ_TOP, 583 E_TSP_HAL_RESET_CTRL_PKT_DEMUX0, 584 E_TSP_HAL_RESET_CTRL_PKT_DEMUX1, 585 E_TSP_HAL_RESET_CTRL_PKT_DEMUX2, 586 E_TSP_HAL_RESET_CTRL_PKT_DEMUX3, 587 E_TSP_HAL_RESET_CTRL_PKT_DEMUX4, 588 E_TSP_HAL_RESET_CTRL_PKT_DEMUX5, 589 E_TSP_HAL_RESET_CTRL_PKT_DEMUX6, 590 591 E_TSP_HAL_RESET_CTRL_PVR1, 592 E_TSP_HAL_RESET_CTRL_PVR2, 593 E_TSP_HAL_RESET_CTRL_PVR3, 594 E_TSP_HAL_RESET_CTRL_PVR4, 595 E_TSP_HAL_RESET_CTRL_PVR5, 596 E_TSP_HAL_RESET_CTRL_PVR6, 597 E_TSP_HAL_RESET_CTRL_PVR7, 598 E_TSP_HAL_RESET_CTRL_PVR8, 599 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1, 600 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR2, 601 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR3, 602 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR4, 603 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR5, 604 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR6, 605 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR7, 606 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR8, 607 E_TSP_HAL_RESET_CTRL_SP_D0, 608 E_TSP_HAL_RESET_CTRL_SP_D1, 609 E_TSP_HAL_RESET_CTRL_SP_D2, 610 E_TSP_HAL_RESET_CTRL_SP_D3, 611 E_TSP_HAL_RESET_CTRL_SP_D4, 612 E_TSP_HAL_RESET_CTRL_SP_D5, 613 E_TSP_HAL_RESET_CTRL_SP_D6, 614 615 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0, 616 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT1, 617 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT2, 618 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT3, 619 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT4, 620 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT5, 621 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT6, 622 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0, 623 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_1, 624 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_2, 625 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_3, 626 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_4, 627 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_5, 628 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_6, 629 630 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0, 631 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER1, 632 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER2, 633 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER3, 634 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER4, 635 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER5, 636 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER6, 637 E_TSP_HAL_RESET_CTRL_PCRFLT_0, 638 E_TSP_HAL_RESET_CTRL_PCRFLT_1, 639 E_TSP_HAL_RESET_CTRL_PCRFLT_2, 640 E_TSP_HAL_RESET_CTRL_PCRFLT_3, 641 E_TSP_HAL_RESET_CTRL_PCRFLT_4, 642 E_TSP_HAL_RESET_CTRL_PCRFLT_5, 643 E_TSP_HAL_RESET_CTRL_PCRFLT_6, 644 645 E_TSP_HAL_RESET_PATH0, 646 E_TSP_HAL_RESET_PATH1, 647 E_TSP_HAL_RESET_PATH2, 648 E_TSP_HAL_RESET_PATH3, 649 E_TSP_HAL_RESET_PATH4, 650 E_TSP_HAL_RESET_PATH5, 651 E_TSP_HAL_RESET_PATH6, 652 E_TSP_HAL_RESET_OTV, 653 E_TSP_HAL_RESET_DEBUG_TABLE, 654 E_TSP_HAL_RESET_DMA_ENG, 655 E_TSP_HAL_RESET_SEC_CMP, 656 E_TSP_HAL_RESET_SECFLT_REG, 657 E_TSP_HAL_RESET_SEC, 658 E_TSP_HAL_RESET_PID_TABLE, 659 660 E_TSP_HAL_RESET_CTRL_INVALID, 661 662 } TSP_HAL_RESET_CTRL; 663 664 typedef enum 665 { 666 E_TSP_FQ_MUX_OUT_PATH = 0, 667 E_TSP_FQ_MUX_OUT_MUX_0, 668 E_TSP_FQ_MUX_OUT_MUX_1, 669 E_TSP_FQ_MUX_OUT_MUX_2, 670 671 E_TSP_FQ_MUX_OUT_INVALID, 672 673 } TSP_FQ_MUX_OUT_SRC; 674 675 typedef enum 676 { 677 E_TSP_HAL_MIU_SEL_MMFI = 0, 678 E_TSP_HAL_MIU_SEL_FQ = 1, 679 680 E_TSP_HAL_MIU_SEL_INVALID, 681 682 } TSP_HAL_MIU_SEL_TYPE; 683 684 //-------------------------------------------------------------------------------------------------- 685 // PVR HAL API 686 //-------------------------------------------------------------------------------------------------- 687 // Static Register Mapping for external access 688 #define REG_PIDFLT_BASE0 (0x00240000UL) 689 #define REG_PIDFLT_BASE1 (0x00241000UL) 690 #define REG_PIDFLT_BASE2 (0x00242000UL) 691 #define REG_SECFLT_BASE (0x00221000UL) 692 #define REG_SECBUF_BASE (0x00221024UL) 693 #define REG_SECFLT_BUFID_H_BASE (0x00230FD0UL) // section flt buf_id[8] 694 695 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 696 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 697 #define _REGPid2 ((REG_Pid*) (REG_PIDFLT_BASE2)) 698 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 699 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 700 701 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 702 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 703 #define PPIDFLT2(_fltid) (&(_REGPid2->Flt[_fltid])) 704 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 705 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 706 707 708 //******************** PIDFLT DEFINE START ********************// 709 //===== [PPIDFLT #0]: 0x240000 =====// 710 // PID 711 #define TSP_PIDFLT_PID_MASK 0x00001FFF 712 #define TSP_PIDFLT_PID_SHFT 0 713 714 // PIDFLT SRC 715 typedef enum _TSP_PIDFLT_SRC 716 { 717 E_TSP_PIDFLT_LIVE0, 718 E_TSP_PIDFLT_LIVE1, 719 E_TSP_PIDFLT_LIVE2, 720 E_TSP_PIDFLT_LIVE3, 721 E_TSP_PIDFLT_LIVE4, 722 E_TSP_PIDFLT_LIVE5, 723 E_TSP_PIDFLT_LIVE6, 724 E_TSP_PIDFLT_FILE0, 725 E_TSP_PIDFLT_FILE1, 726 E_TSP_PIDFLT_FILE2, 727 E_TSP_PIDFLT_FILE3, 728 E_TSP_PIDFLT_FILE4, 729 E_TSP_PIDFLT_FILE5, 730 E_TSP_PIDFLT_FILE6, 731 E_TSP_PIDFLT_INVALID, 732 } TSP_PIDFLT_SRC; 733 734 // Path_SRC 735 #define TSP_PIDFLT_IN_MASK 0x0000E000 736 #define TSP_PIDFLT_TSIF_SHFT 13 737 #define TSP_PIDFLT_TSIF0 0x01 738 #define TSP_PIDFLT_TSIF1 0x02 739 #define TSP_PIDFLT_TSIF2 0x03 740 #define TSP_PIDFLT_TSIF3 0x04 741 #define TSP_PIDFLT_TSIF4 0x05 742 #define TSP_PIDFLT_TSIF5 0x06 743 #define TSP_PIDFLT_TSIF6 0x07 744 #define TSP_PIDFLT_TSIF_MAX 0x08 745 746 // SRC ID 747 #define TSP_PIDFLT_SRCID_MASK 0x003F0000 748 #define TSP_PIDFLT_SRCID_SHIFT 16 749 750 // PKT_RUSH_PASS 751 #define TSP_PID_FLT_PKTPUSH_PASS 0x00400000 752 753 // PVR_LUT_EN 754 #define TSP_PIDFLT_OUT_LUT 0x00800000 755 756 //===== [PPIDFLT #1]: 0x241000 =====// 757 // PIDFLT DST 758 typedef enum _TSP_PIDFLT_DST 759 { 760 E_TSP_PIDFLT_DST_VIDEO, 761 E_TSP_PIDFLT_DST_AUDIO, 762 E_TSP_PIDFLT_DST_PVR, 763 764 E_TSP_PIDFLT_DST_INVALID, 765 } TSP_PIDFLT_DST; 766 767 // Audio 0~5 768 #define TSP_PIDFLT_OUT_MASK 0x03FFFFFF 769 #define TSP_PIDFLT_OUT_SHFT 0 770 #define TSP_PIDFLT_OUT_NONE 0x00000000 771 #define TSP_PIDFLT_OUT_AFIFO 0x00000001 772 #define TSP_PIDFLT_OUT_AFIFO2 0x00000002 773 #define TSP_PIDFLT_OUT_AFIFO3 0x00000004 774 #define TSP_PIDFLT_OUT_AFIFO4 0x00000008 775 #define TSP_PIDFLT_OUT_AFIFO5 0x00000010 776 #define TSP_PIDFLT_OUT_AFIFO6 0x00000020 777 // AF & Sec 778 #define TSP_PIDFLT_OUT_SECAF 0x00000040 779 #define TSP_PIDFLT_OUT_SECFLT 0x00000080 780 // Video 0~7 781 #define TSP_PIDFLT_OUT_VFIFO 0x00000100 782 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000200 783 #define TSP_PIDFLT_OUT_VFIFO3 0x00000400 784 #define TSP_PIDFLT_OUT_VFIFO4 0x00000800 785 #define TSP_PIDFLT_OUT_VFIFO5 0x00001000 786 #define TSP_PIDFLT_OUT_VFIFO6 0x00002000 787 #define TSP_PIDFLT_OUT_VFIFO7 0x00004000 788 #define TSP_PIDFLT_OUT_VFIFO8 0x00008000 789 // PVR 1~10 790 #define TSP_PIDFLT_OUT_PVR1 0x00010000 791 #define TSP_PIDFLT_OUT_PVR2 0x00020000 792 #define TSP_PIDFLT_OUT_PVR3 0x00040000 793 #define TSP_PIDFLT_OUT_PVR4 0x00080000 794 #define TSP_PIDFLT_OUT_PVR5 0x00100000 795 #define TSP_PIDFLT_OUT_PVR6 0x00200000 796 #define TSP_PIDFLT_OUT_PVR7 0x00400000 797 #define TSP_PIDFLT_OUT_PVR8 0x00800000 798 #define TSP_PIDFLT_OUT_PVR9 0x01000000 799 #define TSP_PIDFLT_OUT_PVR10 0x02000000 800 801 #define TSP_PIDFLT_PVRFLT_MASK 0x03FF0000 802 #define TSP_PIDFLT_PVRFLT_SHIFT 16 803 804 //===== [PPIDFLT #2]: 0x242000 =====// 805 // Section filter Id (0~511) 806 #define TSP_PIDFLT_SECFLT_MASK 0x000001FF 807 #define TSP_PIDFLT_SECFLT_SHFT 0 808 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 809 // FIQ_LUT 810 #define TSP_PIDFLT_FIQ_LUT_MASK 0x0000F000 811 #define TSP_PIDFLT_FIQ_LUT_SHIFT 12 812 // MULTI_PVR 813 #define TSP_PIDFLT_MULTI_PVR_MASK 0x00FF0000 814 #define TSP_PIDFLT_MULTI_PVR_SHIFT 16 815 816 //******************** PIDFLT DEFINE END ********************// 817 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 818 MS_U32 TSP32_IdrR(TSP32 *preg); 819 820 //=========================TSIF================================ 821 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 822 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 823 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 824 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 825 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 826 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 827 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 828 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 829 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 830 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 831 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 832 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 833 834 //=========================TSP================================ 835 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 836 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 837 void HAL_TSP_Reset(MS_BOOL bEn); 838 void HAL_TSP_Power(MS_BOOL bEn); 839 void HAL_TSP_CPU(MS_BOOL bEn); 840 void HAL_TSP_HwPatch(void); 841 void HAL_TSP_RestoreFltState(void); 842 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 843 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 844 void HAL_TSP_SaveFltState(void); 845 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 846 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 847 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 848 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart); 849 850 //=========================TSO================================ 851 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 852 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 853 854 //=========================Filein================================ 855 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 856 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 857 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 858 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 859 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 860 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 861 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 862 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 863 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 864 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 865 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 866 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 867 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 868 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 869 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 870 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 871 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 872 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass);// for PS mode A/V fifo pull back 873 874 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 875 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 876 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 877 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 878 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 879 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 880 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 881 882 //=========================PCR FLT================================ 883 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 884 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 885 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 886 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 887 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc); 888 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 889 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 890 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 891 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId); 892 893 //=========================STC================================ 894 void HAL_TSP_STC_Init(void); 895 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 896 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 897 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); // @NOTE: need to modify 898 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 899 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 900 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); // @NOTE: need to modify 901 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); // @NOTE: need to modify 902 903 //=========================FIFO================================ 904 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 905 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 906 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 907 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 908 void HAL_TSP_FIFO_ClearAll (void); 909 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 910 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 911 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 912 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 913 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 914 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 915 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 916 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 917 918 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 919 MS_U16 HAL_TSP_FIFO_ReadPkt(TSP_DST_SEQ eFltType); // read A/V fifo data 920 void HAL_TSP_FIFO_ReadEn(TSP_DST_SEQ eFltType, MS_BOOL bEn); // 921 void HAL_TSP_FIFO_Connect(TSP_DST_SEQ eFltType,MS_BOOL bEn); // 922 void HAL_TSP_FIFO_BD_AUD_En(TSP_DST_SEQ eAudioType, MS_BOOL bMainChEn, MS_BOOL bEn); 923 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 924 void HAL_TSP_TRACE_MARK_En(TSP_DST_SEQ eFltType,MS_BOOL bEn); 925 926 //=========================VQ================================ 927 MS_BOOL HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 928 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 929 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 930 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 931 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId); 932 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 933 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 934 935 //=========================Pid Flt================================ 936 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 937 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 938 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 939 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 940 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 941 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 942 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 943 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 944 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 945 void HAL_TSP_PidFlt_SetLutEn(MS_U32 fltId, MS_BOOL bEn); 946 void HAL_TSP_PidFlt_SetFqLutEn(MS_U32 fltId, MS_U32 u32FqLutEng, MS_BOOL bEn); 947 void HAL_TSP_PidFlt_SetMultiPvrEn(MS_U32 fltId, MS_U32 u32MultiPvrEng, MS_U32 u32MultiPvrChId, MS_BOOL bEn); 948 949 //=========================SecFlt================================ 950 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 951 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 952 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 953 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 954 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 955 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 956 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 957 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 958 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 959 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 960 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 961 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 962 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 963 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 964 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 965 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 966 967 //=========================Sec Buf================================ 968 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 969 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 970 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 971 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 972 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 973 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 974 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 975 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 976 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 977 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 978 979 //=========================PVR================================ 980 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 981 void HAL_PVR_Exit(MS_U32 u32PVREng); 982 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 983 /* 984 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 985 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 986 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 987 */ 988 void HAL_PVR_FlushData(MS_U32 u32PVREng); 989 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 990 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 991 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 992 void HAL_PVR_Start(MS_U32 u32PVREng); 993 void HAL_PVR_Stop(MS_U32 u32PVREng); 994 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 995 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 996 void HAL_PVR_RecNull(MS_U32 u32PVREng, MS_BOOL bSet); 997 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 998 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 999 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 1000 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 1001 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 1002 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 1003 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 1004 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 1005 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 1006 void HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng, MS_U32 u32Stamp); 1007 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 1008 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng, MS_BOOL bEnable); 1009 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng, MS_U32 u32PauseTime); 1010 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 1011 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 1012 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 1013 void HAL_TSP_PVR_SPSConfig(MS_U32 u32PVREng, MS_BOOL CTR_mode); 1014 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsIf, MS_BOOL CTR_mode); 1015 1016 //=========================FQ================================ 1017 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 1018 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 1019 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 1020 MS_BOOL HAL_TSP_FQ_MuxOutPathSrc(MS_U32 u32FQEng, TSP_FQ_MUX_OUT_SRC *peSrc, MS_BOOL bSet); 1021 1022 //=========================HCMD================================ 1023 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 1024 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 1025 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 1026 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 1027 MS_BOOL HAL_TSP_HCMD_Alive(void); 1028 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 1029 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 1030 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 1031 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 1032 1033 //=========================INT================================ 1034 void HAL_TSP_INT_Enable(MS_U32 u32Mask); 1035 void HAL_TSP_INT_Disable(MS_U32 u32Mask); 1036 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask); 1037 MS_U32 HAL_TSP_INT_GetHW(void); 1038 void HAL_TSP_INT_ClrSW(void); 1039 MS_U32 HAL_TSP_INT_GetSW(void); 1040 1041 //=========================Mapping================================ 1042 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 1043 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 1044 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 1045 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 1046 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 1047 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 1048 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 1049 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng); 1050 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 1051 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 1052 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 1053 1054 //========================DSCMB Functions=================================== 1055 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 1056 1057 //========================MOBF Functions===================================== 1058 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 1059 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 1060 1061 //========================Protection range=================================== 1062 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 1063 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 1064 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 1065 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 1066 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 1067 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 1068 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 1069 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 1070 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 1071 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 1072 1073 //========================Debug table============================= 1074 // @TODO Renaming Load and Get 1075 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 1076 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf, MS_BOOL bEn); 1077 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock); // @NOTE: prototype is changed (ref: Keres-series line) 1078 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32TsIf); 1079 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 1080 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 1081 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 1082 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 1083 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 1084 1085 // @TODO Implement Drop and Dis Hal 1086 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 1087 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 1088 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn, MS_BOOL bPayload); 1089 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_DST_SEQ eAvType, MS_BOOL bDrop); // @NOTE: prototype is changed (ref: Keres-series line) 1090 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 1091 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 1092 1093 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 1094 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf, MS_BOOL bEn); 1095 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(MS_U32 u32TsIf); 1096 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32TsIf); 1097 1098 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); // @NOTE: need to delete 1099 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); // @NOTE: need to delete 1100 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); // @NOTE: need to delete 1101 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); // @NOTE: need to delete 1102 1103 //========================MergeStream Functions============================= 1104 void HAL_TSP_PktConverter_Init(void); 1105 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 1106 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 1107 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 1108 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 1109 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable); 1110 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 1111 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path); 1112 1113 //==========================TSIO ============================================ 1114 void HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath, MS_U32 u32Idx, MS_BOOL bEn); 1115 void HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath, MS_U32 u32eng, MS_BOOL bEn); 1116 1117 #endif // #ifndef __HAL_TSP_H__ 1118