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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halMultiPVR.c
97 // @brief Multi-PVR HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #include "MsCommon.h"
107 #include "regMultiPVR.h"
108 #include "halMultiPVR.h"
109
110 //--------------------------------------------------------------------------------------------------
111 // Driver Compiler Option
112 //--------------------------------------------------------------------------------------------------
113
114
115 //--------------------------------------------------------------------------------------------------
116 // TSP Hardware Abstraction Layer
117 //--------------------------------------------------------------------------------------------------
118 static REG_MULTI_PVR_ENG_Ctrl *_RegMultiPvrCtrl = NULL;
119
120 //-------------------------------------------------------------------------------------------------
121 // Local Functions
122 //-------------------------------------------------------------------------------------------------
REG32_R(REG32_MULTI_PVR * reg)123 static MS_U32 REG32_R(REG32_MULTI_PVR *reg)
124 {
125 MS_U32 value = 0;
126 value = (reg)->low;
127 value |= (reg)->high << 16;
128 return value;
129 }
130
REG16_R(REG16_MULTI_PVR * reg)131 static MS_U16 REG16_R(REG16_MULTI_PVR *reg)
132 {
133 MS_U16 value = 0;
134 value = (reg)->data;
135 return value;
136 }
137
138 #define REG32_W(reg, value) { (reg)->low = ((value) & 0x0000FFFF); \
139 (reg)->high = ((value) >> 16); }
140
141 #define REG16_W(reg, value) { (reg)->data = ((value) & 0x0000FFFF); }
142
143 #define _AND_(flag, bit) ((flag) & (bit))
144
145 #define _SET_(flag, bit) ((flag) | (bit))
146 #define _CLR_(flag, bit) ((flag) & (~(bit)))
147
148 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value))
149 #define REG32_SET(reg, value) REG32_W(reg, _SET_(REG32_R(reg), value))
150 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value))
151 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value))
152
153 #define REG16_MSK_W(reg, mask, value) REG16_W((reg), _CLR_(REG16_R(reg), (mask)) | _AND_((value), (mask)))
154 #define REG32_MSK_W(reg, mask, value) REG32_W((reg), _CLR_(REG32_R(reg), (mask)) | _AND_((value), (mask)))
155
156 typedef struct
157 {
158 MS_U16 VCID : 8;
159 MS_U16 RdPos : 3;
160 MS_U16 Clr : 1;
161 MS_U16 RW : 1;
162 MS_U16 Active : 1;
163 MS_U16 RdAddrLsb : 1;
164 MS_U16 PingpongEn : 1;
165 } ST_ACPU_CMD;
166
167 typedef struct
168 {
169 MS_U16 AlignEn : 1;
170 MS_U16 MiuSel : 2;
171 MS_U16 IntEn : 1;
172 MS_U16 MOBF : 5;
173 MS_U16 SecureFlag : 1;
174 MS_U16 TimestampEn : 1;
175 MS_U16 Padding : 5;
176 } ST_ACPU_FLAG;
177
_HAL_MultiPVR_IdrW(ST_ACPU_CMD stCmd,ST_ACPU_FLAG stFlag,MS_U32 u32Head,MS_U32 u32Tail)178 static void _HAL_MultiPVR_IdrW(ST_ACPU_CMD stCmd, ST_ACPU_FLAG stFlag, MS_U32 u32Head, MS_U32 u32Tail)
179 {
180 REG32_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_43_44, u32Head);
181 REG32_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_45_46, u32Tail);
182 REG16_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_41, *((MS_U16*)&stCmd));
183 REG16_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_42, *((MS_U16*)&stFlag));
184 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_40, CFG_MULTI_PVR_40_REG_ACPU_ACTIVE);
185 }
186
187 //acpu_rd_position = 0 (used size)
188 // = 1 (acpu_flag)
189 // = 4 (tail)
190 // = 5 (head)
_HAL_MultiPVR_IdrR(MS_U32 u32ChId,MS_U8 u8RdPos,MS_BOOL bRdAddrLsb)191 static MS_U32 _HAL_MultiPVR_IdrR(MS_U32 u32ChId, MS_U8 u8RdPos, MS_BOOL bRdAddrLsb)
192 {
193 ST_ACPU_CMD stCmd;
194
195 memset(&stCmd, 0, sizeof(ST_ACPU_CMD));
196 stCmd.VCID = u32ChId & 0xFF;
197 stCmd.RdPos = u8RdPos;
198 stCmd.RdAddrLsb = bRdAddrLsb;
199 REG16_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_41, *((MS_U16*)&stCmd));
200 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_40, CFG_MULTI_PVR_40_REG_ACPU_ACTIVE);
201
202 return REG32_R(&_RegMultiPvrCtrl->CFG_MULTI_PVR_47_48);
203 }
204
205 #define MULTI_PVR_GET_USED_SIZE0(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 0, 0); u32RetVal; })
206 #define MULTI_PVR_GET_USED_SIZE1(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 0, 1); u32RetVal; })
207 #define MULTI_PVR_GET_ACPU_FLAG(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 1, 0) >> 16; u32RetVal; })
208 #define MULTI_PVR_GET_HEAD0(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 5, 0); u32RetVal; })
209 #define MULTI_PVR_GET_TAIL0(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 4, 0); u32RetVal; })
210 #define MULTI_PVR_GET_HEAD1(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 5, 1); u32RetVal; })
211 #define MULTI_PVR_GET_TAIL1(ChId) ({ MS_U32 u32RetVal = _HAL_MultiPVR_IdrR(ChId, 4, 1); u32RetVal; })
212
213 #define MULTI_PVR_ENG_CHK(PvrEng, RetVal) if(PvrEng >= TSP_MULTI_PVR_ENG_NUM) \
214 { \
215 HAL_MULTI_PVR_DBGMSG(E_HAL_MULTI_PVR_DBG_LEVEL_ERR, \
216 E_HAL_MULTI_PVR_DBG_MODEL_ALL, \
217 printf("[MULTI_PVR_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n", \
218 __FUNCTION__, __LINE__, PvrEng) \
219 ); \
220 return RetVal; \
221 }
222
223 #define MULTI_PVR_CHID_CHK(PvrChId, RetVal) if(PvrChId >= TSP_MULTI_PVR_CH_NUM) \
224 { \
225 HAL_MULTI_PVR_DBGMSG(E_HAL_MULTI_PVR_DBG_LEVEL_ERR, \
226 E_HAL_MULTI_PVR_DBG_MODEL_ALL, \
227 printf("[MULTI_PVR_ERR][%s][%d] Wrong PVR ChId : 0x%x !!\n", \
228 __FUNCTION__, __LINE__, PvrChId) \
229 ); \
230 return RetVal; \
231 }
232
233 //-------------------------------------------------------------------------------------------------
234 // Debug Message
235 //-------------------------------------------------------------------------------------------------
236 typedef enum
237 {
238 E_HAL_MULTI_PVR_DBG_LEVEL_NONE, // no debug message shown
239 E_HAL_MULTI_PVR_DBG_LEVEL_ERR, // only shows error message that can't be recover
240 E_HAL_MULTI_PVR_DBG_LEVEL_WARN, // error case can be recover, like retry
241 E_HAL_MULTI_PVR_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
242 E_HAL_MULTI_PVR_DBG_LEVEL_INFO, // information for internal parameter
243 E_HAL_MULTI_PVR_DBG_LEVEL_FUNC, // Function trace and input parameter trace
244 E_HAL_MULTI_PVR_DBG_LEVEL_TRACE, // debug trace
245 } EN_HAL_MULTI_PVR_DBGMSG_LEVEL;
246
247 typedef enum
248 {
249 E_HAL_MULTI_PVR_DBG_MODEL_NONE, // @temporarily , need to refine
250 E_HAL_MULTI_PVR_DBG_MODEL_ALL,
251 } EN_HAL_MULTI_PVR_DBGMSG_MODEL;
252
253 #define HAL_MULTI_PVR_DBGMSG(_level,_model,_f) do {if(_u32MultiPvrDbgLevel >= (_level)&&((_u32MultiPvrDbgModel&_model)!=0)) (_f);} while(0)
254 static MS_U32 _u32MultiPvrDbgLevel = E_HAL_MULTI_PVR_DBG_LEVEL_ERR;
255 static MS_U32 _u32MultiPvrDbgModel = E_HAL_MULTI_PVR_DBG_MODEL_ALL;
256
257
HAL_MultiPVR_SetBank(MS_VIRT u32BankAddr)258 void HAL_MultiPVR_SetBank(MS_VIRT u32BankAddr)
259 {
260 _RegMultiPvrCtrl = (REG_MULTI_PVR_ENG_Ctrl*)(u32BankAddr + 0xC1400); //MultiPVR: 0x160A
261 }
262
HAL_MultiPVR_Init(MS_U32 u32PVREng,MS_U32 pktDmxId)263 void HAL_MultiPVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId)
264 {
265 MULTI_PVR_ENG_CHK(u32PVREng,);
266
267 // input src
268 REG16_MSK_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_71, CFG_MULTI_PVR_71_REG_INPUT_SRC_MASK, (((MS_U16)pktDmxId) << CFG_MULTI_PVR_71_REG_INPUT_SRC_SHIFT));
269
270 // record ts
271 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_TS);
272
273 // record null
274 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_DIS_NULL_PKT);
275
276 // enbale Multi-PVR
277 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_EN);
278 }
279
HAL_MultiPVR_Exit(MS_U32 u32PVREng)280 void HAL_MultiPVR_Exit(MS_U32 u32PVREng)
281 {
282 MULTI_PVR_ENG_CHK(u32PVREng,);
283
284 // disable Multi-PVR
285 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_EN);
286
287 // clear input src
288 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_71, CFG_MULTI_PVR_71_REG_INPUT_SRC_MASK);
289
290 // reset record ts
291 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_TS);
292
293 // reset record null
294 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_DIS_NULL_PKT);
295 }
296
HAL_MultiPVR_FlushData(MS_U32 u32PVREng)297 void HAL_MultiPVR_FlushData(MS_U32 u32PVREng)
298 {
299 MULTI_PVR_ENG_CHK(u32PVREng,);
300
301 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_DMA_FLUSH_EN);
302 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_DMA_FLUSH_EN);
303 }
304
HAL_MultiPVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)305 void HAL_MultiPVR_Skip_Scrmb(MS_U32 u32PVREng, MS_BOOL bSkip)
306 {
307 MULTI_PVR_ENG_CHK(u32PVREng,);
308
309 if(bSkip)
310 {
311 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_MASK_SCR_PVR_EN);
312 }
313 else
314 {
315 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_MASK_SCR_PVR_EN);
316 }
317 }
318
HAL_MultiPVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)319 void HAL_MultiPVR_Block_Dis(MS_U32 u32PVREng, MS_BOOL bDisable)
320 {
321 MULTI_PVR_ENG_CHK(u32PVREng,);
322
323 if(bDisable)
324 {
325 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_PVR_BLOCK_DISABLE);
326 }
327 else
328 {
329 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_PVR_BLOCK_DISABLE);
330 }
331 }
332
HAL_MultiPVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)333 void HAL_MultiPVR_BurstLen(MS_U32 u32PVREng, MS_U16 u16BurstMode)
334 {
335 MULTI_PVR_ENG_CHK(u32PVREng,);
336
337 REG16_MSK_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_BURST_LEN_MASK, (u16BurstMode << CFG_MULTI_PVR_00_REG_PVR_BURST_LEN_SHIFT));
338 }
339
HAL_MultiPVR_Start(MS_U32 u32PVREng,MS_U32 u32ChId)340 void HAL_MultiPVR_Start(MS_U32 u32PVREng, MS_U32 u32ChId)
341 {
342 MULTI_PVR_ENG_CHK(u32PVREng,);
343 MULTI_PVR_CHID_CHK(u32ChId,);
344
345 ST_ACPU_CMD stCmd;
346 ST_ACPU_FLAG stFlag;
347
348 memset(&stCmd, 0, sizeof(ST_ACPU_CMD));
349 memset(&stFlag, 0, sizeof(ST_ACPU_FLAG));
350
351 // read head , tail
352 MS_U32 u32Head0 = MULTI_PVR_GET_HEAD0(u32ChId);
353 MS_U32 u32Head1 = MULTI_PVR_GET_HEAD1(u32ChId);
354 MS_U32 u32Tail0 = MULTI_PVR_GET_TAIL0(u32ChId);
355 MS_U32 u32Tail1 = MULTI_PVR_GET_TAIL1(u32ChId);
356
357 // read acpu_flag
358 *((MS_U16*)&stFlag) = MULTI_PVR_GET_ACPU_FLAG(u32ChId);
359
360 // write pingpong buf #0
361 stCmd.VCID = u32ChId & 0xFF;
362 stCmd.Clr = 1;
363 stCmd.RW = 1;
364 stCmd.Active = 1; // PVR
365 stCmd.RdAddrLsb = 0;
366 stCmd.PingpongEn = 1;
367 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head0, u32Tail0);
368
369 // write pingpong buf #1
370 stCmd.RdAddrLsb = 1;
371 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head1, u32Tail1);
372 }
373
HAL_MultiPVR_Stop(MS_U32 u32PVREng,MS_U32 u32ChId)374 void HAL_MultiPVR_Stop(MS_U32 u32PVREng, MS_U32 u32ChId)
375 {
376 MULTI_PVR_ENG_CHK(u32PVREng,);
377 MULTI_PVR_CHID_CHK(u32ChId,);
378
379 ST_ACPU_CMD stCmd;
380 ST_ACPU_FLAG stFlag;
381
382 memset(&stCmd, 0, sizeof(ST_ACPU_CMD));
383 memset(&stFlag, 0, sizeof(ST_ACPU_FLAG));
384
385 // read head , tail
386 MS_U32 u32Head0 = MULTI_PVR_GET_HEAD0(u32ChId);
387 MS_U32 u32Head1 = MULTI_PVR_GET_HEAD1(u32ChId);
388 MS_U32 u32Tail0 = MULTI_PVR_GET_TAIL0(u32ChId);
389 MS_U32 u32Tail1 = MULTI_PVR_GET_TAIL1(u32ChId);
390
391 // read acpu_flag
392 *((MS_U16*)&stFlag) = MULTI_PVR_GET_ACPU_FLAG(u32ChId);
393
394 // write pingpong buf #0
395 stCmd.VCID = u32ChId & 0xFF;
396 stCmd.Clr = 1;
397 stCmd.RW = 1;
398 stCmd.Active = 0; // drop pkt
399 stCmd.RdAddrLsb = 0;
400 stCmd.PingpongEn = 1;
401 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head0, u32Tail0);
402
403 // write pingpong buf #1
404 stCmd.RdAddrLsb = 1;
405 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head1, u32Tail1);
406 }
407
HAL_MultiPVR_Pause(MS_U32 u32PVREng,MS_BOOL bPause)408 void HAL_MultiPVR_Pause(MS_U32 u32PVREng, MS_BOOL bPause)
409 {
410 MULTI_PVR_ENG_CHK(u32PVREng,);
411
412 if(bPause)
413 {
414 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_PAUSE);
415 }
416 else
417 {
418 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_00, CFG_MULTI_PVR_00_REG_PVR_STR2MI_PAUSE);
419 }
420 }
421
HAL_MultiPVR_RecPid(MS_U32 u32PVREng,MS_BOOL bSet)422 void HAL_MultiPVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet)
423 {
424 MULTI_PVR_ENG_CHK(u32PVREng,);
425
426 if(bSet)
427 {
428 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_ALL);
429 }
430 else
431 {
432 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_RECORD_ALL);
433 }
434 }
435
HAL_MultiPVR_RecNull(MS_U32 u32PVREng,MS_BOOL bSet)436 void HAL_MultiPVR_RecNull(MS_U32 u32PVREng, MS_BOOL bSet)
437 {
438 MULTI_PVR_ENG_CHK(u32PVREng,);
439
440 if(bSet)
441 {
442 REG16_CLR(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_DIS_NULL_PKT);
443 }
444 else
445 {
446 REG16_SET(&_RegMultiPvrCtrl->CFG_MULTI_PVR_70, CFG_MULTI_PVR_70_REG_DIS_NULL_PKT);
447 }
448 }
449
HAL_MultiPVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng,MS_U32 u32ChId,MS_U32 u32StartAddr0,MS_U32 u32StartAddr1)450 void HAL_MultiPVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32ChId, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
451 {
452 MULTI_PVR_ENG_CHK(u32PVREng,);
453 MULTI_PVR_CHID_CHK(u32ChId,);
454
455 ST_ACPU_CMD stCmd;
456 ST_ACPU_FLAG stFlag;
457
458 memset(&stCmd, 0, sizeof(ST_ACPU_CMD));
459 memset(&stFlag, 0, sizeof(ST_ACPU_FLAG));
460
461 // read tail
462 MS_U32 u32Tail0 = MULTI_PVR_GET_TAIL0(u32ChId);
463 MS_U32 u32Tail1 = MULTI_PVR_GET_TAIL1(u32ChId);
464
465 // read acpu_flag
466 *((MS_U16*)&stFlag) = MULTI_PVR_GET_ACPU_FLAG(u32ChId);
467
468 // write pingpong buf #0
469 stCmd.VCID = u32ChId & 0xFF;
470 stCmd.Clr = 1;
471 stCmd.RW = 1;
472 stCmd.Active = 0; // drop pkt
473 stCmd.RdAddrLsb = 0;
474 stCmd.PingpongEn = 1;
475 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32StartAddr0, u32Tail0);
476
477 // write pingpong buf #1
478 stCmd.RdAddrLsb = 1;
479 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32StartAddr1, u32Tail1);
480 }
481
HAL_MultiPVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng,MS_U32 u32ChId,MS_U32 u32EndAddr0,MS_U32 u32EndAddr1)482 void HAL_MultiPVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32ChId, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
483 {
484 MULTI_PVR_ENG_CHK(u32PVREng,);
485 MULTI_PVR_CHID_CHK(u32ChId,);
486
487 ST_ACPU_CMD stCmd;
488 ST_ACPU_FLAG stFlag;
489
490 memset(&stCmd, 0, sizeof(ST_ACPU_CMD));
491 memset(&stFlag, 0, sizeof(ST_ACPU_FLAG));
492
493 // read head
494 MS_U32 u32Head0 = MULTI_PVR_GET_HEAD0(u32ChId);
495 MS_U32 u32Head1 = MULTI_PVR_GET_HEAD1(u32ChId);
496
497 // read acpu_flag
498 *((MS_U16*)&stFlag) = MULTI_PVR_GET_ACPU_FLAG(u32ChId);
499
500 // write pingpong buf #0
501 stCmd.VCID = u32ChId & 0xFF;
502 stCmd.Clr = 1;
503 stCmd.RW = 1;
504 stCmd.Active = 0; // drop pkt
505 stCmd.RdAddrLsb = 0;
506 stCmd.PingpongEn = 1;
507 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head0, u32EndAddr0);
508
509 // write pingpong buf #1
510 stCmd.RdAddrLsb = 1;
511 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head1, u32EndAddr1);
512 }
513
HAL_MultiPVR_GetWritePtr(MS_U32 u32PVREng,MS_U32 u32ChId)514 MS_U32 HAL_MultiPVR_GetWritePtr(MS_U32 u32PVREng, MS_U32 u32ChId)
515 {
516 MULTI_PVR_ENG_CHK(u32PVREng, 0);
517 MULTI_PVR_CHID_CHK(u32ChId, 0);
518
519 MS_U32 u32UsedSize0 = MULTI_PVR_GET_USED_SIZE0(u32ChId);
520
521 if(u32UsedSize0 == 0)
522 {
523 MS_U32 u32UsedSize1 = MULTI_PVR_GET_USED_SIZE1(u32ChId);
524
525 if(u32UsedSize1 == 0)
526 {
527 REG16_MSK_W(&_RegMultiPvrCtrl->CFG_MULTI_PVR_50, CFG_MULTI_PVR_50_REG_SGDMA_OUT_VC_STATUS_SEL_MASK, ((MS_U16)u32ChId << CFG_MULTI_PVR_50_REG_SGDMA_OUT_VC_STATUS_SEL_SHIFT));
528 MS_BOOL bPingpongPtr = (REG16_R(&_RegMultiPvrCtrl->CFG_MULTI_PVR_51) & CFG_MULTI_PVR_51_REG_SGDMA_OUT_VC_STATUS_PINGPONG_PTR);
529
530 if(bPingpongPtr)
531 {
532 return MULTI_PVR_GET_HEAD1(u32ChId);
533 }
534 else
535 {
536 return MULTI_PVR_GET_HEAD0(u32ChId);
537 }
538 }
539 else
540 {
541 return (MULTI_PVR_GET_HEAD1(u32ChId) + u32UsedSize1);
542 }
543 }
544 else
545 {
546 return (MULTI_PVR_GET_HEAD0(u32ChId) + u32UsedSize0);
547 }
548 }
549
HAL_MultiPVR_SetStrPacketMode(MS_U32 u32PVREng,MS_U32 u32ChId,MS_BOOL bSet)550 void HAL_MultiPVR_SetStrPacketMode(MS_U32 u32PVREng, MS_U32 u32ChId, MS_BOOL bSet)
551 {
552 MULTI_PVR_ENG_CHK(u32PVREng,);
553 MULTI_PVR_CHID_CHK(u32ChId,);
554
555 ST_ACPU_CMD stCmd;
556 ST_ACPU_FLAG stFlag;
557
558 memset(&stCmd, 0, sizeof(ST_ACPU_CMD));
559 memset(&stFlag, 0, sizeof(ST_ACPU_FLAG));
560
561 // read head , tail
562 MS_U32 u32Head0 = MULTI_PVR_GET_HEAD0(u32ChId);
563 MS_U32 u32Head1 = MULTI_PVR_GET_HEAD1(u32ChId);
564 MS_U32 u32Tail0 = MULTI_PVR_GET_TAIL0(u32ChId);
565 MS_U32 u32Tail1 = MULTI_PVR_GET_TAIL1(u32ChId);
566
567 // read acpu_flag
568 *((MS_U16*)&stFlag) = MULTI_PVR_GET_ACPU_FLAG(u32ChId);
569
570 stFlag.TimestampEn = !!bSet; // 188 or 192
571
572 // write pingpong buf #0
573 stCmd.VCID = u32ChId & 0xFF;
574 stCmd.Clr = 1;
575 stCmd.RW = 1;
576 stCmd.Active = 0; // drop pkt
577 stCmd.RdAddrLsb = 0;
578 stCmd.PingpongEn = 1;
579 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head0, u32Tail0);
580
581 // write pingpong buf #1
582 stCmd.RdAddrLsb = 1;
583 _HAL_MultiPVR_IdrW(stCmd, stFlag, u32Head1, u32Tail1);
584 }
585
HAL_MultiPVR_SetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32ChId,MS_U32 u32Stamp)586 void HAL_MultiPVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32ChId, MS_U32 u32Stamp)
587 {
588 // Not support...
589 // (1) live-in: use FIQ timestamp
590 // (2) file-in: can't write to PVR
591 }
592
HAL_MultiPVR_GetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32ChId)593 MS_U32 HAL_MultiPVR_GetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32ChId)
594 {
595 // Not support...
596 // (1) live-in: use FIQ timestamp
597 // (2) file-in: can't write to PVR
598 return 0;
599 }
600