1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2010-2012 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: mmfilein.h 98 // Description: Multimedia File In (MMFILEIN) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _MMFILEIN_REG_H_ 103 #define _MMFILEIN_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define MMFI_ENGINE_NUM (2) 137 138 #define MMFI_PIDFLT0_NUM (6) 139 #define MMFI_PIDFLT1_NUM (6) 140 141 #define MMFI_PIDFLT_NUM_ALL (MMFI_PIDFLT0_NUM+MMFI_PIDFLT1_NUM) 142 143 #define MMFI_PID_NULL 0x1FFF 144 145 //------------------------------------------------------------------------------------------------- 146 // Harware Capability 147 //------------------------------------------------------------------------------------------------- 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 153 #define REG_CTRL_BASE_MMFI0 (0x27E00UL) // Bank: 0x113F , Offset: 0x00 154 #define REG_CTRL_BASE_MMFI1 (0x27FB8UL) // Bank: 0x113F , Offset: 0x6E 155 156 typedef struct _REG32_MM 157 { 158 volatile MS_U16 L; 159 volatile MS_U16 empty_L; 160 volatile MS_U16 H; 161 volatile MS_U16 empty_H; 162 } REG32_MM; 163 164 165 typedef struct _REG16_MM 166 { 167 volatile MS_U16 data; 168 volatile MS_U16 _resv; 169 } REG16_MM; 170 171 typedef struct _REG_Ctrl_MMFI 172 { 173 //---------------------------------------------- 174 // 0xBF802A00 MIPS direct access 175 //---------------------------------------------- 176 // CPU(byte) 177 REG32_MM PidFlt[MMFI_PIDFLT0_NUM]; // 0x00~0x0B 178 #define MMFI_PIDFLT_PID_MASK 0x00001FFF 179 #define MMFI_PIDFLT_EN_MASK 0x07FFE000 180 #define MMFI_PIDFLT_AFIFO_EN 0x00002000 181 #define MMFI_PIDFLT_AFIFOB_EN 0x00004000 182 #define MMFI_PIDFLT_AFIFOC_EN 0x00008000 183 #define MMFI_PIDFLT_AFIFOD_EN 0x00010000 184 #define MMFI_PIDFLT_AFIFOE_EN 0x00020000 185 #define MMFI_PIDFLT_AFIFOF_EN 0x00040000 186 187 #define MMFI_PIDFLT_VFIFO_EN 0x00080000 188 #define MMFI_PIDFLT_V3DFIFO_EN 0x00100000 189 #define MMFI_PIDFLT_VFIFO3_EN 0x00200000 190 #define MMFI_PIDFLT_VFIFO4_EN 0x00400000 191 #define MMFI_PIDFLT_VFIFO5_EN 0x00800000 192 #define MMFI_PIDFLT_VFIFO6_EN 0x01000000 193 #define MMFI_PIDFLT_VFIFO7_EN 0x02000000 194 #define MMFI_PIDFLT_VFIFO8_EN 0x04000000 195 196 REG32_MM Cfg; // 0x0C~0x0D 197 //------------------------- no use , just for compatibility -------------------------// 198 #define MMFI_CFG_ALT_TS_SIZE 0x00000000 199 #define MMFI_CFG_DUP_PKT_SKIP 0x00000000 200 #define MMFI_CFG_TEI_SKIP 0x00000000 201 #define MMFI_CFG_APID_BYPASS 0x00000000 202 #define MMFI_CFG_APIDB_BYPASS 0x00000000 203 #define MMFI_CFG_VPID_BYPASS 0x00000000 204 #define MMFI_CFG_VPID3D_BYPASS 0x00000000 205 //-----------------------------------------------------------------------------------// 206 #define MMFI_CFG_LPCR2_LD 0x00000001 207 #define MMFI_CFG_LPCR2_WLD 0x00000002 208 #define MMFI_CFG_CLR_PIDFLT_BYTE_CNT 0x00000008 209 #define MMFI_CFG_INIT_TIMESTAMP_RSTART_EN 0x00000010 210 #define MMFI_CFG_FIXED_TIMESTAMP_RING_BANK_EN 0x00000020 211 #define MMFI_CFG_FIXED_LPCR_RING_BANK_EN 0x00000040 212 #define MMFI_CFG_FIND_LOSS_SYNC_BYTE_RVU 0x00000080 213 214 #define MMFI_CFG_MMFI_ABORT 0x00010000 215 #define MMFI_CFG_DIS_MIU_RQ 0x00020000 216 #define MMFI_CFG_RADDR_READ 0x00040000 217 #define MMFI_CFG_BYTETIMER_EN 0x00080000 218 #define MMFI_CFG_2MI_RPRIORITY 0x00800000 219 #define MMFI_CFG_PS_AUD_EN 0x01000000 220 #define MMFI_CFG_PS_AUDB_EN 0x02000000 221 #define MMFI_CFG_PS_VD_EN 0x04000000 222 #define MMFI_CFG_PS_V3D_EN 0x08000000 223 #define MMFI_CFG_MEM_TS_ORDER 0x10000000 224 #define MMFI_CFG_MEM_TS_DATA_ENDIAN 0x20000000 225 #define MMFI_CFG_PKT192_EN 0x40000000 226 #define MMFI_CFG_PKT192_BLK_DISABLE 0x80000000 227 #define MMFI_CFG_FILEIN_MODE_MASK (MMFI_CFG_PS_AUD_EN|MMFI_CFG_PS_AUDB_EN|MMFI_CFG_PS_VD_EN|MMFI_CFG_PS_V3D_EN) 228 229 REG16_MM CFG2; // 0x0E 230 //------------------------- no use , just for compatibility -------------------------// 231 #define MMFI_CFG2_MMFI_APIDC_BYPASS 0x00000000 232 #define MMFI_CFG2_MMFI_APIDD_BYPASS 0x00000000 233 //-----------------------------------------------------------------------------------// 234 #define MMFI_CFG2_C27M_EN 0x00000001 235 #define MMFI_CFG2_MMFI_PS_VD3_EN 0x00000002 236 #define MMFI_CFG2_MMFI_PS_VD4_EN 0x00000004 237 #define MMFI_CFG2_MMFI_PS_VD5_EN 0x00000008 238 #define MMFI_CFG2_MMFI_PS_VD6_EN 0x00000010 239 #define MMFI_CFG2_MMFI_PS_VD7_EN 0x00000020 240 #define MMFI_CFG2_MMFI_PS_VD8_EN 0x00000040 241 #define MMFI_CFG2_MMFI_PS_AUDC_EN 0x00000080 242 #define MMFI_CFG2_MMFI_PS_AUDD_EN 0x00000100 243 #define MMFI_CFG2_FILEIN_PAUSE 0x00000200 244 #define MMFI_CFG2_WB_FSM_RESET 0x00000400 245 #define MMFI_CFG2_MMFI_PS_AUDE_EN 0x00000800 246 #define MMFI_CFG2_MMFI_PS_AUDF_EN 0x00001000 247 #define MMFI_CFG2_FILEIN_MODE_MASK ( MMFI_CFG2_MMFI_PS_AUDC_EN | MMFI_CFG2_MMFI_PS_AUDD_EN \ 248 | MMFI_CFG2_MMFI_PS_AUDE_EN | MMFI_CFG2_MMFI_PS_AUDF_EN \ 249 | MMFI_CFG2_MMFI_PS_VD3_EN | MMFI_CFG2_MMFI_PS_VD4_EN \ 250 | MMFI_CFG2_MMFI_PS_VD5_EN | MMFI_CFG2_MMFI_PS_VD6_EN \ 251 | MMFI_CFG2_MMFI_PS_VD7_EN | MMFI_CFG2_MMFI_PS_VD8_EN) 252 253 REG16_MM CFG3; // 0x0F (reserved) 254 #define MMFI_CFG3_MMFI_PS_VD3_EN 0x0000 // not support 255 #define MMFI_CFG3_MMFI_PS_VD4_EN 0x0000 // not support 256 #define MMFI_CFG3_FILEIN_MODE_MASK (MMFI_CFG3_MMFI_PS_VD3_EN | MMFI_CFG3_MMFI_PS_VD4_EN) 257 258 REG32_MM FileIn_RAddr; // 0x10~0x11 259 REG32_MM FileIn_RNum; // 0x12~0x13 260 REG16_MM FileIn_Ctrl; // 0x14 261 #define MMFI_FILEIN_CTRL_START 0x0001 262 #define MMFI_FILEIN_CTRL_DONE 0x0002 263 #define MMFI_FILEIN_CTRL_INIT_TRUST 0x0004 264 #define MMFI_FILEIN_CTRL_ABORT 0x0010 265 #define MMFI_FILEIN_CTRL_MOBF_EN 0x0020 // Not used (for compability) 266 #define MMFI_FILEIN_CTRL_MASK 0x0013 267 268 REG16_MM CmdQSts; // 0x15 269 #define MMFI_CMDQ_SIZE 8 270 #define MMFI_CMDQSTS_WRCNT_MASK 0x000F 271 #define MMFI_CMDQSTS_FIFO_FULL 0x0040 272 #define MMFI_CMDQSTS_FIFO_EMPTY 0x0080 273 #define MMFI_CMDQSTS_FIFO_WRLEVEL_MASK 0x0300 274 #define MMFI_CMDQSTS_FIFO_WRLEVEL_SHIFT 8 275 276 REG16_MM FileIn_Timer; // 0x16 277 #define MMFI_FILEIN_TIMER_MASK 0x00FF 278 #define MMFI_FILEIN_TIMER_SHIFT 0 279 280 REG32_MM TsHeader; // 0x17~0x18 281 #define MMFI_HD_CCNT_MASK 0x0000000F 282 #define MMFI_HD_AF_MASK 0x00000030 283 #define MMFI_HD_AF_SHIFT 4 284 #define MMFI_HD_SCRAMBLE_MASK 0x000000C0 285 #define MMFI_HD_SCRAMBLE_SHIFT 6 286 #define MMFI_HD_PID 0x001FFF00 287 #define MMFI_HD_PID_SHIFT 8 288 #define MMFI_HD_TS_PRIORITY_MASK 0x00200000 289 #define MMFI_HD_TS_PRIORITY_SHIFT 21 290 #define MMFI_HD_PAYLOAD_START_FLG_MASK 0x00400000 291 #define MMFI_HD_PAYLOAD_START_FLG_SHIFT 22 292 #define MMFI_HD_ERR_FLG_MASK 0x00800000 293 #define MMFI_HD_ERR_FLG_SHIFT 23 294 295 REG32_MM LPcr2_Buf; // 0x19~0x1A 296 297 REG32_MM TimeStamp_FIn; // 0x1B~0x1C 298 299 REG16_MM PktChkSize; // 0x1D 300 #define MMFI_PKTCHK_SIZE_MASK 0x00FF 301 #define MMFI_SYNC_BYTE_MASK 0xFF00 302 #define MMFI_SYNC_BYTE_SHIFT 8 303 304 REG16_MM MOBFKey; // 0x1E 305 #define MMFI_MOBFKEY_MASK 0x001F 306 307 REG32_MM RAddr; // 0x1F~0x20 308 #define MMFI_TSP2MI_RADDR_MASK 0x0FFFFFFF 309 310 REG32_MM InitTimeStamp; // 0x21~0x22 311 312 REG16_MM SyncBytePrivilege; // 0x23 313 #define MMFI_SYNC_BYTE_PRIVILEGE_MASK 0x00FF 314 #define MMFI_SYNC_BYTE_PRIVILEGE_SHIFT 0 315 #define MMFI_REPLACE_SYNC_BYTE_PRIVILEGE_MASK 0xFF00 316 #define MMFI_REPLACE_SYNC_BYTE_PRIVILEGE_SHIFT 8 317 318 REG16_MM ChkPrivilegeSyncByteEn; // 0x24 319 320 REG16_MM RVU; // 0x25 321 #define MMFI_RVU_PSI_EN 0x0001 322 #define MMFI_RVU_TEI_EN 0x0002 323 #define MMFI_RVU_ERR_CLR 0x0004 324 #define MMFI_RVU_EN 0x0008 325 #define MMFI_RVU_TIMESTAMP_EN 0x0010 326 #define MMFI_RVU_HD_0000_TO_SECTION 0x0020 327 #define MMFI_RVU_HD_1100_TO_SECTION 0x0040 328 #define MMFI_RVU_HD_10x0_11x0_TO_SECTION 0x0080 329 #define MMFI_RVU_PAYLOAD_128_MODE 0x0100 330 #define MMFI_RVU_SUPPORT_NB 0x0200 331 #define MMFI_RVU_FIND_LOSS_SYNC_BYTE 0x0400 332 #define MMFI_RVU_PKT130_EVER_ERR_FLAG 0x8000 333 334 REG16_MM AtsCfg; // 0x26 (Box NOT use) 335 336 REG16_MM CFG_MM_27_2F[0x30 - 0x27]; // reserved 337 338 } REG_Ctrl_MMFI; 339 340 typedef struct _REG_Ctrl_MMFI1 341 { 342 REG16_MM SWRst; // 0x6E 343 #define MMFI_SWRST_MASK 0x07FF 344 #define MMFI_SW_RSTZ_MMFILEIN_DISABLE 0x0001 // low active 345 #define MMFI_RST_WB_DMA0 0x0002 346 #define MMFI_RST_CMDQ0 0x0004 347 #define MMFI_RST_TSIF0 0x0008 348 #define MMFI_RST_WB0 0x0010 349 #define MMFI_RST_WB_DMA1 0x0020 350 #define MMFI_RST_CMDQ1 0x0040 351 #define MMFI_RST_TSIF1 0x0080 352 #define MMFI_RST_WB1 0x0100 353 #define MMFI_RST_PATH0 0x0200 354 #define MMFI_RST_PATH1 0x0400 355 #define MMFI_RST_ALL 0x07FE 356 #define MMFI_RST_CLK_STAMP 0x2000 357 #define MMFI_RST_LPCR_27M_EN_MMFI0 0x4000 358 #define MMFI_RST_LPCR_27M_EN_MMFI1 0x8000 359 360 REG16_MM HWInt; // 0x6F 361 //------------------------- no use , just for compatibility -------------------------// 362 #define MMFI_HWINT_STS_VD3D_ERR1 0x0000 363 #define MMFI_HWINT_STS_AUAUB_ERR1 0x0000 364 #define MMFI_HWINT_STS_VD3D_ERR0 0x0000 365 #define MMFI_HWINT_STS_AUAUB_ERR0 0x0000 366 //-----------------------------------------------------------------------------------// 367 #define MMFI_HWINT_SRC_MASK 0x00FF 368 #define MMFI_HWINT_SRC_FILEIN_DONE1 0x0004 369 #define MMFI_HWINT_SRC_FILEIN_DONE0 0x0008 370 #define MMFI_HWINT_SRC_ERR_PKTS1 0x0010 371 #define MMFI_HWINT_SRC_ERR_PKTS0 0x0020 372 #define MMFI_HWINT_STS_MASK 0xFF00 373 #define MMFI_HWINT_STS_SHIFT 8 374 #define MMFI_HWINT_STS_FILEIN_DONE1 0x0400 375 #define MMFI_HWINT_STS_FILEIN_DONE0 0x0800 376 #define MMFI_HWINT_STS_ERR_PKTS0 0x1000 377 #define MMFI_HWINT_STS_ERR_PKTS1 0x2000 378 379 } REG_Ctrl_MMFI1; 380 381 #endif // _MMFILEIN_REG_H_ 382