1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 4 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 //VQ define 36 #define VQ_NUM 4 37 #define VQ_PACKET_UNIT_LEN 208 38 39 #define TSP_TSIF0 0x00 40 #define TSP_TSIF1 0x01 41 #define TSP_TSIF2 0x02 42 #define TSP_TSIF3 0x03 43 #define TSP_TSIF4 0x04 // not support 44 #define TSP_TSIF5 0x05 // not support 45 #define TSP_TSIF6 0x06 // not support 46 47 //FQ define 48 #define TSP_FQ_NUM 4 49 50 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 51 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 52 //######################################################################### 53 //#### Software Capability Macro Start 54 //######################################################################### 55 56 #define TSP_CA_RESERVED_FLT_NUM 1 57 #define TSP_RECFLT_NUM 1 58 #define TSP_PIDFLT_REC_NUM (TSP_PIDFLT_NUM - TSP_PCRFLT_NUM) // 0~189 (0 for CA) 59 // 193 for Err 60 // 192 for REC 61 // 191 for PCR1 62 // 190 for PCR0 63 64 #if HW_PCRFLT_ENABLE 65 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 66 #else 67 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 68 #endif 69 70 //######################################################################### 71 //#### Software Capability Macro End 72 //######################################################################### 73 74 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 75 #define TSP_CAFLT_START_ID 0 76 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) // 1 77 78 // section FLT ID 79 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID // 1 80 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID // 1 81 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 82 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 83 84 // PID 85 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID // 1 86 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 87 88 // PCR 89 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID // 192 90 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 91 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) // 196 92 93 // REC 94 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID // 196 95 96 //-------------------------------------------------------------------------------------------------- 97 // Driver Compiler Option 98 //-------------------------------------------------------------------------------------------------- 99 100 101 //-------------------------------------------------------------------------------------------------- 102 // PVR Hardware Abstraction Layer 103 //-------------------------------------------------------------------------------------------------- 104 105 // HW characteristic 106 107 typedef enum _PVRENG_SEQ 108 { 109 E_TSP_PVR_PVRENG_START = 0, 110 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 111 E_TSP_PVR_PVRENG_1, 112 E_TSP_PVR_PVRENG_2, 113 E_TSP_PVR_PVRENG_3, 114 E_TSP_PVR_PVRENG_END, 115 E_TSP_PVR_ENG_INVALID, 116 } PVRENG_SEQ; 117 118 typedef enum _FILEENG_SEQ 119 { 120 E_FILEENG_TSIF0 = TSP_TSIF0, 121 E_FILEENG_TSIF1 = TSP_TSIF1, 122 E_FILEENG_TSIF2 = TSP_TSIF2, 123 E_FILEENG_TSIF3 = TSP_TSIF3, 124 E_FILEENG_INVALID, 125 126 } FILEENG_SEQ; 127 128 #if 1 // Destination type 129 typedef enum _TSP_DST_SEQ 130 { 131 E_TSP_DST_FIFO_VIDEO, 132 E_TSP_DST_FIFO_VIDEO3D, 133 E_TSP_DST_FIFO_VIDEO3, //Not support 134 E_TSP_DST_FIFO_VIDEO4, //Not support 135 E_TSP_DST_FIFO_VIDEO5, //Not support 136 E_TSP_DST_FIFO_VIDEO6, //Not support 137 E_TSP_DST_FIFO_VIDEO7, //Not support 138 E_TSP_DST_FIFO_VIDEO8, //Not support 139 140 E_TSP_DST_FIFO_AUDIO, 141 E_TSP_DST_FIFO_AUDIO2, 142 E_TSP_DST_FIFO_AUDIO3, 143 E_TSP_DST_FIFO_AUDIO4, 144 E_TSP_DST_FIFO_AUDIO5, //Not support 145 E_TSP_DST_FIFO_AUDIO6, //Not support 146 147 E_TSP_DST_INVALID, 148 } TSP_DST_SEQ; 149 #else 150 #define TSP_FltType MS_U32 151 /// TS stream fifo type (Exclusive usage) 152 #define E_TSP_FLT_FIFO_MASK 0x000000FF 153 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 154 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 155 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 156 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 157 #endif 158 159 typedef enum _TSP_SRC_SEQ{ 160 E_TSP_SRC_PKTDMX0, 161 E_TSP_SRC_PKTDMX1, 162 E_TSP_SRC_PKTDMX2, 163 E_TSP_SRC_PKTDMX3, 164 E_TSP_SRC_PKTDMX4, //not used 165 E_TSP_SRC_PKTDMX5, //not used 166 E_TSP_SRC_MMFI0, 167 E_TSP_SRC_MMFI1, 168 169 E_TSP_SRC_INVALID, 170 } TSP_SRC_SEQ; 171 172 typedef enum _TSIF_CFG 173 { 174 // @NOTE should be Exclusive usage 175 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 176 E_TSP_TSIF_CFG_EN = 0x0001, 177 E_TSP_TSIF_CFG_PARA = 0x0002, 178 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 179 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 180 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 181 E_TSP_TSIF_CFG_3WIRE = 0x0010 182 } TSP_TSIF_CFG; 183 184 // for stream input source 185 typedef enum _HAL_TS_PAD 186 { 187 E_TSP_TS_PAD_EXT0, 188 E_TSP_TS_PAD_EXT1, 189 E_TSP_TS_PAD_EXT2, 190 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 191 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 192 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 193 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 194 E_TSP_TS_PAD_EXT7, // not support 195 E_TSP_TS_PAD_INTER0, 196 E_TSP_TS_PAD_INTER1, 197 E_TSP_TS_PAD_TSOUT0, 198 E_TSP_TS_PAD_TSOUT1, // not support 199 E_TSP_TS_PAD_TSIOOUT0, 200 E_TSP_TS_PAD_INVALID, 201 } TSP_TS_PAD; 202 203 // for ts pad mode 204 typedef enum _HAL_TS_PAD_MUX_MODE 205 { 206 E_TSP_TS_PAD_MUX_PARALLEL, // in 207 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 208 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 209 E_TSP_TS_PAD_MUX_TSO, // out 210 E_TSP_TS_PAD_MUX_S2P, // out 211 E_TSP_TS_PAD_MUX_S2P1, // out 212 E_TSP_TS_PAD_MUX_DEMOD, // out 213 214 E_TSP_TS_PAD_MUX_INVALID 215 } TSP_TS_PAD_MUX_MODE; 216 217 218 // for pkt converter mode 219 typedef enum _HAL_TS_PKT_CONVERTER_MODE 220 { 221 E_TSP_PKT_CONVERTER_188Mode = 0, 222 E_TSP_PKT_CONVERTER_CIMode = 1, 223 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 224 E_TSP_PKT_CONVERTER_ATSMode = 3, 225 E_TSP_PKT_CONVERTER_MxLMode = 4, 226 E_TSP_PKT_CONVERTER_NagraDongleMode = 5, 227 E_TSP_PKT_CONVERTER_Invalid, 228 } TSP_TS_PKT_CONVERTER_MODE; 229 230 typedef enum _HAL_TS_MXL_PKT_MODE 231 { 232 E_TSP_TS_MXL_PKT_192 = 4, 233 E_TSP_TS_MXL_PKT_196 = 8, 234 E_TSP_TS_MXL_PKT_200 = 12, 235 E_TSP_TS_MXL_PKT_INVALID, 236 } TSP_TS_MXL_PKT_MODE; 237 238 typedef enum _HAL_TSP_CLK_TYPE 239 { 240 E_TSP_HAL_TSP_CLK, 241 E_TSP_HAL_STC_CLK, 242 E_TSP_HAL_INVALID 243 } EN_TSP_HAL_CLK_TYPE; 244 245 typedef struct _HAL_TSP_CLK_STATUS 246 { 247 MS_BOOL bEnable; 248 MS_BOOL bInvert; 249 MS_U8 u8ClkSrc; 250 } ST_TSP_HAL_CLK_STATUS; 251 252 typedef enum _PCR_SRC 253 { 254 /* register setting for kaiser pcr 255 0: tsif0 256 1: tsif1 257 2: tsif2 258 3: tsif3 259 4: tsif4 260 5: tsif5 261 6: un-used 262 7: un-used 263 8: pkt merge 0 264 9: pkt merge 1 265 a: MM file in 1 266 b: MM file in 2 267 */ 268 E_TSP_PCR_SRC_TSIF0 = 0, 269 E_TSP_PCR_SRC_TSIF1, 270 E_TSP_PCR_SRC_TSIF2, 271 E_TSP_PCR_SRC_TSIF3, 272 E_TSP_PCR_SRC_TSIF4, 273 E_TSP_PCR_SRC_TSIF5, 274 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 275 E_TSP_PCR_SRC_PKT_MERGE1, 276 E_TSP_PCR_SRC_MMFI0, 277 E_TSP_PCR_SRC_MMFI1, 278 E_TSP_PCR_SRC_INVALID, 279 } TSP_PCR_SRC; 280 281 typedef enum _HAL_TSP_TSIF // for HW TSIF 282 { 283 E_TSP_HAL_TSIF_0 , 284 E_TSP_HAL_TSIF_1 , 285 E_TSP_HAL_TSIF_2 , 286 E_TSP_HAL_TSIF_3 , 287 E_TSP_HAL_TSIF_4 , // not support 288 E_TSP_HAL_TSIF_5 , // not support 289 E_TSP_HAL_TSIF_6 , // not support 290 291 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 292 E_TSP_HAL_TSIF_PVR0 , 293 E_TSP_HAL_TSIF_PVR1 , 294 E_TSP_HAL_TSIF_PVR2 , 295 E_TSP_HAL_TSIF_PVR3 , 296 E_TSP_HAL_TSIF_INVALID , 297 } TSP_HAL_TSIF; 298 299 300 typedef enum _TSP_HAL_FileState 301 { 302 /// Command Queue is Idle 303 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 304 /// Command Queue is Busy 305 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 306 /// Command Queue is Paused. 307 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 308 309 E_TSP_HAL_FILE_STATE_INVALID, 310 }TSP_HAL_FileState; 311 312 typedef enum 313 { 314 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 315 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 316 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 317 318 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 319 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 320 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 321 322 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 323 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 324 325 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 326 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 327 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 328 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 329 330 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 331 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 332 333 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 334 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 335 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 336 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 337 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 338 339 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 340 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 341 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 342 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 343 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 344 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 345 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 346 347 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 348 349 //27 is reserved, and can not be used 350 351 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 352 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 353 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 354 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 355 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 356 357 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 358 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 359 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 360 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 361 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 362 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 363 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 364 E_TSP_HAL_CAP_FIQ_NUM = 40, 365 E_TSP_HAL_CAP_TYPE_NULL, 366 } TSP_HAL_CAP_TYPE; 367 368 // @F_TODO remove unused enum member 369 typedef enum 370 { 371 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PCRFLT_END_ID - TSP_PIDFLT_START_ID), 372 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 373 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 374 375 E_TSP_HAL_CAP_VAL_RECENG_NUM = 4, 376 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 377 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 378 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 379 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 380 381 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 382 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 383 384 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 385 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 4, //internal demod // [ToDo] STC number... by MM problem Jason-YH.Sun 386 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 387 E_TSP_HAL_CAP_VAL_VQ_NUM = 4, 388 389 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 390 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 391 392 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 393 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 394 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 395 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 396 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 397 398 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 399 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 400 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 401 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 402 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 403 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 404 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 405 406 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 407 408 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 4, 409 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 4, 410 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 411 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 412 413 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 414 415 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 416 } TSP_HAL_CAP_VAL; 417 418 /// TSP TEI Remove Error Packet Infomation 419 typedef enum 420 { 421 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 422 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 423 424 }TSP_HAL_TEI_RmPktType; 425 426 // TSP TimeStamp Clk Select 427 typedef enum 428 { 429 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 430 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 431 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 432 433 } TSP_HAL_TimeStamp_Clk; 434 435 /// TSP Packet Converter Input Mode 436 typedef enum 437 { 438 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 439 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 440 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 441 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 442 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 443 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 444 E_TSP_HAL_PKT_MODE_MXL_200, ///< MXL mode (200 bytes) 445 E_TSP_HAL_PKT_MODE_ND, ///< Nagra Dongle mode (192 bytes) 446 447 E_TSP_HAL_PKT_MODE_INVALID 448 }TSP_HAL_PKT_MODE; 449 450 //---------------------------------- 451 /// DMX debug table information structure 452 //---------------------------------- 453 454 typedef enum 455 { 456 E_TSP_HAL_FLOW_LIVE0, 457 E_TSP_HAL_FLOW_LIVE1, 458 E_TSP_HAL_FLOW_LIVE2, 459 E_TSP_HAL_FLOW_LIVE3, 460 E_TSP_HAL_FLOW_LIVE4, // not support 461 E_TSP_HAL_FLOW_LIVE5, // not support 462 E_TSP_HAL_FLOW_LIVE6, // not support 463 464 E_TSP_HAL_FLOW_FILE0, 465 E_TSP_HAL_FLOW_FILE1, 466 E_TSP_HAL_FLOW_FILE2, 467 E_TSP_HAL_FLOW_FILE3, 468 E_TSP_HAL_FLOW_FILE4, // not support 469 E_TSP_HAL_FLOW_FILE5, // not support 470 E_TSP_HAL_FLOW_FILE6, // not support 471 472 E_TSP_HAL_FLOW_MMFI0, 473 E_TSP_HAL_FLOW_MMFI1, 474 475 E_TSP_HAL_FLOW_INVALID, 476 477 } TSP_HAL_FLOW; 478 479 typedef enum 480 { 481 E_TSP_HAL_GATING_PATH0 = 0, 482 E_TSP_HAL_GATING_PATH1, 483 E_TSP_HAL_GATING_PATH2, 484 E_TSP_HAL_GATING_PATH3, 485 E_TSP_HAL_GATING_PATH4, 486 E_TSP_HAL_GATING_PATH5, 487 E_TSP_HAL_GATING_TSP_ENG, 488 E_TSP_HAL_GATING_FIQ, 489 E_TSP_HAL_GATING_PVR1, 490 E_TSP_HAL_GATING_PVR2, 491 E_TSP_HAL_GATING_PVR3, 492 E_TSP_HAL_GATING_PVR4, 493 494 E_TSP_HAL_MIU_CLK_GATING_PATH0 = 17, 495 E_TSP_HAL_MIU_CLK_GATING_PATH1, 496 E_TSP_HAL_MIU_CLK_GATING_PATH2, 497 E_TSP_HAL_MIU_CLK_GATING_PATH3, 498 E_TSP_HAL_MIU_CLK_GATING_PATH4, 499 E_TSP_HAL_MIU_CLK_GATING_PATH5, 500 E_TSP_HAL_MIU_CLK_GATING_TSP_ENG, 501 E_TSP_HAL_MIU_CLK_GATING_FIQ, 502 E_TSP_HAL_MIU_CLK_GATING_PVR1, 503 E_TSP_HAL_MIU_CLK_GATING_PVR2, 504 E_TSP_HAL_MIU_CLK_GATING_PVR3, 505 E_TSP_HAL_MIU_CLK_GATING_PVR4, 506 E_TSP_HAL_MIU_CLK_GATING_MMFI0, 507 E_TSP_HAL_MIU_CLK_GATING_MMFI1, 508 509 E_TSP_HAL_GATING_FIQ0 = 31, 510 E_TSP_HAL_GATING_FIQ1, 511 E_TSP_HAL_GATING_FIQ2, 512 E_TSP_HAL_GATING_FIQ3, 513 E_TSP_HAL_GATING_FIQ4, 514 E_TSP_HAL_GATING_FIQ5, 515 516 E_TSP_HAL_MIU_CLK_GATING_FIQ0, 517 E_TSP_HAL_MIU_CLK_GATING_FIQ1, 518 E_TSP_HAL_MIU_CLK_GATING_FIQ2, 519 E_TSP_HAL_MIU_CLK_GATING_FIQ3, 520 E_TSP_HAL_MIU_CLK_GATING_FIQ4, 521 E_TSP_HAL_MIU_CLK_GATING_FIQ5, 522 523 E_TSP_HAL_GATING_INVALID, 524 525 } TSP_HAL_GATING; 526 527 typedef enum 528 { 529 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0 = 0, 530 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER1, 531 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER2, 532 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER3, 533 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER4, 534 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER5, 535 536 E_TSP_HAL_RESET_CTRL_FIQ0 = 8, 537 E_TSP_HAL_RESET_CTRL_FIQ1, 538 E_TSP_HAL_RESET_CTRL_FIQ2, 539 E_TSP_HAL_RESET_CTRL_FIQ3, 540 E_TSP_HAL_RESET_CTRL_FIQ4, 541 E_TSP_HAL_RESET_CTRL_FIQ5, 542 543 E_TSP_HAL_RESET_CTRL_VQ_TX0 = 16, 544 E_TSP_HAL_RESET_CTRL_VQ_TX1, 545 E_TSP_HAL_RESET_CTRL_VQ_TX2, 546 E_TSP_HAL_RESET_CTRL_VQ_TX3, 547 E_TSP_HAL_RESET_CTRL_VQ_TX4, 548 E_TSP_HAL_RESET_CTRL_VQ_TX5, 549 E_TSP_HAL_RESET_CTRL_VQ_RX, 550 E_TSP_HAL_RESET_CTRL_VQ_TOP, 551 E_TSP_HAL_RESET_CTRL_PKT_DEMUX0, 552 E_TSP_HAL_RESET_CTRL_PKT_DEMUX1, 553 E_TSP_HAL_RESET_CTRL_PKT_DEMUX2, 554 E_TSP_HAL_RESET_CTRL_PKT_DEMUX3, 555 E_TSP_HAL_RESET_CTRL_PKT_DEMUX4, 556 E_TSP_HAL_RESET_CTRL_PKT_DEMUX5, 557 558 E_TSP_HAL_RESET_CTRL_PVR1 = 32, 559 E_TSP_HAL_RESET_CTRL_PVR2, 560 E_TSP_HAL_RESET_CTRL_PVR3, 561 E_TSP_HAL_RESET_CTRL_PVR4, 562 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1, 563 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR2, 564 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR3, 565 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR4, 566 E_TSP_HAL_RESET_CTRL_SP_D0, 567 E_TSP_HAL_RESET_CTRL_SP_D1, 568 E_TSP_HAL_RESET_CTRL_SP_D2, 569 E_TSP_HAL_RESET_CTRL_SP_D3, 570 E_TSP_HAL_RESET_CTRL_SP_D4, 571 E_TSP_HAL_RESET_CTRL_SP_D5, 572 573 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0 = 48, 574 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT1, 575 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT2, 576 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT3, 577 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT4, 578 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT5, 579 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0, 580 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_1, 581 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_2, 582 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_3, 583 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_4, 584 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_5, 585 586 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0 = 64, 587 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER1, 588 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER2, 589 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER3, 590 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER4, 591 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER5, 592 E_TSP_HAL_RESET_CTRL_PCRFLT_0, 593 E_TSP_HAL_RESET_CTRL_PCRFLT_1, 594 E_TSP_HAL_RESET_CTRL_PCRFLT_2, 595 E_TSP_HAL_RESET_CTRL_PCRFLT_3, 596 E_TSP_HAL_RESET_CTRL_PCRFLT_4, 597 E_TSP_HAL_RESET_CTRL_PCRFLT_5, 598 599 E_TSP_HAL_RESET_PATH0 = 80, 600 E_TSP_HAL_RESET_PATH1, 601 E_TSP_HAL_RESET_PATH2, 602 E_TSP_HAL_RESET_PATH3, 603 E_TSP_HAL_RESET_PATH4, 604 E_TSP_HAL_RESET_PATH5, 605 E_TSP_HAL_RESET_OTV, 606 E_TSP_HAL_RESET_DEBUG_TABLE, 607 E_TSP_HAL_RESET_DMA_ENG, 608 E_TSP_HAL_RESET_SEC_CMP, 609 E_TSP_HAL_RESET_SECFLT_REG, 610 E_TSP_HAL_RESET_SEC, 611 E_TSP_HAL_RESET_PID_TABLE, 612 613 E_TSP_HAL_RESET_CTRL_INVALID, 614 615 } TSP_HAL_RESET_CTRL; 616 617 typedef enum 618 { 619 E_TSP_HAL_MIU_SEL_MMFI = 0, 620 E_TSP_HAL_MIU_SEL_FQ = 1, 621 622 E_TSP_HAL_MIU_SEL_INVALID, 623 624 } TSP_HAL_MIU_SEL_TYPE; 625 626 //-------------------------------------------------------------------------------------------------- 627 // PVR HAL API 628 //-------------------------------------------------------------------------------------------------- 629 // Static Register Mapping for external access 630 #define REG_PIDFLT_BASE0 (0x00240000UL) 631 #define REG_PIDFLT_BASE1 (0x00241000UL) 632 #define REG_SECFLT_BASE (0x00221000UL) 633 #define REG_SECBUF_BASE (0x00221024UL) 634 #define REG_CTRL_BASE (0x00210200UL) 635 636 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 637 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 638 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 639 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 640 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 641 642 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 643 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 644 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 645 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 646 647 //#define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 648 649 //#define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 650 651 652 653 //******************** PIDFLT DEFINE START ********************// 654 // PID 655 #define TSP_PIDFLT_PID_MASK 0x00001FFF 656 #define TSP_PIDFLT_PID_SHFT 0 657 658 // Continuous counter 659 #define TSP_PIDFLT_CC_MASK 0xFF000000 660 #define TSP_PIDFLT_CC_SHFT 24 661 662 // PIDFLT SRC 663 typedef enum _TSP_PIDFLT_SRC 664 { 665 E_TSP_PIDFLT_LIVE0, 666 E_TSP_PIDFLT_LIVE1, 667 E_TSP_PIDFLT_LIVE2, 668 E_TSP_PIDFLT_LIVE3, 669 E_TSP_PIDFLT_LIVE4, // not support 670 E_TSP_PIDFLT_LIVE5, // not support 671 E_TSP_PIDFLT_LIVE6, // not support 672 E_TSP_PIDFLT_FILE0, 673 E_TSP_PIDFLT_FILE1, 674 E_TSP_PIDFLT_FILE2, 675 E_TSP_PIDFLT_FILE3, 676 E_TSP_PIDFLT_FILE4, // not support 677 E_TSP_PIDFLT_FILE5, // not support 678 E_TSP_PIDFLT_FILE6, // not support 679 E_TSP_PIDFLT_INVALID, 680 } TSP_PIDFLT_SRC; 681 682 #define TSP_PIDFLT_IN_MASK 0x0000E000 683 #define TSP_PIDFLT_TSIF_SHFT 13 684 #define TSP_PIDFLT_TSIF0 0x00 685 #define TSP_PIDFLT_TSIF1 0x01 686 #define TSP_PIDFLT_TSIF2 0x02 687 #define TSP_PIDFLT_TSIF3 0x03 688 #define TSP_PIDFLT_TSIF_MAX 0x04 689 690 // Section filter Id (0~63) 691 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 692 #define TSP_PIDFLT_SECFLT_SHFT 0 693 694 // PIDFLT DST 695 typedef enum _TSP_PIDFLT_DST 696 { 697 E_TSP_PIDFLT_DST_VIDEO, 698 E_TSP_PIDFLT_DST_AUDIO, 699 E_TSP_PIDFLT_DST_PVR, 700 701 E_TSP_PIDFLT_DST_INVALID, 702 } TSP_PIDFLT_DST; 703 704 // AF/Sec/Video/V3D/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 705 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 706 #define TSP_PIDFLT_OUT_MASK 0x00DFFF00 707 #define TSP_PIDFLT_OUT_SHFT 8 708 #define TSP_PIDFLT_OUT_NONE 0x00000000 709 #define TSP_PIDFLT_OUT_SECAF 0x00000100 710 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 711 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 712 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 713 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 714 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 715 #define TSP_PIDFLT_OUT_VFIFO3 0x00004000 716 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 717 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 718 #define TSP_PIDFLT_OUT_VFIFO4 0x00800000 719 720 721 // SRC ID 722 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 723 #define TSP_PIDFLT_SRCID_SHIFT 28 724 725 726 727 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 728 #define TSP_PIDFLT_PVRFLT_SHFT 15 729 //enable LUT 730 #define TSP_PIDFLT_OUT_LUT 0x00400000 731 732 #define TSP_PIDFLT_OUT_PVR1 0x00008000 733 #define TSP_PIDFLT_OUT_PVR2 0x00010000 734 #define TSP_PIDFLT_OUT_PVR3 0x00020000 735 #define TSP_PIDFLT_OUT_PVR4 0x00040000 736 737 738 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 739 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 740 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 741 742 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 743 #define TSP_PIDFLT_TSOFLT_SHFT 22 744 #define TSP_PID_FLT_OUT_TSO0 0x00400000 745 746 //******************** PIDFLT DEFINE END ********************// 747 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 748 MS_U32 TSP32_IdrR(TSP32 *preg); 749 750 //=========================TSIF================================ 751 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 752 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 753 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 754 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 755 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 756 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 757 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 758 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 759 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 760 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 761 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 762 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 763 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 764 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 765 766 //=========================TSP================================ 767 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 768 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 769 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 770 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 771 void HAL_TSP_Reset(MS_BOOL bEn); 772 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 773 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 774 void HAL_TSP_Power(MS_BOOL bEn); 775 void HAL_TSP_CPU(MS_BOOL bEn); 776 void HAL_TSP_ResetCPU(MS_BOOL bReset); 777 void HAL_TSP_HwPatch(void); 778 void HAL_TSP_RestoreFltState(void); 779 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 780 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 781 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 782 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 783 void HAL_TSP_SaveFltState(void); 784 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 785 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 786 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 787 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 788 789 //=========================TSO================================ 790 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 791 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 792 793 //=========================Filein================================ 794 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 795 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 796 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 797 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 798 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 799 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 800 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 801 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 802 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 803 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 804 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 805 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 806 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 807 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 808 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 809 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 810 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 811 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass);// for PS mode A/V fifo pull back 812 813 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 814 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 815 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 816 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 817 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 818 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 819 /* 820 // Only used by [HW test code] 821 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 822 */ 823 824 //=========================PCR FLT================================ 825 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 826 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 827 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 828 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 829 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 830 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 831 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 832 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 833 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId); 834 835 //=========================STC================================ 836 void HAL_TSP_STC_Init(void); 837 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 838 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 839 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 840 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 841 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 842 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 843 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 844 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 845 846 //=========================FIFO================================ 847 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 848 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 849 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 850 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 851 void HAL_TSP_FIFO_ClearAll (void); 852 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 853 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 854 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 855 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 856 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 857 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 858 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 859 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 860 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 861 862 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 863 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 864 void HAL_TSP_PS_SRC(MS_U32 tsIf); 865 void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 866 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 867 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 868 void HAL_TSP_FIFO_ReadEn(MS_BOOL bEn); // 869 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 870 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 871 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 872 873 //=========================VQ================================ 874 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 875 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 876 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 877 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 878 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 879 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 880 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 881 882 //=========================Pid Flt================================ 883 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 884 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 885 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 886 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 887 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 888 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 889 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 890 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 891 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 892 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 893 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 894 895 //=========================SecFlt================================ 896 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 897 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 898 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 899 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 900 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 901 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 902 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 903 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 904 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 905 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 906 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 907 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 908 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 909 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 910 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 911 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 912 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 913 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 914 915 //=========================Sec Buf================================ 916 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 917 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 918 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 919 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 920 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 921 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 922 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 923 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 924 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 925 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 926 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart); 927 928 //=========================PVR================================ 929 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 930 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 931 void HAL_PVR_Exit(MS_U32 u32PVREng); 932 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 933 /* 934 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 935 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 936 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 937 */ 938 void HAL_PVR_FlushData(MS_U32 u32PVREng); 939 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 940 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 941 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 942 void HAL_PVR_Start(MS_U32 u32PVREng); 943 void HAL_PVR_Stop(MS_U32 u32PVREng); 944 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 945 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 946 void HAL_PVR_RecNull(MS_BOOL bSet); 947 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 948 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 949 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 950 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 951 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 952 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 953 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 954 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 955 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 956 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 957 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 958 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 959 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 960 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 961 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 962 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 963 /* 964 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 965 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 966 */ 967 968 //=========================FQ================================ 969 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 970 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 971 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 972 973 //=========================HCMD================================ 974 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 975 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 976 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 977 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 978 MS_BOOL HAL_TSP_HCMD_Alive(void); 979 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 980 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 981 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 982 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 983 984 //=========================INT================================ 985 void HAL_TSP_INT_Enable(MS_U32 u32Mask); 986 void HAL_TSP_INT_Disable(MS_U32 u32Mask); 987 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask); 988 MS_U32 HAL_TSP_INT_GetHW(void); 989 void HAL_TSP_INT_ClrSW(void); 990 MS_U32 HAL_TSP_INT_GetSW(void); 991 992 //=========================Mapping================================ 993 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 994 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 995 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 996 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 997 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 998 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 999 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 1000 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng); 1001 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 1002 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 1003 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 1004 1005 //========================DSCMB Functions=================================== 1006 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 1007 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 1008 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 1009 1010 //========================MOBF Functions===================================== 1011 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 1012 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 1013 1014 //========================Protection range=================================== 1015 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 1016 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 1017 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 1018 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 1019 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 1020 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 1021 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 1022 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 1023 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 1024 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 1025 1026 //========================Debug table============================= 1027 void HAL_TSP_FltNullPkt_En(MS_BOOL bEn); 1028 1029 // @TODO Renaming Load and Get 1030 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 1031 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 1032 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock); 1033 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 1034 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 1035 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 1036 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 1037 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 1038 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 1039 1040 // @TODO Implement Drop and Dis Hal 1041 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 1042 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 1043 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 1044 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 1045 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 1046 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 1047 1048 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 1049 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 1050 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 1051 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 1052 1053 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 1054 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 1055 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 1056 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 1057 1058 //========================MergeStream Functions============================= 1059 void HAL_TSP_PktConverter_Init(void); 1060 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 1061 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 1062 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 1063 1064 /* 1065 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 1066 */ 1067 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 1068 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable); 1069 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 1070 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 1071 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path); 1072 1073 //==========================TSIO ============================================ 1074 void HAL_TSP_Privilege_Enable(MS_BOOL bEnable); 1075 1076 void HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath, MS_U32 u32Idx, MS_BOOL bEn); 1077 void HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath, MS_U32 u32eng, MS_BOOL bEn); 1078 1079 #endif // #ifndef __HAL_PVR_H__ 1080