1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halPVR.c
20 // @brief PVR HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "halCHIP.h"
25 #include "regTSP.h"
26 #include "halTSP.h"
27 #include "drvSYS.h"
28
29 #ifdef CONFIG_MSTAR_CLKM
30 #include "drvCLKM.h"
31 #endif
32
33 #define TSP_MIU_SEL_BITS_LEN 2
34
35 //--------------------------------------------------------------------------------------------------
36 // Driver Compiler Option
37 //--------------------------------------------------------------------------------------------------
38
39
40 //--------------------------------------------------------------------------------------------------
41 // TSP Hardware Abstraction Layer
42 //--------------------------------------------------------------------------------------------------
43 MS_VIRT _u32RegBase = 0;
44
45 static REG_Ctrl* _RegCtrl = NULL; // TSP0 and TSP1
46 static REG_Ctrl2* _RegCtrl2 = NULL; // TSP3
47 static REG_Ctrl3* _RegCtrl3 = NULL; // TSP4
48 static REG_Ctrl4* _RegCtrl4 = NULL; // TSP6
49 static REG_Ctrl5* _RegCtrl5 = NULL; // TSP7
50 static REG_Ctrl6* _RegCtrl6 = NULL; // TSP8
51 static REG_Ctrl7* _RegCtrl7 = NULL; // TSP9
52 static REG_Ctrl8* _RegCtrl8 = NULL; // TSP10
53 static REG_Ctrl8_1* _RegCtrl8_1 = NULL; // TSP10
54
55
56
57
58 // @F_TODO These parameters need to be combined with global variables in Utopia 2.0
59 static MS_U32 _u32PidFltReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
60 static MS_U32 _u32PidDstReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
61 static MS_U32 _u32SecReg[(TSP_SECFLT_NUM * ((sizeof(REG_SecFlt) - sizeof(((REG_SecFlt*)0)->_x50))/sizeof(TSP32)))];
62
63
64 //-------------------------------------------------------------------------------------------------
65 // Local Functions
66 //-------------------------------------------------------------------------------------------------
67 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value);
68
_delay(MS_U32 usec)69 static void _delay(MS_U32 usec)
70 {
71 MsOS_DelayTaskUs_Poll(usec);
72 }
73
REG32_R(REG32 * reg)74 static MS_U32 REG32_R(REG32 *reg)
75 {
76 MS_U32 value = 0;
77 value = (reg)->low;
78 value |= (reg)->high << 16;
79 return value;
80 }
81
82
REG16_R(REG16 * reg)83 static MS_U16 REG16_R(REG16 *reg)
84 {
85 MS_U16 value = 0;
86 value = (reg)->data;
87 return value;
88 }
89
90 static MS_BOOL _u32RegDump = 0;
91 static void _REG32_DUMP(REG32 * reg, MS_U32 value );
92 static void _REG16_DUMP(REG16 * reg, MS_U16 value);
93
94 #if 0
95 #define REG32_W(reg, value); { (reg)->low = ((value) & 0x0000FFFF); \
96 (reg)->high = ((value) >> 16);\
97 if(_u32RegDump)\
98 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n", (((MS_U32)(&(reg)->low) - _u32RegBase)>>(1+8)), ((((MS_U32)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1,(value) & 0x0000FFFF);\
99 printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)(&(reg)->high) - _u32RegBase)>>(1+8)),((((MS_U32)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1, (value) >> 16);}}
100
101 #define REG16_W(reg, value); {(reg)->data = ((value) & 0x0000FFFF);\
102 if(_u32RegDump)\
103 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)reg) - _u32RegBase)>>(1+8), ((((MS_U32)reg - _u32RegBase)>>1)&0xFF)>>1, (value) & 0x0000FFFF);}}
104 #endif
105 #define REG32_W(reg, value) { (reg)->low = ((value) & 0x0000FFFF); \
106 (reg)->high = ((value) >> 16);\
107 if(_u32RegDump){_REG32_DUMP(reg, value);}}
108
109 #define REG16_W(reg, value) {(reg)->data = ((value) & 0x0000FFFF);\
110 if(_u32RegDump){_REG16_DUMP(reg, value);}}
111
112
113 #define _AND_(flag, bit) ((flag) & (bit) )
114
115 #define _SET_(flag, bit) ((flag) | (bit) )
116 #define _CLR_(flag, bit) ((flag) & (~(bit)))
117
118 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value))
119 #define REG32_SET(reg, value) REG32_W(reg, _SET_(REG32_R(reg), value))
120 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value))
121 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value))
122
123 #define REG16_MSK_W(reg, mask, value) REG16_W((reg), _CLR_(REG16_R(reg), (mask)) | _AND_((value), (mask)))
124 #define REG32_MSK_W(reg, mask, value) REG32_W((reg), _CLR_(REG32_R(reg), (mask)) | _AND_((value), (mask)))
125
126 #define MIU_BUS (4)
127
128
129 //-------------------------------------------------------------------------------------------------
130 // Debug Message
131 //-------------------------------------------------------------------------------------------------
132 typedef enum
133 {
134 E_HAL_TSP_DBG_LEVEL_NONE, // no debug message shown
135 E_HAL_TSP_DBG_LEVEL_ERR, // only shows error message that can't be recover
136 E_HAL_TSP_DBG_LEVEL_WARN, // error case can be recover, like retry
137 E_HAL_TSP_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
138 E_HAL_TSP_DBG_LEVEL_INFO, // information for internal parameter
139 E_HAL_TSP_DBG_LEVEL_FUNC, // Function trace and input parameter trace
140 E_HAL_TSP_DBG_LEVEL_TRACE, // debug trace
141 } EN_HAL_TSP_DBGMSG_LEVEL;
142
143 typedef enum
144 {
145 E_HAL_TSP_DBG_MODEL_NONE, // @temporarily , need to refine
146 E_HAL_TSP_DBG_MODEL_ALL,
147 } EN_HAL_TSP_DBGMSG_MODEL;
148
149 #define HAL_TSP_DBGMSG(_level,_model,_f) do {if(_u32TSPDbgLevel >= (_level)&&((_u32TSPDbgModel&_model)!=0)) (_f);} while(0)
150 static MS_U32 _u32TSPDbgLevel = E_HAL_TSP_DBG_LEVEL_ERR;
151 static MS_U32 _u32TSPDbgModel = E_HAL_TSP_DBG_MODEL_ALL;
152
153
154 //--------------------------------------------------------------------------------------------------
155 // Implementation
156 //--------------------------------------------------------------------------------------------------
TSP32_IdrW(TSP32 * preg,MS_U32 value)157 void TSP32_IdrW(TSP32 *preg, MS_U32 value)
158 {
159 MS_U32 tempDump = _u32RegDump;
160 if(_u32RegDump)
161 {
162 //test_chip_top.write_ind32('h00221004, 32'hffffffff); //indirect .... (address,data)
163 _u32RegDump = 0;
164 printf("test_chip_top.write_ind32(\'h%08lx, 32\'h%08lx);\n", (long unsigned int)preg, (long unsigned int)value);
165 }
166 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
167 REG32_W(&_RegCtrl->Idr_Write, value);
168 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE);
169 _u32RegDump = tempDump;
170 }
171
TSP32_IdrR(TSP32 * preg)172 MS_U32 TSP32_IdrR(TSP32 *preg)
173 {
174 MS_U32 tempDump = _u32RegDump;
175 if(_u32RegDump)
176 {
177 _u32RegDump = 0;
178 }
179 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
180 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ);
181 _u32RegDump = tempDump;
182 return REG32_R(&_RegCtrl->Idr_Read);
183 }
184
HAL_TSP_SetBank(MS_VIRT u32BankAddr)185 void HAL_TSP_SetBank(MS_VIRT u32BankAddr)
186 {
187 _u32RegBase = u32BankAddr;
188 _RegCtrl = (REG_Ctrl*) (u32BankAddr + 0x2A00UL); // TSP0 0x1015, TSP1 0x1016
189 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); // TSP3 0x1702,
190 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); // TSP4 0x1703
191 _RegCtrl4 = (REG_Ctrl4*)(u32BankAddr + 0xC2000UL); // TSP6 0x1610
192 _RegCtrl5 = (REG_Ctrl5*)(u32BankAddr + 0xC2200UL); // TSP7 0x1611
193 _RegCtrl6 = (REG_Ctrl6*)(u32BankAddr + 0xC4E00UL); // TSP8 0x1627
194 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); // TSP9 0x170C
195 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); // TSP10 0x170D
196 _RegCtrl8_1 = (REG_Ctrl8_1*)(u32BankAddr + 0xE1B00UL); // TSP10 0x170D , offset(16-bits): 0x40
197 }
198
HAL_TSP_RegDump(MS_BOOL bEnable)199 void HAL_TSP_RegDump(MS_BOOL bEnable)
200 {
201 _u32RegDump = bEnable;
202 }
203 #if 1
_REG32_DUMP(REG32 * reg,MS_U32 value)204 static void _REG32_DUMP(REG32* reg, MS_U32 value )
205 {
206 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7h06 ....reg ,16h400a ......
207 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7h06 ....reg ,16h400a ......
208 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
209 MS_U32 bank = ((MS_VIRT)(&(reg)->low) - _u32RegBase)>>(1+8);
210 MS_U32 addr_low = ((((MS_VIRT)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1;
211 MS_U32 addr_high = ((((MS_VIRT)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1;
212 MS_U32 val_low = (value) & 0x0000FFFF;
213 MS_U32 val_high = ((value) & 0xFFFF0000 )>>16;
214
215 if(bank == 0x15)
216 {
217 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
218 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
219 }
220 else if(bank == 0x16)
221 {
222 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
223 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
224 }
225 else if(bank == 0x38)
226 {
227 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
228 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
229 }
230 }
_REG16_DUMP(REG16 * reg,MS_U16 value)231 static void _REG16_DUMP(REG16* reg, MS_U16 value )
232 {
233 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7h06 ....reg ,16h400a ......
234 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7h06 ....reg ,16h400a ......
235 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
236 MS_U32 bank = ((MS_VIRT)(&(reg)) - _u32RegBase)>>(1+8);
237 MS_U32 addr = ((((MS_VIRT)(&(reg)) - _u32RegBase)>>1)&0xFF)>>1;
238 MS_U32 val = (value) & 0x0000FFFF;
239
240 if(bank == 0x15)
241 {
242 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
243 }
244 else if(bank == 0x16)
245 {
246 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
247 }
248 else if(bank == 0x38)
249 {
250 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
251 }
252 }
253 #endif
254
HAL_TSP_HwPatch(void)255 void HAL_TSP_HwPatch(void)
256 {
257 //For sram
258 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE);
259 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
260
261 // @F_TODO check these setting with Stephen
262 // TSP_HW_CFG4_WSTAT_CH_EN <--this is bit disable HW sync section buf id with section filter id
263 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WSTAT_CH_EN);
264
265 // Bad initial value of TSP_CTRL1
266 // Suppose Standby mode for TSP should NOT be enabled.
267 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
268 // Disable it by SW at this stage.
269 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);
270
271 //enable PVR record to bypass header
272 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2);
273 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC);
274 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC);
275
276 // load lpcr1 for all pvr engines, HW default value may be wrong
277 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
278 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
279 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
280 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
281
282 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
283
284 //Disable TSP_RM_OVF_GLITCH to fix that section A would occur overflow when section B occured overflow at first.
285 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN*/);
286
287 //Disable all live pathes block mechanism
288 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_VQTX3_BLOCK_DIS*/);
289 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH);
290
291 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode
292
293 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
294
295 //record null packets for record-all case
296 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD | TSP_REC_NULL);
297 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP);
298
299 //Disable pvr1 & pvr2 block mechanism
300 //DisableAV FIFO block mechanism for live path
301 //REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLOCK_DIS|TSP_V_BLOCK_DIS|TSP_A_BLOCK_DIS|TSP_AD_BLOCK_DIS); // by angie
302
303 // Serial mode config
304 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T);
305 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT);
306 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT)
307
308 // Internal Sync Patch
309 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T);
310
311 // Chip after Kirin will lost data when byte timer enable and delay set to 0 setting this bit to fix this issue
312 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN);
313
314 // Fix load fw secure issue (dma_start = 1 , polling dma_done , dma_start = 0)
315 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW);
316
317 // Fix pass_pkt_timestamp will hang issue
318 REG16_SET(&_RegCtrl6->CFG6_60, TSP_INIT_TIMESTAMP_RESTART_EN);
319
320 // Merge stream through FIQ ECO config
321 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_DELAY);
322 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_REVERSE_BLOCK);
323
324 // Fix filter null packet
325 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT);
326
327 // Fixed miu_req & miu_last
328 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_VQ_MIU_REG_FLUSH);
329
330 // Fixed PVR eng write pointer to next addr
331 REG16_SET(&_RegCtrl6->CFG6_2A, PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN);
332 }
333
334 // ------------ initial config ------------
335 // Sync Byte: 0x47 , 0x48 .... , 0x4e
336 // Source id : 0 , 1 , ... , 7
337 // User can use "HAL_TSP_PktConverter_SetSyncByte()" to change Sync Byte configuration
338 // , and use "HAL_TSP_PktConverter_SetSrcId()" to change Source id configuration
HAL_TSP_PktConverter_Init(void)339 void HAL_TSP_PktConverter_Init(void)
340 {
341 MS_U8 u8Path, u8Idx;
342 MS_U8 u8SyncByte, u8SrcId;
343
344 for(u8Path = 0; u8Path < TSP_TSIF_NUM; ++u8Path)
345 {
346 HAL_TSP_PktConverter_ForceSync(u8Path,TRUE); //default: FALSE
347 HAL_TSP_PktConverter_SrcIdFlt(u8Path,TRUE); //default: FALSE
348
349 u8SyncByte = 0x47;
350 u8SrcId = 0;
351
352 for(u8Idx = 0; u8Idx < TSP_MERGESTREAM_NUM; ++u8Idx,++u8SyncByte,++u8SrcId)
353 {
354 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Idx, &u8SyncByte, TRUE);
355 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Idx, &u8SrcId, TRUE);
356 }
357 }
358 }
359
360
HAL_TSP_Reset(MS_BOOL bEn)361 void HAL_TSP_Reset(MS_BOOL bEn)
362 {
363 //MS_U16 reg;
364
365 if (bEn)
366 {
367 #if 0
368
369 // WB DMA source won't be reset by SW_RST bit so we use HWPATCH to make it's source to default
370 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
371 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
372
373 #endif
374 // reset CMDQ for tsif 0~3
375 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
376 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
377 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
378 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
379 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
380 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
381 }
382 else
383 {
384 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
385
386 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
387 // set CMDQ for tsif 0~3
388 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
389 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
390 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
391 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
392 }
393 }
394
395
HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)396 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)
397 {
398 switch(tsIf)
399 {
400 case 0: if(bEn)
401 {
402 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
403 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
404 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
405 }
406 else
407 {
408 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
409 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
410 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
411 }
412 break;
413 case 1: if(bEn)
414 {
415 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
416 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
417 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
418 }
419 else
420 {
421 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
422 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
423 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
424 }
425 break;
426 case 2: if(bEn)
427 {
428 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
429 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
430 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
431 }
432 else
433 {
434 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
435 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
436 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
437 }
438 break;
439 case 3: if(bEn)
440 {
441 REG16_SET(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3);
442 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3);
443 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3);
444 }
445 else
446 {
447 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3);
448 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3);
449 REG16_CLR(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3);
450 }
451 break;
452 default: break;
453 }
454 }
455
HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType,MS_U8 u8Index,ST_TSP_HAL_CLK_STATUS * pstClkStatus)456 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus)
457 {
458 switch(eClkType)
459 {
460 case E_TSP_HAL_TSP_CLK:
461 pstClkStatus->bEnable = !(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_DISABLE);
462 pstClkStatus->bInvert = !!(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_INVERT);
463 pstClkStatus->u8ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_CLK_MASK) >> REG_CLKGEN0_TSP_SRC_SHIFT;
464 break;
465 default:
466 return FALSE;
467 }
468
469 return TRUE;
470 }
471
HAL_TSP_Power(MS_BOOL bEn)472 void HAL_TSP_Power(MS_BOOL bEn)
473 {
474 if(bEn)
475 {
476 #ifdef CONFIG_MSTAR_CLKM
477
478 MS_S32 s32Handle;
479
480 // Enable TSP Clk
481 s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
482 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSP_FAST");
483 // Enable STC1,2 Clk
484 // STC0
485 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc0");
486 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STC0_BUF");
487 // STC1
488 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc1");
489 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STC0_BUF");
490 // Stamp
491 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
492 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STAMP_NORMAL");
493 // Parser
494 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
495 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_PARSER_NORMAL");
496 // Enable TSIF => Disable TSIF
497 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
498 //TS0
499 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
500 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
501 //TS1
502 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
503 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
504 //TS2
505 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
506 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
507 //TS3
508 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
509 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
510
511 //TSO0
512 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
513 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSOIN0_PAD0");
514
515 #else
516
517 // Enable TSP Clk
518 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & ~REG_CLKGEN0_TSP_CLK_MASK)
519 | (REG_CLKGEN0_TSP_SRC_192MHZ << REG_CLKGEN0_TSP_SRC_SHIFT);
520 // Enable STC1,2 Clk
521 // STC0
522 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) & ~REG_CLKGEN0_STC0_MASK)
523 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT));
524 // STC1
525 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) & ~REG_CLKGEN0_STC1_MASK)
526 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT));
527
528 // Stamp
529 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) & ~REG_CLKGEN0_STAMP_MASK);
530
531 // Parser
532 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) & ~REG_CLKGEN0_PARSER_MASK);
533
534 // Enable TSIF => Disable TSIF
535 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
536 //TS0
537 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK);
538
539 //TS1
540 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS1_SHIFT));
541
542 //TS2
543 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS2_SHIFT));
544
545 //TS3
546 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT));
547
548 //TSO0
549 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK);
550
551 #endif
552
553 // TSP Boot clk sel
554 TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) = (TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) & ~REG_TOP_TSP_BOOT_CLK_SEL_MASK) | REG_TOP_TSP_BOOT_CLK_SEL_TSP;
555
556 // TSP SRAM sel
557 TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) = TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) | REG_MMFI_TSP_SEL_SRAM_EN;
558
559 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
560
561 // Disable MCM
562 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
563 }
564 else
565 {
566 // Enable MCM
567 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
568
569 #ifdef CONFIG_MSTAR_CLKM
570
571 MS_S32 s32Handle;
572
573 // Disable TSP Clk
574 // [2016.10.11] Because AESDMA share clk with TSP. We can't disable TSP clk.
575 // s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
576 // Drv_Clkm_Clk_Gate_Disable(s32Handle);
577
578 // Disable STC Clk
579 //STC0
580 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc0");
581 Drv_Clkm_Clk_Gate_Disable(s32Handle);
582 //STC0
583 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc1");
584 Drv_Clkm_Clk_Gate_Disable(s32Handle);
585 // Stamp
586 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
587 Drv_Clkm_Clk_Gate_Disable(s32Handle);
588 // Parser
589 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
590 Drv_Clkm_Clk_Gate_Disable(s32Handle);
591 //TS0
592 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
593 Drv_Clkm_Clk_Gate_Disable(s32Handle);
594 //TS1
595 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
596 Drv_Clkm_Clk_Gate_Disable(s32Handle);
597 //TS2
598 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
599 Drv_Clkm_Clk_Gate_Disable(s32Handle);
600 //TS3
601 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
602 Drv_Clkm_Clk_Gate_Disable(s32Handle);
603
604 //TSO0
605 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
606 Drv_Clkm_Clk_Gate_Disable(s32Handle);
607
608 #else
609 // Disable TSP Clk
610 // [2016.10.11] Because AESDMA share clk with TSP. We can't disable TSP clk.
611 // TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK),(REG_CLKGEN0_TSP_DISABLE << REG_CLKGEN0_TSP_SHIFT));
612
613 // Disable STC Clk
614 //STC0
615 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC0_SHIFT));
616 //STC1
617 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC1_SHIFT));
618
619 // Stamp
620 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK),(REG_CLKGEN0_STAMP_DISABLE << REG_CLKGEN0_STAMP_SHIFT));
621
622 // Parser
623 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK),(REG_CLKGEN0_PARSER_DISABLE << REG_CLKGEN0_PARSER_SHIFT));
624
625 // Disable TSIF clk
626 //TS0
627 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS0_SHIFT));
628 //TS1
629 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS1_SHIFT));
630 //TS2
631 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS2_SHIFT));
632 //TS3
633 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT));
634
635 //TSO0
636 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT));
637
638 #endif
639
640 }
641 }
642
HAL_TSP_CPU(MS_BOOL bEn)643 void HAL_TSP_CPU(MS_BOOL bEn)
644 {
645 if (bEn)
646 {
647 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
648 }
649 else
650 {
651 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
652 }
653 }
HAL_TSP_ResetCPU(MS_BOOL bReset)654 void HAL_TSP_ResetCPU(MS_BOOL bReset)
655 {
656 // @NOTE TRUE for stop cpu clock
657 if (bReset)
658 {
659 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
660 }
661 else
662 {
663 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
664 }
665 }
666
667
HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr,MS_U32 u32FwSize)668 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize)
669 {
670
671 #define _TSP_QMEM_I_MASK 0xffffc000 //code: 0x2000, data: 0x1000, total: 0x3000
672 #define _TSP_QMEM_I_ADDR_HIT 0x00000000
673 #define _TSP_QMEM_I_ADDR_MISS 0xffffffff
674 #define _TSP_QMEM_D_MASK 0xffffc000
675 #define _TSP_QMEM_D_ADDR_HIT 0x00000000
676 #define _TSP_QMEM_D_ADDR_MISS 0xffffffff
677 #define _TSP_QMEM_SIZE 0x1000 // 16K bytes, 32bit aligment //0x4000 this is 4 byte address
678
679 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit
680
681 MS_U32 u32DnldCtrl = 0;
682 MS_U32 u32DnldCtrl1 = 0;
683
684 // Check MIU select
685 MS_U8 u8MiuSel = 0;
686 MS_PHY phyMiuOffsetFWBuf = 0;
687 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFWBuf, u32FwPhyAddr);
688 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN0_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN0_SHIFT) & REG_MIU_SEL_FILEIN0_MASK));
689
690 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;
691 u32DnldCtrl1 = u32DnldCtrl >> 16;
692
693 REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register
694 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1);
695 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE);
696 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
697 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START);
698
699 //@TODO temprarily comment because of Secure Protect
700 #if 1
701 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE))
702 {
703 }
704 #endif
705
706
707 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
708
709 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK);
710 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT);
711 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK);
712 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT);
713
714 #undef _TSP_QMEM_I_MASK
715 #undef _TSP_QMEM_I_ADDR_HIT
716 #undef _TSP_QMEM_I_ADDR_MISS
717 #undef _TSP_QMEM_D_MASK
718 #undef _TSP_QMEM_D_ADDR_HIT
719 #undef _TSP_QMEM_D_ADDR_MISS
720 #undef _TSP_QMEM_SIZE
721
722 return TRUE;
723 }
724
HAL_TSP_RestoreFltState(void)725 void HAL_TSP_RestoreFltState(void)
726 {
727 MS_U32 u32Size;
728 TSP32 * pRegEnd;
729 TSP32 * pReg;
730 int i, j;
731
732 for (i = 0; i < TSP_PIDFLT_NUM; i++)
733 {
734 TSP32_IdrW(&(_REGPid0->Flt[i]), _u32PidFltReg[i]);
735 TSP32_IdrW(&(_REGPid1->Flt[i]), _u32PidDstReg[i]);
736 }
737
738 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
739
740 for (i = 0; i < TSP_SECFLT_NUM; i++)
741 {
742 pReg = (TSP32*)&(_REGSec->Flt[i]);
743 pRegEnd = pReg + u32Size;
744 j = 0;
745 for ( ; pReg < pRegEnd; pReg++)
746 {
747 TSP32_IdrW(pReg, _u32SecReg[i*u32Size+j]);
748 j++;
749 }
750 }
751
752 }
753
HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)754 void HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
755 {
756 if(bEn)
757 {
758 switch(pktDmxId)
759 {
760 case 0:
761 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
762 break;
763 case 1:
764 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
765 break;
766 case 2:
767 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
768 break;
769 case 3:
770 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3);
771 break;
772 default:
773 break;
774 }
775 }
776 else
777 {
778 switch(pktDmxId)
779 {
780 case 0:
781 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
782 break;
783 case 1:
784 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
785 break;
786 case 2:
787 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
788 break;
789 case 3:
790 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3);
791 break;
792 default:
793 break;
794 }
795 }
796 }
797
HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)798 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
799 {
800 if(bEn)
801 {
802 switch(pktDmxId)
803 {
804 case 0:
805 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
806 break;
807 case 1:
808 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
809 break;
810 case 2:
811 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
812 break;
813 case 3:
814 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3);
815 break;
816 default:
817 break;
818 }
819 }
820 else
821 {
822 switch(pktDmxId)
823 {
824 case 0:
825 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
826 break;
827 case 1:
828 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
829 break;
830 case 2:
831 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
832 break;
833 case 3:
834 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3);
835 break;
836 default:
837 break;
838 }
839 }
840 }
841
HAL_TSP_SetTSIF(MS_U16 u16TSIF,TSP_TSIF_CFG u16Cfg,MS_BOOL bFileIn)842 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn)
843 {
844 if(bFileIn)
845 {
846 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, TRUE); // this returns true only we don't check the return value
847 HAL_TSP_TSIF_LiveEn(u16TSIF, FALSE); // this returns true only we don't check the return value
848 }
849 else
850 {
851 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, FALSE);
852 HAL_TSP_TSIF_LiveEn(u16TSIF, TRUE);
853 }
854
855 if(bFileIn != TRUE)
856 {
857 HAL_TSP_TSIF_BitSwap(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_BITSWAP)?TRUE:FALSE));
858 HAL_TSP_TSIF_ExtSync(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_EXTSYNC)?TRUE:FALSE));
859 HAL_TSP_TSIF_Parl (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_PARA )?TRUE:FALSE));
860 HAL_TSP_TSIF_3Wire (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_3WIRE )?TRUE:FALSE));
861 }
862
863 return TRUE;
864 }
865
HAL_TSP_TSIF_LiveEn(MS_U32 tsIf,MS_BOOL bEnable)866 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable)
867 {
868 if(bEnable)
869 {
870 switch(tsIf)
871 {
872 case 0:
873 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
874 break;
875 case 1:
876 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
877 break;
878 case 2:
879 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
880 break;
881 case 3:
882 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN);
883 break;
884 default:
885 return FALSE;
886 }
887 }
888 else
889 {
890 switch(tsIf)
891 {
892 case 0:
893 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
894 break;
895 case 1:
896 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
897 break;
898 case 2:
899 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
900 break;
901 case 3:
902 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN);
903 break;
904 default:
905 return FALSE;
906 }
907 }
908
909 return TRUE;
910 }
911
HAL_TSP_TSIF_SelPad(MS_U32 tsIf,TSP_TS_PAD eTSPad)912 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad) // @FIXME modify this parameter to enum plz
913 {
914 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
915 MS_U32 pad_src = REG_TOP_TS_SRC_EXT0;
916 #ifdef CONFIG_MSTAR_CLKM
917 MS_S32 handle;
918 MS_U8 u8NameIdx = 0;
919 char* u8ClkSrcNames[] =
920 {
921 "CLK_TS0_PAD0",
922 "CLK_TS0_PAD1",
923 "CLK_TS0_PAD2",
924 "CLK_TS0_PAD3",
925 "CLK_TS0_PAD4",
926 "CLK_TS0_PAD5",
927 "CLK_TS0_PAD6",
928 "CLK_TS0_PADTSO",
929 "CLK_TS0_PADTSIO",
930 "CLK_TS0_PADINTER0",
931 "CLK_TS0_PADINTER1"
932 };
933 #endif
934
935 //@NOTE
936 //EX3~6 are serial mode and ts2_padmax_mode must be 2 or 3.
937
938
939 switch (eTSPad)
940 {
941 default:
942 case E_TSP_TS_PAD_EXT0:
943 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
944 pad_src = REG_TOP_TS_SRC_EXT0;
945 break;
946 case E_TSP_TS_PAD_EXT1:
947 clk_src = REG_CLKGEN0_TS_SRC_EXT1;
948 pad_src = REG_TOP_TS_SRC_EXT1;
949 break;
950 case E_TSP_TS_PAD_EXT2:
951 clk_src = REG_CLKGEN0_TS_SRC_EXT2;
952 pad_src = REG_TOP_TS_SRC_EXT2;
953 break;
954 case E_TSP_TS_PAD_EXT3:
955 clk_src = REG_CLKGEN0_TS_SRC_EXT3;
956 pad_src = REG_TOP_TS_SRC_EXT3;
957 break;
958 case E_TSP_TS_PAD_EXT4:
959 clk_src = REG_CLKGEN0_TS_SRC_EXT4;
960 pad_src = REG_TOP_TS_SRC_EXT4;
961 break;
962 case E_TSP_TS_PAD_EXT5:
963 clk_src = REG_CLKGEN0_TS_SRC_EXT5;
964 pad_src = REG_TOP_TS_SRC_EXT5;
965 break;
966 case E_TSP_TS_PAD_EXT6:
967 clk_src = REG_CLKGEN0_TS_SRC_EXT6;
968 pad_src = REG_TOP_TS_SRC_EXT6;
969 break;
970 case E_TSP_TS_PAD_TSOUT0:
971 clk_src = REG_CLKGEN0_TS_SRC_TSO0;
972 pad_src = REG_TOP_TS_SRC_TSO0;
973 break;
974 case E_TSP_TS_PAD_TSIOOUT0:
975 clk_src = REG_CLKGEN0_TS_SRC_TSIO0;
976 pad_src = REG_TOP_TS_SRC_TSIO0;
977 break;
978 case E_TSP_TS_PAD_INTER0:
979 clk_src = REG_CLKGEN0_TS_SRC_DMD0;
980 pad_src = REG_TOP_TS_SRC_DMD0;
981 break;
982 case E_TSP_TS_PAD_INTER1:
983 clk_src = REG_CLKGEN0_TS_SRC_DMD1;
984 pad_src = REG_TOP_TS_SRC_DMD1;
985 break;
986 }
987
988 #ifdef CONFIG_MSTAR_CLKM
989 switch(clk_src)
990 {
991 case REG_CLKGEN0_TS_SRC_EXT0:
992 u8NameIdx = 0;
993 break;
994 case REG_CLKGEN0_TS_SRC_EXT1:
995 u8NameIdx = 1;
996 break;
997 case REG_CLKGEN0_TS_SRC_EXT2:
998 u8NameIdx = 2;
999 break;
1000 case REG_CLKGEN0_TS_SRC_EXT3:
1001 u8NameIdx = 3;
1002 break;
1003 case REG_CLKGEN0_TS_SRC_EXT4:
1004 u8NameIdx = 4;
1005 break;
1006 case REG_CLKGEN0_TS_SRC_EXT5:
1007 u8NameIdx = 5;
1008 break;
1009 case REG_CLKGEN0_TS_SRC_EXT6:
1010 u8NameIdx = 6;
1011 break;
1012 case REG_CLKGEN0_TS_SRC_TSO0:
1013 u8NameIdx = 7;
1014 break;
1015 case REG_CLKGEN0_TS_SRC_TSIO0:
1016 u8NameIdx = 8;
1017 break;
1018 case REG_CLKGEN0_TS_SRC_TSIO0:
1019 u8NameIdx = 9;
1020 break;
1021 case REG_CLKGEN0_TS_SRC_TSIO0:
1022 u8NameIdx = 10;
1023 break;
1024 default:
1025 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1026 u8NameIdx = 0;
1027 break;
1028 }
1029 #endif
1030
1031 //@FIXME use enum instead of constant
1032 switch (tsIf)
1033 {
1034 case 0:
1035 TSP_TOP_REG(REG_TOP_TS0_MUX) = (TSP_TOP_REG(REG_TOP_TS0_MUX) & ~REG_TOP_TS_SRC_MASK) | (pad_src<<REG_TOP_TS0_SHIFT);
1036 #ifdef CONFIG_MSTAR_CLKM
1037 handle = Drv_Clkm_Get_Handle("g_clk_ts");
1038 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1039 #else
1040 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK) | (clk_src<<(REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1041 #endif
1042 break;
1043
1044 case 1:
1045 TSP_TOP_REG(REG_TOP_TS1_MUX) = (TSP_TOP_REG(REG_TOP_TS1_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS1_SHIFT)) | (pad_src<<REG_TOP_TS1_SHIFT);
1046 #ifdef CONFIG_MSTAR_CLKM
1047 handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1048 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1049 #else
1050 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1051 #endif
1052 break;
1053 case 2:
1054 TSP_TOP_REG(REG_TOP_TS2_MUX) = (TSP_TOP_REG(REG_TOP_TS2_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS2_SHIFT)) | (pad_src<<REG_TOP_TS2_SHIFT);
1055 #ifdef CONFIG_MSTAR_CLKM
1056 handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1057 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1058 #else
1059 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1060 #endif
1061 break;
1062 case 3:
1063 TSP_TOP_REG(REG_TOP_TS3_MUX) = (TSP_TOP_REG(REG_TOP_TS3_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS3_SHIFT)) | (pad_src<<REG_TOP_TS3_SHIFT);
1064 #ifdef CONFIG_MSTAR_CLKM
1065 handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1066 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1067 #else
1068 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1069 #endif
1070 break;
1071
1072 default:
1073 return FALSE;
1074 }
1075 return TRUE;
1076 }
1077
_HAL_TSO_SetPad1OutMux(MS_BOOL bSet)1078 static void _HAL_TSO_SetPad1OutMux(MS_BOOL bSet)
1079 {
1080 if(bSet)
1081 {
1082 TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) = TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) & ~(REG_TOP_TS1MODE_MASK << REG_TOP_TS1MODE_SHIFT);
1083 }
1084 else
1085 {
1086 TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) = ((TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) & ~(REG_TOP_TS1MODE_MASK << REG_TOP_TS1MODE_SHIFT)) | (REG_TOP_TS1MODE_INPUT << REG_TOP_TS1MODE_SHIFT));
1087 }
1088 }
1089
HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)1090 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)
1091 {
1092 _HAL_TSO_SetPad1OutMux(bSet);
1093 }
1094
HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad,TSP_TS_PAD_MUX_MODE eOutPadMode,TSP_TS_PAD eInPad,TSP_TS_PAD_MUX_MODE eInPadMode,MS_BOOL bEnable)1095 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable)
1096 {
1097 MS_U16 u16Temp = 0;
1098
1099 switch(eOutPad) // output pad
1100 {
1101 case E_TSP_TS_PAD_EXT1: // TS_pad #1
1102 if(eInPad == E_TSP_TS_PAD_EXT1) // output pad == input pad ?
1103 {
1104 return FALSE;
1105 }
1106
1107 _HAL_TSO_SetPad1OutMux(bEnable); // set pad mode (input or output)
1108
1109 switch(eOutPadMode) // set pad output mode
1110 {
1111 case E_TSP_TS_PAD_MUX_TSO:
1112 // input from TSO
1113 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT)) | (REG_TOP_TS_OUT_MODE_TSO << REG_TOP_TS_OUT_MODE_SHIFT);
1114 break;
1115 case E_TSP_TS_PAD_MUX_S2P:
1116 // input from S2P
1117 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT)) | (REG_TOP_TS_OUT_MODE_S2P << REG_TOP_TS_OUT_MODE_SHIFT);
1118
1119 u16Temp = REG_TSO_TSP_S2P_EN | REG_TSO_TSP_S2P_TS_SIN_C0 | REG_TSO_TSP_S2P_TS_SIN_C1; // S2P enable bit , serial bit count setting
1120 if(eInPadMode == E_TSP_TS_PAD_MUX_PARALLEL)
1121 {
1122 u16Temp |= REG_TSO_TSP_BYPASS_S2P; // bypass S2P: if input is parallel , set it
1123 }
1124 else if(eInPadMode == E_TSP_TS_PAD_MUX_3WIRED_SERIAL)
1125 {
1126 u16Temp |= REG_TSO_TSP_S2P_3WIRE; // input pad is 3-wire serial
1127 }
1128
1129 // S2P config
1130 TSP_TSO_REG(REG_TSO_TSP_CONFIG0) = (TSP_TSO_REG(REG_TSO_TSP_CONFIG0) & ~REG_TSO_TSP_S2P_MASK) | u16Temp;
1131 // select S2P input pad
1132 TSP_TOP_REG(REG_TOP_TSO4_5_MUX) = (TSP_TOP_REG(REG_TOP_TSO4_5_MUX) & ~REG_TOP_TSO4_MASK)
1133 | (eInPad << REG_TOP_TSO4_SHIFT);
1134 // select S2P input clk source
1135 #ifdef CONFIG_MSTAR_CLKM
1136 {
1137 MS_S32 handle;
1138 MS_U8 u8NameIdx = 0;
1139 char* u8ClkSrcNames[] =
1140 {
1141 "CLK_S2P0_PAD0",
1142 "CLK_S2P0_PAD1",
1143 "CLK_S2P0_PAD2",
1144 "CLK_S2P0_PAD3",
1145 "CLK_S2P0_PAD4",
1146 "CLK_S2P0_PAD5",
1147 "CLK_S2P0_PAD6"
1148 };
1149
1150 switch(eInPad)
1151 {
1152 case E_TSP_TS_PAD_EXT0:
1153 u8NameIdx = 0;
1154 break;
1155 case E_TSP_TS_PAD_EXT1:
1156 u8NameIdx = 1;
1157 break;
1158 case E_TSP_TS_PAD_EXT2:
1159 u8NameIdx = 2;
1160 break;
1161 case E_TSP_TS_PAD_EXT3:
1162 u8NameIdx = 3;
1163 break;
1164 case E_TSP_TS_PAD_EXT4:
1165 u8NameIdx = 4;
1166 break;
1167 case E_TSP_TS_PAD_EXT5:
1168 u8NameIdx = 5;
1169 break;
1170 case E_TSP_TS_PAD_EXT6:
1171 u8NameIdx = 6;
1172 break;
1173 default:
1174 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1175 u8NameIdx = 0;
1176 break;
1177 }
1178
1179 handle = Drv_Clkm_Get_Handle("g_clk_s2p_in");
1180 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
1181 }
1182 #else
1183 TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) = (TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) & ~(REG_CLKGEN0_S2P_IN_CLK_MASK << REG_CLKGEN0_S2P_IN_CLK_SHIFT))
1184 | ((eInPad & REG_CLKGEN0_S2P_IN_CLK_SRC_MASK) << (REG_CLKGEN0_S2P_IN_CLK_SHIFT + REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT));
1185 #endif
1186 break;
1187 case E_TSP_TS_PAD_MUX_S2P1:
1188 // input from S2P1
1189 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1190 | (REG_TOP_TS_OUT_MODE_S2P1 << REG_TOP_TS_OUT_MODE_SHIFT);
1191
1192 u16Temp = REG_TSO_TSP_S2P1_EN | REG_TSO_TSP_S2P1_TS_SIN_C0 | REG_TSO_TSP_S2P1_TS_SIN_C1;// S2P1 enable bit , serial bit count setting
1193 if(eInPadMode == E_TSP_TS_PAD_MUX_PARALLEL)
1194 {
1195 u16Temp |= REG_TSO_TSP_BYPASS_S2P1; // bypass S2P1: if input is parallel , set it
1196 }
1197 else if(eInPadMode == E_TSP_TS_PAD_MUX_3WIRED_SERIAL)
1198 {
1199 u16Temp |= REG_TSO_TSP_S2P1_3WIRE; // input pad is 3-wire serial
1200 }
1201 // S2P1 config
1202 TSP_TSO_REG(REG_TSO_TSP_CONFIG0) = (TSP_TSO_REG(REG_TSO_TSP_CONFIG0) & ~REG_TSO_TSP_S2P1_MASK) | u16Temp;
1203 // select S2P1 input pad
1204 TSP_TOP_REG(REG_TOP_TSO4_5_MUX) = (TSP_TOP_REG(REG_TOP_TSO4_5_MUX) & ~REG_TOP_TSO5_MASK)
1205 | (eInPad << REG_TOP_TSO5_SHIFT);
1206 #ifdef CONFIG_MSTAR_CLKM
1207 {
1208 MS_S32 handle;
1209 MS_U8 u8NameIdx = 0;
1210 char* u8ClkSrcNames[] =
1211 {
1212 "CLK_S2P1_PAD0",
1213 "CLK_S2P1_PAD1",
1214 "CLK_S2P1_PAD2",
1215 "CLK_S2P1_PAD3",
1216 "CLK_S2P1_PAD4",
1217 "CLK_S2P1_PAD5",
1218 "CLK_S2P1_PAD6"
1219 };
1220
1221 switch(eInPad)
1222 {
1223 case E_TSP_TS_PAD_EXT0:
1224 u8NameIdx = 0;
1225 break;
1226 case E_TSP_TS_PAD_EXT1:
1227 u8NameIdx = 1;
1228 break;
1229 case E_TSP_TS_PAD_EXT2:
1230 u8NameIdx = 2;
1231 break;
1232 case E_TSP_TS_PAD_EXT3:
1233 u8NameIdx = 3;
1234 break;
1235 case E_TSP_TS_PAD_EXT4:
1236 u8NameIdx = 4;
1237 break;
1238 case E_TSP_TS_PAD_EXT5:
1239 u8NameIdx = 5;
1240 break;
1241 case E_TSP_TS_PAD_EXT6:
1242 u8NameIdx = 6;
1243 break;
1244 default:
1245 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1246 u8NameIdx = 0;
1247 break;
1248 }
1249
1250 handle = Drv_Clkm_Get_Handle("g_clk_s2p1_in");
1251 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
1252 }
1253 #else
1254 // select S2P1 input clk source
1255 TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) = (TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) & ~(REG_CLKGEN0_S2P_IN_CLK_MASK << REG_CLKGEN0_S2P1_IN_CLK_SHIFT))
1256 | ((eInPad & REG_CLKGEN0_S2P_IN_CLK_SRC_MASK) << (REG_CLKGEN0_S2P1_IN_CLK_SHIFT + REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT));
1257 #endif
1258
1259 break;
1260 default:
1261 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%d] Warining wrong output PAD Mode:%u\n",__FUNCTION__,__LINE__, eOutPadMode));
1262 return FALSE;
1263 }
1264 break;
1265 default:
1266 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1267 return FALSE;
1268 }
1269
1270 return TRUE;
1271 }
1272
_TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad,MS_U32 * pu32PADSrc,MS_U32 * pu32CLKSrc)1273 static MS_BOOL _TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad, MS_U32* pu32PADSrc, MS_U32* pu32CLKSrc)
1274 {
1275 switch (eTSPad)
1276 {
1277 case E_TSP_TS_PAD_EXT0:
1278 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
1279 *pu32PADSrc = REG_TOP_TS_SRC_EXT0;
1280 break;
1281 case E_TSP_TS_PAD_EXT1:
1282 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT1;
1283 *pu32PADSrc = REG_TOP_TS_SRC_EXT1;
1284 break;
1285 case E_TSP_TS_PAD_INTER0:
1286 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_DMD0;
1287 *pu32PADSrc = REG_TOP_TS_SRC_DMD0;
1288 break;
1289 case E_TSP_TS_PAD_TSOUT0:
1290 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_TSO0;
1291 *pu32PADSrc = REG_TOP_TS_SRC_TSO0;
1292 break;
1293
1294 default:
1295 return FALSE;
1296 }
1297
1298 return TRUE;
1299 }
1300
HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng,TSP_TS_PAD eTSPad)1301 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad)
1302 {
1303 MS_U32 u32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
1304 MS_U32 u32PADSrc = REG_TOP_TS_SRC_EXT0;
1305 _TSP_Hal_TSPAD2RelatedReg_Mapping(eTSPad, &u32PADSrc, &u32CLKSrc);
1306
1307 switch(u32TSOEng)
1308 {
1309 case 0:
1310 TSP_TOP_REG(REG_TOP_TSO0_MUX) = (TSP_TOP_REG(REG_TOP_TSO0_MUX) & ~REG_TOP_TS_SRC_MASK) | u32PADSrc;
1311 #ifdef CONFIG_MSTAR_CLKM
1312 {
1313 MS_S32 handle;
1314 MS_U8 u8NameIdx = 0;
1315 char* u8ClkSrcNames[] =
1316 {
1317 "CLK_TSOIN0_PAD0",
1318 "CLK_TSOIN0_PAD1",
1319 "CLK_TSOIN0_PAD2",
1320 "CLK_TSOIN0_PAD3",
1321 "CLK_TSOIN0_PAD4",
1322 "CLK_TSOIN0_PAD5",
1323 "CLK_TSOIN0_PAD6"
1324 };
1325
1326 switch(u32CLKSrc)
1327 {
1328 case REG_CLKGEN0_TS_SRC_EXT0:
1329 u8NameIdx = 0;
1330 break;
1331 case REG_CLKGEN0_TS_SRC_EXT1:
1332 u8NameIdx = 1;
1333 break;
1334 case REG_CLKGEN0_TS_SRC_EXT2:
1335 u8NameIdx = 2;
1336 break;
1337 case REG_CLKGEN0_TS_SRC_EXT3:
1338 u8NameIdx = 3;
1339 break;
1340 case REG_CLKGEN0_TS_SRC_EXT4:
1341 u8NameIdx = 4;
1342 break;
1343 case REG_CLKGEN0_TS_SRC_EXT5:
1344 u8NameIdx = 5;
1345 break;
1346 default:
1347 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1348 u8NameIdx = 0;
1349 break;
1350 }
1351
1352 handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
1353 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1354 }
1355 #else
1356 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK)
1357 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1358 #endif
1359 return TRUE;
1360
1361 default:
1362 return FALSE;
1363 }
1364 }
1365
1366
HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf,MS_BOOL bClkInv)1367 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv)
1368 {
1369 if (bClkInv)
1370 {
1371 switch (tsIf)
1372 {
1373 case 0:
1374 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
1375 break;
1376 case 1:
1377 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
1378 break;
1379 case 2:
1380 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
1381 break;
1382 case 3:
1383 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
1384 break;
1385 default:
1386 return FALSE;
1387 }
1388 }
1389 else
1390 {
1391 switch (tsIf)
1392 {
1393 case 0:
1394 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
1395 break;
1396 case 1:
1397 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
1398 break;
1399 case 2:
1400 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
1401 break;
1402 case 3:
1403 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
1404 break;
1405 default:
1406 return FALSE;
1407 }
1408 }
1409 return TRUE;
1410 }
1411
HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf,MS_BOOL bClkDis)1412 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis)
1413 {
1414 if (bClkDis)
1415 {
1416 #ifdef CONFIG_MSTAR_CLKM
1417 MS_S32 s32Handle;
1418
1419 switch (tsIf)
1420 {
1421 case 0:
1422 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
1423 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1424 break;
1425 case 1:
1426 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1427 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1428 break;
1429 case 2:
1430 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1431 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1432 break;
1433 case 3:
1434 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1435 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1436 break;
1437 default:
1438 return FALSE;
1439 }
1440 #else
1441 switch (tsIf)
1442 {
1443 case 0:
1444 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1445 break;
1446 case 1:
1447 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1448 break;
1449 case 2:
1450 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1451 break;
1452 case 3:
1453 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1454 break;
1455 default:
1456 return FALSE;
1457 }
1458 #endif
1459 }
1460 else
1461 {
1462 #ifdef CONFIG_MSTAR_CLKM
1463 MS_S32 s32Handle;
1464 MS_U16 u16ClkSrc;
1465 MS_U8 u8NameIdx = 0;
1466 char* u8ClkSrcNames[] =
1467 {
1468 "CLK_TS0_PAD0",
1469 "CLK_TS0_PAD1",
1470 "CLK_TS0_PAD2",
1471 "CLK_TS0_PAD3",
1472 "CLK_TS0_PAD4",
1473 "CLK_TS0_PAD5",
1474 "CLK_TS0_PAD6",
1475 "CLK_TS0_PADTSO"
1476 };
1477
1478 switch (tsIf)
1479 {
1480 case 0:
1481 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
1482 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & REG_CLKGEN0_TS_MASK) >> (REG_CLKGEN0_TS0_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1483 break;
1484 case 1:
1485 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1486 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) >> (REG_CLKGEN0_TS1_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1487 break;
1488 case 2:
1489 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1490 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) >> (REG_CLKGEN0_TS2_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1491 break;
1492 case 3:
1493 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1494 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1495 break;
1496 default:
1497 return FALSE;
1498 }
1499
1500 switch(u16ClkSrc)
1501 {
1502 case REG_CLKGEN0_TS_SRC_EXT0:
1503 u8NameIdx = 0;
1504 break;
1505 case REG_CLKGEN0_TS_SRC_EXT1:
1506 u8NameIdx = 1;
1507 break;
1508 case REG_CLKGEN0_TS_SRC_EXT2:
1509 u8NameIdx = 2;
1510 break;
1511 case REG_CLKGEN0_TS_SRC_EXT3:
1512 u8NameIdx = 3;
1513 break;
1514 case REG_CLKGEN0_TS_SRC_EXT4:
1515 u8NameIdx = 4;
1516 break;
1517 case REG_CLKGEN0_TS_SRC_EXT5:
1518 u8NameIdx = 5;
1519 break;
1520 case REG_CLKGEN0_TS_SRC_EXT6:
1521 u8NameIdx = 6;
1522 break;
1523 case REG_CLKGEN0_TS_SRC_TSO0:
1524 u8NameIdx = 7;
1525 break;
1526 default:
1527 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1528 u8NameIdx = 0;
1529 break;
1530 }
1531
1532 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
1533 #else
1534 switch (tsIf)
1535 {
1536 case 0:
1537 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1538 break;
1539 case 1:
1540 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1541 break;
1542 case 2:
1543 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1544 break;
1545 case 3:
1546 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1547 break;
1548 default:
1549 return FALSE;
1550 }
1551 #endif
1552 }
1553 return TRUE;
1554 }
1555
1556 // @NOTE tsif0 and tsif2 can do filein and livein simulatenously,so tsif0 tsif2's output are both live TS Data
HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1557 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1558 {
1559 if(bEnable)
1560 {
1561 switch(eFileEng)
1562 {
1563 case E_FILEENG_TSIF0:
1564 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firmware or playback)
1565 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS
1566 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable
1567 break;
1568 case E_FILEENG_TSIF1:
1569 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firmware or playback) we don't use this fileEng for FW
1570 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
1571 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
1572 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable
1573 break;
1574 case E_FILEENG_TSIF2:
1575 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
1576 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
1577 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
1578 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
1579 break;
1580 case E_FILEENG_TSIF3:
1581 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3);
1582 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3);
1583 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3);
1584 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3);
1585 break;
1586 default:
1587 return FALSE;
1588 }
1589 }
1590 else
1591 {
1592 switch(eFileEng)
1593 {
1594 case E_FILEENG_TSIF0:
1595 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
1596 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL);
1597 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN);
1598 break;
1599 case E_FILEENG_TSIF1:
1600 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1);
1601 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
1602 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
1603 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN);
1604 break;
1605 case E_FILEENG_TSIF2:
1606 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
1607 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
1608 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
1609 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
1610 break;
1611 case E_FILEENG_TSIF3:
1612 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3);
1613 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3);
1614 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3);
1615 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3);
1616 break;
1617 default:
1618 return FALSE;
1619 }
1620 }
1621
1622 return TRUE;
1623 }
1624
HAL_TSP_TSIF_BitSwap(MS_U32 tsIf,MS_BOOL bEnable)1625 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable)
1626 {
1627 if(bEnable)
1628 {
1629 switch(tsIf)
1630 {
1631 case 0:
1632 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1633 break;
1634 case 1:
1635 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1636 break;
1637 case 2:
1638 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1639 break;
1640 case 3:
1641 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP);
1642 break;
1643 default:
1644 return;
1645 }
1646 }
1647 else
1648 {
1649 switch(tsIf)
1650 {
1651 case 0:
1652 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1653 break;
1654 case 1:
1655 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1656 break;
1657 case 2:
1658 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1659 break;
1660 case 3:
1661 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP);
1662 break;
1663 default:
1664 return;
1665 }
1666 }
1667 }
1668
HAL_TSP_TSIF_ExtSync(MS_U32 tsIf,MS_BOOL bEnable)1669 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable)
1670 {
1671 if(bEnable)
1672 {
1673 //printf("External Sync\n");
1674
1675 switch(tsIf)
1676 {
1677 case 0:
1678 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1679 break;
1680 case 1:
1681 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1682 break;
1683 case 2:
1684 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1685 break;
1686 case 3:
1687 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3);
1688 break;
1689 default:
1690 return;
1691 }
1692 }
1693 else
1694 {
1695 //printf("Internal Sync\n");
1696
1697 switch(tsIf)
1698 {
1699 case 0:
1700 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1701 break;
1702 case 1:
1703 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1704 break;
1705 case 2:
1706 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1707 break;
1708 case 3:
1709 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3);
1710 break;
1711 default:
1712 return;
1713 }
1714 }
1715 }
1716
1717 #if 0
1718 void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable)
1719 {
1720 if(bEnable)
1721 {
1722 switch(tsIf)
1723 {
1724 case 0:
1725 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1726 break;
1727 case 1:
1728 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1729 break;
1730 case 2:
1731 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1732 break;
1733 case 3:
1734 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3);
1735 break;
1736 default:
1737 return;
1738 }
1739 }
1740 else
1741 {
1742 switch(tsIf)
1743 {
1744 case 0:
1745 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1746 break;
1747 case 1:
1748 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1749 break;
1750 case 2:
1751 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1752 break;
1753 case 3:
1754 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3);
1755 break;
1756 default:
1757 return;
1758 }
1759
1760 }
1761 }
1762 #endif
1763
1764
HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng,MS_BOOL bBypass)1765 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass)
1766 {
1767 if(bBypass)
1768 {
1769 switch (eFileEng)
1770 {
1771 case E_FILEENG_TSIF0:
1772 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP);
1773 break;
1774 case E_FILEENG_TSIF1:
1775 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1);
1776 break;
1777 case E_FILEENG_TSIF2:
1778 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2);
1779 break;
1780 case E_FILEENG_TSIF3:
1781 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3);
1782 break;
1783 default:
1784 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng : %d !\n",__FILE__,__FUNCTION__,__LINE__,eFileEng));
1785 break;
1786 }
1787 //REG16_MSK_W(&_RegCtrl3->CFG3_10,CFG3_10_PS_MODE_SRC_MASK,(eFileEng << CFG3_10_PS_MODE_SRC_SHIFT));
1788 }
1789 else
1790 {
1791 switch (eFileEng)
1792 {
1793 case E_FILEENG_TSIF0:
1794 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP);
1795 break;
1796 case E_FILEENG_TSIF1:
1797 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1);
1798 break;
1799 case E_FILEENG_TSIF2:
1800 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2);
1801 break;
1802 case E_FILEENG_TSIF3:
1803 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3);
1804 break;
1805 default:
1806 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng : %d !\n",__FILE__,__FUNCTION__,__LINE__,eFileEng));
1807 break;
1808 }
1809 }
1810 }
1811
1812
HAL_TSP_TSIF_Parl(MS_U32 tsIf,MS_BOOL bEnable)1813 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable)
1814 {
1815 if(bEnable)
1816 {
1817 switch(tsIf)
1818 {
1819 case 0:
1820 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1821 break;
1822 case 1:
1823 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1824 break;
1825 case 2:
1826 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1827 break;
1828 case 3:
1829 REG16_SET(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3);
1830 break;
1831 default:
1832 return;
1833 }
1834 }
1835 else
1836 {
1837 switch(tsIf)
1838 {
1839 case 0:
1840 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1841 break;
1842 case 1:
1843 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1844 break;
1845 case 2:
1846 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1847 break;
1848 case 3:
1849 REG16_CLR(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3);
1850 break;
1851 default:
1852 return;
1853 }
1854 }
1855 }
1856
HAL_TSP_PAD_3Wire(MS_U32 u32Pad,MS_BOOL bEnable)1857 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable)
1858 {
1859 #if 0 //@NOTE: Kano do NOT need to set
1860 if(bEnable)
1861 {
1862 switch(u32Pad)
1863 {
1864 case 0:
1865 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS0_3WIRE_EN;
1866 break;
1867 case 1:
1868 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS1_3WIRE_EN;
1869 break;
1870 case 2:
1871 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1)| REG_TOP_TSP_TS2_3WIRE_EN;
1872 break;
1873 case 3:
1874 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) | REG_TOP_TSP_TS3_3WIRE_EN;
1875 break;
1876
1877 default:
1878 return;
1879 }
1880 }
1881 else
1882 {
1883 switch(u32Pad)
1884 {
1885 case 0:
1886 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS0_3WIRE_EN;
1887 break;
1888 case 1:
1889 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS1_3WIRE_EN;
1890 break;
1891 case 2:
1892 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) & ~REG_TOP_TSP_TS2_3WIRE_EN;
1893 break;
1894 case 3:
1895 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) & ~REG_TOP_TSP_TS3_3WIRE_EN;
1896 break;
1897 default:
1898 return;
1899 }
1900 }
1901 #endif
1902 }
1903
HAL_TSP_TSIF_3Wire(MS_U32 tsIf,MS_BOOL bEnable)1904 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable)
1905 {
1906 if(bEnable)
1907 {
1908 switch(tsIf)
1909 {
1910 case 0:
1911 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1912 break;
1913 case 1:
1914 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1915 break;
1916 case 2:
1917 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1918 break;
1919 case 3:
1920 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3);
1921 break;
1922 default:
1923 return;
1924 }
1925 }
1926 else
1927 {
1928 switch(tsIf)
1929 {
1930 case 0:
1931 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1932 break;
1933 case 1:
1934 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1935 break;
1936 case 2:
1937 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1938 break;
1939 case 3:
1940 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3);
1941 break;
1942 default:
1943 return;
1944 }
1945 }
1946
1947 }
1948
HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId,MS_BOOL bEn)1949 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn)
1950 {
1951 if(bEn)
1952 {
1953 REG16_SET(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
1954 }
1955 else
1956 {
1957 REG16_CLR(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
1958 }
1959 }
1960
HAL_TSP_ReDirect_File(MS_U32 reDir,MS_U32 tsIf,MS_BOOL bEn)1961 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn)
1962 {
1963 //@NOTE Not support in KANO(K7)
1964 #if 0
1965 MS_U16 u16Src = 0;
1966
1967 if((reDir > 0) || (tsIf > 1))
1968 return;
1969
1970 if(bEn)
1971 {
1972 u16Src = (MS_U16)(tsIf + 1) << CFG_01_PDFLT2_FILE_SRC_SHIFT;
1973 }
1974
1975 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src);
1976 #endif
1977 }
1978
1979 // [ToDo]
HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)1980 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)
1981 {
1982 if(bEn)
1983 {
1984 switch(u32Tsif)
1985 {
1986 case 0:
1987 switch (eFltType)
1988 {
1989 case E_TSP_DST_FIFO_VIDEO:
1990 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
1991 break;
1992 case E_TSP_DST_FIFO_VIDEO3D:
1993 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
1994 break;
1995 case E_TSP_DST_FIFO_AUDIO:
1996 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
1997 break;
1998 case E_TSP_DST_FIFO_AUDIO2:
1999 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
2000 break;
2001 case E_TSP_DST_FIFO_AUDIO3:
2002 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AC_EN);
2003 break;
2004 case E_TSP_DST_FIFO_AUDIO4:
2005 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX0_TRACE_MARK_AD_EN);
2006 break;
2007 default:
2008 break;
2009 }
2010 break;
2011 case 1:
2012 switch (eFltType)
2013 {
2014 case E_TSP_DST_FIFO_VIDEO:
2015 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
2016 break;
2017 case E_TSP_DST_FIFO_VIDEO3D:
2018 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
2019 break;
2020 case E_TSP_DST_FIFO_AUDIO:
2021 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
2022 break;
2023 case E_TSP_DST_FIFO_AUDIO2:
2024 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
2025 break;
2026 case E_TSP_DST_FIFO_AUDIO3:
2027 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AC_EN);
2028 break;
2029 case E_TSP_DST_FIFO_AUDIO4:
2030 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX1_TRACE_MARK_AD_EN);
2031 break;
2032 default:
2033 break;
2034 }
2035 break;
2036 case 2:
2037 switch (eFltType)
2038 {
2039 case E_TSP_DST_FIFO_VIDEO:
2040 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
2041 break;
2042 case E_TSP_DST_FIFO_VIDEO3D:
2043 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
2044 break;
2045 case E_TSP_DST_FIFO_AUDIO:
2046 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
2047 break;
2048 case E_TSP_DST_FIFO_AUDIO2:
2049 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
2050 break;
2051 case E_TSP_DST_FIFO_AUDIO3:
2052 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AC_EN);
2053 break;
2054 case E_TSP_DST_FIFO_AUDIO4:
2055 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX2_TRACE_MARK_AD_EN);
2056 break;
2057 default:
2058 break;
2059 }
2060 break;
2061 case 3:
2062 switch (eFltType)
2063 {
2064 case E_TSP_DST_FIFO_VIDEO:
2065 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN);
2066 break;
2067 case E_TSP_DST_FIFO_VIDEO3D:
2068 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN);
2069 break;
2070 case E_TSP_DST_FIFO_AUDIO:
2071 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN);
2072 break;
2073 case E_TSP_DST_FIFO_AUDIO2:
2074 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN);
2075 break;
2076 case E_TSP_DST_FIFO_AUDIO3:
2077 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AC_EN);
2078 break;
2079 case E_TSP_DST_FIFO_AUDIO4:
2080 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX3_TRACE_MARK_AD_EN);
2081 break;
2082 default:
2083 break;
2084 }
2085 break;
2086 default:
2087 break;
2088 }
2089 }
2090 else
2091 {
2092 switch(u32Tsif)
2093 {
2094 case 0:
2095 switch (eFltType)
2096 {
2097 case E_TSP_DST_FIFO_VIDEO:
2098 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
2099 break;
2100 case E_TSP_DST_FIFO_VIDEO3D:
2101 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
2102 break;
2103 case E_TSP_DST_FIFO_AUDIO:
2104 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
2105 break;
2106 case E_TSP_DST_FIFO_AUDIO2:
2107 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
2108 break;
2109 case E_TSP_DST_FIFO_AUDIO3:
2110 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AC_EN);
2111 break;
2112 case E_TSP_DST_FIFO_AUDIO4:
2113 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX0_TRACE_MARK_AD_EN);
2114 break;
2115 default:
2116 break;
2117 }
2118 break;
2119 case 1:
2120 switch (eFltType)
2121 {
2122 case E_TSP_DST_FIFO_VIDEO:
2123 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
2124 break;
2125 case E_TSP_DST_FIFO_VIDEO3D:
2126 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
2127 break;
2128 case E_TSP_DST_FIFO_AUDIO:
2129 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
2130 break;
2131 case E_TSP_DST_FIFO_AUDIO2:
2132 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
2133 break;
2134 case E_TSP_DST_FIFO_AUDIO3:
2135 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AC_EN);
2136 break;
2137 case E_TSP_DST_FIFO_AUDIO4:
2138 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX1_TRACE_MARK_AD_EN);
2139 break;
2140 default:
2141 break;
2142 }
2143 break;
2144 case 2:
2145 switch (eFltType)
2146 {
2147 case E_TSP_DST_FIFO_VIDEO:
2148 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
2149 break;
2150 case E_TSP_DST_FIFO_VIDEO3D:
2151 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
2152 break;
2153 case E_TSP_DST_FIFO_AUDIO:
2154 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
2155 break;
2156 case E_TSP_DST_FIFO_AUDIO2:
2157 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
2158 break;
2159 case E_TSP_DST_FIFO_AUDIO3:
2160 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AC_EN);
2161 break;
2162 case E_TSP_DST_FIFO_AUDIO4:
2163 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX2_TRACE_MARK_AD_EN);
2164 break;
2165 default:
2166 break;
2167 }
2168 break;
2169 case 3:
2170 switch (eFltType)
2171 {
2172 case E_TSP_DST_FIFO_VIDEO:
2173 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN);
2174 break;
2175 case E_TSP_DST_FIFO_VIDEO3D:
2176 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN);
2177 break;
2178 case E_TSP_DST_FIFO_AUDIO:
2179 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN);
2180 break;
2181 case E_TSP_DST_FIFO_AUDIO2:
2182 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN);
2183 break;
2184 case E_TSP_DST_FIFO_AUDIO3:
2185 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AC_EN);
2186 break;
2187 case E_TSP_DST_FIFO_AUDIO4:
2188 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_PKTDMX3_TRACE_MARK_AD_EN);
2189 break;
2190 default:
2191 break;
2192 }
2193 break;
2194 default:
2195 break;
2196 }
2197 }
2198 }
2199
HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)2200 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)
2201 {
2202
2203 if(bEn == TRUE)
2204 {
2205 switch(u32BD)
2206 {
2207 case 0:
2208 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
2209 break;
2210 case 1:
2211 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
2212 break;
2213 default:
2214 printf("Not support !!\n");
2215 break;
2216 }
2217 }
2218 else
2219 {
2220 switch(u32BD)
2221 {
2222 case 0:
2223 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
2224 break;
2225 case 1:
2226 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
2227 break;
2228 default:
2229 printf("Not support !!\n");
2230 break;
2231
2232 }
2233 }
2234
2235 }
2236
HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng,MS_U32 u32PktSize)2237 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize)
2238 {
2239 MS_U32 u32PktLen = u32PktSize;
2240 MS_U16 u16value = 0;
2241
2242 if(u32PktSize == 130)
2243 {
2244 u32PktLen = 188;
2245 }
2246 else if(u32PktSize == 134)
2247 {
2248 u32PktLen = 192;
2249 }
2250
2251 if(u32PktSize == 130 || u32PktSize == 134) //RVU
2252 {
2253 if(u32PktSize == 134)
2254 {
2255 switch(eFileEng)
2256 {
2257 case E_FILEENG_TSIF0:
2258 u16value = HW4_CFG36_RVU_TIMESTAMP_EN0;
2259 break;
2260 case E_FILEENG_TSIF1:
2261 u16value = HW4_CFG36_RVU_TIMESTAMP_EN1;
2262 break;
2263 case E_FILEENG_TSIF2:
2264 u16value = CFG4_54_RVU_TIMESTAMP_EN2;
2265 break;
2266 case E_FILEENG_TSIF3:
2267 u16value = CFG4_54_RVU_TIMESTAMP_EN3;
2268 break;
2269 default:
2270 printf("Not support !!\n");
2271 break;
2272 }
2273 }
2274
2275 switch(eFileEng)
2276 {
2277 case E_FILEENG_TSIF0:
2278 u16value |= (HW4_CFG36_RVU_PSI_EN0 | HW4_CFG36_RVU_EN0);
2279 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
2280 break;
2281 case E_FILEENG_TSIF1:
2282 u16value |= (HW4_CFG36_RVU_PSI_EN1 | HW4_CFG36_RVU_EN1);
2283 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
2284 break;
2285 case E_FILEENG_TSIF2:
2286 u16value |= (CFG4_54_RVU_PSI_EN2 | CFG4_54_RVU_EN2);
2287 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
2288 break;
2289 case E_FILEENG_TSIF3:
2290 u16value |= (CFG4_54_RVU_PSI_EN3 | CFG4_54_RVU_EN3);
2291 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
2292 break;
2293 default:
2294 printf("Not support !!\n");
2295 return;
2296 }
2297
2298 }
2299 else
2300 {
2301 switch(eFileEng)
2302 {
2303 case E_FILEENG_TSIF0:
2304 u16value = HW4_CFG36_RVU_PSI_EN0 | HW4_CFG36_RVU_EN0 | HW4_CFG36_RVU_TIMESTAMP_EN0;
2305 REG16_CLR(&_RegCtrl3->CFG3_36, u16value);
2306 break;
2307 case E_FILEENG_TSIF1:
2308 u16value = HW4_CFG36_RVU_PSI_EN1 | HW4_CFG36_RVU_EN1 | HW4_CFG36_RVU_TIMESTAMP_EN1;
2309 REG16_CLR(&_RegCtrl3->CFG3_36, u16value);
2310 break;
2311 case E_FILEENG_TSIF2:
2312 u16value = CFG4_54_RVU_PSI_EN2 | CFG4_54_RVU_EN2 | CFG4_54_RVU_TIMESTAMP_EN2;
2313 REG16_CLR(&_RegCtrl4->CFG4_54, u16value);
2314 break;
2315 case E_FILEENG_TSIF3:
2316 u16value = CFG4_54_RVU_PSI_EN3 | CFG4_54_RVU_EN3 | CFG4_54_RVU_TIMESTAMP_EN3;
2317 REG16_CLR(&_RegCtrl4->CFG4_54, u16value);
2318 break;
2319 default:
2320 printf("Not support !!\n");
2321 return;
2322 }
2323 }
2324
2325 switch(eFileEng)
2326 {
2327 case E_FILEENG_TSIF0:
2328 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE);
2329 REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) | (TSP_PKT_SIZE_MASK & (u32PktLen-1)));
2330 break;
2331 case E_FILEENG_TSIF1:
2332 REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PKT_CHK_SIZE_FIN1 & (u32PktLen-1)));
2333 break;
2334 case E_FILEENG_TSIF2:
2335 REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FIN2) | (CFG_07_PKT_CHK_SIZE_FIN2 & (u32PktLen-1)));
2336 break;
2337 case E_FILEENG_TSIF3:
2338 REG16_W(&_RegCtrl2->CFG_0C, (REG16_R(&_RegCtrl2->CFG_0C) & ~CFG_0C_PKT_CHK_SIZE_FIN3) | (CFG_0C_PKT_CHK_SIZE_FIN3 & (u32PktLen-1)));
2339 break;
2340 default:
2341 break;
2342 }
2343 }
2344
HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng,MS_U32 addr)2345 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr)
2346 {
2347 // Check MIU select
2348 MS_U8 u8MiuSel;
2349 MS_PHY phyMiuOffsetFileinAddr;
2350 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, addr);
2351
2352 switch(eFileEng)
2353 {
2354 case E_FILEENG_TSIF0:
2355 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN0_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN0_SHIFT) & REG_MIU_SEL_FILEIN0_MASK));
2356 REG32_W(&_RegCtrl->TsDma_Addr, phyMiuOffsetFileinAddr);
2357 break;
2358 case E_FILEENG_TSIF1:
2359 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN1_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN1_SHIFT) & REG_MIU_SEL_FILEIN1_MASK));
2360 REG32_W(&_RegCtrl2->CFG_30_31, phyMiuOffsetFileinAddr);
2361 break;
2362 case E_FILEENG_TSIF2:
2363 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN2_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN2_SHIFT) & REG_MIU_SEL_FILEIN2_MASK));
2364 REG32_W(&_RegCtrl2->CFG_35_36, phyMiuOffsetFileinAddr);
2365 break;
2366 case E_FILEENG_TSIF3:
2367 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN3_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN3_SHIFT) & REG_MIU_SEL_FILEIN3_MASK));
2368 REG32_W(&_RegCtrl2->CFG_3A_3B, phyMiuOffsetFileinAddr);
2369 break;
2370 default:
2371 break;
2372 }
2373 }
2374
HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng,MS_U32 size)2375 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size)
2376 {
2377 switch(eFileEng)
2378 {
2379 case E_FILEENG_TSIF0:
2380 REG32_W(&_RegCtrl->TsDma_Size, size);
2381 break;
2382 case E_FILEENG_TSIF1:
2383 REG32_W(&_RegCtrl2->CFG_32_33, size);
2384 break;
2385 case E_FILEENG_TSIF2:
2386 REG32_W(&_RegCtrl2->CFG_37_38, size);
2387 break;
2388 case E_FILEENG_TSIF3:
2389 REG32_W(&_RegCtrl2->CFG_3C_3D, size);
2390 break;
2391 default:
2392 break;
2393 }
2394 }
2395
HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)2396 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)
2397 {
2398 switch(eFileEng)
2399 {
2400 case E_FILEENG_TSIF0:
2401 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START);
2402 break;
2403 case E_FILEENG_TSIF1:
2404 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START);
2405 break;
2406 case E_FILEENG_TSIF2:
2407 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START);
2408 break;
2409 case E_FILEENG_TSIF3:
2410 REG16_SET(&_RegCtrl2->CFG_3E, CFG_3E_FILEIN_CTRL_TSIF3_START);
2411 break;
2412 default:
2413 break;
2414 }
2415 }
2416
HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)2417 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)
2418 {
2419 switch (eFileEng)
2420 {
2421 case E_FILEENG_TSIF0:
2422 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
2423 return TRUE;
2424 case E_FILEENG_TSIF1:
2425 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
2426 return TRUE;
2427 case E_FILEENG_TSIF2:
2428 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
2429 return TRUE;
2430 case E_FILEENG_TSIF3:
2431 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE);
2432 return TRUE;
2433 default:
2434 return FALSE;
2435 }
2436 }
2437
HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)2438 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)
2439 {
2440 switch (eFileEng)
2441 {
2442 case E_FILEENG_TSIF0:
2443 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
2444 return TRUE;
2445 case E_FILEENG_TSIF1:
2446 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
2447 return TRUE;
2448 case E_FILEENG_TSIF2:
2449 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
2450 return TRUE;
2451 case E_FILEENG_TSIF3:
2452 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE);
2453 return TRUE;
2454 default:
2455 return FALSE;
2456 }
2457 }
2458
HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)2459 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)
2460 {
2461 switch(eFileEng)
2462 {
2463 case E_FILEENG_TSIF0:
2464 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START));
2465 break;
2466 case E_FILEENG_TSIF1:
2467 REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START));
2468 break;
2469 case E_FILEENG_TSIF2:
2470 REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START));
2471 break;
2472 case E_FILEENG_TSIF3:
2473 REG16_SET(&_RegCtrl2->CFG_3E, (CFG_3E_FILEIN_INIT_TRUST_TSIF3 | CFG_3E_FILEIN_CTRL_TSIF3_START));
2474 break;
2475 default:
2476 break;
2477 }
2478 }
2479
HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng,MS_BOOL bEn)2480 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn)
2481 {
2482 if(bEn)
2483 {
2484 switch(eFileEng)
2485 {
2486 case E_FILEENG_TSIF0:
2487 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
2488 break;
2489 case E_FILEENG_TSIF1:
2490 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
2491 break;
2492 case E_FILEENG_TSIF2:
2493 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
2494 break;
2495 case E_FILEENG_TSIF3:
2496 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3);
2497 break;
2498 default:
2499 break;
2500 }
2501 }
2502 else
2503 {
2504 switch(eFileEng)
2505 {
2506 case E_FILEENG_TSIF0:
2507 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
2508 break;
2509 case E_FILEENG_TSIF1:
2510 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
2511 break;
2512 case E_FILEENG_TSIF2:
2513 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
2514 break;
2515 case E_FILEENG_TSIF3:
2516 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3);
2517 break;
2518 default:
2519 break;
2520 }
2521 }
2522 }
2523
HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)2524 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
2525 {
2526 if(bEnable)
2527 {
2528 switch(eFileEng)
2529 {
2530 case E_FILEENG_TSIF0:
2531 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
2532 break;
2533 case E_FILEENG_TSIF1:
2534 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
2535 break;
2536 case E_FILEENG_TSIF2:
2537 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
2538 break;
2539 case E_FILEENG_TSIF3:
2540 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
2541 break;
2542 default:
2543 break;
2544 }
2545 }
2546 else
2547 {
2548 switch(eFileEng)
2549 {
2550 case E_FILEENG_TSIF0:
2551 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
2552 break;
2553 case E_FILEENG_TSIF1:
2554 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
2555 break;
2556 case E_FILEENG_TSIF2:
2557 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
2558 break;
2559 case E_FILEENG_TSIF3:
2560 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
2561 break;
2562 default:
2563 break;
2564 }
2565 }
2566 }
2567
HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)2568 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)
2569 {
2570 switch(eFileEng)
2571 {
2572 case E_FILEENG_TSIF0:
2573 return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT));
2574 case E_FILEENG_TSIF1:
2575 return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT));
2576 case E_FILEENG_TSIF2:
2577 return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT));
2578 case E_FILEENG_TSIF3:
2579 return (CFG_41_REG_TSIF3_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT));
2580
2581 default:
2582 return 0;
2583 }
2584 }
2585
HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)2586 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)
2587 {
2588 switch(eFileEng)
2589 {
2590 case E_FILEENG_TSIF0:
2591 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT);
2592 case E_FILEENG_TSIF1:
2593 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT);
2594 case E_FILEENG_TSIF2:
2595 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT);
2596 case E_FILEENG_TSIF3:
2597 return (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT);
2598 default:
2599 return 0;
2600 }
2601 }
2602
HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)2603 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)
2604 {
2605 switch(eFileEng)
2606 {
2607 case E_FILEENG_TSIF0:
2608 return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
2609 case E_FILEENG_TSIF1:
2610 return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2611 case E_FILEENG_TSIF2:
2612 return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2613 case E_FILEENG_TSIF3:
2614 return ((REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2615 default:
2616 return 0;
2617 }
2618 }
2619
HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng,MS_U32 delay,MS_BOOL bEnable)2620 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable)
2621 {
2622 if(bEnable)
2623 {
2624 switch(eFileEng)
2625 {
2626 case E_FILEENG_TSIF0:
2627 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK);
2628 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
2629 break;
2630 case E_FILEENG_TSIF1:
2631 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1);
2632 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
2633 break;
2634 case E_FILEENG_TSIF2:
2635 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2);
2636 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
2637 break;
2638 case E_FILEENG_TSIF3:
2639 REG16_W(&_RegCtrl2->CFG_0D, delay & CFG_0D_TSP_FILE_TIMER3);
2640 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3);
2641 break;
2642 default:
2643 break;
2644 }
2645 }
2646 else
2647 {
2648 switch(eFileEng)
2649 {
2650 case E_FILEENG_TSIF0:
2651 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
2652 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000);
2653 break;
2654 case E_FILEENG_TSIF1:
2655 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
2656 REG16_W(&_RegCtrl2->CFG_03, 0x0000);
2657 break;
2658 case E_FILEENG_TSIF2:
2659 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
2660 REG16_W(&_RegCtrl2->CFG_08, 0x0000);
2661 break;
2662 case E_FILEENG_TSIF3:
2663 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3);
2664 REG16_W(&_RegCtrl2->CFG_0D, 0x0000);
2665 break;
2666 default:
2667 break;
2668 }
2669 }
2670 }
2671
HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)2672 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)
2673 {
2674 switch(eFileEng)
2675 {
2676 case E_FILEENG_TSIF0:
2677 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE);
2678 case E_FILEENG_TSIF1:
2679 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE);
2680 case E_FILEENG_TSIF2:
2681 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE);
2682 case E_FILEENG_TSIF3:
2683 return !(REG16_R(&_RegCtrl2->CFG_3E) & CFG_3E_FILEIN_CTRL_TSIF3_DONE);
2684 default:
2685 return 0;
2686 }
2687 }
2688
2689 // Only used by [HW test code]
2690 /*
2691 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng)
2692 {
2693 return !HAL_TSP_Filein_Status(eFileEng);
2694 }
2695 */
2696
2697 //To do : only tsif0 has pause functionality in Kaiser
HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)2698 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)
2699 {
2700 TSP_HAL_FileState state = E_TSP_HAL_FILE_STATE_INVALID;
2701 MS_U32 u32Status = HAL_TSP_Filein_Status(eFileEng);
2702
2703 // @FIXME in kaiser u01 only tsif0 file eng has pause function
2704 switch (eFileEng)
2705 {
2706 case E_FILEENG_TSIF0:
2707 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE )
2708 {
2709 state = E_TSP_HAL_FILE_STATE_PAUSE;
2710 }
2711 else if (u32Status)
2712 {
2713 state = E_TSP_HAL_FILE_STATE_BUSY;
2714 }
2715 else
2716 {
2717 state = E_TSP_HAL_FILE_STATE_IDLE;
2718 }
2719 break;
2720 case E_FILEENG_TSIF1:
2721 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF1_FILE_PAUSE)
2722 {
2723 state = E_TSP_HAL_FILE_STATE_PAUSE;
2724 }
2725 else if (u32Status)
2726 {
2727 state = E_TSP_HAL_FILE_STATE_BUSY;
2728 }
2729 else
2730 {
2731 state = E_TSP_HAL_FILE_STATE_IDLE;
2732 }
2733 break;
2734 case E_FILEENG_TSIF2:
2735 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF2_FILE_PAUSE)
2736 {
2737 state = E_TSP_HAL_FILE_STATE_PAUSE;
2738 }
2739 else if (u32Status)
2740 {
2741 state = E_TSP_HAL_FILE_STATE_BUSY;
2742 }
2743 else
2744 {
2745 state = E_TSP_HAL_FILE_STATE_IDLE;
2746 }
2747 break;
2748 case E_FILEENG_TSIF3:
2749 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF3_FILE_PAUSE)
2750 {
2751 state = E_TSP_HAL_FILE_STATE_PAUSE;
2752 }
2753 else if (u32Status)
2754 {
2755 state = E_TSP_HAL_FILE_STATE_BUSY;
2756 }
2757 else
2758 {
2759 state = E_TSP_HAL_FILE_STATE_IDLE;
2760 }
2761 break;
2762 default:
2763 state = E_TSP_HAL_FILE_STATE_INVALID;
2764 break;
2765 }
2766 return state;
2767 }
2768
HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)2769 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)
2770 {
2771 if(bSet)
2772 {
2773 switch(eFileEng)
2774 {
2775 case E_FILEENG_TSIF0:
2776 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
2777 break;
2778 case E_FILEENG_TSIF1:
2779 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
2780 break;
2781 case E_FILEENG_TSIF2:
2782 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
2783 break;
2784 case E_FILEENG_TSIF3:
2785 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3);
2786 break;
2787 default:
2788 break;
2789 }
2790 }
2791 else
2792 {
2793 switch(eFileEng)
2794 {
2795 case E_FILEENG_TSIF0:
2796 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
2797 break;
2798 case E_FILEENG_TSIF1:
2799 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
2800 break;
2801 case E_FILEENG_TSIF2:
2802 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
2803 break;
2804 case E_FILEENG_TSIF3:
2805 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3);
2806 break;
2807 default:
2808 break;
2809 }
2810 }
2811
2812 }
2813
HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng,MS_BOOL bEn)2814 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn)
2815 {
2816 if(bEn)
2817 {
2818 switch(eFileEng)
2819 {
2820 case E_FILEENG_TSIF0:
2821 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
2822 break;
2823 case E_FILEENG_TSIF1:
2824 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
2825 break;
2826 case E_FILEENG_TSIF2:
2827 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
2828 break;
2829 case E_FILEENG_TSIF3:
2830 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3);
2831 default:
2832 break;
2833 }
2834 }
2835 else
2836 {
2837 switch(eFileEng)
2838 {
2839 case E_FILEENG_TSIF0:
2840 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
2841 break;
2842 case E_FILEENG_TSIF1:
2843 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
2844 break;
2845 case E_FILEENG_TSIF2:
2846 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
2847 break;
2848 case E_FILEENG_TSIF3:
2849 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3);
2850 break;
2851 default:
2852 break;
2853 }
2854 }
2855 }
2856
2857 #if 0
2858 static void _HAL_TSP_FILEIN_ResetPktTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32InitTimeStamp)
2859 {
2860 switch(eFileEng)
2861 {
2862 case E_FILEENG_TSIF0:
2863 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
2864 REG32_W(&_RegCtrl6->CFG6_50_51, u32InitTimeStamp);
2865 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
2866 break;
2867 case E_FILEENG_TSIF1:
2868 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
2869 REG32_W(&_RegCtrl6->CFG6_52_53, u32InitTimeStamp);
2870 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
2871 break;
2872 case E_FILEENG_TSIF2:
2873 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
2874 REG32_W(&_RegCtrl6->CFG6_54_55, u32InitTimeStamp);
2875 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
2876 break;
2877 case E_FILEENG_TSIF3:
2878 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3);
2879 REG32_W(&_RegCtrl6->CFG6_56_57, u32InitTimeStamp);
2880 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3);
2881 break;
2882 default:
2883 break;
2884 }
2885 }
2886 #endif
2887
HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32Stamp)2888 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp)
2889 {
2890 switch(eFileEng)
2891 {
2892 case E_FILEENG_TSIF0:
2893 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
2894 REG32_W(&_RegCtrl->LPcr2, u32Stamp);
2895 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
2896 break;
2897 case E_FILEENG_TSIF1:
2898 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
2899 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp);
2900 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
2901 break;
2902 case E_FILEENG_TSIF2:
2903 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
2904 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp);
2905 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
2906 break;
2907 case E_FILEENG_TSIF3:
2908 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3);
2909 REG32_W(&_RegCtrl2->CFG_54_55, u32Stamp);
2910 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3);
2911 break;
2912 default:
2913 break;
2914 }
2915
2916 // Fix pass_pkt_timestamp will hang issue by TSP8,0x60[3] : reg_init_timestamp_restart_en
2917 // _HAL_TSP_FILEIN_ResetPktTimeStamp(eFileEng, 0);
2918 }
2919
HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng,TSP_HAL_TimeStamp_Clk eTimeStampClk)2920 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk)
2921 {
2922 switch(eFileEng)
2923 {
2924 case E_FILEENG_TSIF0:
2925 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2926 {
2927 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
2928 }
2929 else
2930 {
2931 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
2932 }
2933 break;
2934 case E_FILEENG_TSIF1:
2935 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2936 {
2937 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
2938 }
2939 else
2940 {
2941 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
2942 }
2943 break;
2944 case E_FILEENG_TSIF2:
2945 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2946 {
2947 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
2948 }
2949 else
2950 {
2951 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
2952 }
2953 break;
2954 case E_FILEENG_TSIF3:
2955 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2956 {
2957 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M);
2958 }
2959 else
2960 {
2961 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M);
2962 }
2963 break;
2964 default:
2965 break;
2966 }
2967 }
2968
HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)2969 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)
2970 {
2971 MS_U32 u32Stamp = 0;
2972 switch(eFileEng)
2973 {
2974 case E_FILEENG_TSIF0:
2975 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
2976 u32Stamp = REG32_R(&_RegCtrl->LPcr2);
2977 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
2978 break;
2979 case E_FILEENG_TSIF1:
2980 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
2981 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51);
2982 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
2983 break;
2984 case E_FILEENG_TSIF2:
2985 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
2986 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53);
2987 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
2988 break;
2989 case E_FILEENG_TSIF3:
2990 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3);
2991 u32Stamp = REG32_R(&_RegCtrl2->CFG_54_55);
2992 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3);
2993 break;
2994 default:
2995 u32Stamp = 0;
2996 break;
2997 }
2998 return u32Stamp;
2999 }
3000
HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)3001 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)
3002 {
3003 switch(eFileEng)
3004 {
3005 case E_FILEENG_TSIF0:
3006 return REG32_R(&_RegCtrl->TimeStamp_FileIn);
3007 case E_FILEENG_TSIF1:
3008 return REG32_R(&_RegCtrl2->CFG_42_43);
3009 case E_FILEENG_TSIF2:
3010 return REG32_R(&_RegCtrl2->CFG_44_45);
3011 case E_FILEENG_TSIF3:
3012 return REG32_R(&_RegCtrl2->CFG_46_47);
3013 default:
3014 break;
3015 }
3016 return 0;
3017 }
3018
HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng,MS_PHY * pu32Addr)3019 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr)
3020 {
3021 switch(eFileEng)
3022 {
3023 case E_FILEENG_TSIF0:
3024 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK);
3025 break;
3026 case E_FILEENG_TSIF1:
3027 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1);
3028 break;
3029 case E_FILEENG_TSIF2:
3030 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2);
3031 break;
3032 case E_FILEENG_TSIF3:
3033 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6E_6F) & CFG_6E_6F_TSP2MI_RADDR_S_TSIF3);
3034 break;
3035 default:
3036 break;
3037 }
3038
3039 }
3040
HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)3041 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
3042 {
3043 if(bEnable)
3044 {
3045 switch(eFileEng)
3046 {
3047 case E_FILEENG_TSIF0:
3048 REG16_SET(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET);
3049 break;
3050 case E_FILEENG_TSIF1:
3051 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
3052 break;
3053 case E_FILEENG_TSIF2:
3054 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
3055 break;
3056 case E_FILEENG_TSIF3:
3057 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3);
3058 break;
3059 default:
3060 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
3061 break;
3062 }
3063 }
3064 else
3065 {
3066 switch(eFileEng)
3067 {
3068 case E_FILEENG_TSIF0:
3069 REG16_CLR(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET);
3070 break;
3071 case E_FILEENG_TSIF1:
3072 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
3073 break;
3074 case E_FILEENG_TSIF2:
3075 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
3076 break;
3077 case E_FILEENG_TSIF3:
3078 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3);
3079 break;
3080 default:
3081 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
3082 break;
3083 }
3084 }
3085 }
3086
HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng,MS_BOOL bEnable,MS_U32 u32Key)3087 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key)
3088 {
3089 if(bEnable)
3090 {
3091 switch(eFileEng)
3092 {
3093 case E_FILEENG_TSIF0:
3094 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK));
3095 break;
3096 case E_FILEENG_TSIF1:
3097 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK));
3098 break;
3099 case E_FILEENG_TSIF2:
3100 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK));
3101 break;
3102 case E_FILEENG_TSIF3:
3103 REG16_W(&_RegCtrl2->CFG_77, (u32Key & CFG_77_FI_MOBF_INDEC_TSIF3_MASK));
3104 break;
3105 default:
3106 break;
3107 }
3108 }
3109 else
3110 {
3111 switch(eFileEng)
3112 {
3113 case E_FILEENG_TSIF0:
3114 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0);
3115 break;
3116 case E_FILEENG_TSIF1:
3117 REG16_W(&_RegCtrl2->CFG_75, 0);
3118 break;
3119 case E_FILEENG_TSIF2:
3120 REG16_W(&_RegCtrl2->CFG_76, 0);
3121 break;
3122 case E_FILEENG_TSIF3:
3123 REG16_W(&_RegCtrl2->CFG_77, 0);
3124 break;
3125 default:
3126 break;
3127 }
3128 }
3129 }
3130
HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)3131 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
3132 {
3133 switch (ePidFltSrc)
3134 {
3135 case E_TSP_PIDFLT_LIVE0:
3136 return TSP_PIDFLT_TSIF0;
3137 case E_TSP_PIDFLT_LIVE1:
3138 return TSP_PIDFLT_TSIF2;
3139 case E_TSP_PIDFLT_LIVE2:
3140 return TSP_PIDFLT_TSIF3;
3141 case E_TSP_PIDFLT_LIVE3:
3142 return TSP_PIDFLT_TSIF1;
3143 case E_TSP_PIDFLT_FILE0:
3144 return TSP_PIDFLT_TSIF1;
3145 case E_TSP_PIDFLT_FILE1:
3146 return TSP_PIDFLT_TSIF3;
3147 case E_TSP_PIDFLT_FILE2:
3148 return TSP_PIDFLT_TSIF0;
3149 case E_TSP_PIDFLT_FILE3:
3150 return TSP_PIDFLT_TSIF2;
3151 default:
3152 printf("[TSP_ERR][%s][%d] Wrong filter source!!!\n",__FUNCTION__, __LINE__);
3153 break;
3154 }
3155
3156 return 0;
3157 }
3158
HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId,MS_U32 u32FltIn)3159 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn)
3160 {
3161 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
3162 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_IN_MASK) | ((u32FltIn << TSP_PIDFLT_TSIF_SHFT) & TSP_PIDFLT_IN_MASK));
3163 }
3164
HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId,MS_U32 u32FltOut)3165 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut)
3166 {
3167 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3168 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_OUT_MASK)) | (u32FltOut & TSP_PIDFLT_OUT_MASK)));
3169 }
3170
HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId,MS_U32 u32SrcID)3171 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID)
3172 {
3173 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3174 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcID << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
3175 }
3176
HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId,MS_U32 u32SecFltId)3177 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId)
3178 {
3179 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3180 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
3181 }
3182
HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId,MS_U32 u32PVREng,MS_BOOL bEn)3183 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn)
3184 {
3185 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3186 if(bEn)
3187 {
3188 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK) | (((1 << u32PVREng) << TSP_PIDFLT_PVRFLT_SHFT) & TSP_PIDFLT_PVRFLT_MASK));
3189 }
3190 else
3191 {
3192 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK));
3193 }
3194 }
3195
HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId,MS_U8 u8Enable)3196 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable)
3197 {
3198 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3199 if(u8Enable)
3200 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) | (TSP_PID_FLT_PKTPUSH_PASS));
3201 else
3202 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) & ~(TSP_PID_FLT_PKTPUSH_PASS));
3203 }
3204
HAL_TSP_PidFlt_SetPid(MS_U32 fltId,MS_U32 u32Pid)3205 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32Pid)
3206 {
3207 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
3208 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PID_MASK) | ((u32Pid << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
3209 }
3210
3211 //-------------------------------------------------------------------------------------------------
3212 // For section filter part
3213 //-------------------------------------------------------------------------------------------------
3214
HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)3215 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)
3216 {
3217 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN);
3218 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT));
3219 }
3220
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFlt,MS_U32 u32FltType)3221 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType)
3222 {
3223 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_USER_MASK) | (u32FltType << TSP_SECFLT_USER_SHFT));
3224 }
3225
3226
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFlt,MS_U32 u32SecFltMode)3227 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode)
3228 {
3229 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
3230 }
3231
3232
3233 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFlt,MS_U8 * pu8Mask)3234 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask)
3235 {
3236 MS_U32 i,j;
3237 MS_U32 u32Temp;
3238
3239 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3240 {
3241 j = (i << 2);
3242 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
3243 TSP32_IdrW((TSP32 *)&pSecFlt->Mask[i], u32Temp);
3244 }
3245 }
3246
3247
3248 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFlt,MS_U8 * pu8NMask)3249 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask)
3250 {
3251 MS_U32 i,j;
3252 MS_U32 u32Temp;
3253
3254 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3255 {
3256 j = (i<< 2);
3257 u32Temp = (pu8NMask[j]) | (pu8NMask[j+ 1] << 8 ) | (pu8NMask[j+ 2] << 16 )| (pu8NMask[j+ 3] << 24);
3258 TSP32_IdrW((TSP32 *)&pSecFlt->NMask[i], u32Temp);
3259 }
3260 }
3261
3262
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFlt,MS_U8 * pu8Match)3263 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match)
3264 {
3265 MS_U32 i,j;
3266 MS_U32 u32Temp;
3267
3268 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3269 {
3270 j = (i<< 2);
3271 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
3272 TSP32_IdrW((TSP32 *)&pSecFlt->Match[i], u32Temp);
3273 }
3274 }
3275
3276
3277 //[LIMIT] Is impossible to identify the pidfilter is assigned a secfilter/buffer or not
HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt * pSecFlt,MS_U16 u16BufId)3278 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId)
3279 {
3280 TSP32_IdrW( &pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_SECBUF_MASK)
3281 | ((u16BufId << TSP_SECFLT_SECBUF_SHFT) & TSP_SECFLT_SECBUF_MASK) );
3282 }
3283
3284
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFlt)3285 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt)
3286 {
3287 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_SECBUF_MASK) >> TSP_SECFLT_SECBUF_SHFT);
3288 }
3289
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFlt)3290 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt)
3291 {
3292 return (TSP32_IdrR(pPidFlt) & TSP_PIDFLT_OUT_MASK);
3293 }
3294
HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)3295 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)
3296 {
3297 // don't have to implement no reference
3298 }
3299
3300
3301 // @FIXME: Is it secflt or secbuf?
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFlt)3302 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt)
3303 {
3304 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
3305 }
3306
3307
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFlt)3308 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt)
3309 {
3310 TSP32_IdrW(&pSecFlt->Ctrl, 0);
3311 }
3312
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFlt)3313 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt)
3314 {
3315 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
3316 }
3317
3318
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFlt)3319 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFlt)
3320 {
3321 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
3322 }
3323
3324
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFlt)3325 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFlt)
3326 {
3327 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_PCRRST);
3328 }
3329
3330
HAL_TSP_SecFlt_TryAlloc(REG_SecFlt * pSecFlt,MS_U16 u16TSPId)3331 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId)
3332 {
3333 MS_U32 reg;
3334
3335 //_TSP_HW_Lock();
3336
3337 // rmn counter doesn't need 32bit (check 13818) so we use some of it to store owner and alloc info
3338 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & (TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
3339 if (reg & TSP_SECFLT_ALLOC_MASK)
3340 {
3341 //_TSP_HW_Unlock();
3342 return FALSE;
3343 }
3344 reg |= TSP_SECFLT_ALLOC_MASK | ((u16TSPId<<TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK);
3345 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
3346
3347 //_TSP_HW_Unlock();
3348 return TRUE;
3349 }
3350
3351
HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt * pSecFlt,MS_BOOL bSet)3352 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet)
3353 {
3354 if(bSet)
3355 {
3356 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_MODE_AUTO_CRCCHK);
3357 }
3358 else
3359 {
3360 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_AUTO_CRCCHK);
3361 }
3362 }
3363
3364
HAL_TSP_SecFlt_Free(REG_SecFlt * pSecFlt)3365 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt)
3366 {
3367 MS_U32 reg;
3368
3369 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
3370 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
3371 }
3372
HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt * pSecFlt)3373 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt)
3374 {
3375 TSP32_IdrW(&pSecFlt->RmnCnt, TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECBUF_RMNCNT_MASK));
3376 }
3377
3378 //-------------------------------------------------------------------------------------------------
3379 // For section buffer part
3380 //-------------------------------------------------------------------------------------------------
HAL_TSP_SecBuf_SetBuf(REG_SecBuf * pSecBuf,MS_U32 u32StartAddr,MS_U32 u32BufSize)3381 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize)
3382 {
3383 // Check MIU select
3384 MS_U8 u8MiuSel;
3385 MS_PHY phyMiuOffsetSecBuf;
3386 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetSecBuf, u32StartAddr);
3387 REG16_W(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW, (REG16_R(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW) & (~REG_MIU_SEL_SECTION_MASK)) | ((u8MiuSel << REG_MIU_SEL_SECTION_SHIFT) & REG_MIU_SEL_SECTION_MASK));
3388
3389 MS_U32 owner;
3390 // To avoid SW read hidden HW byte enable information.
3391 owner = TSP32_IdrR(&pSecBuf->Start); // @FIXME local variable but not used?
3392
3393 TSP32_IdrW(&pSecBuf->Start, phyMiuOffsetSecBuf);
3394 TSP32_IdrW(&pSecBuf->End, phyMiuOffsetSecBuf + u32BufSize);
3395 }
3396
3397
HAL_TSP_SecBuf_SetRead(REG_SecBuf * pSecBuf,MS_U32 u32ReadAddr)3398 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr)
3399 {
3400 TSP32_IdrW(&pSecBuf->Read, u32ReadAddr);
3401 }
3402
3403
HAL_TSP_SecBuf_GetStart(REG_SecBuf * pSecBuf)3404 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf)
3405 {
3406 return TSP32_IdrR(&pSecBuf->Start);
3407 }
3408
3409
HAL_TSP_SecBuf_GetEnd(REG_SecBuf * pSecBuf)3410 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf)
3411 {
3412 return TSP32_IdrR(&pSecBuf->End);
3413 }
3414
3415
HAL_TSP_SecBuf_GetBufCur(REG_SecBuf * pSecBuf)3416 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf)
3417 {
3418 //BufCur is control by firmware
3419 //we use Cur pointer to receive the newest data
3420 //and use write pointer to guarantee that the data between
3421 //read and write pointer is correct, so that user won't get
3422 //unverified data.
3423 return TSP32_IdrR(&pSecBuf->Cur);
3424 }
3425
3426
HAL_TSP_SecBuf_Reset(REG_SecBuf * pSecBuf)3427 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf)
3428 {
3429 MS_U32 start;
3430
3431 start = TSP32_IdrR(&pSecBuf->Start);
3432
3433 TSP32_IdrW(&pSecBuf->Cur, start);
3434 TSP32_IdrW(&pSecBuf->Read, start);
3435 TSP32_IdrW(&pSecBuf->Write, start);
3436
3437 start = ( (MS_VIRT)pSecBuf - (MS_VIRT)REG_SECBUF_BASE ) / sizeof(REG_SecBuf) ;
3438 HAL_TSP_HCMD_BufRst(start); // @FIXME seems we don't need to do this
3439 }
3440
3441
HAL_TSP_SecBuf_GetRead(REG_SecBuf * pSecBuf)3442 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf)
3443 {
3444 return TSP32_IdrR((TSP32*)&pSecBuf->Read);
3445 }
3446
3447
HAL_TSP_SecBuf_GetWrite(REG_SecBuf * pSecBuf)3448 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf)
3449 {
3450 return TSP32_IdrR((TSP32*)&pSecBuf->Write);
3451 }
3452
3453
HAL_TSP_SecBuf_TryAlloc(REG_SecBuf * pSecBuf,MS_U16 u16TSPId)3454 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId)
3455 {
3456 // @TODO make sure the owner and alloc info is necessary or not.
3457 MS_U32 reg;
3458
3459 //_TSP_HW_Lock();
3460
3461 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK);
3462 //if (reg & TSP_SECBUF_ALLOC_MASK)
3463 //{
3464 // //_TSP_HW_Unlock();
3465 // return FALSE;
3466 //}
3467 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK);
3468 //TSP32_IdrW(&pSecBuf->Start, reg);
3469
3470 //_TSP_HW_Unlock();
3471 return TRUE;
3472 }
3473
3474
HAL_TSP_SecBuf_Free(REG_SecBuf * pSecBuf)3475 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf)
3476 {
3477 // @TODO ref to HAL_TSP_SecBuf_TryAlloc
3478 TSP32_IdrW(&pSecBuf->Start, 0x0);
3479 }
3480
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFlt)3481 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt)
3482 {
3483 return ((TSP32_IdrR(pPidFlt) & TSP_PIDFLT_PID_MASK) >> TSP_PIDFLT_PID_SHFT);
3484 }
3485
HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId,MS_BOOL bEnable)3486 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable)
3487 {
3488 switch(pcrFltId)
3489 {
3490 case 0:
3491 if(bEnable)
3492 {
3493 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
3494 }
3495 else
3496 {
3497 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
3498 }
3499 break;
3500 case 1:
3501 if(bEnable)
3502 {
3503 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
3504 }
3505 else
3506 {
3507 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
3508 }
3509 break;
3510 case 2:
3511 if(bEnable)
3512 {
3513 REG16_SET(&_RegCtrl8_1->CFG8_44, CFG8_44_PIDFLT_PCR2_EN);
3514 }
3515 else
3516 {
3517 REG16_CLR(&_RegCtrl8_1->CFG8_44, CFG8_44_PIDFLT_PCR2_EN);
3518 }
3519 break;
3520 case 3:
3521 if(bEnable)
3522 {
3523 REG16_SET(&_RegCtrl8_1->CFG8_45, CFG8_45_PIDFLT_PCR3_EN);
3524 }
3525 else
3526 {
3527 REG16_CLR(&_RegCtrl8_1->CFG8_45, CFG8_45_PIDFLT_PCR3_EN);
3528 }
3529 break;
3530 default:
3531 break;
3532 }
3533 }
3534
HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId,MS_U32 u32Pid)3535 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid)
3536 {
3537 switch(pcrFltId)
3538 {
3539 case 0:
3540 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid);
3541 break;
3542 case 1:
3543 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid);
3544 break;
3545 case 2:
3546 REG16_MSK_W(&_RegCtrl8_1->CFG8_44, CFG8_44_PIDFLT_PCR2_PID_MASK, u32Pid);
3547 break;
3548 case 3:
3549 REG16_MSK_W(&_RegCtrl8_1->CFG8_45, CFG8_45_PIDFLT_PCR3_PID_MASK, u32Pid);
3550 break;
3551 default:
3552 break;
3553 }
3554
3555 }
3556
HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)3557 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)
3558 {
3559 switch(pcrFltId)
3560 {
3561 case 0:
3562 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK);
3563 case 1:
3564 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK);
3565 case 2:
3566 return (REG16_R(&_RegCtrl8_1->CFG8_44) & CFG8_44_PIDFLT_PCR2_PID_MASK);
3567 case 3:
3568 return (REG16_R(&_RegCtrl8_1->CFG8_45) & CFG8_45_PIDFLT_PCR3_PID_MASK);
3569 default:
3570 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
3571 return PVR_PIDFLT_DEF;
3572 }
3573 }
3574
HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId,TSP_PCR_SRC src)3575 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src)
3576 {
3577 switch(pcrFltId)
3578 {
3579 case 0:
3580 //src 0
3581 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT);
3582 break;
3583 case 1:
3584 //src 1
3585 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT);
3586 break;
3587 case 2:
3588 //src 2
3589 REG16_MSK_W(&_RegCtrl8_1->CFG8_42, CFG8_42_PCR2_SRC_MASK, src << CFG8_42_PCR2_SRC_SHIFT);
3590 break;
3591 case 3:
3592 //src 3
3593 REG16_MSK_W(&_RegCtrl8_1->CFG8_43, CFG8_43_PCR3_SRC_MASK, src << CFG8_43_PCR3_SRC_SHIFT);
3594 break;
3595 default:
3596 break;
3597 }
3598 }
3599
HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId,MS_U32 u32SrcId)3600 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId)
3601 {
3602 switch(pcrFltId)
3603 {
3604 case 0:
3605 REG16_MSK_W(&_RegCtrl3->CFG3_72, CFG3_72_PIDFLT_PCR0_SRC_ID_MASK, u32SrcId<<CFG3_72_PIDFLT_PCR0_SRC_ID_SHIFT);
3606 break;
3607 case 1:
3608 REG16_MSK_W(&_RegCtrl3->CFG3_72, CFG3_72_PIDFLT_PCR1_SRC_ID_MASK, u32SrcId<<CFG3_72_PIDFLT_PCR1_SRC_ID_SHIFT);
3609 break;
3610 case 2:
3611 REG16_MSK_W(&_RegCtrl8_1->CFG8_46, CFG8_46_REG_PIDFLT_PCR2_SRC_ID_MASK, u32SrcId<<CFG8_46_REG_PIDFLT_PCR2_SRC_ID_SHIFT);
3612 break;
3613 case 3:
3614 REG16_MSK_W(&_RegCtrl8_1->CFG8_46, CFG8_46_REG_PIDFLT_PCR3_SRC_ID_MASK, u32SrcId<<CFG8_46_REG_PIDFLT_PCR3_SRC_ID_SHIFT);
3615 break;
3616 default:
3617 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
3618 break;
3619 }
3620 }
3621
HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId,TSP_PCR_SRC * pPcrSrc)3622 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc)
3623 {
3624 switch(pcrFltId)
3625 {
3626 case 0:
3627 //src 0
3628 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT;
3629 break;
3630 case 1:
3631 //src 1
3632 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT;
3633 break;
3634 case 2:
3635 //src 2
3636 *pPcrSrc = (REG16_R(&_RegCtrl8_1->CFG8_42) & CFG8_42_PCR2_SRC_MASK) >> CFG8_42_PCR2_SRC_SHIFT;
3637 break;
3638 case 3:
3639 //src 3
3640 *pPcrSrc = (REG16_R(&_RegCtrl8_1->CFG8_43) & CFG8_43_PCR3_SRC_MASK) >> CFG8_43_PCR3_SRC_SHIFT;
3641 break;
3642 default:
3643 break;
3644 }
3645 }
3646
HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)3647 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
3648 {
3649 TSP_PCR_SRC ePcrSrc = E_TSP_PCR_SRC_INVALID;
3650 switch(ePidFltSrc)
3651 {
3652 case E_TSP_PIDFLT_LIVE0:
3653 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
3654 break;
3655 case E_TSP_PIDFLT_LIVE1:
3656 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
3657 break;
3658 case E_TSP_PIDFLT_LIVE2:
3659 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
3660 break;
3661 case E_TSP_PIDFLT_LIVE3:
3662 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
3663 break;
3664 case E_TSP_PIDFLT_FILE0:
3665 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
3666 break;
3667 case E_TSP_PIDFLT_FILE1:
3668 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
3669 break;
3670 case E_TSP_PIDFLT_FILE2:
3671 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
3672 break;
3673 case E_TSP_PIDFLT_FILE3:
3674 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
3675 break;
3676 default:
3677 printf("[TSP_ERR][%s][%d] Wrong Flt Src type!!!\n",__FUNCTION__,__LINE__);
3678 break;
3679 }
3680 return ePcrSrc;
3681
3682 }
3683
3684
HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)3685 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
3686 {
3687 switch(pcrFltId)
3688 {
3689 case 0:
3690 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
3691 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L);
3692 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1;
3693 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
3694 break;
3695 case 1:
3696 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
3697 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L);
3698 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1;
3699 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
3700 break;
3701 case 2:
3702 REG16_SET(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_READ);
3703 *pu32Pcr = REG32_R(&_RegCtrl8_1->CFG8_60_61);
3704 *pu32Pcr_H = (MS_U32)(REG16_R(&_RegCtrl8_1->CFG8_62) & 0x1);
3705 REG16_CLR(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_READ);
3706 break;
3707 case 3:
3708 REG16_SET(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_READ);
3709 *pu32Pcr = REG32_R(&_RegCtrl8_1->CFG8_63_64);
3710 *pu32Pcr_H = (MS_U32)(REG16_R(&_RegCtrl8_1->CFG8_65) & 0x1);
3711 REG16_CLR(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_READ);
3712 break;
3713
3714 default:
3715 break;
3716 }
3717 }
3718
HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)3719 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)
3720 {
3721 switch(pcrFltId)
3722 {
3723 case 0:
3724 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
3725 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
3726 break;
3727 case 1:
3728 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
3729 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
3730 break;
3731 case 2:
3732 REG16_CLR(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_RESET);
3733 REG16_SET(&_RegCtrl8_1->CFG8_42, CFG8_42_REG_PCR2_RESET);
3734 break;
3735 case 3:
3736 REG16_CLR(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_RESET);
3737 REG16_SET(&_RegCtrl8_1->CFG8_43, CFG8_43_REG_PCR3_RESET);
3738 break;
3739 default:
3740 break;
3741 }
3742 }
3743
3744
HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)3745 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)
3746 {
3747 switch(pcrFltId)
3748 {
3749 case 0:
3750 //REG16_CLR(&_RegCtrl->HwInt2_Stat,TSP_HWINT2_PCR0_UPDATE_END);
3751 REG16_W(&_RegCtrl->HwInt2_Stat,
3752 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) |
3753 (~TSP_HWINT2_PCR0_UPDATE_END & TSP_HWINT2_STATUS_MASK));
3754 break;
3755 case 1:
3756 //REG16_CLR(&_RegCtrl->HwInt2_Stat,TSP_HWINT2_PCR1_UPDATE_END);
3757 REG16_W(&_RegCtrl->HwInt2_Stat,
3758 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) |
3759 (~TSP_HWINT2_PCR1_UPDATE_END & TSP_HWINT2_STATUS_MASK));
3760 break;
3761 case 2:
3762 //REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT2_PCR2_UPDATE_END);
3763 REG16_W(&_RegCtrl->HwInt3_Stat,
3764 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) |
3765 (~TSP_HWINT3_PCR2_UPDATE_END & TSP_HWINT3_STATUS_MASK));
3766 break;
3767 case 3:
3768 //REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT2_PCR3_UPDATE_END);
3769 REG16_W(&_RegCtrl->HwInt3_Stat,
3770 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) |
3771 (~TSP_HWINT3_PCR3_UPDATE_END & TSP_HWINT3_STATUS_MASK));
3772 break;
3773 default:
3774 break;
3775 }
3776 }
3777
HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)3778 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)
3779 {
3780 switch(pcrFltId)
3781 {
3782 case 0:
3783 return (TSP_HWINT2_PCR0_UPDATE_END_EN << 8);
3784 case 1:
3785 return (TSP_HWINT2_PCR1_UPDATE_END_EN << 8);
3786 case 2:
3787 return (TSP_HWINT3_PCR2_UPDATE_END_EN << 16);
3788 case 3:
3789 return (TSP_HWINT3_PCR3_UPDATE_END_EN << 16);
3790 default:
3791 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
3792 return 0;
3793 }
3794 }
3795
HAL_TSP_STC_Init(void)3796 void HAL_TSP_STC_Init(void)
3797 {
3798 /////////////Set STC control by HK////////////////
3799 // select synth from chip top : bit 1 -> 0 -> controlled by HK
3800 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
3801 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
3802
3803 // set HK STC synth CW
3804 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
3805 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000;
3806 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800;
3807 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000;
3808 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = 0x2800;
3809
3810 // set STC synth
3811 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3812 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
3813 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3814 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3815 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
3816 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3817
3818 #if 0 // we don't use TSP CPU to control STC anymmore, so we don't have to do the following
3819 /////////////Set STC control by TSP////////////////
3820 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
3821 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
3822 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL;
3823
3824 // set TSP STC synth CW
3825 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
3826 TSP32_IdrW((TSP32 *)(0x0021024c<<1), 0x28000000);
3827 TSP32_IdrW((TSP32 *)(0x00210280<<1), 0x28000000); //STC1
3828
3829 // t2 , t3 had no 0x0021025c, it was add after t4, eanble synthesizer
3830 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x01);
3831 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x01);
3832 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x02); //STC1
3833 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x02);
3834 #endif
3835 }
3836
HAL_TSP_GetSTCSynth(MS_U32 Eng,MS_U32 * u32Sync)3837 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync)
3838 {
3839 switch (Eng)
3840 {
3841 case 0:
3842 // get HK STC synth CW
3843 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L);
3844 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ;
3845 break;
3846 case 1:
3847 // get HK STC synth CW
3848 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L);
3849 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) << 16 ;
3850 break;
3851 }
3852 }
3853
HAL_TSP_SetSTCSynth(MS_U32 Eng,MS_U32 u32Sync)3854 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync)
3855 {
3856 switch (Eng)
3857 {
3858 case 0:
3859 //set STC controller : HK or TSP CPU
3860 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
3861
3862 // set HK STC synth CW
3863 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF;
3864 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16;
3865
3866 // set STC synth : toggle update bit
3867 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3868 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
3869 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3870 break;
3871 case 1:
3872 //set STC controller : HK or TSP CPU
3873 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
3874
3875 // set HK STC synth CW
3876 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF;
3877 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = u32Sync >> 16;
3878
3879 // set STC synth : toggle update bit
3880 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3881 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
3882 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3883 break;
3884 }
3885 }
3886
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)3887 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
3888 {
3889 if (bEnable)
3890 {
3891 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
3892 }
3893 else
3894 {
3895 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
3896 }
3897 }
3898
HAL_TSP_STC64_Set(MS_U32 Eng,MS_U32 stcH,MS_U32 stcL)3899 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL)
3900 {
3901 switch (Eng)
3902 {
3903 case 0:
3904 REG32_W(&_RegCtrl->Pcr_L, stcL);
3905 REG32_W(&_RegCtrl->Pcr_H, stcH);
3906 break;
3907 case 1:
3908 REG32_W(&_RegCtrl->PCR64_2_L, stcL);
3909 REG32_W(&_RegCtrl->PCR64_2_H, stcH);
3910 break;
3911 }
3912 }
3913
HAL_TSP_STC64_Get(MS_U32 Eng,MS_U32 * pStcH,MS_U32 * pStcL)3914 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL)
3915 {
3916 switch (Eng)
3917 {
3918 case 0:
3919 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3920 *pStcH = REG32_R(&_RegCtrl->Pcr_H);
3921 *pStcL = REG32_R(&_RegCtrl->Pcr_L);
3922 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3923 break;
3924 case 1:
3925 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
3926 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H);
3927 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L);
3928 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
3929 break;
3930 }
3931 }
3932
HAL_TSP_STC33_CmdQSet(MS_U32 stcH,MS_U32 stcL)3933 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL)
3934 {
3935 // @TODO ask designer for the difference between 64bit STC and 33 Bit STC
3936 // and it's hw limit (like: cmdQ delay)
3937 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H);
3938 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL);
3939 }
3940
HAL_TSP_STC33_CmdQGet(MS_U32 * pStcH,MS_U32 * pStcL)3941 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL)
3942 {
3943 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3944 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H;
3945 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ);
3946 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3947 }
3948
HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType,MS_U32 pktDmxId)3949 void HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType, MS_U32 pktDmxId)
3950 {
3951 switch (eFltType)
3952 {
3953 case E_TSP_DST_FIFO_VIDEO :
3954 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT);
3955 break;
3956 case E_TSP_DST_FIFO_VIDEO3D :
3957 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT);
3958 break;
3959 case E_TSP_DST_FIFO_AUDIO :
3960 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT);
3961 break;
3962 case E_TSP_DST_FIFO_AUDIO2 :
3963 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT);
3964 break;
3965 case E_TSP_DST_FIFO_AUDIO3 :
3966 REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDC_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDC_SRC_SHIFT);
3967 break;
3968 case E_TSP_DST_FIFO_AUDIO4 :
3969 REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDD_SRC_SHIFT);
3970 break;
3971 default:
3972 break;
3973 }
3974 }
3975
HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType,TSP_SRC_SEQ * pktDmxId)3976 void HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId)
3977 {
3978 switch (eFltType)
3979 {
3980 case E_TSP_DST_FIFO_VIDEO :
3981 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT;
3982 break;
3983 case E_TSP_DST_FIFO_VIDEO3D:
3984 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT;
3985 break;
3986 case E_TSP_DST_FIFO_AUDIO :
3987 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT;
3988 break;
3989 case E_TSP_DST_FIFO_AUDIO2 :
3990 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT;
3991 break;
3992 case E_TSP_DST_FIFO_AUDIO3 :
3993 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDC_SRC_MASK) >> TSP_AUDC_SRC_SHIFT;
3994 break;
3995 case E_TSP_DST_FIFO_AUDIO4 :
3996 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDD_SRC_MASK) >> TSP_AUDD_SRC_SHIFT;
3997 break;
3998 default:
3999 break;
4000 }
4001 }
4002
HAL_TSP_FIFO_ClearAll()4003 void HAL_TSP_FIFO_ClearAll()
4004 {
4005 // clear ALL FIFO !!!
4006 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4007 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4008 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4009 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4010 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4011 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4012
4013 }
4014
4015
HAL_TSP_FIFO_ReadEn(MS_BOOL bEn)4016 void HAL_TSP_FIFO_ReadEn(MS_BOOL bEn)
4017 {
4018 if(bEn == TRUE)
4019 {
4020 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
4021 }
4022 else
4023 {
4024 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
4025 }
4026
4027 }
4028
HAL_TSP_FIFO_ReadPkt(void)4029 MS_U16 HAL_TSP_FIFO_ReadPkt(void)
4030 {
4031 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK);
4032 }
4033
HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)4034 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)
4035 {
4036 switch (eFltType)
4037 {
4038 case E_TSP_DST_FIFO_VIDEO:
4039 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4040 break;
4041 case E_TSP_DST_FIFO_VIDEO3D:
4042 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V3D) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4043 break;
4044 case E_TSP_DST_FIFO_AUDIO:
4045 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_A) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4046 break;
4047 case E_TSP_DST_FIFO_AUDIO2:
4048 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AB) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4049 break;
4050 case E_TSP_DST_FIFO_AUDIO3:
4051 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AC) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4052 break;
4053 case E_TSP_DST_FIFO_AUDIO4:
4054 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AD) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
4055 break;
4056 default:
4057 break;
4058 }
4059 }
4060
4061
4062
4063
4064 //@NOTE for TS mode
4065 //@TODO need to rename (TS enable or PKTDMX_BYPASS)
HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)4066 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
4067 {
4068 if(bEn)
4069 {
4070 switch (eFltType)
4071 {
4072 case E_TSP_DST_FIFO_VIDEO:
4073 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
4074 break;
4075 case E_TSP_DST_FIFO_VIDEO3D:
4076 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
4077 break;
4078 case E_TSP_DST_FIFO_AUDIO:
4079 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
4080 break;
4081 case E_TSP_DST_FIFO_AUDIO2:
4082 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
4083 break;
4084 case E_TSP_DST_FIFO_AUDIO3:
4085 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS);
4086 break;
4087 case E_TSP_DST_FIFO_AUDIO4:
4088 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS);
4089 break;
4090 default:
4091 break;
4092 }
4093 }
4094 else
4095 {
4096 switch (eFltType)
4097 {
4098 case E_TSP_DST_FIFO_VIDEO:
4099 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
4100 break;
4101 case E_TSP_DST_FIFO_VIDEO3D:
4102 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
4103 break;
4104 case E_TSP_DST_FIFO_AUDIO:
4105 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
4106 break;
4107 case E_TSP_DST_FIFO_AUDIO2:
4108 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
4109 break;
4110 case E_TSP_DST_FIFO_AUDIO3:
4111 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS);
4112 break;
4113 case E_TSP_DST_FIFO_AUDIO4:
4114 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS);
4115 break;
4116 default:
4117 break;
4118
4119 }
4120 }
4121 }
4122
HAL_TSP_PS_SRC(MS_U32 tsIf)4123 void HAL_TSP_PS_SRC(MS_U32 tsIf)
4124 {
4125 REG16_MSK_W(&_RegCtrl3->CFG3_10, CFG3_10_PS_MODE_SRC_MASK,(((MS_U16)tsIf)<< CFG3_10_PS_MODE_SRC_SHIFT));
4126 }
4127
4128
4129
4130 //PS MODE
4131 //NEED TO rename
HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)4132 void HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
4133 {
4134 if(bEn)
4135 {
4136 switch (eFltType)
4137 {
4138 case E_TSP_DST_FIFO_VIDEO:
4139 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4140 break;
4141 case E_TSP_DST_FIFO_VIDEO3D:
4142 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4143 break;
4144 case E_TSP_DST_FIFO_AUDIO:
4145 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4146 break;
4147 case E_TSP_DST_FIFO_AUDIO2:
4148 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4149 break;
4150 case E_TSP_DST_FIFO_AUDIO3:
4151 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4152 break;
4153 case E_TSP_DST_FIFO_AUDIO4:
4154 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4155 break;
4156 default:
4157 break;
4158 }
4159 }
4160 else
4161 {
4162 switch (eFltType)
4163 {
4164 case E_TSP_DST_FIFO_VIDEO :
4165 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4166 break;
4167 case E_TSP_DST_FIFO_VIDEO3D:
4168 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4169 break;
4170 case E_TSP_DST_FIFO_AUDIO :
4171 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4172 break;
4173 case E_TSP_DST_FIFO_AUDIO2 :
4174 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4175 break;
4176 case E_TSP_DST_FIFO_AUDIO3 :
4177 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4178 break;
4179 case E_TSP_DST_FIFO_AUDIO4 :
4180 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4181 break;
4182 default:
4183 break;
4184 }
4185 }
4186 }
4187
HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng,TSP_DST_SEQ eFltType)4188 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType)
4189 {
4190 // (K6 HW CL)
4191 // PS mode source sel need to be independent
4192
4193 switch (eFltType)
4194 {
4195 case E_TSP_DST_FIFO_VIDEO:
4196 REG16_MSK_W(&_RegCtrl8_1->CFG8_48,CFG8_48_REG_PS_MODE_SRC_V_MASK, (eFileEng << CFG8_48_REG_PS_MODE_SRC_V_SHIFT));
4197 break;
4198 case E_TSP_DST_FIFO_VIDEO3D:
4199 REG16_MSK_W(&_RegCtrl8_1->CFG8_48,CFG8_48_REG_PS_MODE_SRC_V3D_MASK,(eFileEng << CFG8_48_REG_PS_MODE_SRC_V3D_SHIFT));
4200 break;
4201 case E_TSP_DST_FIFO_AUDIO:
4202 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_A_MASK, (eFileEng << CFG8_47_REG_PS_MODE_SRC_A_SHIFT));
4203 break;
4204 case E_TSP_DST_FIFO_AUDIO2:
4205 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_AD_MASK, (eFileEng << CFG8_47_REG_PS_MODE_SRC_AD_SHIFT));
4206 break;
4207 case E_TSP_DST_FIFO_AUDIO3:
4208 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_AC_MASK, (eFileEng << CFG8_47_REG_PS_MODE_SRC_AC_SHIFT));
4209 break;
4210 case E_TSP_DST_FIFO_AUDIO4:
4211 REG16_MSK_W(&_RegCtrl8_1->CFG8_47,CFG8_47_REG_PS_MODE_SRC_ADD_MASK,(eFileEng << CFG8_47_REG_PS_MODE_SRC_ADD_SHIFT));
4212 break;
4213 default:
4214 break;
4215 }
4216 }
4217
HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)4218 MS_U32 HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)
4219 {
4220 switch (eFltType)
4221 {
4222 case E_TSP_DST_FIFO_VIDEO :
4223 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK;
4224 case E_TSP_DST_FIFO_VIDEO3D :
4225 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK;
4226 case E_TSP_DST_FIFO_AUDIO :
4227 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK;
4228 case E_TSP_DST_FIFO_AUDIO2 :
4229 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK;
4230 case E_TSP_DST_FIFO_AUDIO3 :
4231 return REG16_R(&_RegCtrl2->CFG_74) & CFG_74_MATCHECED_APID_C_MASK;
4232 case E_TSP_DST_FIFO_AUDIO4 :
4233 return REG16_R(&_RegCtrl2->CFG_7C) & CFG_7C_MATCHECED_APID_D_MASK;
4234 default:
4235 return PVR_PIDFLT_DEF;
4236 }
4237 }
4238
HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType,MS_BOOL bReset)4239 void HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType, MS_BOOL bReset)
4240 {
4241 if (bReset)
4242 {
4243 switch (eFltType)
4244 {
4245 case E_TSP_DST_FIFO_VIDEO :
4246 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
4247 break;
4248 case E_TSP_DST_FIFO_VIDEO3D:
4249 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
4250 break;
4251 case E_TSP_DST_FIFO_AUDIO :
4252 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
4253 break;
4254 case E_TSP_DST_FIFO_AUDIO2 :
4255 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
4256 break;
4257 case E_TSP_DST_FIFO_AUDIO3 :
4258 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO3);
4259 break;
4260 case E_TSP_DST_FIFO_AUDIO4 :
4261 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4);
4262 break;
4263 default :
4264 break;
4265 }
4266 }
4267 else
4268 {
4269 switch (eFltType)
4270 {
4271 case E_TSP_DST_FIFO_VIDEO :
4272 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
4273 break;
4274 case E_TSP_DST_FIFO_VIDEO3D:
4275 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
4276 break;
4277 case E_TSP_DST_FIFO_AUDIO :
4278 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
4279 break;
4280 case E_TSP_DST_FIFO_AUDIO2 :
4281 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
4282 break;
4283 case E_TSP_DST_FIFO_AUDIO3 :
4284 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO3);
4285 break;
4286 case E_TSP_DST_FIFO_AUDIO4 :
4287 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4);
4288 break;
4289 default :
4290 break;
4291 }
4292 }
4293
4294 _delay(1);
4295 }
4296
HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)4297 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)
4298 {
4299 if(bSkip)
4300 {
4301 switch(eFltType)
4302 {
4303 case E_TSP_DST_FIFO_VIDEO:
4304 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
4305 break;
4306 case E_TSP_DST_FIFO_VIDEO3D:
4307 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
4308 break;
4309 case E_TSP_DST_FIFO_AUDIO:
4310 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
4311 break;
4312 case E_TSP_DST_FIFO_AUDIO2:
4313 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
4314 break;
4315 case E_TSP_DST_FIFO_AUDIO3:
4316 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN);
4317 break;
4318 case E_TSP_DST_FIFO_AUDIO4:
4319 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN);
4320 break;
4321 default:
4322 break;
4323 }
4324 }
4325 else
4326 {
4327 switch(eFltType)
4328 {
4329 case E_TSP_DST_FIFO_VIDEO:
4330 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
4331 break;
4332 case E_TSP_DST_FIFO_VIDEO3D:
4333 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
4334 break;
4335 case E_TSP_DST_FIFO_AUDIO:
4336 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
4337 break;
4338 case E_TSP_DST_FIFO_AUDIO2:
4339 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
4340 break;
4341 case E_TSP_DST_FIFO_AUDIO3:
4342 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN);
4343 break;
4344 case E_TSP_DST_FIFO_AUDIO4:
4345 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN);
4346 break;
4347 default:
4348 break;
4349 }
4350
4351 }
4352 }
4353
4354
HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType,MS_BOOL bDisable)4355 void HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType, MS_BOOL bDisable)
4356 {
4357 if(bDisable)
4358 {
4359 switch(eFltType)
4360 {
4361 case E_TSP_DST_FIFO_VIDEO:
4362 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
4363 break;
4364 case E_TSP_DST_FIFO_VIDEO3D:
4365 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
4366 break;
4367 case E_TSP_DST_FIFO_AUDIO :
4368 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
4369 break;
4370 case E_TSP_DST_FIFO_AUDIO2 :
4371 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
4372 break;
4373 case E_TSP_DST_FIFO_AUDIO3 :
4374 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS);
4375 break;
4376 case E_TSP_DST_FIFO_AUDIO4 :
4377 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS);
4378 break;
4379 default:
4380 break;
4381 }
4382 }
4383 else
4384 {
4385 switch(eFltType)
4386 {
4387 case E_TSP_DST_FIFO_VIDEO:
4388 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
4389 break;
4390 case E_TSP_DST_FIFO_VIDEO3D:
4391 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
4392 break;
4393 case E_TSP_DST_FIFO_AUDIO :
4394 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
4395 break;
4396 case E_TSP_DST_FIFO_AUDIO2 :
4397 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
4398 break;
4399 case E_TSP_DST_FIFO_AUDIO3 :
4400 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS);
4401 break;
4402 case E_TSP_DST_FIFO_AUDIO4 :
4403 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS);
4404 break;
4405 default:
4406 break;
4407 }
4408 }
4409 }
4410
HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)4411 MS_BOOL HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)
4412 {
4413 MS_U32 u32Matched = 0;
4414 switch (eFltType)
4415 {
4416 case E_TSP_DST_FIFO_VIDEO :
4417 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO;
4418 break;
4419 case E_TSP_DST_FIFO_VIDEO3D:
4420 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D;
4421 break;
4422 case E_TSP_DST_FIFO_AUDIO :
4423 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO;
4424 break;
4425 case E_TSP_DST_FIFO_AUDIO2 :
4426 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2;
4427 break;
4428 case E_TSP_DST_FIFO_AUDIO3 :
4429 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO3;
4430 break;
4431 case E_TSP_DST_FIFO_AUDIO4 :
4432 u32Matched = REG16_R(&_RegCtrl->PktChkSizeFilein) & TSP_RESET_AFIFO4;
4433 break;
4434 default :
4435 return FALSE;
4436 }
4437 return (u32Matched) ? TRUE: FALSE;
4438 }
4439
HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)4440 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)
4441 {
4442 #define E_TSP_FIFO_STATUS_ISRESET 0x80000000
4443 #define E_TSP_FIFO_STATUS_EMPTY 0x00000001
4444 #define E_TSP_FIFO_STATUS_OVERFLOW 0x00000002
4445 #define E_TSP_FIFO_STATUS_LEVEL 0x0000000C
4446 #define TSP_FIFO_STATUS_LEVEL_SHFT 2 //shift the value get from HAL_TSP_FIFO_Level to the u32Status level position
4447 // @NOTE please follow K2 like series to return this value
4448 // since API layer didn't define for each column
4449 // we only defined that 0x80000000 stands for this fifo reset is High
4450 // 0x00000001 stands for this fifo is empty
4451 // 0x00000002 stands for this fifo is overflow
4452 // 0x0000000C is a mask for this fifo level
4453 // this is exclusive usage
4454 MS_U32 u32Status = 0;
4455 if (HAL_TSP_FIFO_IsReset(eFltType))
4456 {
4457 u32Status |= E_TSP_FIFO_STATUS_ISRESET;
4458 }
4459 if (HAL_TSP_FIFO_Empty(eFltType))
4460 {
4461 u32Status |= E_TSP_FIFO_STATUS_EMPTY;
4462 }
4463 if (HAL_TSP_FIFO_Overflow(eFltType))
4464 {
4465 u32Status |= E_TSP_FIFO_STATUS_OVERFLOW;
4466 }
4467
4468 u32Status |= ((HAL_TSP_FIFO_Level(eFltType)<<TSP_FIFO_STATUS_LEVEL_SHFT)&E_TSP_FIFO_STATUS_LEVEL);
4469
4470 return u32Status;
4471 }
4472
HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)4473 MS_U32 HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)
4474 {
4475 switch (eFltType)
4476 {
4477 case E_TSP_DST_FIFO_VIDEO :
4478 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT;
4479 case E_TSP_DST_FIFO_VIDEO3D :
4480 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT;
4481 case E_TSP_DST_FIFO_AUDIO :
4482 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT;
4483 case E_TSP_DST_FIFO_AUDIO2 :
4484 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT;
4485 case E_TSP_DST_FIFO_AUDIO3 :
4486 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_LEVEL) >> TSP_AFIFOC_LEVEL_SHFT;
4487 case E_TSP_DST_FIFO_AUDIO4:
4488 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_LEVEL) >> TSP_AFIFOD_LEVEL_SHFT;
4489 default :
4490 return 0;
4491 }
4492 }
4493
HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)4494 MS_BOOL HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)
4495 {
4496 switch (eFltType)
4497 {
4498 case E_TSP_DST_FIFO_VIDEO :
4499 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT;
4500 case E_TSP_DST_FIFO_VIDEO3D :
4501 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT;
4502 case E_TSP_DST_FIFO_AUDIO :
4503 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT;
4504 case E_TSP_DST_FIFO_AUDIO2 :
4505 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT;
4506 case E_TSP_DST_FIFO_AUDIO3 :
4507 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_FULL) >> TSP_AFIFOC_FULL_SHFT;
4508 case E_TSP_DST_FIFO_AUDIO4 :
4509 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_FULL) >> TSP_AFIFOD_FULL_SHFT;
4510 default :
4511 return FALSE;
4512 }
4513 }
4514
HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)4515 MS_BOOL HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)
4516 {
4517 switch (eFltType)
4518 {
4519 case E_TSP_DST_FIFO_VIDEO :
4520 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT;
4521 case E_TSP_DST_FIFO_VIDEO3D:
4522 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT;
4523 case E_TSP_DST_FIFO_AUDIO :
4524 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT;
4525 case E_TSP_DST_FIFO_AUDIO2 :
4526 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT;
4527 case E_TSP_DST_FIFO_AUDIO3 :
4528 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_EMPTY) >> TSP_AFIFOC_EMPTY_SHFT;
4529 case E_TSP_DST_FIFO_AUDIO4 :
4530 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_EMPTY) >> TSP_AFIFOD_EMPTY_SHFT;
4531 default :
4532 return FALSE;
4533 }
4534 }
4535
_HAL_TSP_VQ_TxConfig(MS_U32 vqId)4536 static MS_BOOL _HAL_TSP_VQ_TxConfig(MS_U32 vqId)
4537 {
4538 // reg_vq_wr_threshold = 0x8
4539 // reg_vq_forcefire_cnt_1k= 0xC
4540
4541 switch(vqId)
4542 {
4543 case 0:
4544 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ0_WR_THRESHOLD_SHIFT) & TSP_VQ0_WR_THRESHOLD_MASK));
4545 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT) & TSP_VQ0_FORCE_FIRE_CNT_1K_MASK));
4546 break;
4547 case 1:
4548 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ1_WR_THRESHOLD_SHIFT) & TSP_VQ1_WR_THRESHOLD_MASK));
4549 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ1_FORCEFIRE_CNT_1K_MASK));
4550 break;
4551 case 2:
4552 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ2_WR_THRESHOLD_SHIFT) & TSP_VQ2_WR_THRESHOLD_MASK));
4553 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ2_FORCEFIRE_CNT_1K_MASK));
4554 break;
4555 case 3:
4556 REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ3_WR_THRESHOLD_SHIFT) & TSP_VQ3_WR_THRESHOLD_MASK));
4557 REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ3_FORCEFIRE_CNT_1K_MASK));
4558 break;
4559 default:
4560 return FALSE;
4561 }
4562 return TRUE;
4563 }
4564
HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr,MS_U32 u32BufLen)4565 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen)
4566 {
4567 MS_U32 vqId = 0;
4568 MS_U32 u32VQ_PktNum = 0;
4569 MS_U32 u32Addr = 0;
4570 MS_U32 u32OneBufSize = 0;
4571
4572 // Check MIU select
4573 MS_U8 u8MiuSel = 0;
4574 _phy_to_miu_offset(u8MiuSel, u32Addr, u32BaseAddr);
4575 REG16_W(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW, (REG16_R(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW) & (~REG_MIU_SEL_VQ_MASK)) | ((u8MiuSel << REG_MIU_SEL_VQ_SHIFT) & REG_MIU_SEL_VQ_MASK));
4576
4577 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment
4578 u32VQ_PktNum = u32OneBufSize / VQ_PACKET_UNIT_LEN;
4579
4580 for(vqId = 0; vqId < VQ_NUM; vqId ++)
4581 {
4582 if(TRUE != _HAL_TSP_VQ_TxConfig(vqId))
4583 {
4584 return FALSE;
4585 }
4586
4587 // in kaiser we needs to set 6 VQ and the base unit is 208 so total vq size should be N*208*6
4588 if (TRUE != HAL_TSP_VQ_Buffer(vqId, u32Addr, u32VQ_PktNum))
4589 {
4590 return FALSE;
4591 }
4592 u32Addr += u32OneBufSize;
4593 }
4594
4595 HAL_TSP_VQ_Enable(TRUE);
4596 return TRUE;
4597
4598 }
4599
HAL_TSP_VQ_Buffer(MS_U32 vqId,MS_PHYADDR u32BaseAddr,MS_U32 u32VQ_PktNum)4600 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32VQ_PktNum)
4601 {
4602 switch(vqId)
4603 {
4604 case 0:
4605 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS));
4606 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum);
4607 break;
4608 case 1:
4609 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS));
4610 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum);
4611 break;
4612 case 2:
4613 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS));
4614 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum);
4615 break;
4616 case 3:
4617 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS));
4618 REG16_W(&_RegCtrl->VQ3_Size, u32VQ_PktNum);
4619 break;
4620 default:
4621 return FALSE;
4622 }
4623 return TRUE;
4624 }
4625
HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)4626 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)
4627 {
4628 if(bDis == TRUE)
4629 {
4630 switch(vqId)
4631 {
4632 case 0:
4633 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
4634 break;
4635 case 1:
4636 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
4637 break;
4638 case 2:
4639 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
4640 break;
4641 case 3:
4642 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS);
4643 break;
4644 default:
4645 return FALSE;
4646 }
4647 }
4648 else
4649 {
4650 switch(vqId)
4651 {
4652 case 0:
4653 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
4654 break;
4655 case 1:
4656 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
4657 break;
4658 case 2:
4659 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
4660 break;
4661 case 3:
4662 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS);
4663 break;
4664 default:
4665 return FALSE;
4666 }
4667 }
4668
4669 return TRUE;
4670 }
4671
HAL_TSP_VQ_Enable(MS_BOOL bEn)4672 void HAL_TSP_VQ_Enable(MS_BOOL bEn)
4673 {
4674 if (bEn)
4675 {
4676 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
4677 }
4678 else
4679 {
4680 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
4681 }
4682 }
HAL_TSP_VQ_Reset(MS_U32 vqId,MS_BOOL bEn)4683 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn)
4684 {
4685 if(bEn)
4686 {
4687 switch(vqId)
4688 {
4689 case 0:
4690 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
4691 break;
4692 case 1:
4693 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
4694 break;
4695 case 2:
4696 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
4697 break;
4698 case 3:
4699 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET);
4700 break;
4701 default:
4702 break;
4703 }
4704 }
4705 else
4706 {
4707 switch(vqId)
4708 {
4709 case 0:
4710 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
4711 break;
4712 case 1:
4713 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
4714 break;
4715 case 2:
4716 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
4717 break;
4718 case 3:
4719 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET);
4720 break;
4721 default:
4722 break;
4723 }
4724 }
4725 }
4726
HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId,MS_BOOL bEn)4727 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn)
4728 {
4729 if(bEn)
4730 {
4731 switch(vqId)
4732 {
4733 case 0:
4734 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
4735 break;
4736 case 1:
4737 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
4738 break;
4739 case 2:
4740 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
4741 break;
4742 case 3:
4743 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN);
4744 break;
4745 default:
4746 break;
4747 }
4748 }
4749 else
4750 {
4751 switch(vqId)
4752 {
4753 case 0:
4754 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
4755 break;
4756 case 1:
4757 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
4758 break;
4759 case 2:
4760 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
4761 break;
4762 case 3:
4763 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN);
4764 break;
4765 default:
4766 break;
4767 }
4768 }
4769 }
4770
HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId,MS_BOOL bEn)4771 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn)
4772 {
4773 if(bEn)
4774 {
4775 switch(vqId)
4776 {
4777 case 0:
4778 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
4779 break;
4780 case 1:
4781 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
4782 break;
4783 case 2:
4784 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
4785 break;
4786 case 3:
4787 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT);
4788 break;
4789 default:
4790 break;
4791 }
4792 }
4793 else
4794 {
4795 switch(vqId)
4796 {
4797 case 0:
4798 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
4799 break;
4800 case 1:
4801 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
4802 break;
4803 case 2:
4804 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
4805 break;
4806 case 3:
4807 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT);
4808 break;
4809 default:
4810 break;
4811 }
4812 }
4813 }
4814
HAL_PVR_Init(MS_U32 u32PVREng,MS_U32 pktDmxId)4815 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId)
4816 {
4817 switch(u32PVREng)
4818 {
4819 case 0:
4820 // PVR 1
4821 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
4822 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)pktDmxId) << TSP_PVR1_SRC_SHIFT));
4823 break;
4824 case 1:
4825 // PVR 2
4826 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
4827 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U16)pktDmxId) & 0x01) << TSP_PVR2_SRC_SHIFT_L));
4828 REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)pktDmxId) >> 1) << TSP_PVR2_SRC_SHIFT_H));
4829 break;
4830 case 2:
4831 // PVR 3
4832 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC, pktDmxId << CFG_15_PVR3_SRC_SHIFT);
4833 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN);
4834 break;
4835 case 3:
4836 // PVR 3
4837 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC, pktDmxId << CFG_15_PVR4_SRC_SHIFT);
4838 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN);
4839 break;
4840 default:
4841 break;
4842 }
4843 }
4844
HAL_PVR_Exit(MS_U32 u32PVREng)4845 void HAL_PVR_Exit(MS_U32 u32PVREng)
4846 {
4847 switch(u32PVREng)
4848 {
4849 case 0:
4850 //reset pvr control registers
4851 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
4852 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK);
4853
4854 //reset write address
4855 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4856 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4857 break;
4858 case 1:
4859 //reset pvr control registers
4860 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
4861 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L);
4862 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H);
4863
4864 //reset write address
4865 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4866 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4867 break;
4868 case 2:
4869 //reset pvr control registers
4870 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC);
4871 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN);
4872
4873 //reset write address
4874 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4875 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4876 break;
4877 case 3:
4878 //reset pvr control registers
4879 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC);
4880 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN);
4881
4882 //reset write address
4883 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4884 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4885 break;
4886 default:
4887 break;
4888 }
4889
4890 //reset time-stamp
4891 HAL_PVR_SetPVRTimeStamp(u32PVREng,0);
4892
4893 }
4894
HAL_PVR_Start(MS_U32 u32PVREng)4895 void HAL_PVR_Start(MS_U32 u32PVREng)
4896 {
4897 switch(u32PVREng)
4898 {
4899 case 0:
4900 //reset write address
4901 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4902 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4903
4904 //enable string to miu
4905 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
4906 break;
4907 case 1:
4908 //reset write address
4909 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4910 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4911
4912 //enable string to miu
4913 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
4914 break;
4915 case 2:
4916 //reset write address
4917 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4918 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4919
4920 //enable string to miu
4921 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN);
4922 break;
4923 case 3:
4924 //reset write address
4925 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4926 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4927
4928 //enable string to miu
4929 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN);
4930 break;
4931 default:
4932 break;
4933 }
4934 }
4935
HAL_PVR_Stop(MS_U32 u32PVREng)4936 void HAL_PVR_Stop(MS_U32 u32PVREng)
4937 {
4938 switch(u32PVREng)
4939 {
4940 case 0:
4941 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
4942 break;
4943 case 1:
4944 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
4945 break;
4946 case 2:
4947 //clear string to miu
4948 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN);
4949 break;
4950 case 3:
4951 //clear string to miu
4952 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN);
4953 break;
4954 default:
4955 break;
4956 }
4957 }
4958
HAL_PVR_Pause(MS_U32 u32PVREng,MS_BOOL bPause)4959 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause)
4960 {
4961 if(bPause)
4962 {
4963 switch(u32PVREng)
4964 {
4965 case 0:
4966 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
4967 break;
4968 case 1:
4969 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
4970 break;
4971 case 2:
4972 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE);
4973 break;
4974 case 3:
4975 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE);
4976 break;
4977 default:
4978 break;
4979 }
4980 }
4981 else
4982 {
4983 switch(u32PVREng)
4984 {
4985 case 0:
4986 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
4987 break;
4988 case 1:
4989 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
4990 break;
4991 case 2:
4992 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE);
4993 break;
4994 case 3:
4995 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE);
4996 break;
4997 default:
4998 break;
4999 }
5000 }
5001 }
5002
HAL_PVR_RecPid(MS_U32 u32PVREng,MS_BOOL bSet)5003 void HAL_PVR_RecPid(MS_U32 u32PVREng , MS_BOOL bSet)
5004 {
5005 if(bSet)
5006 {
5007 switch(u32PVREng)
5008 {
5009 case 0:
5010 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
5011 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
5012 break;
5013 case 1:
5014 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
5015 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
5016 break;
5017 case 2:
5018 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC);
5019 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3);
5020 break;
5021 case 3:
5022 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC);
5023 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4);
5024 break;
5025 default:
5026 break;
5027 }
5028 }
5029 else
5030 {
5031 switch(u32PVREng)
5032 {
5033 case 0:
5034 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
5035 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
5036 break;
5037 case 1:
5038 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
5039 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
5040 break;
5041 case 2:
5042 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC);
5043 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3);
5044 break;
5045 case 3:
5046 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC);
5047 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4);
5048 break;
5049 default:
5050 break;
5051 }
5052 }
5053 }
5054
HAL_PVR_RecNull(MS_BOOL bSet)5055 void HAL_PVR_RecNull(MS_BOOL bSet)
5056 {
5057 if(bSet == TRUE)
5058 {
5059 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
5060 }
5061 else
5062 {
5063 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
5064 }
5065 }
5066
HAL_PVR_SetBuf(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0,MS_U32 u32StartAddr1,MS_U32 u32BufSize1)5067 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1)
5068 {
5069 // Check MIU select
5070 MS_U8 u8MiuSel;
5071 MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;
5072 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32StartAddr0);
5073 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf1, u32StartAddr1);
5074
5075 MS_U32 u32EndAddr0 = phyMiuOffsetPvrBuf0 + u32BufSize0;
5076 MS_U32 u32EndAddr1 = phyMiuOffsetPvrBuf1 + u32BufSize1;
5077 //MS_U32 u32Temp;
5078 switch(u32PVREng)
5079 {
5080 case 0:
5081 // Select MIU
5082 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR1_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR1_SHIFT) & REG_MIU_SEL_PVR1_MASK));
5083
5084 //head1
5085 REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5086 //end1
5087 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5088 //mid1
5089 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5090
5091 //head2
5092 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
5093 //end2
5094 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
5095 //mid2
5096 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK);
5097 break;
5098 case 1:
5099 // Select MIU
5100 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR2_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR2_SHIFT) & REG_MIU_SEL_PVR2_MASK));
5101
5102 //head1
5103 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5104 //end1
5105 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5106 //mid1
5107 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5108
5109 //head2
5110 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5111 //end2
5112 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5113 //mid2
5114 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5115 break;
5116 case 2:
5117 // Select MIU
5118 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR3_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR3_SHIFT) & REG_MIU_SEL_PVR3_MASK));
5119
5120 //head1
5121 REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);
5122 //end1
5123 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL);
5124 //mid1
5125 REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID);
5126
5127 //head2
5128 REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2);
5129 //end2
5130 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2);
5131 //mid2
5132 REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2);
5133 break;
5134 case 3:
5135 // Select MIU
5136 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR4_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR4_SHIFT) & REG_MIU_SEL_PVR4_MASK));
5137
5138 //head1
5139 REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);
5140 //end1
5141 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL);
5142 //mid1
5143 REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID);
5144
5145 //head2
5146 REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2);
5147 //end2
5148 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2);
5149 //mid2
5150 REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2);
5151 break;
5152
5153 default:
5154 break;
5155 }
5156 }
5157
HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32StartAddr1)5158 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
5159 {
5160 //MS_U32 u32Temp;
5161 switch(u32PVREng)
5162 {
5163 case 0:
5164 //head1
5165 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5166
5167 //head2
5168 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
5169 break;
5170 case 1:
5171 //head1
5172 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5173
5174 //head2
5175 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5176
5177 break;
5178 case 2:
5179 //head1
5180 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);
5181
5182 //head2
5183 REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2);
5184 break;
5185 case 3:
5186 //head1
5187 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);
5188
5189 //head2
5190 REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2);
5191 break;
5192 default:
5193 break;
5194 }
5195 }
5196
HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng,MS_U32 u32MidAddr0,MS_U32 u32MidAddr1)5197 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng , MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
5198 {
5199 switch(u32PVREng)
5200 {
5201 case 0:
5202 //mid1
5203 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
5204
5205 //mid2
5206 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK);
5207 break;
5208 case 1:
5209 //mid1
5210 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
5211
5212 //mid2
5213 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK);
5214 break;
5215 case 2:
5216 //mid1
5217 REG32_W(&(_RegCtrl2->CFG_19_1A), (u32MidAddr0>>4) & CFG_19_1A_PVR3_STR2MI_MID);
5218
5219 //mid2
5220 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2);
5221 break;
5222 case 3:
5223 //mid1
5224 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID);
5225
5226 //mid2
5227 REG32_W(&(_RegCtrl2->CFG_2C_2D), (u32MidAddr1>>4) & CFG_2C_2D_PVR4_STR2MI_MID2);
5228 break;
5229 default:
5230 break;
5231 }
5232 }
5233
HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng,MS_U32 u32EndAddr0,MS_U32 u32EndAddr1)5234 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng , MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
5235 {
5236 switch(u32PVREng)
5237 {
5238 case 0:
5239 //end1
5240 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5241
5242 //end2
5243 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
5244 break;
5245 case 1:
5246 //end1
5247 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5248
5249 //end2
5250 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5251 break;
5252 case 2:
5253 //end1
5254 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL);
5255
5256 //end2
5257 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2);
5258 break;
5259 case 3:
5260 //end1
5261 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL);
5262
5263 //end2
5264 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2);
5265 break;
5266 default:
5267 break;
5268 }
5269 }
5270
HAL_PVR_GetWritePtr(MS_U32 u32PVREng)5271 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng)
5272 {
5273 switch(u32PVREng)
5274 {
5275 case 0:
5276 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS);
5277 break;
5278 case 1:
5279 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS);
5280 break;
5281 case 2:
5282 return (REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS);
5283 break;
5284 case 3:
5285 return (REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS);
5286 break;
5287 default:
5288 break;
5289 }
5290 return 0;
5291 }
5292
5293
HAL_PVR_GetEngSrc(MS_U32 u32EngDst,TSP_SRC_SEQ * eSrc)5294 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc)
5295 {
5296 MS_U16 u16Value = 0;
5297
5298 switch(u32EngDst)
5299 {
5300 case 0:
5301 // PVR 1
5302 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT);
5303 break;
5304 case 1:
5305 // PVR 2
5306 u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L) >> TSP_PVR2_SRC_SHIFT_L;
5307 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1);
5308 *eSrc = (TSP_SRC_SEQ)u16Value;
5309 break;
5310 case 2:
5311 // PVR 3
5312 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR3_SRC) >> CFG_15_PVR3_SRC_SHIFT);
5313 break;
5314 case 3:
5315 // PVR 4
5316 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR4_SRC) >> CFG_15_PVR4_SRC_SHIFT);
5317 break;
5318 default:
5319 break;
5320 }
5321 }
5322
5323
5324 // kaiser Only!!!
HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)5325 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)
5326 {
5327 switch (u32FileEng)
5328 {
5329 case 0: //File in Eng 0
5330 return E_FILEENG_TSIF1;
5331 case 1: //File in Eng 1
5332 return E_FILEENG_TSIF3;
5333 case 2: //File in Eng 2
5334 return E_FILEENG_TSIF0;
5335 case 3: //File in Eng 3
5336 return E_FILEENG_TSIF2;
5337 default:
5338 return E_FILEENG_INVALID;
5339 }
5340 }
5341
5342 // @NOTE for backward competible when calling flowset pvr
5343 // kaiser Only!!!
HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)5344 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)
5345 {
5346 switch(u32Eng)
5347 {
5348 case 0:
5349 return E_TSP_SRC_PKTDMX2;
5350 case 1:
5351 return E_TSP_SRC_PKTDMX3;
5352 case 2:
5353 return E_TSP_SRC_PKTDMX2;
5354 case 3:
5355 return E_TSP_SRC_PKTDMX3;
5356 default:
5357 return E_TSP_SRC_INVALID;
5358 }
5359 }
5360
5361 // kaiser Only!!!
HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF,MS_BOOL bFileIn)5362 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF, MS_BOOL bFileIn)
5363 {
5364 MS_U32 u32PhyTSIF = 0;
5365 switch (eTSIF)
5366 {
5367 case E_TSP_HAL_TSIF_0:
5368 if(bFileIn)
5369 u32PhyTSIF = TSP_TSIF1; // @NOTE tsif1 is used for playback0 file-in
5370 else
5371 u32PhyTSIF = TSP_TSIF0;
5372 break;
5373 case E_TSP_HAL_TSIF_1:
5374 if(bFileIn)
5375 u32PhyTSIF = TSP_TSIF3; // @NOTE tsif3 is used for playback0 file-in
5376 else
5377 u32PhyTSIF = TSP_TSIF2;
5378 break;
5379 case E_TSP_HAL_TSIF_2:
5380 if(bFileIn)
5381 u32PhyTSIF = TSP_TSIF0;
5382 else
5383 u32PhyTSIF = TSP_TSIF3;
5384 break;
5385 case E_TSP_HAL_TSIF_3:
5386 if(bFileIn)
5387 u32PhyTSIF = TSP_TSIF2;
5388 else
5389 u32PhyTSIF = TSP_TSIF1;
5390 break;
5391 case E_TSP_HAL_TSIF_PVR0:
5392 u32PhyTSIF = TSP_TSIF2;
5393 break;
5394 case E_TSP_HAL_TSIF_PVR1:
5395 u32PhyTSIF = TSP_TSIF3;
5396 break;
5397 case E_TSP_HAL_TSIF_PVR2:
5398 u32PhyTSIF = TSP_TSIF2;
5399 break;
5400 case E_TSP_HAL_TSIF_PVR3:
5401 u32PhyTSIF = TSP_TSIF3;
5402 break;
5403 default:
5404 printf("[PVR ERROR][%s][%d] mapping TSIF error\n",__FUNCTION__,__LINE__);
5405 break;
5406 }
5407
5408 return u32PhyTSIF;
5409 }
5410
5411
5412 // kaiser Only!!!
HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)5413 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)
5414 {
5415 // @NOTE we map hw pkt dmx setting to api layer flow at this function
5416
5417 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
5418
5419 switch (eSrc)
5420 {
5421 case E_TSP_SRC_PKTDMX0:
5422 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
5423 break;
5424 case E_TSP_SRC_PKTDMX1:
5425 ePidFltSrc = E_TSP_PIDFLT_FILE0;
5426 break;
5427 case E_TSP_SRC_PKTDMX2:
5428 ePidFltSrc = E_TSP_PIDFLT_LIVE1;
5429 break;
5430 case E_TSP_SRC_PKTDMX3:
5431 ePidFltSrc = E_TSP_PIDFLT_FILE1;
5432 break;
5433 default:
5434 // @TODO add assert
5435 printf ("[TSP_ERR][%s][%d] Wrong Engine Source!!\n", __FUNCTION__,__LINE__);
5436 break;
5437 }
5438
5439 return ePidFltSrc;
5440 }
5441
HAL_TSP_GetDefaultFileinEng(void)5442 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void)
5443 {
5444 return E_FILEENG_TSIF1;
5445 }
5446
HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType,MS_U32 u32Eng)5447 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng)
5448 {
5449 if(eDstType == E_TSP_PIDFLT_DST_VIDEO)
5450 {
5451 switch(u32Eng)
5452 {
5453 case 0:
5454 return TSP_PIDFLT_OUT_VFIFO;
5455 case 1:
5456 return TSP_PIDFLT_OUT_VFIFO3D;
5457 default:
5458 printf("[TSP ERROR][%s][%d] mapping Vfifo eng error\n", __FUNCTION__, __LINE__);
5459 return 0;
5460 }
5461 }
5462 else if(eDstType == E_TSP_PIDFLT_DST_AUDIO)
5463 {
5464 switch(u32Eng)
5465 {
5466 case 0:
5467 return TSP_PIDFLT_OUT_AFIFO;
5468 case 1:
5469 return TSP_PIDFLT_OUT_AFIFO2;
5470 case 2:
5471 return TSP_PIDFLT_OUT_AFIFO3;
5472 case 3:
5473 return TSP_PIDFLT_OUT_AFIFO4;
5474 default:
5475 printf("[TSP ERROR][%s][%d] mapping Afifo eng error\n", __FUNCTION__, __LINE__);
5476 return 0;
5477 }
5478 }
5479 else if(eDstType == E_TSP_PIDFLT_DST_PVR)
5480 {
5481 switch(u32Eng)
5482 {
5483 case 0:
5484 return TSP_PIDFLT_OUT_PVR1;
5485 case 1:
5486 return TSP_PIDFLT_OUT_PVR2;
5487 case 2:
5488 return TSP_PIDFLT_OUT_PVR3;
5489 case 3:
5490 return TSP_PIDFLT_OUT_PVR4;
5491 default:
5492 printf("[TSP ERROR][%s][%d] mapping PVR eng error\n",__FUNCTION__,__LINE__);
5493 return 0;
5494 }
5495 }
5496 else
5497 {
5498 printf("[TSP ERROR][%s][%d] pid filter destination type error\n", __FUNCTION__, __LINE__);
5499 return 0;
5500 }
5501 }
5502
HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)5503 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)
5504 {
5505 MS_U32 u32Fq = 0;
5506
5507 switch (u32Tsif)
5508 {
5509 case 0:
5510 u32Fq = 0;
5511 break;
5512 case 1:
5513 u32Fq = 2;
5514 break;
5515 case 2:
5516 u32Fq = 3;
5517 break;
5518 case 3:
5519 u32Fq = 1;
5520 break;
5521 default:
5522 printf("[PVR ERROR][%s][%d] mapping TSIF:%u error\n",__FUNCTION__,__LINE__,(unsigned int)u32Tsif);
5523 break;
5524 }
5525
5526 return u32Fq;
5527 }
5528
HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)5529 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)
5530 {
5531 switch(u8Pad3WireId)
5532 {
5533 case 3:
5534 return E_TSP_TS_PAD_EXT3;
5535 case 4:
5536 return E_TSP_TS_PAD_EXT4;
5537 case 5:
5538 return E_TSP_TS_PAD_EXT5;
5539 case 6:
5540 return E_TSP_TS_PAD_EXT6;
5541 default:
5542 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] mapping 3WirePad:%u error\n",__FUNCTION__,__LINE__,u8Pad3WireId));
5543 return E_TSP_TS_PAD_INVALID;
5544 }
5545 }
5546
HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng,MS_BOOL bSet)5547 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng , MS_BOOL bSet)
5548 {
5549 if(bSet)
5550 {
5551 switch(u32PVREng)
5552 {
5553 case 0:
5554 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN);
5555 break;
5556 case 1:
5557 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
5558 break;
5559 case 2:
5560 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN);
5561 break;
5562 case 3:
5563 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN);
5564 break;
5565 default:
5566 break;
5567 }
5568 }
5569 else
5570 {
5571 switch(u32PVREng)
5572 {
5573 case 0:
5574 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN);
5575 break;
5576 case 1:
5577 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
5578 break;
5579 case 2:
5580 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN);
5581 break;
5582 case 3:
5583 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN);
5584 break;
5585 default:
5586 break;
5587 }
5588 }
5589 }
5590
HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)5591 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)
5592 {
5593 MS_U32 u32lpcr = 0;
5594 switch(u32PVREng)
5595 {
5596 case 0:
5597 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
5598
5599 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1);
5600
5601 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
5602
5603 return u32lpcr;
5604 case 1:
5605 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
5606
5607 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1);
5608
5609 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
5610 return u32lpcr;
5611 case 2:
5612 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
5613
5614 u32lpcr = REG32_R((&_RegCtrl2->CFG_62_63));
5615
5616 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
5617 return u32lpcr;
5618 case 3:
5619 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
5620
5621 u32lpcr = REG32_R((&_RegCtrl2->CFG_64_65));
5622
5623 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
5624 return u32lpcr;
5625 default:
5626 break;
5627 }
5628 return 0;
5629 }
5630
HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32Stamp)5631 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng , MS_U32 u32Stamp)
5632 {
5633 switch(u32PVREng)
5634 {
5635 case 0:
5636 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
5637
5638 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp);
5639
5640 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
5641 break;
5642 case 1:
5643 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
5644
5645 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp);
5646
5647 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
5648 break;
5649 case 2:
5650 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD);
5651
5652 REG32_W((&_RegCtrl2->CFG_62_63), u32Stamp);
5653
5654 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD);
5655 break;
5656 case 3:
5657 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD);
5658
5659 REG32_W((&_RegCtrl2->CFG_64_65), u32Stamp);
5660
5661 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD);
5662 break;
5663 default:
5664 break;
5665 }
5666 }
5667
HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng,MS_U32 u32Stamp)5668 void HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng , MS_U32 u32Stamp)
5669 {
5670 switch(u32PVREng)
5671 {
5672 case 0:
5673 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
5674
5675 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp);
5676
5677 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
5678 break;
5679 case 1:
5680 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
5681
5682 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp);
5683
5684 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
5685 break;
5686 case 2:
5687 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2);
5688
5689 REG32_W(&_RegCtrl2->CFG_5A_5B, u32Stamp);
5690
5691 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2);
5692 break;
5693 case 3:
5694 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3);
5695
5696 REG32_W(&_RegCtrl2->CFG_5C_5D, u32Stamp);
5697
5698 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3);
5699 break;
5700 default:
5701 break;
5702 }
5703 }
5704
HAL_PVR_Alignment_Enable(MS_U32 u32PVREng,MS_BOOL bEnable)5705 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable)
5706 {
5707 if(bEnable)
5708 {
5709 switch(u32PVREng)
5710 {
5711 case 0:
5712 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
5713 break;
5714 case 1:
5715 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
5716 break;
5717 case 2:
5718 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN);
5719 break;
5720 case 3:
5721 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN);
5722 break;
5723 default:
5724 break;
5725 }
5726 }
5727 else
5728 {
5729 switch(u32PVREng)
5730 {
5731 case 0:
5732 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
5733 break;
5734 case 1:
5735 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
5736 break;
5737 case 2:
5738 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN);
5739 break;
5740 case 3:
5741 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN);
5742 break;
5743 default:
5744 break;
5745 }
5746 }
5747 }
5748
HAL_PVR_FlushData(MS_U32 u32PVREng)5749 void HAL_PVR_FlushData(MS_U32 u32PVREng)
5750 {
5751 switch(u32PVREng)
5752 {
5753 case 0:
5754 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
5755 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
5756 break;
5757 case 1:
5758 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
5759 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
5760 break;
5761 case 2:
5762 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA);
5763 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA);
5764 break;
5765 case 3:
5766 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA);
5767 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA);
5768 break;
5769 default:
5770 break;
5771 }
5772 }
5773
HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)5774 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)
5775 {
5776 if(bSkip)
5777 {
5778 switch(u32PVREng)
5779 {
5780 case 0:
5781 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
5782 break;
5783 case 1:
5784 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
5785 break;
5786 case 2:
5787 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN);
5788 break;
5789 case 3:
5790 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN);
5791 break;
5792 default:
5793 break;
5794 }
5795 }
5796 else
5797 {
5798 switch(u32PVREng)
5799 {
5800 case 0:
5801 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
5802 break;
5803 case 1:
5804 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
5805 break;
5806 case 2:
5807 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN);
5808 break;
5809 case 3:
5810 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN);
5811 break;
5812 default:
5813 break;
5814 }
5815 }
5816 }
5817
5818
HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)5819 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)
5820 {
5821 if(bDisable)
5822 {
5823 switch(u32PVREng)
5824 {
5825 case 0:
5826 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
5827 break;
5828 case 1:
5829 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
5830 break;
5831 case 2:
5832 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS);
5833 break;
5834 case 3:
5835 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS);
5836 break;
5837 default:
5838 break;
5839 }
5840 }
5841 else
5842 {
5843 switch(u32PVREng)
5844 {
5845 case 0:
5846 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
5847 break;
5848 case 1:
5849 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
5850 break;
5851 case 2:
5852 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS);
5853 break;
5854 case 3:
5855 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS);
5856 break;
5857 default:
5858 break;
5859 }
5860
5861 }
5862 }
5863
HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)5864 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)
5865 {
5866 switch(u32PVREng)
5867 {
5868 case 0:
5869 REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT));
5870 break;
5871 case 1:
5872 REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_SHIFT));
5873 break;
5874 case 2:
5875 REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN_SHIFT));
5876 break;
5877 case 3:
5878 REG16_MSK_W(&_RegCtrl2->CFG_23, CFG_23_PVR4_BURST_LEN_MASK, (u16BurstMode << CFG_23_PVR4_BURST_LEN_SHIFT));
5879 break;
5880 default:
5881 break;
5882 }
5883 }
5884
HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng,MS_BOOL bLocal_Stream)5885 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream)
5886 {
5887 if (u32PVREng>=TSP_PVRENG_NUM)
5888 {
5889 return;
5890 }
5891
5892 if (bLocal_Stream) //Stream
5893 {
5894 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
5895 }
5896 else //local
5897 {
5898 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
5899 }
5900 }
5901
HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)5902 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)
5903 {
5904 if(bEnable)
5905 {
5906 switch(u32PVREng)
5907 {
5908 case 0:
5909 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
5910 break;
5911 case 1:
5912 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
5913 break;
5914 case 2:
5915 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3);
5916 break;
5917 case 3:
5918 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4);
5919 break;
5920 default:
5921 break;
5922 }
5923 }
5924 else
5925 {
5926 switch(u32PVREng)
5927 {
5928 case 0:
5929 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
5930 break;
5931 case 1:
5932 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
5933 break;
5934 case 2:
5935 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3);
5936 break;
5937 case 3:
5938 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4);
5939 break;
5940 default:
5941 break;
5942 }
5943 }
5944 }
5945
HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)5946 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)
5947 {
5948 switch(u32PVREng)
5949 {
5950 case 0:
5951 REG32_W(&_RegCtrl3->CFG3_44_45, u32PauseTime);
5952 break;
5953 case 1:
5954 REG32_W(&_RegCtrl3->CFG3_46_47, u32PauseTime);
5955 break;
5956 case 2:
5957 REG32_W(&_RegCtrl3->CFG3_48_49, u32PauseTime);
5958 break;
5959 case 3:
5960 REG32_W(&_RegCtrl3->CFG3_4A_4B, u32PauseTime);
5961 break;
5962 default:
5963 break;
5964 }
5965 }
5966
HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId,MS_BOOL bEnable)5967 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId, MS_BOOL bEnable)
5968 {
5969 if (bEnable)
5970 {
5971 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
5972 }
5973 else
5974 {
5975 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
5976 }
5977 }
5978
HAL_PVR_MOBF_Enable(MS_U32 u32PVREng,MS_BOOL bEnable,MS_U32 u32Key)5979 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key)
5980 {
5981 switch(u32PVREng)
5982 {
5983 case 0:
5984 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK));
5985 break;
5986 case 1:
5987 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK));
5988 break;
5989 case 2:
5990 REG16_W(&_RegCtrl2->CFG_78_7B[0], (u32Key & CFG_78_PVR3_INDEX));
5991 break;
5992 case 3:
5993 REG16_W(&_RegCtrl2->CFG_78_7B[2], (u32Key & CFG_78_PVR3_INDEX));
5994 break;
5995 default:
5996 break;
5997 }
5998 }
5999
6000 /*
6001 void HAL_PVR_SetTSIF(MS_U32 u32PVREng , MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
6002 {
6003 if (bPara)
6004 {
6005 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
6006 }
6007 else
6008 {
6009 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
6010 }
6011
6012 if (bExtSync)
6013 {
6014 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
6015 }
6016 else
6017 {
6018 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
6019 }
6020
6021 if (bDataSWP)
6022 {
6023 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6024 }
6025 else
6026 {
6027 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6028 }
6029 }
6030
6031 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis)
6032 {
6033 if(bDis)
6034 {
6035 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
6036 }
6037 else
6038 {
6039 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
6040 }
6041 }
6042
6043 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn)
6044 {
6045 if(bEn)
6046 {
6047 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6048 }
6049 else
6050 {
6051 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
6052 }
6053 }
6054 */
6055
HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)6056 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)
6057 {
6058 MS_U32 u32Data;
6059
6060 //reserved
6061 switch (u32Type)
6062 {
6063
6064 case INFO_FW_VERSION:
6065 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
6066 break;
6067 case INFO_FW_DATE:
6068 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE);
6069 break;
6070 default:
6071 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
6072 break;
6073
6074 }
6075
6076 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO);
6077
6078 _delay(10); // supposed TSP is able to respond in 10us
6079 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6080 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6081
6082 return u32Data;
6083 }
6084
HAL_TSP_HCMD_BufRst(MS_U32 u32Value)6085 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value)
6086 {
6087 // MS_U32 u32Data;
6088
6089 REG32_W(&_RegCtrl->MCU_Data0 , u32Value);
6090 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST);
6091 _delay(10); // supposed TSP is able to respond in 10us
6092
6093 return TRUE;
6094 }
6095
HAL_TSP_HCMD_Read(MS_U32 u32Addr)6096 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr)
6097 {
6098 MS_U32 u32Data;
6099
6100 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
6101 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ);
6102
6103 _delay(10); // supposed TSP is able to respond in 10us
6104 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6105 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6106
6107 return u32Data;
6108 }
6109
6110
HAL_TSP_HCMD_Write(MS_U32 u32Addr,MS_U32 u32Value)6111 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value)
6112 {
6113 MS_U32 u32Data;
6114
6115 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
6116 REG32_W(&_RegCtrl->MCU_Data1, u32Value);
6117 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE);
6118
6119 _delay(10); // supposed TSP is able to respond in 10us
6120 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6121 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6122
6123 return TRUE;
6124 }
6125
6126
HAL_TSP_HCMD_Alive(void)6127 MS_BOOL HAL_TSP_HCMD_Alive(void)
6128 {
6129 MS_U32 u32Data;
6130
6131 REG32_W(&_RegCtrl->MCU_Data1, 0);
6132 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD
6133 _delay(10); // supposed TSP is able to respond in 10us
6134 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6135 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6136
6137 return (u32Data == TSP_MCU_DATA_ALIVE)? TRUE : FALSE;
6138 }
6139
HAL_TSP_HCMD_SET(MS_U32 mcu_cmd,MS_U32 mcu_data0,MS_U32 mcu_data1)6140 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1)
6141 {
6142 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0);
6143 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1);
6144 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd);
6145 }
6146
HAL_TSP_HCMD_GET(MS_U32 * pmcu_cmd,MS_U32 * pmcu_data0,MS_U32 * pmcu_data1)6147 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1)
6148 {
6149 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd);
6150 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0);
6151 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1);
6152 }
6153
HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId,MS_BOOL bDis)6154 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis)
6155 {
6156 MS_U32 u32Data = bDis ;
6157
6158 REG32_W(&_RegCtrl->MCU_Data0, FltId);
6159 REG32_W(&_RegCtrl->MCU_Data1,u32Data);
6160 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here
6161 _delay(10); // supposed TSP is able to respond in 10us
6162 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6163
6164 return ;
6165 }
6166
HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)6167 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)
6168 {
6169 MS_U32 u32Data;
6170
6171 REG32_W(&_RegCtrl->MCU_Data0, u32Enable);
6172 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG);
6173
6174 _delay(10); // supposed TSP is able to respond in 10us
6175 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6176 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6177
6178 return REG32_R(&_RegCtrl->MCU_Data1);
6179 }
6180
HAL_TSP_GetDBGStatus(MS_U16 u16Sel)6181 MS_U32 HAL_TSP_GetDBGStatus(MS_U16 u16Sel)
6182 {
6183 REG16_CLR(&_RegCtrl->DBG_SEL, TSP_DBG_SEL_MASK);
6184 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK));
6185
6186 return REG32_R(&_RegCtrl->TSP_Debug);
6187 }
6188
6189 // [ToDo...]
HAL_TSP_INT_Enable(MS_U32 u32Mask)6190 void HAL_TSP_INT_Enable(MS_U32 u32Mask)
6191 {
6192 // u32Mask [0:7] for bank 0x15 7e bit[0:7]
6193 /*
6194 7: audio/video packet error
6195 6: DMA read done
6196 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15]
6197 4: TSP_FILE_RP meets TSP_FILE_TAIL.
6198 3: TSP_FILE_RP meets TSP_FILE_MID.
6199 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15]
6200 1: STR2MI_WADR meets STR2MI_MID.
6201 0: STR2MI_WADR meets STR2MI_TAIL."
6202 */
6203 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask) | TSP_HWINT_STATUS_MASK);
6204
6205 // u32Mask [8:15] for bank 0x16 6c bit[0:7]
6206 /*
6207 [7] : PVR2 meet_tail or PVR2_meet_mid
6208 [6] : vq0, vq1, vq2, vq3 overflow interrupt
6209 [5] : all DMA write address not in the protect zone interrupt
6210 [4] : PVR_cb meet the mid or PVR_cb meet the tail
6211 [3] : pcr filter 0 update finish
6212 [2] : pcr filter 1 update finish
6213 [1] : OTV HW interrupt
6214 [0] : reserved
6215 */
6216 REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK);
6217
6218 // u32Mask [16:23] for bank 0x16 6f bit[0:7]
6219 /*
6220 [7:2] : reserved
6221 [1] : pcr filter 3 update finish
6222 [0] : pcr filter 2 update finish
6223 */
6224 REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)) | TSP_HWINT3_STATUS_MASK);
6225 }
6226
6227
6228 // [ToDo...]
HAL_TSP_INT_Disable(MS_U32 u32Mask)6229 void HAL_TSP_INT_Disable(MS_U32 u32Mask)
6230 {
6231 //REG16_CLR(&_RegCtrl->HwInt_Stat, TSP_HWINT_EN_MASK & u32Mask);
6232 //REG16_CLR(&_RegCtrl->HwInt2_Stat, TSP_HWINT2_EN_MASK & (u32Mask >> 8));
6233
6234 REG16_W(&_RegCtrl->HwInt_Stat,
6235 (REG16_R(&_RegCtrl->HwInt_Stat) & ~(TSP_HWINT_EN_MASK & (u32Mask))) | TSP_HWINT_STATUS_MASK);
6236
6237 REG16_W(&_RegCtrl->HwInt2_Stat,
6238 (REG16_R(&_RegCtrl->HwInt2_Stat) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) | TSP_HWINT2_STATUS_MASK);
6239
6240 REG16_W(&_RegCtrl->HwInt3_Stat,
6241 (REG16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16))) | TSP_HWINT3_STATUS_MASK);
6242 }
6243
6244
6245 // [ToDo...]
HAL_TSP_INT_ClrHW(MS_U32 u32Mask)6246 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask)
6247 {
6248 //REG16_CLR(&_RegCtrl->HwInt_Stat, (u32Mask & 0x00FF) << 8);
6249 //REG16_CLR(&_RegCtrl->HwInt2_Stat, u32Mask & 0xFF00);
6250
6251 REG16_W(&_RegCtrl->HwInt_Stat,
6252 (REG16_R(&_RegCtrl->HwInt_Stat) & (~TSP_HWINT_STATUS_MASK)) |
6253 (((~u32Mask) << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK) );
6254
6255 REG16_W(&_RegCtrl->HwInt2_Stat,
6256 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) |
6257 (((~(u32Mask >> 8))<< TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS_MASK) );
6258
6259 REG16_W(&_RegCtrl->HwInt3_Stat,
6260 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) |
6261 (((~(u32Mask >> 16))<< TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK) );
6262 }
6263
6264 // [ToDo...]
HAL_TSP_INT_GetHW(void)6265 MS_U32 HAL_TSP_INT_GetHW(void)
6266 {
6267 MS_U32 status;
6268
6269 status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS_SHIFT) << 16);
6270
6271
6272 status |= ((MS_U32)(((REG16_R(&_RegCtrl->HwInt2_Stat) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STATUS_SHIFT) << 8));
6273
6274
6275 status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_SHIFT));
6276
6277 return (status & 0x00FFFFFF);
6278 }
6279
HAL_TSP_INT_ClrSW(void)6280 void HAL_TSP_INT_ClrSW(void)
6281 {
6282 REG32_W(&_RegCtrl->SwInt_Stat, 0);
6283 }
6284
HAL_TSP_INT_GetSW(void)6285 MS_U32 HAL_TSP_INT_GetSW(void)
6286 {
6287 return REG32_R(&_RegCtrl->SwInt_Stat);
6288 }
6289
HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx,MS_U32 inputSrc)6290 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc)
6291 {
6292 switch (bufIdx)
6293 {
6294 case 0:
6295 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2));
6296 break;
6297 case 1:
6298 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2));
6299 break;
6300 case 2:
6301 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2));
6302 break;
6303 case 3:
6304 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF3_SRC, inputSrc<<(bufIdx * 2));
6305 break;
6306 default:
6307 break;
6308 }
6309 }
6310
HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)6311 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)
6312 {
6313 if (bByPassEn)
6314 {
6315 REG16_SET(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
6316 }
6317 else
6318 {
6319 REG16_CLR(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
6320 }
6321 }
6322
6323 //@TODO
6324 #if 1
HAL_TSP_FileIn_SPDConfig(MS_U32 tsif,MS_BOOL CTR_mode)6325 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode)
6326 {
6327 if(CTR_mode == TRUE)
6328 {
6329 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05));
6330 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable
6331 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV
6332 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000);
6333 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000);
6334 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000);
6335 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld
6336 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV
6337 }
6338
6339 switch(tsif)
6340 {
6341 case 0: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI0_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6342 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6343 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6344 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6345 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6346 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6347 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6348 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6349 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6350 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY0);
6351 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF0_BYPASS);//bypass SPD
6352 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET); //TSIF SPD reset
6353 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET);
6354 break;
6355 case 1: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI1_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6356 /*
6357 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x2222); //file-in SPD key
6358 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x2222);
6359 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x2222);
6360 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x2222);
6361 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x3333);
6362 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x3333);
6363 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x3333);
6364 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x3333);
6365 */
6366 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6367 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6368 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6369 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6370 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6371 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6372 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6373 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6374 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY1);
6375 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF1_BYPASS);//bypass SPD
6376 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET); //TSIF SPD reset
6377 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET);
6378 break;
6379 case 2: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI2_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6380 /*
6381 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x4444); //file-in SPD key
6382 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x4444);
6383 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x4444);
6384 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x4444);
6385 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x5555);
6386 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x5555);
6387 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x5555);
6388 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x5555);
6389 */
6390 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6391 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6392 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6393 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6394 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6395 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6396 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6397 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6398 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY2);
6399 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF2_BYPASS);//bypass SPD
6400 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET); //TSIF SPD reset
6401 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET);
6402 break;
6403 case 3: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI3_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6404 /*
6405 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x6666); //file-in SPD key
6406 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x6666);
6407 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x6666);
6408 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x6666);
6409 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x7777);
6410 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x7777);
6411 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x7777);
6412 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x7777);
6413 */
6414 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6415 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6416 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6417 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6418 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6419 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6420 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6421 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6422 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY3);
6423 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF3_BYPASS);//bypass SPD
6424 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET); //TSIF SPD reset
6425 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET);
6426 break;
6427 default:printf("Not Support !!\n");
6428 break;
6429 }
6430 }
6431 #endif
6432
6433 // for TSO
HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId,MS_U32 u32TSOEng,MS_BOOL bEn)6434 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn)
6435 {
6436 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
6437 if(bEn)
6438 {
6439 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_TSOFLT_MASK) | (((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK));
6440 }
6441 else
6442 {
6443 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~(((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK)));
6444 }
6445 }
6446
HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap,MS_U32 * pu32CapInfo)6447 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo)
6448 {
6449 switch (eCap)
6450 {
6451 case E_TSP_HAL_CAP_TYPE_PIDFLT_NUM :
6452 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PIDFLT_NUM;
6453 break;
6454
6455 case E_TSP_HAL_CAP_TYPE_SECFLT_NUM :
6456 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECFLT_NUM;
6457 break;
6458
6459 case E_TSP_HAL_CAP_TYPE_SECBUF_NUM :
6460 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_NUM;
6461 break;
6462
6463 case E_TSP_HAL_CAP_TYPE_RECENG_NUM :
6464 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECENG_NUM;
6465 break;
6466
6467 case E_TSP_HAL_CAP_TYPE_RECFLT_NUM :
6468 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_NUM;
6469 break;
6470
6471 case E_TSP_HAL_CAP_TYPE_TSIF_NUM :
6472 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSIF_NUM;
6473 break;
6474
6475 case E_TSP_HAL_CAP_TYPE_DEMOD_NUM :
6476 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_DEMOD_NUM;
6477 break;
6478
6479 case E_TSP_HAL_CAP_TYPE_TSPAD_NUM :
6480 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSPAD_NUM;
6481 break;
6482
6483 case E_TSP_HAL_CAP_TYPE_VQ_NUM :
6484 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_NUM;
6485 break;
6486
6487 case E_TSP_HAL_CAP_TYPE_CAFLT_NUM :
6488 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAFLT_NUM;
6489 break;
6490
6491 case E_TSP_HAL_CAP_TYPE_CAKEY_NUM :
6492 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAKEY_NUM;
6493 break;
6494
6495 case E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN :
6496 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_ALIGN;
6497 break;
6498
6499 case E_TSP_HAL_CAP_TYPE_PVR_ALIGN:
6500 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PVR_ALIGN;
6501 break;
6502
6503 case E_TSP_HAL_CAP_TYPE_FW_ALIGN :
6504 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_ALIGN;
6505 break;
6506
6507 case E_TSP_HAL_CAP_TYPE_VQ_ALIGN :
6508 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_ALIGN;
6509 break;
6510
6511 case E_TSP_HAL_CAP_TYPE_VQ_PITCH :
6512 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_PITCH;
6513 break;
6514
6515 case E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM:
6516 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM;
6517 break;
6518
6519 case E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM:
6520 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM;
6521 break;
6522
6523 case E_TSP_HAL_CAP_TYPE_HW_TYPE:
6524 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HW_TYPE;
6525 break;
6526
6527 case E_TSP_HAL_CAP_TYPE_RECFLT_IDX :
6528 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_IDX;
6529 break;
6530
6531 case E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX :
6532 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX;
6533 break;
6534
6535 case E_TSP_HAL_CAP_TYPE_VFIFO_NUM:
6536 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VFIFO_NUM;
6537 break;
6538
6539 case E_TSP_HAL_CAP_TYPE_AFIFO_NUM:
6540 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_AFIFO_NUM;
6541 break;
6542
6543 case E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT:
6544 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT;
6545 break;
6546
6547 case E_TSP_HAL_CAP_FIQ_NUM:
6548 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FIQ_NUM;
6549 break;
6550
6551 case E_TSP_HAL_CAP_FW_BUF_SIZE:
6552 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_BUF_SIZE;
6553 break;
6554 case E_TSP_HAL_CAP_FW_BUF_RANGE:
6555 *(pu32CapInfo) = TSP_FW_BUF_LOW_BUD;
6556 *(pu32CapInfo + 1) = TSP_FW_BUF_UP_BUD;
6557 break;
6558 case E_TSP_HAL_CAP_VQ_BUF_RANGE:
6559 *(pu32CapInfo) = TSP_VQ_BUF_LOW_BUD;
6560 *(pu32CapInfo + 1) = TSP_VQ_BUF_UP_BUD;
6561 break;
6562 case E_TSP_HAL_CAP_SEC_BUF_RANGE:
6563 *(pu32CapInfo) = TSP_SEC_BUF_LOW_BUD;
6564 *(pu32CapInfo + 1) = TSP_SEC_BUF_UP_BUD;
6565 break;
6566 default:
6567 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_NULL;
6568 return FALSE;
6569 }
6570
6571 return TRUE;
6572 }
6573
HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)6574 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)
6575 {
6576 if(bEnable)
6577 {
6578 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
6579 }
6580 else
6581 {
6582 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
6583 }
6584 }
6585
HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType,MS_BOOL bEnable)6586 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable)
6587 {
6588 if(bEnable)
6589 {
6590 switch (eHalPktType)
6591 {
6592 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
6593 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
6594 break;
6595 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
6596 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
6597 break;
6598 default:
6599 break;
6600 }
6601 }
6602 else
6603 {
6604 switch (eHalPktType)
6605 {
6606 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
6607 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
6608 break;
6609 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
6610 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
6611 break;
6612 default:
6613 break;
6614 }
6615 }
6616 }
6617
HAL_TSP_TEI_SKIP(MS_U32 tsIf,MS_BOOL bEnable)6618 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable)
6619 {
6620 if(bEnable)
6621 {
6622 switch (tsIf)
6623 {
6624 case 0:
6625 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
6626 break;
6627 case 1:
6628 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
6629 break;
6630 case 2:
6631 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
6632 break;
6633 case 3:
6634 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3);
6635 break;
6636 default:
6637 break;
6638 }
6639 }
6640 else
6641 {
6642 switch (tsIf)
6643 {
6644 case 0:
6645 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
6646 break;
6647 case 1:
6648 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
6649 break;
6650 case 2:
6651 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
6652 break;
6653 case 3:
6654 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3);
6655 break;
6656 default:
6657 break;
6658 }
6659 }
6660
6661 }
6662
HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)6663 void HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)
6664 {
6665 switch (eFltType)
6666 {
6667 case E_TSP_DST_FIFO_VIDEO :
6668 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
6669 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
6670 break;
6671 case E_TSP_DST_FIFO_VIDEO3D:
6672 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
6673 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
6674 break;
6675 case E_TSP_DST_FIFO_AUDIO :
6676 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
6677 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
6678 break;
6679 case E_TSP_DST_FIFO_AUDIO2 :
6680 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
6681 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
6682 break;
6683 case E_TSP_DST_FIFO_AUDIO3 :
6684 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
6685 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
6686 break;
6687 case E_TSP_DST_FIFO_AUDIO4 :
6688 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
6689 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
6690 break;
6691 default :
6692 printf("[%s][%s][%d] Clear AVPktNum Error\n",__FILE__,__FUNCTION__,__LINE__);
6693 break;
6694 }
6695 }
6696
HAL_TSP_FltNullPkt_En(MS_BOOL bEn)6697 void HAL_TSP_FltNullPkt_En(MS_BOOL bEn)
6698 {
6699 if(bEn == TRUE)
6700 {
6701 REG16_SET(&_RegCtrl3->CFG3_2D,CFG3_2D_FILTER_NULL_PKT);
6702 }
6703 else
6704 {
6705 REG16_CLR(&_RegCtrl3->CFG3_2D,CFG3_2D_FILTER_NULL_PKT);
6706 }
6707 }
6708
HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)6709 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)
6710 {
6711 if(bEn == TRUE)
6712 {
6713 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
6714 }
6715 else
6716 {
6717 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
6718 }
6719 }
6720
HAL_TSP_OR_Address_Protect(MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)6721 void HAL_TSP_OR_Address_Protect(MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
6722 {
6723 MS_U8 u8MiuSel;
6724 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
6725 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
6726 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
6727
6728 if (u8MiuSel >= E_CHIP_MIU_0){
6729 REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK));
6730 REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK));
6731 }
6732 }
6733
HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)6734 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)
6735 {
6736
6737 if(bEn == TRUE)
6738 {
6739 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
6740 }
6741 else
6742 {
6743 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
6744 }
6745 }
6746
HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)6747 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
6748 {
6749 MS_U8 u8MiuSel;
6750 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
6751 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
6752 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
6753
6754 if (u8MiuSel >= E_CHIP_MIU_0){
6755 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_DMAW_BND_MASK);
6756 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_DMAW_BND_MASK);
6757
6758 switch(u8SecID)
6759 {
6760 case 0:
6761 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd);
6762 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd);
6763 break;
6764 case 1:
6765 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd);
6766 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd);
6767 break;
6768 default:
6769 break;
6770 }
6771 }
6772 }
6773
HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)6774 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)
6775 {
6776 if(bEnable)
6777 {
6778 switch(u32PVREng)
6779 {
6780 case 0:
6781 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
6782 break;
6783 case 1:
6784 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
6785 break;
6786 case 2:
6787 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN);
6788 break;
6789 case 3:
6790 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN);
6791 break;
6792 default:
6793 break;
6794 }
6795 }
6796 else
6797 {
6798 switch(u32PVREng)
6799 {
6800 case 0:
6801 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
6802 break;
6803 case 1:
6804 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
6805 break;
6806 case 2:
6807 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN);
6808 break;
6809 case 3:
6810 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN);
6811 break;
6812 default:
6813 break;
6814 }
6815 }
6816 }
6817
HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)6818 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
6819 {
6820 MS_U8 u8MiuSel;
6821 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
6822 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
6823 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
6824
6825 if (u8MiuSel >= E_CHIP_MIU_0){
6826 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_PVR_MASK);
6827 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_PVR_MASK);
6828
6829 switch(u32PVREng)
6830 {
6831 case 0:
6832 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd);
6833 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd);
6834 break;
6835 case 1:
6836 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd);
6837 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd);
6838 break;
6839 case 2:
6840 REG32_W(&_RegCtrl->DMAW_LBND4, u32LBnd);
6841 REG32_W(&_RegCtrl->DMAW_UBND4, u32UBnd);
6842 break;
6843 case 3:
6844 REG32_W(&_RegCtrl3->CFG3_12_13, u32LBnd);
6845 REG32_W(&_RegCtrl3->CFG3_14_15, u32UBnd);
6846 break;
6847 default:
6848 break;
6849 }
6850 }
6851 }
6852
HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)6853 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)
6854 {
6855 if(bEnable)
6856 {
6857 switch(eFileEng)
6858 {
6859 case E_FILEENG_TSIF0:
6860 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
6861 break;
6862 case E_FILEENG_TSIF1:
6863 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
6864 break;
6865 case E_FILEENG_TSIF2:
6866 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
6867 break;
6868 case E_FILEENG_TSIF3:
6869 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN);
6870 break;
6871 default:
6872 break;
6873 }
6874 }
6875 else
6876 {
6877 switch(eFileEng)
6878 {
6879 case E_FILEENG_TSIF0:
6880 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
6881 break;
6882 case E_FILEENG_TSIF1:
6883 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
6884 break;
6885 case E_FILEENG_TSIF2:
6886 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
6887 break;
6888 case E_FILEENG_TSIF3:
6889 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN);
6890 break;
6891 default:
6892 break;
6893 }
6894 }
6895 }
6896
HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)6897 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
6898 {
6899 MS_U8 u8MiuSel;
6900 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
6901 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
6902 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
6903
6904 if (u8MiuSel >= E_CHIP_MIU_0){
6905 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
6906 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
6907
6908 switch(eFileEng)
6909 {
6910 case E_FILEENG_TSIF0:
6911 REG32_W(&_RegCtrl6->CFG6_30_31, u32LBnd);
6912 REG32_W(&_RegCtrl6->CFG6_32_33, u32UBnd);
6913 break;
6914 case E_FILEENG_TSIF1:
6915 REG32_W(&_RegCtrl6->CFG6_34_35, u32LBnd);
6916 REG32_W(&_RegCtrl6->CFG6_36_37, u32UBnd);
6917 break;
6918 case E_FILEENG_TSIF2:
6919 REG32_W(&_RegCtrl6->CFG6_38_39, u32LBnd);
6920 REG32_W(&_RegCtrl6->CFG6_3A_3B, u32UBnd);
6921 break;
6922 case E_FILEENG_TSIF3:
6923 REG32_W(&_RegCtrl6->CFG6_3C_3D, u32LBnd);
6924 REG32_W(&_RegCtrl6->CFG6_3E_3F, u32UBnd);
6925 break;
6926 default:
6927 break;
6928 }
6929 }
6930 }
6931
HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)6932 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)
6933 {
6934 if(bEnable)
6935 {
6936 switch(u32MMFIEng)
6937 {
6938 case 0:
6939 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
6940 break;
6941 case 1:
6942 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
6943 break;
6944 default:
6945 break;
6946 }
6947 }
6948 else
6949 {
6950 switch(u32MMFIEng)
6951 {
6952 case 0:
6953 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
6954 break;
6955 case 1:
6956 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
6957 break;
6958 default:
6959 break;
6960 }
6961 }
6962 }
6963
HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)6964 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
6965 {
6966 MS_U8 u8MiuSel;
6967 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
6968 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
6969 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
6970
6971 if (u8MiuSel >= E_CHIP_MIU_0){
6972 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
6973 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
6974
6975 switch(u32MMFIEng)
6976 {
6977 case 0:
6978 REG32_W(&_RegCtrl6->CFG6_48_49, u32LBnd);
6979 REG32_W(&_RegCtrl6->CFG6_4A_4B, u32UBnd);
6980 break;
6981 case 1:
6982 REG32_W(&_RegCtrl6->CFG6_4C_4D, u32LBnd);
6983 REG32_W(&_RegCtrl6->CFG6_4E_4F, u32UBnd);
6984 break;
6985 default:
6986 break;
6987 }
6988 }
6989 }
6990
6991
HAL_TSP_SaveFltState(void)6992 void HAL_TSP_SaveFltState(void)
6993 {
6994 MS_U32 u32Size;
6995 TSP32 * pRegEnd;
6996 TSP32 * pReg;
6997 int i, j;
6998
6999 for (i = 0; i < TSP_PIDFLT_NUM; i++)
7000 {
7001 _u32PidFltReg[i] = TSP32_IdrR(&(_REGPid0->Flt[i]));
7002 _u32PidDstReg[i] = TSP32_IdrR(&(_REGPid1->Flt[i]));
7003 }
7004
7005 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
7006 for (i = 0; i < TSP_SECFLT_NUM; i++)
7007 {
7008 pReg = (TSP32*)&(_REGSec->Flt[i]);
7009 pRegEnd = pReg + u32Size;
7010 j = 0;
7011 for ( ; pReg < pRegEnd; pReg++)
7012 {
7013 _u32SecReg[i*u32Size+j] = TSP32_IdrR(pReg);
7014 j++;
7015 }
7016 }
7017 }
7018
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)7019 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
7020 {
7021 MS_U32 u32Data = 0;
7022 MS_BOOL brtn = FALSE;
7023 //printf("\033[31m [%s] Mode = %lX , Config0 =%lX , Config1 = %lX \033[m\n",__FUNCTION__,u32Cmd,u32Config0,u32Config1); // Eason test
7024 switch (u32Cmd)
7025 {
7026 case HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK:
7027 REG32_W(&_RegCtrl->MCU_Data1, u32Config0);
7028 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE);
7029 _delay(10); // supposed TSP is able to respond in 10us
7030 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
7031 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
7032 brtn = (u32Data == TSP_MCU_CMD_SEC_CC_CHECK_DISABLE)? TRUE : FALSE;
7033 break;
7034 default:
7035 break;
7036 }
7037 return brtn;
7038 }
7039
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_BOOL bEnable)7040 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable)
7041 {
7042 printf("[%s] not support!!\n",__FUNCTION__);
7043 return FALSE;
7044 }
7045
HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng,MS_U16 u16CaPvrMode,MS_BOOL bEnable)7046 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable)
7047 {
7048 MS_U16 u16value = REG16_R(&_RegCtrl3->CFG3_38);
7049
7050 switch(u32Eng)
7051 {
7052 case 0:
7053 u16value &= ~(HW4_CFG38_CA_PVR1_SEL_MASK|HW4_CFG38_PKT192_SPS_EN1);
7054 break;
7055 case 1:
7056 u16value &= ~(HW4_CFG38_CA_PVR2_SEL_MASK|HW4_CFG38_PKT192_SPS_EN2);
7057 break;
7058 case 2:
7059 u16value &= ~(HW4_CFG38_CA_PVR3_SEL_MASK|HW4_CFG38_PKT192_SPS_EN3);
7060 break;
7061 case 3:
7062 u16value &= ~(HW4_CFG38_CA_PVR4_SEL_MASK|HW4_CFG38_PKT192_SPS_EN4);
7063 break;
7064 default:
7065 return FALSE;
7066 }
7067
7068 if(bEnable)
7069 {
7070 switch(u32Eng)
7071 {
7072 case 0:
7073 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR1_SEL_SHIFT);
7074 u16value |= HW4_CFG38_PKT192_SPS_EN1;
7075 break;
7076 case 1:
7077 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR2_SEL_SHIFT);
7078 u16value |= HW4_CFG38_PKT192_SPS_EN2;
7079 break;
7080 case 2:
7081 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR3_SEL_SHIFT);
7082 u16value |= HW4_CFG38_PKT192_SPS_EN3;
7083 break;
7084 case 3:
7085 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR4_SEL_SHIFT);
7086 u16value |= HW4_CFG38_PKT192_SPS_EN4;
7087 break;
7088 }
7089 }
7090
7091 REG16_W(&_RegCtrl3->CFG3_38, u16value);
7092
7093 return TRUE;
7094
7095 }
7096
7097 //@TODO
7098 #if 1
HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng,MS_BOOL CTR_mode)7099 void HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng, MS_BOOL CTR_mode)
7100 {
7101 switch(u32Eng)
7102 {
7103 case 0: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN1);
7104 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR1_KEY);
7105 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7106 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7107 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7108 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7109 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7110 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7111 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7112 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7113 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY1);
7114 break;
7115 case 1: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN2);
7116 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR2_KEY);
7117 /*
7118 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x2222);//PVR SPS key
7119 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x2222);
7120 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x2222);
7121 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x2222);
7122 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x3333);
7123 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x3333);
7124 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x3333);
7125 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x3333);
7126 */
7127 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7128 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7129 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7130 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7131 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7132 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7133 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7134 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7135 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY2);
7136 break;
7137 case 2: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN3);
7138 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR3_KEY);
7139 /*
7140 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x4444);//PVR SPS key
7141 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x4444);
7142 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x4444);
7143 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x4444);
7144 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x5555);
7145 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x5555);
7146 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x5555);
7147 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x5555);
7148 */
7149 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7150 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7151 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7152 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7153 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7154 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7155 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7156 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7157 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY3);
7158 break;
7159 case 3: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN4);
7160 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR4_KEY);
7161 /*
7162 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x6666);//PVR SPS key
7163 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x6666);
7164 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x6666);
7165 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x6666);
7166 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x7777);
7167 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x7777);
7168 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x7777);
7169 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x7777);
7170 */
7171 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
7172 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
7173 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
7174 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
7175 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
7176 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
7177 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
7178 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
7179 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY4);
7180 break;
7181 default: printf("Not Support !!\n");
7182 break;
7183 }
7184
7185 if(CTR_mode == TRUE)
7186 {
7187 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05));
7188 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode
7189 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV
7190 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000);
7191 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000);
7192 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000);
7193 REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld
7194 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV
7195 }
7196 }
7197 #endif
7198
7199 // u32GroupId: 0 -> filter0 ~ filter31
7200 // u32GroupId: 1 -> filter32 ~ filter63
7201 // u32GroupId: 2 -> filter64 ~ filter95
7202 // u32GroupId: 3 -> filter96 ~ filter127
7203 // u32GroupId: 4 -> filter128 ~ filter159
7204 // u32GroupId: 5 -> filter160 ~ filter191
7205
7206
HAL_DSCMB_GetStatus(MS_U32 u32PktDmx,MS_U32 u32GroupId,MS_U32 u32PidFltId,MS_U32 * pu32ScmbSts)7207 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts)
7208 {
7209 MS_U16 u16PktDmxSrc;
7210 MS_U16 u16WordId;
7211 MS_U32 u32PIDFltMask = u32PidFltId;
7212
7213 if(u32PidFltId != 0xFFFFFFFF)
7214 {
7215 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
7216 }
7217
7218 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK);
7219
7220 switch(u32PktDmx)
7221 {
7222 case 0:
7223 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX0 << TSP_MATCH_PID_SRC_SHIFT);
7224 break;
7225 case 1:
7226 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX1 << TSP_MATCH_PID_SRC_SHIFT);
7227 break;
7228 case 2:
7229 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX2 << TSP_MATCH_PID_SRC_SHIFT);
7230 break;
7231 case 3:
7232 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX3 << TSP_MATCH_PID_SRC_SHIFT);
7233 break;
7234 default:
7235 break;
7236 }
7237
7238 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc);
7239
7240 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to load match_pid_num
7241
7242 // get status
7243 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze
7244
7245 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK);
7246
7247 if (u32GroupId < 6)
7248 {
7249 u16WordId = _SET_(u16WordId, u32GroupId << TSP_MATCH_PID_SEL_SHIFT);
7250 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId);
7251 }
7252 else
7253 {
7254 printf("[TSP_ERR][%s][%d] Unsupported u32GroupId (%lu)!!!\n",__FUNCTION__, __LINE__, (long unsigned int)u32GroupId);
7255 }
7256
7257 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask);
7258
7259 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable
7260
7261 if(u32PIDFltMask != 0xFFFFFFFF)
7262 {
7263 *pu32ScmbSts = ((*pu32ScmbSts > 0) ? 1: 0);
7264 }
7265
7266 return TRUE;
7267 }
7268
7269 // -------------------------------------------------------------
7270 // Merge Stream
7271 // -------------------------------------------------------------
HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SyncByte,MS_BOOL bSet)7272 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet)
7273 {
7274 REG16 *SynReg=0;
7275 MS_U16 u16Mask = 0x00FF, u16Sync = 0, u16Shift = 0;
7276
7277 switch(u8Path)
7278 {
7279 case TSP_TSIF0:
7280 SynReg = &(_RegCtrl6->SyncByte_tsif0[u8Idx>>1]);
7281 break;
7282 case TSP_TSIF1:
7283 SynReg = &(_RegCtrl6->SyncByte_tsif1[u8Idx>>1]);
7284 break;
7285 case TSP_TSIF2:
7286 SynReg = &(_RegCtrl6->SyncByte_tsif2[u8Idx>>1]);
7287 break;
7288 case TSP_TSIF3:
7289 SynReg = &(_RegCtrl6->SyncByte_tsif3[u8Idx>>1]);
7290 break;
7291 default:
7292 return FALSE;
7293 }
7294
7295
7296 if(u8Idx & 0x1)
7297 {
7298 u16Shift = 8;
7299 }
7300
7301 if(bSet == TRUE)
7302 {
7303 u16Sync = (MS_U16)(*pu8SyncByte & 0xFF);
7304 REG16_W(SynReg,((REG16_R(SynReg) & ~(u16Mask << u16Shift)) | (u16Sync << u16Shift)));
7305 }
7306 else
7307 {
7308 u16Sync = (REG16_R(SynReg) & (u16Mask << u16Shift)) >> u16Shift;
7309 *pu8SyncByte = (MS_U8)u16Sync;
7310 }
7311
7312 return TRUE;
7313
7314 }
7315
HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SrcId,MS_BOOL bSet)7316 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet)
7317 {
7318 REG16 *SrcIdReg =0;
7319 MS_U16 u16SrcId = 0, u16Mask = 0x000F, u16Shift = 0;
7320
7321 switch(u8Path)
7322 {
7323 case TSP_TSIF0:
7324 SrcIdReg = &(_RegCtrl6->SourceId_tsif0[u8Idx>>2]);
7325 break;
7326 case TSP_TSIF1:
7327 SrcIdReg = &(_RegCtrl6->SourceId_tsif1[u8Idx>>2]);
7328 break;
7329 case TSP_TSIF2:
7330 SrcIdReg = &(_RegCtrl6->SourceId_tsif2[u8Idx>>2]);
7331 break;
7332 case TSP_TSIF3:
7333 SrcIdReg = &(_RegCtrl6->SourceId_tsif3[u8Idx>>2]);
7334 break;
7335 default:
7336 return FALSE;
7337 }
7338
7339 switch(u8Idx & 0x3)
7340 {
7341 case 0x1:
7342 u16Shift = 4;
7343 break;
7344 case 0x2:
7345 u16Shift = 8;
7346 break;
7347 case 0x3:
7348 u16Shift = 12;
7349 break;
7350 }
7351
7352 if(bSet == TRUE)
7353 {
7354 u16SrcId = (MS_U16)(*pu8SrcId & 0xFF);
7355 REG16_W(SrcIdReg,((REG16_R(SrcIdReg) & ~(u16Mask << u16Shift)) | (u16SrcId << u16Shift)));
7356 }
7357 else
7358 {
7359 u16SrcId = (REG16_R(SrcIdReg) & (u16Mask << u16Shift)) >> u16Shift;
7360 *pu8SrcId = (MS_U8)u16SrcId;
7361 }
7362
7363 return TRUE;
7364 }
7365
HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path,MS_U8 u8PktHeaderLen)7366 static void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen)
7367 {
7368 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7369
7370 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_MXL_PKT_HEADER_MASK)) | ((u8PktHeaderLen << TSP_MXL_PKT_HEADER_SHIFT) & TSP_MXL_PKT_HEADER_MASK)));
7371 }
7372
HAL_TSP_PktConverter_PktMode(MS_U8 u8Path,TSP_HAL_PKT_MODE ePktMode)7373 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode)
7374 {
7375 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7376
7377 switch(ePktMode)
7378 {
7379 case E_TSP_HAL_PKT_MODE_NORMAL:
7380 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_188Mode));
7381 break;
7382 case E_TSP_HAL_PKT_MODE_CI:
7383 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_CIMode));
7384 break;
7385 case E_TSP_HAL_PKT_MODE_OPEN_CABLE:
7386 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_OpenCableMode));
7387 break;
7388 case E_TSP_HAL_PKT_MODE_ATS:
7389 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_ATSMode));
7390 break;
7391 case E_TSP_HAL_PKT_MODE_MXL_192:
7392 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7393 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,4);
7394 break;
7395 case E_TSP_HAL_PKT_MODE_MXL_196:
7396 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7397 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,8);
7398 break;
7399 case E_TSP_HAL_PKT_MODE_MXL_200:
7400 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7401 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,12);
7402 break;
7403 case E_TSP_HAL_PKT_MODE_ND:
7404 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_NagraDongleMode));
7405 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,1);
7406 break;
7407 default:
7408 printf("[TSP_ERR][%s][%d] Wrong PktConverter Packet Mode!!!\n",__FUNCTION__,__LINE__);
7409 return FALSE;
7410 }
7411
7412 return TRUE;
7413 }
7414
HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path,MS_BOOL bEnable)7415 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable)
7416 {
7417 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7418
7419 if(bEnable)
7420 {
7421 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47)); // Set 1 to force sync byte be 0x47
7422 }
7423 else
7424 {
7425 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47));
7426 }
7427 }
7428
HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path,MS_BOOL bEnable)7429 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable)
7430 {
7431 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7432
7433 if(bEnable)
7434 {
7435 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_SRC_ID_FLT_EN)); // Set 1 to enable filter sync byte and path ID match
7436 }
7437 else
7438 {
7439 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_SRC_ID_FLT_EN));
7440 }
7441 }
7442
7443
HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId,MS_U32 u32SrcId)7444 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId)
7445 {
7446 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
7447 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcId << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
7448 }
7449
HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)7450 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)
7451 {
7452 MS_U8 u8Id;
7453 MS_U8 u8SyncByte;
7454
7455 u8SyncByte = 0x47;
7456 for(u8Id = 0; u8Id < TSP_MERGESTREAM_NUM; u8Id++,u8SyncByte++)
7457 {
7458 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Id, &u8SyncByte, TRUE);
7459 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Id, &u8Id, TRUE);
7460 }
7461 HAL_TSP_PktConverter_PktMode(u8Path,E_TSP_HAL_PKT_MODE_NORMAL);
7462 }
7463
7464
7465 //-------------------------------------------------------------------------------------------------
7466 // For Debug Table
7467 //-------------------------------------------------------------------------------------------------
7468
HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)7469 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)
7470 {
7471 switch (eFlow)
7472 {
7473 case E_TSP_HAL_FLOW_LIVE0:
7474 return E_TSP_SRC_PKTDMX0;
7475 case E_TSP_HAL_FLOW_LIVE1:
7476 return E_TSP_SRC_PKTDMX2;
7477 case E_TSP_HAL_FLOW_LIVE2:
7478 return E_TSP_SRC_PKTDMX3;
7479 case E_TSP_HAL_FLOW_LIVE3:
7480 return E_TSP_SRC_PKTDMX1;
7481 case E_TSP_HAL_FLOW_FILE0:
7482 return E_TSP_SRC_PKTDMX1;
7483 case E_TSP_HAL_FLOW_FILE1:
7484 return E_TSP_SRC_PKTDMX3;
7485 case E_TSP_HAL_FLOW_FILE2:
7486 return E_TSP_SRC_PKTDMX0;
7487 case E_TSP_HAL_FLOW_FILE3:
7488 return E_TSP_SRC_PKTDMX2;
7489 case E_TSP_HAL_FLOW_MMFI0:
7490 return E_TSP_SRC_MMFI0;
7491 case E_TSP_HAL_FLOW_MMFI1:
7492 return E_TSP_SRC_MMFI1;
7493 default:
7494 printf("[TSP_ERR][%s][%d] UnSupported Debug Flow : %d !!!\n",__FUNCTION__, __LINE__,eFlow);
7495 return E_TSP_SRC_INVALID;
7496 }
7497 }
7498
HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)7499 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)
7500 {
7501 MS_U16 u16TSIF = 0;;
7502
7503 switch(u32TsIf)
7504 {
7505 case 0:
7506 u16TSIF = TSIF_SRC_SEL_TSIF0;
7507 break;
7508 case 1:
7509 u16TSIF = TSIF_SRC_SEL_TSIF1;
7510 break;
7511 case 2:
7512 u16TSIF = TSIF_SRC_SEL_TSIF2;
7513 break;
7514 case 3:
7515 u16TSIF = TSIF_SRC_SEL_TSIF3;
7516 break;
7517 default:
7518 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7519 break;
7520 }
7521
7522 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_TSIF_SRC_SEL_MASK,(u16TSIF << CFG5_7F_TSIF_SRC_SEL_SHIFT));
7523 }
7524
HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)7525 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
7526 {
7527 if(bEn == TRUE)
7528 {
7529 switch(u32TsIf)
7530 {
7531 case 0:
7532 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
7533 break;
7534 case 1:
7535 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
7536 break;
7537 case 2:
7538 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
7539 break;
7540 case 3:
7541 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD);
7542 break;
7543 default:
7544 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7545 break;
7546 }
7547 }
7548 else
7549 {
7550 switch(u32TsIf)
7551 {
7552 case 0:
7553 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
7554 break;
7555 case 1:
7556 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
7557 break;
7558 case 2:
7559 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
7560 break;
7561 case 3:
7562 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD);
7563 break;
7564 default:
7565 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7566 break;
7567 }
7568 }
7569
7570 }
7571
HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf,MS_BOOL bLock)7572 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock)
7573 {
7574 if(bLock) // 188 mode
7575 {
7576 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
7577 }
7578 else // Non 188 mode
7579 {
7580 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
7581 }
7582
7583 return REG16_R(&_RegCtrl5->Locked_PKT_Cnt);
7584 }
7585
HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)7586 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)
7587 {
7588 switch (u32Tsif)
7589 {
7590 case 0 :
7591 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
7592 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
7593 break;
7594 case 1:
7595 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
7596 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
7597 break;
7598 case 2:
7599 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
7600 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
7601 break;
7602 case 3:
7603 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR);
7604 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR);
7605 break;
7606 default :
7607 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
7608 break;
7609 }
7610 }
7611
HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)7612 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)
7613 {
7614 switch (eClrSrc)
7615 {
7616 case E_TSP_SRC_PKTDMX0:
7617 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX0 << CFG5_7F_CLR_SRC_SHIFT);
7618 break;
7619 case E_TSP_SRC_PKTDMX1:
7620 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX1 << CFG5_7F_CLR_SRC_SHIFT);
7621 break;
7622 case E_TSP_SRC_PKTDMX2:
7623 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX2 << CFG5_7F_CLR_SRC_SHIFT);
7624 break;
7625 case E_TSP_SRC_PKTDMX3:
7626 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX3 << CFG5_7F_CLR_SRC_SHIFT);
7627 break;
7628 case E_TSP_SRC_MMFI0:
7629 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI0 << CFG5_7F_CLR_SRC_SHIFT);
7630 break;
7631 case E_TSP_SRC_MMFI1:
7632 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI1 << CFG5_7F_CLR_SRC_SHIFT);
7633 break;
7634 default:
7635 printf("[%s][%s][%d] UnSupported Clear Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,eClrSrc);
7636 break;
7637 }
7638 }
7639
HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)7640 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId)
7641 {
7642 MS_U16 u16AvSrc = 0;
7643
7644 switch(ePktDmxId)
7645 {
7646 case E_TSP_SRC_PKTDMX0:
7647 u16AvSrc = AV_PKT_SRC_PKTDMX0;
7648 break;
7649 case E_TSP_SRC_PKTDMX1:
7650 u16AvSrc = AV_PKT_SRC_PKTDMX1;
7651 break;
7652 case E_TSP_SRC_PKTDMX2:
7653 u16AvSrc = AV_PKT_SRC_PKTDMX2;
7654 break;
7655 case E_TSP_SRC_PKTDMX3:
7656 u16AvSrc = AV_PKT_SRC_PKTDMX3;
7657 break;
7658 case E_TSP_SRC_MMFI0:
7659 u16AvSrc = AV_PKT_SRC_MMFI0;
7660 break;
7661 case E_TSP_SRC_MMFI1:
7662 u16AvSrc = AV_PKT_SRC_MMFI1;
7663 break;
7664 default:
7665 printf("[%s][%s][%d] UnSupported AV Source : %d!\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
7666 break;
7667 }
7668
7669 switch (eAvType)
7670 {
7671 case E_TSP_DST_FIFO_VIDEO :
7672 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_SRC_MASK, u16AvSrc << CFG5_7E_VID_SRC_SHIFT);
7673 break;
7674 case E_TSP_DST_FIFO_VIDEO3D :
7675 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_3D_SRC_MASK, u16AvSrc << CFG5_7E_VID_3D_SRC_SHIFT);
7676 break;
7677 case E_TSP_DST_FIFO_AUDIO :
7678 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDA_SRC_MASK, u16AvSrc << CFG5_7E_AUDA_SRC_SHIFT);
7679 break;
7680 case E_TSP_DST_FIFO_AUDIO2 :
7681 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDB_SRC_MASK, u16AvSrc << CFG5_7E_AUDB_SRC_SHIFT);
7682 break;
7683 case E_TSP_DST_FIFO_AUDIO3 :
7684 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_AUDC_SRC_MASK, u16AvSrc << CFG5_78_AUDC_SRC_SHIFT);
7685 break;
7686 case E_TSP_DST_FIFO_AUDIO4 :
7687 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_AUDD_SRC_MASK, u16AvSrc << CFG5_78_AUDD_SRC_SHIFT);
7688 break;
7689 default:
7690 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7691 break;
7692 }
7693 }
7694
HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)7695 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn)
7696 {
7697 if(bEn == TRUE)
7698 {
7699 switch (eAvType)
7700 {
7701 case E_TSP_DST_FIFO_VIDEO :
7702 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
7703 break;
7704 case E_TSP_DST_FIFO_VIDEO3D :
7705 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
7706 break;
7707 case E_TSP_DST_FIFO_AUDIO :
7708 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
7709 break;
7710 case E_TSP_DST_FIFO_AUDIO2 :
7711 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
7712 break;
7713 case E_TSP_DST_FIFO_AUDIO3 :
7714 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD);
7715 break;
7716 case E_TSP_DST_FIFO_AUDIO4 :
7717 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD);
7718 break;
7719 default :
7720 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7721 break;
7722 }
7723 }
7724 else
7725 {
7726 switch (eAvType)
7727 {
7728 case E_TSP_DST_FIFO_VIDEO :
7729 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
7730 break;
7731 case E_TSP_DST_FIFO_VIDEO3D :
7732 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
7733 break;
7734 case E_TSP_DST_FIFO_AUDIO :
7735 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
7736 break;
7737 case E_TSP_DST_FIFO_AUDIO2 :
7738 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
7739 break;
7740 case E_TSP_DST_FIFO_AUDIO3 :
7741 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD);
7742 break;
7743 case E_TSP_DST_FIFO_AUDIO4 :
7744 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD);
7745 break;
7746 default :
7747 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7748 break;
7749 }
7750 }
7751 }
7752
HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)7753 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)
7754 {
7755 switch (eAvType)
7756 {
7757 case E_TSP_DST_FIFO_VIDEO :
7758 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7759 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
7760 case E_TSP_DST_FIFO_VIDEO3D:
7761 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7762 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
7763 case E_TSP_DST_FIFO_AUDIO :
7764 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7765 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
7766 case E_TSP_DST_FIFO_AUDIO2 :
7767 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7768 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
7769 default :
7770 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7771 return 0;
7772 }
7773 }
7774
HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)7775 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)
7776 {
7777 switch (eAvType)
7778 {
7779 case E_TSP_DST_FIFO_VIDEO :
7780 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
7781 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
7782 break;
7783 case E_TSP_DST_FIFO_VIDEO3D :
7784 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
7785 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
7786 break;
7787 case E_TSP_DST_FIFO_AUDIO :
7788 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
7789 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
7790 break;
7791 case E_TSP_DST_FIFO_AUDIO2 :
7792 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
7793 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
7794 break;
7795 case E_TSP_DST_FIFO_AUDIO3 :
7796 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR);
7797 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR);
7798 break;
7799 case E_TSP_DST_FIFO_AUDIO4 :
7800 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR);
7801 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR);
7802 break;
7803 default :
7804 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7805 break;
7806 }
7807 }
7808
HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)7809 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)
7810 {
7811 MS_U16 u16AvType = 0;
7812
7813 switch(eAvType)
7814 {
7815 case E_TSP_DST_FIFO_VIDEO:
7816 u16AvType = DIS_DROP_CNT_V;
7817 break;
7818 case E_TSP_DST_FIFO_VIDEO3D:
7819 u16AvType = DIS_DROP_CNT_V3D;
7820 break;
7821 case E_TSP_DST_FIFO_AUDIO:
7822 u16AvType = DIS_DROP_CNT_A;
7823 break;
7824 case E_TSP_DST_FIFO_AUDIO2:
7825 u16AvType = DIS_DROP_CNT_AD;
7826 break;
7827 case E_TSP_DST_FIFO_AUDIO3:
7828 u16AvType = DIS_DROP_CNT_ADC;
7829 break;
7830 case E_TSP_DST_FIFO_AUDIO4:
7831 u16AvType = DIS_DROP_CNT_ADD;
7832 break;
7833 default:
7834 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7835 break;
7836 }
7837
7838 switch(ePktDmxId)
7839 {
7840 case E_TSP_SRC_PKTDMX0:
7841 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL_SHIFT));
7842 break;
7843 case E_TSP_SRC_PKTDMX1:
7844 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL1_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL1_SHIFT));
7845 break;
7846 case E_TSP_SRC_PKTDMX2:
7847 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL2_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL2_SHIFT));
7848 break;
7849 case E_TSP_SRC_PKTDMX3:
7850 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL3_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL3_SHIFT));
7851 break;
7852 case E_TSP_SRC_MMFI0:
7853 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT));
7854 break;
7855 case E_TSP_SRC_MMFI1:
7856 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT));
7857 break;
7858 default:
7859 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
7860 break;
7861 }
7862 }
7863
HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)7864 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)
7865 {
7866 if(bEn == TRUE)
7867 {
7868 switch (eAvType)
7869 {
7870 case E_TSP_DST_FIFO_VIDEO :
7871 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
7872 break;
7873 case E_TSP_DST_FIFO_VIDEO3D :
7874 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
7875 break;
7876 case E_TSP_DST_FIFO_AUDIO :
7877 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
7878 break;
7879 case E_TSP_DST_FIFO_AUDIO2 :
7880 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
7881 break;
7882 case E_TSP_DST_FIFO_AUDIO3 :
7883 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD);
7884 break;
7885 case E_TSP_DST_FIFO_AUDIO4 :
7886 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD);
7887 break;
7888 default :
7889 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7890 break;
7891 }
7892 }
7893 else
7894 {
7895 switch (eAvType)
7896 {
7897 case E_TSP_DST_FIFO_VIDEO :
7898 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
7899 break;
7900 case E_TSP_DST_FIFO_VIDEO3D :
7901 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
7902 break;
7903 case E_TSP_DST_FIFO_AUDIO :
7904 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
7905 break;
7906 case E_TSP_DST_FIFO_AUDIO2 :
7907 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
7908 break;
7909 case E_TSP_DST_FIFO_AUDIO3 :
7910 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD);
7911 break;
7912 case E_TSP_DST_FIFO_AUDIO4 :
7913 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD);
7914 break;
7915 default :
7916 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7917 break;
7918 }
7919 }
7920 }
7921
HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)7922 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)
7923 {
7924 if(bPayload)
7925 {
7926 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
7927 }
7928 else
7929 {
7930 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
7931 }
7932
7933 if(bEn == TRUE)
7934 {
7935 switch (eAvType)
7936 {
7937 case E_TSP_DST_FIFO_VIDEO :
7938 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
7939 break;
7940 case E_TSP_DST_FIFO_VIDEO3D :
7941 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD);
7942 break;
7943 case E_TSP_DST_FIFO_AUDIO :
7944 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
7945 break;
7946 case E_TSP_DST_FIFO_AUDIO2 :
7947 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
7948 break;
7949 case E_TSP_DST_FIFO_AUDIO3 :
7950 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD);
7951 break;
7952 case E_TSP_DST_FIFO_AUDIO4 :
7953 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD);
7954 break;
7955 default :
7956 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7957 break;
7958 }
7959 }
7960 else
7961 {
7962 switch (eAvType)
7963 {
7964 case E_TSP_DST_FIFO_VIDEO :
7965 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
7966 break;
7967 case E_TSP_DST_FIFO_VIDEO3D :
7968 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD);
7969 break;
7970 case E_TSP_DST_FIFO_AUDIO :
7971 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
7972 break;
7973 case E_TSP_DST_FIFO_AUDIO2 :
7974 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
7975 break;
7976 case E_TSP_DST_FIFO_AUDIO3 :
7977 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD);
7978 break;
7979 case E_TSP_DST_FIFO_AUDIO4 :
7980 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD);
7981 break;
7982 default :
7983 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7984 break;
7985 }
7986 }
7987 }
7988
HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId,MS_BOOL bDrop)7989 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop)
7990 {
7991 if(bDrop)
7992 {
7993 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
7994 }
7995 else
7996 {
7997 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
7998 }
7999
8000 switch (ePktDmxId)
8001 {
8002 case E_TSP_SRC_PKTDMX0:
8003 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_0);
8004 case E_TSP_SRC_PKTDMX1:
8005 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_1);
8006 case E_TSP_SRC_PKTDMX2:
8007 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_2);
8008 case E_TSP_SRC_PKTDMX3:
8009 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_3);
8010 case E_TSP_SRC_MMFI0:
8011 return REG16_R(&_RegCtrl5->CFG5_0B);
8012 case E_TSP_SRC_MMFI1:
8013 return REG16_R(&_RegCtrl5->CFG5_0C);
8014 default :
8015 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
8016 return 0;
8017 }
8018 }
8019
HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)8020 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)
8021 {
8022 switch (eAvType)
8023 {
8024 case E_TSP_DST_FIFO_VIDEO :
8025 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
8026 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
8027 break;
8028 case E_TSP_DST_FIFO_VIDEO3D :
8029 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
8030 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
8031 break;
8032 case E_TSP_DST_FIFO_AUDIO :
8033 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
8034 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
8035 break;
8036 case E_TSP_DST_FIFO_AUDIO2 :
8037 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
8038 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
8039 break;
8040 case E_TSP_DST_FIFO_AUDIO3 :
8041 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR);
8042 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR);
8043 break;
8044 case E_TSP_DST_FIFO_AUDIO4 :
8045 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR);
8046 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR);
8047 break;
8048 default :
8049 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8050 break;
8051 }
8052 }
8053
HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)8054 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)
8055 {
8056 switch (eAvType)
8057 {
8058 case E_TSP_DST_FIFO_VIDEO :
8059 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
8060 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
8061 break;
8062 case E_TSP_DST_FIFO_VIDEO3D :
8063 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
8064 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
8065 break;
8066 case E_TSP_DST_FIFO_AUDIO :
8067 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
8068 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
8069 break;
8070 case E_TSP_DST_FIFO_AUDIO2 :
8071 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
8072 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
8073 break;
8074 case E_TSP_DST_FIFO_AUDIO3 :
8075 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
8076 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
8077 break;
8078 case E_TSP_DST_FIFO_AUDIO4 :
8079 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
8080 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
8081 break;
8082 default :
8083 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
8084 break;
8085 }
8086 }
8087
HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)8088 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)
8089 {
8090 MS_U16 u16TSIF = 0;;
8091
8092 switch(u32TsIf)
8093 {
8094 case 0:
8095 u16TSIF = TSIF_SRC_SEL_TSIF0;
8096 break;
8097 case 1:
8098 u16TSIF = TSIF_SRC_SEL_TSIF1;
8099 break;
8100 case 2:
8101 u16TSIF = TSIF_SRC_SEL_TSIF2;
8102 break;
8103 case 3:
8104 u16TSIF = TSIF_SRC_SEL_TSIF3;
8105 break;
8106 default:
8107 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8108 break;
8109 }
8110
8111 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_ERR_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_ERR_PKT_SRC_SEL_SHIFT));
8112 }
8113
HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)8114 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
8115 {
8116 if(bEn == TRUE)
8117 {
8118 switch(u32TsIf)
8119 {
8120 case 0:
8121 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
8122 break;
8123 case 1:
8124 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
8125 break;
8126 case 2:
8127 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
8128 break;
8129 case 3:
8130 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD);
8131 break;
8132 default:
8133 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8134 break;
8135 }
8136 }
8137 else
8138 {
8139 switch(u32TsIf)
8140 {
8141 case 0:
8142 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
8143 break;
8144 case 1:
8145 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
8146 break;
8147 case 2:
8148 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
8149 break;
8150 case 3:
8151 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD);
8152 break;
8153 default:
8154 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8155 break;
8156 }
8157 }
8158
8159 }
8160
HAL_TSP_Debug_ErrPktCnt_Get(void)8161 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void)
8162 {
8163 return REG16_R(&_RegCtrl5->Err_PKT_Cnt);
8164 }
8165
HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)8166 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)
8167 {
8168 switch (u32Tsif)
8169 {
8170 case 0 :
8171 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
8172 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
8173 break;
8174 case 1:
8175 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
8176 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
8177 break;
8178 case 2 :
8179 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
8180 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
8181 break;
8182 case 3 :
8183 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR);
8184 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR);
8185 break;
8186
8187 default :
8188 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
8189 break;
8190 }
8191 }
8192
HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)8193 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)
8194 {
8195 MS_U16 u16TSIF = 0;;
8196
8197 switch(u32TsIf)
8198 {
8199 case 0:
8200 u16TSIF = TSIF_SRC_SEL_TSIF0;
8201 break;
8202 case 1:
8203 u16TSIF = TSIF_SRC_SEL_TSIF1;
8204 break;
8205 case 2:
8206 u16TSIF = TSIF_SRC_SEL_TSIF2;
8207 break;
8208 case 3:
8209 u16TSIF = TSIF_SRC_SEL_TSIF3;
8210 break;
8211 default:
8212 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8213 break;
8214 }
8215
8216 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_INPUT_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_INPUT_PKT_SRC_SEL_SHIT));
8217 }
8218
HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)8219 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
8220 {
8221 if(bEn == TRUE)
8222 {
8223 switch(u32TsIf)
8224 {
8225 case 0:
8226 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
8227 break;
8228 case 1:
8229 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
8230 break;
8231 case 2:
8232 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
8233 break;
8234 case 3:
8235 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD);
8236 break;
8237 default:
8238 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8239 break;
8240 }
8241 }
8242 else
8243 {
8244 switch(u32TsIf)
8245 {
8246 case 0:
8247 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
8248 break;
8249 case 1:
8250 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
8251 break;
8252 case 2:
8253 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
8254 break;
8255 case 3:
8256 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD);
8257 break;
8258 default:
8259 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8260 break;
8261 }
8262 }
8263 }
8264
HAL_TSP_Debug_InputPktCnt_Get(void)8265 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void)
8266 {
8267 return REG16_R(&_RegCtrl5->Input_PKT_Cnt);
8268 }
8269
HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)8270 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)
8271 {
8272 switch (u32Tsif)
8273 {
8274 case 0 :
8275 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
8276 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
8277 break;
8278 case 1:
8279 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
8280 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
8281 break;
8282 case 2 :
8283 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
8284 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
8285 break;
8286 case 3 :
8287 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR);
8288 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR);
8289 break;
8290
8291 default :
8292 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
8293 break;
8294 }
8295
8296 }
8297
HAL_TSP_Privilege_Enable(MS_BOOL bEnable)8298 void HAL_TSP_Privilege_Enable(MS_BOOL bEnable)
8299 {
8300 if (bEnable)
8301 {
8302 REG16_SET(&_RegCtrl3->CFG3_7C, CFG3_7C_PRIVILEGE_FLAG);
8303 }
8304 else
8305 {
8306 REG16_CLR(&_RegCtrl3->CFG3_7C, CFG3_7C_PRIVILEGE_FLAG);
8307 }
8308 }
8309
HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng,MS_U32 u32FQSrc)8310 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc)
8311 {
8312 // not support
8313 return TRUE;
8314 }
8315
HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)8316 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)
8317 {
8318 // not support
8319 return 0;
8320 }
8321
HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng,MS_BOOL bFltNull)8322 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull)
8323 {
8324 if(bFltNull)
8325 {
8326 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT);
8327 }
8328 else
8329 {
8330 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT);
8331 }
8332
8333 return TRUE;
8334 }
8335
HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath,MS_U32 u32Eng,MS_BOOL bEn)8336 void HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath, MS_U32 u32Eng, MS_BOOL bEn)
8337 {
8338 if(bEn)
8339 {
8340 switch(ePath)
8341 {
8342 case E_TSP_HAL_GATING_PATH0:
8343 case E_TSP_HAL_GATING_PATH1:
8344 case E_TSP_HAL_GATING_PATH2:
8345 case E_TSP_HAL_GATING_PATH3:
8346 case E_TSP_HAL_GATING_PATH4:
8347 case E_TSP_HAL_GATING_PATH5:
8348 if(u32Eng > TSP_TSIF_NUM)
8349 {
8350 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8351 return;
8352 }
8353 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PATH0 << u32Eng);
8354 break;
8355
8356 case E_TSP_HAL_GATING_TSP_ENG:
8357 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_TSP_ENG);
8358 break;
8359 case E_TSP_HAL_GATING_FIQ:
8360 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_FIQ);
8361 break;
8362
8363 case E_TSP_HAL_GATING_PVR1:
8364 case E_TSP_HAL_GATING_PVR2:
8365 case E_TSP_HAL_GATING_PVR3:
8366 case E_TSP_HAL_GATING_PVR4:
8367 if(u32Eng > TSP_PVRENG_NUM)
8368 {
8369 printf("[%s][%s][%d] UnSupported PVR eng : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8370 return;
8371 }
8372 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PVR1 << u32Eng);
8373 break;
8374
8375 case E_TSP_HAL_MIU_CLK_GATING_PATH0:
8376 case E_TSP_HAL_MIU_CLK_GATING_PATH1:
8377 case E_TSP_HAL_MIU_CLK_GATING_PATH2:
8378 case E_TSP_HAL_MIU_CLK_GATING_PATH3:
8379 case E_TSP_HAL_MIU_CLK_GATING_PATH4:
8380 case E_TSP_HAL_MIU_CLK_GATING_PATH5:
8381 if(u32Eng > TSP_TSIF_NUM)
8382 {
8383 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8384 return;
8385 }
8386 REG16_SET(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_PATH0 << u32Eng);
8387 break;
8388
8389 case E_TSP_HAL_MIU_CLK_GATING_TSP_ENG:
8390 REG16_SET(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_TSP_ENG);
8391 break;
8392
8393 case E_TSP_HAL_GATING_FIQ0:
8394 case E_TSP_HAL_GATING_FIQ1:
8395 case E_TSP_HAL_GATING_FIQ2:
8396 case E_TSP_HAL_GATING_FIQ3:
8397 case E_TSP_HAL_GATING_FIQ4:
8398 case E_TSP_HAL_GATING_FIQ5:
8399 if(u32Eng > TSP_FQ_NUM)
8400 {
8401 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8402 return;
8403 }
8404 REG16_SET(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_CLK_GATING_FIQ0 << u32Eng);
8405 break;
8406
8407 case E_TSP_HAL_MIU_CLK_GATING_FIQ0:
8408 case E_TSP_HAL_MIU_CLK_GATING_FIQ1:
8409 case E_TSP_HAL_MIU_CLK_GATING_FIQ2:
8410 case E_TSP_HAL_MIU_CLK_GATING_FIQ3:
8411 case E_TSP_HAL_MIU_CLK_GATING_FIQ4:
8412 case E_TSP_HAL_MIU_CLK_GATING_FIQ5:
8413 if(u32Eng > TSP_FQ_NUM)
8414 {
8415 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8416 return;
8417 }
8418 REG16_SET(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_MIU_CLK_GATING_FIQ0 << u32Eng);
8419 break;
8420 default :
8421 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
8422 break;
8423 }
8424 }
8425 else
8426 {
8427 switch(ePath)
8428 {
8429 case E_TSP_HAL_GATING_PATH0:
8430 case E_TSP_HAL_GATING_PATH1:
8431 case E_TSP_HAL_GATING_PATH2:
8432 case E_TSP_HAL_GATING_PATH3:
8433 case E_TSP_HAL_GATING_PATH4:
8434 case E_TSP_HAL_GATING_PATH5:
8435 if(u32Eng > TSP_TSIF_NUM)
8436 {
8437 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8438 return;
8439 }
8440 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PATH0 << u32Eng);
8441 break;
8442
8443 case E_TSP_HAL_GATING_TSP_ENG:
8444 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_TSP_ENG);
8445 break;
8446 case E_TSP_HAL_GATING_FIQ:
8447 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_FIQ);
8448 break;
8449
8450 case E_TSP_HAL_GATING_PVR1:
8451 case E_TSP_HAL_GATING_PVR2:
8452 case E_TSP_HAL_GATING_PVR3:
8453 case E_TSP_HAL_GATING_PVR4:
8454 if(u32Eng > TSP_PVRENG_NUM)
8455 {
8456 printf("[%s][%s][%d] UnSupported PVR eng : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8457 return;
8458 }
8459 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PVR1 << u32Eng);
8460 break;
8461
8462 case E_TSP_HAL_MIU_CLK_GATING_PATH0:
8463 case E_TSP_HAL_MIU_CLK_GATING_PATH1:
8464 case E_TSP_HAL_MIU_CLK_GATING_PATH2:
8465 case E_TSP_HAL_MIU_CLK_GATING_PATH3:
8466 case E_TSP_HAL_MIU_CLK_GATING_PATH4:
8467 case E_TSP_HAL_MIU_CLK_GATING_PATH5:
8468 if(u32Eng > TSP_TSIF_NUM)
8469 {
8470 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8471 return;
8472 }
8473
8474 REG16_CLR(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_PATH0 << u32Eng);
8475 break;
8476
8477 case E_TSP_HAL_MIU_CLK_GATING_TSP_ENG:
8478 REG16_CLR(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_TSP_ENG);
8479 break;
8480
8481 case E_TSP_HAL_GATING_FIQ0:
8482 case E_TSP_HAL_GATING_FIQ1:
8483 case E_TSP_HAL_GATING_FIQ2:
8484 case E_TSP_HAL_GATING_FIQ3:
8485 case E_TSP_HAL_GATING_FIQ4:
8486 case E_TSP_HAL_GATING_FIQ5:
8487 if(u32Eng > TSP_FQ_NUM)
8488 {
8489 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8490 return;
8491 }
8492 REG16_CLR(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_CLK_GATING_FIQ0 << u32Eng);
8493 break;
8494
8495 case E_TSP_HAL_MIU_CLK_GATING_FIQ0:
8496 case E_TSP_HAL_MIU_CLK_GATING_FIQ1:
8497 case E_TSP_HAL_MIU_CLK_GATING_FIQ2:
8498 case E_TSP_HAL_MIU_CLK_GATING_FIQ3:
8499 case E_TSP_HAL_MIU_CLK_GATING_FIQ4:
8500 case E_TSP_HAL_MIU_CLK_GATING_FIQ5:
8501 if(u32Eng > TSP_FQ_NUM)
8502 {
8503 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
8504 return;
8505 }
8506 REG16_CLR(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_MIU_CLK_GATING_FIQ1 << u32Eng);
8507 break;
8508
8509 default :
8510 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
8511 break;
8512 }
8513 }
8514
8515 }
8516
HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath,MS_U32 u32Idx,MS_BOOL bEn)8517 void HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath, MS_U32 u32Idx, MS_BOOL bEn)
8518 {
8519
8520 if(bEn)
8521 {
8522 switch(ePath)
8523 {
8524 case E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0:
8525 if(u32Idx > TSP_TSIF_NUM)
8526 return;
8527 REG16_SET(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_PKT_CONVERTER0 << u32Idx);
8528 break;
8529 case E_TSP_HAL_RESET_CTRL_FIQ0:
8530 if(u32Idx > TSP_TSIF_NUM)
8531 return;
8532 REG16_SET(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_FIQ0 << u32Idx);
8533 break;
8534 case E_TSP_HAL_RESET_CTRL_VQ_TX0:
8535 if(u32Idx > TSP_TSIF_NUM)
8536 return;
8537 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TX0 << u32Idx);
8538 break;
8539 case E_TSP_HAL_RESET_CTRL_VQ_RX:
8540 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_RX);
8541 break;
8542 case E_TSP_HAL_RESET_CTRL_VQ_TOP:
8543 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TOP);
8544 break;
8545 case E_TSP_HAL_RESET_CTRL_PKT_DEMUX0:
8546 if(u32Idx > TSP_TSIF_NUM)
8547 return;
8548 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_PKT_DEMUX0 << u32Idx);
8549 break;
8550 case E_TSP_HAL_RESET_CTRL_PVR1:
8551 if(u32Idx > TSP_TSIF_NUM)
8552 return;
8553 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_PVR1 << u32Idx);
8554 break;
8555 case E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1:
8556 if(u32Idx > TSP_TSIF_NUM)
8557 return;
8558 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR1 << u32Idx);
8559 break;
8560 case E_TSP_HAL_RESET_CTRL_SP_D0:
8561 if(u32Idx > TSP_TSIF_NUM)
8562 return;
8563 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_SP_D0 << u32Idx);
8564 break;
8565 case E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0:
8566 if(u32Idx > TSP_TSIF_NUM)
8567 return;
8568 REG16_SET(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_FILTER_NULL_PKT0 << u32Idx);
8569 break;
8570 case E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0:
8571 if(u32Idx > TSP_TSIF_NUM)
8572 return;
8573 REG16_SET(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_DIRECTV_130_188_0 << u32Idx);
8574 break;
8575 case E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0:
8576 if(u32Idx > TSP_TSIF_NUM)
8577 return;
8578 REG16_SET(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_SRC_ID_PARSER0 << u32Idx);
8579 break;
8580 case E_TSP_HAL_RESET_CTRL_PCRFLT_0:
8581 if(u32Idx > TSP_TSIF_NUM)
8582 return;
8583 REG16_SET(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_PCRFLT_0 << u32Idx);
8584 break;
8585 case E_TSP_HAL_RESET_PATH0:
8586 if(u32Idx > TSP_TSIF_NUM)
8587 return;
8588 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PATH0 << u32Idx);
8589 break;
8590 case E_TSP_HAL_RESET_OTV:
8591 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_OTV);
8592 break;
8593 case E_TSP_HAL_RESET_DEBUG_TABLE:
8594 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DEBUG_TABLE);
8595 break;
8596 case E_TSP_HAL_RESET_DMA_ENG:
8597 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DMA_ENG);
8598 break;
8599 case E_TSP_HAL_RESET_SEC_CMP:
8600 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC_CMP);
8601 break;
8602 case E_TSP_HAL_RESET_SECFLT_REG:
8603 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SECFLT_REG);
8604 break;
8605 case E_TSP_HAL_RESET_SEC:
8606 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC);
8607 break;
8608 case E_TSP_HAL_RESET_PID_TABLE:
8609 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PID_TABLE);
8610 break;
8611
8612 default :
8613 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
8614 break;
8615 }
8616 }
8617 else
8618 {
8619 switch(ePath)
8620 {
8621 case E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0:
8622 if(u32Idx > TSP_TSIF_NUM)
8623 return;
8624 REG16_CLR(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_PKT_CONVERTER0 << u32Idx);
8625 break;
8626 case E_TSP_HAL_RESET_CTRL_FIQ0:
8627 if(u32Idx > TSP_TSIF_NUM)
8628 return;
8629 REG16_CLR(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_FIQ0 << u32Idx);
8630 break;
8631 case E_TSP_HAL_RESET_CTRL_VQ_TX0:
8632 if(u32Idx > TSP_TSIF_NUM)
8633 return;
8634 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TX0 << u32Idx);
8635 break;
8636 case E_TSP_HAL_RESET_CTRL_VQ_RX:
8637 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_RX);
8638 break;
8639 case E_TSP_HAL_RESET_CTRL_VQ_TOP:
8640 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TOP);
8641 break;
8642 case E_TSP_HAL_RESET_CTRL_PKT_DEMUX0:
8643 if(u32Idx > TSP_TSIF_NUM)
8644 return;
8645 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_PKT_DEMUX0 << u32Idx);
8646 break;
8647 case E_TSP_HAL_RESET_CTRL_PVR1:
8648 if(u32Idx > TSP_TSIF_NUM)
8649 return;
8650 REG16_CLR(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_PVR1 << u32Idx);
8651 break;
8652 case E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1:
8653 if(u32Idx > TSP_TSIF_NUM)
8654 return;
8655 REG16_CLR(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR1 << u32Idx);
8656 break;
8657 case E_TSP_HAL_RESET_CTRL_SP_D0:
8658 if(u32Idx > TSP_TSIF_NUM)
8659 return;
8660 REG16_CLR(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_SP_D0 << u32Idx);
8661 break;
8662 case E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0:
8663 if(u32Idx > TSP_TSIF_NUM)
8664 return;
8665 REG16_CLR(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_FILTER_NULL_PKT0 << u32Idx);
8666 break;
8667 case E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0:
8668 if(u32Idx > TSP_TSIF_NUM)
8669 return;
8670 REG16_CLR(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_DIRECTV_130_188_0 << u32Idx);
8671 break;
8672 case E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0:
8673 if(u32Idx > TSP_TSIF_NUM)
8674 return;
8675 REG16_CLR(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_SRC_ID_PARSER0 << u32Idx);
8676 break;
8677 case E_TSP_HAL_RESET_CTRL_PCRFLT_0:
8678 if(u32Idx > TSP_TSIF_NUM)
8679 return;
8680 REG16_CLR(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_PCRFLT_0 << u32Idx);
8681 break;
8682 case E_TSP_HAL_RESET_PATH0:
8683 if(u32Idx > TSP_TSIF_NUM)
8684 return;
8685 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PATH0 << u32Idx);
8686 break;
8687 case E_TSP_HAL_RESET_OTV:
8688 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_OTV);
8689 break;
8690 case E_TSP_HAL_RESET_DEBUG_TABLE:
8691 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DEBUG_TABLE);
8692 break;
8693 case E_TSP_HAL_RESET_DMA_ENG:
8694 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DMA_ENG);
8695 break;
8696 case E_TSP_HAL_RESET_SEC_CMP:
8697 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC_CMP);
8698 break;
8699 case E_TSP_HAL_RESET_SECFLT_REG:
8700 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SECFLT_REG);
8701 break;
8702 case E_TSP_HAL_RESET_SEC:
8703 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC);
8704 break;
8705 case E_TSP_HAL_RESET_PID_TABLE:
8706 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PID_TABLE);
8707 break;
8708
8709 default :
8710 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
8711 break;
8712 }
8713 }
8714
8715 }
8716
HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType,MS_U8 u8Eng,MS_PHY phyBufStart)8717 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart)
8718 {
8719 MS_U8 u8MiuSel = 0;
8720 MS_PHY phyMiuOffsetFileinAddr = 0;
8721 MS_U8 u8Shift = u8Eng * TSP_MIU_SEL_BITS_LEN;
8722
8723 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, phyBufStart);
8724
8725 switch(eType)
8726 {
8727 case E_TSP_HAL_MIU_SEL_MMFI:
8728 REG16_MSK_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG_MIU_SEL_MMFI0_MASK << u8Shift), (u8MiuSel << (REG_MIU_SEL_MMFI0_SHIFT + u8Shift)));
8729 break;
8730 case E_TSP_HAL_MIU_SEL_FQ:
8731 REG16_MSK_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG_MIU_SEL_FIQ0_MASK << u8Shift), (u8MiuSel << (REG_MIU_SEL_FIQ0_SHIFT + u8Shift)));
8732 break;
8733 default:
8734 break;
8735 }
8736 }
8737
8738