1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 4 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 // PVR buffer define 36 #define PVR_NON_OVERWRITE (MS_U64)0xDEADBEEFDEADBEEFLL 37 // If the PVR buffer in non-OverWrite state, the first 8 bytes of the PVR buffer must be the PVR_NON_OVERWRITE value 38 39 //VQ define 40 #define VQ_NUM 4 41 #define VQ_PACKET_UNIT_LEN 208 42 43 #define TSP_TSIF0 0x00 44 #define TSP_TSIF1 0x01 45 #define TSP_TSIF2 0x02 46 #define TSP_TSIF3 0x03 47 #define TSP_TSIF4 0x04 // not support 48 #define TSP_TSIF5 0x05 // not support 49 #define TSP_TSIF6 0x06 // not support 50 51 //FQ define 52 #define TSP_FQ_NUM 4 53 54 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 55 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 56 57 //######################################################################### 58 //#### Software Capability Macro Start 59 //######################################################################### 60 61 #define TSP_CA_RESERVED_FLT_NUM 1 62 #define TSP_RECFLT_NUM 1 63 #define TSP_PIDFLT_REC_NUM TSP_PIDFLT_NUM // 0~191 (0 for CA) 64 // 197 for Err 65 // 196 for REC 66 // 195 for PCR3 67 // 194 for PCR2 68 // 193 for PCR1 69 // 192 for PCR0 70 71 #if HW_PCRFLT_ENABLE 72 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 73 #else 74 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 75 #endif 76 77 //######################################################################### 78 //#### Software Capability Macro End 79 //######################################################################### 80 81 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 82 #define TSP_CAFLT_START_ID 0 83 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) // 1 84 85 // section FLT ID 86 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID // 1 87 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID // 1 88 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 89 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 90 91 // PID 92 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID // 1 93 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 94 95 // PCR 96 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID // 192 97 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 98 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) // 196 99 100 // REC 101 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID // 196 102 103 //-------------------------------------------------------------------------------------------------- 104 // Driver Compiler Option 105 //-------------------------------------------------------------------------------------------------- 106 107 108 //-------------------------------------------------------------------------------------------------- 109 // PVR Hardware Abstraction Layer 110 //-------------------------------------------------------------------------------------------------- 111 112 // HW characteristic 113 114 typedef enum _PVRENG_SEQ 115 { 116 E_TSP_PVR_PVRENG_START = 0, 117 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 118 E_TSP_PVR_PVRENG_1, 119 E_TSP_PVR_PVRENG_2, 120 E_TSP_PVR_PVRENG_3, 121 E_TSP_PVR_PVRENG_END, 122 E_TSP_PVR_ENG_INVALID, 123 } PVRENG_SEQ; 124 125 typedef enum _FILEENG_SEQ 126 { 127 E_FILEENG_TSIF0 = TSP_TSIF0, 128 E_FILEENG_TSIF1 = TSP_TSIF1, 129 E_FILEENG_TSIF2 = TSP_TSIF2, 130 E_FILEENG_TSIF3 = TSP_TSIF3, 131 E_FILEENG_INVALID, 132 133 } FILEENG_SEQ; 134 135 #if 1 // Destination type 136 typedef enum _TSP_DST_SEQ 137 { 138 E_TSP_DST_FIFO_VIDEO, 139 E_TSP_DST_FIFO_VIDEO3D, 140 E_TSP_DST_FIFO_VIDEO3, 141 E_TSP_DST_FIFO_VIDEO4, 142 E_TSP_DST_FIFO_VIDEO5, //Not support 143 E_TSP_DST_FIFO_VIDEO6, //Not support 144 E_TSP_DST_FIFO_VIDEO7, //Not support 145 E_TSP_DST_FIFO_VIDEO8, //Not support 146 147 E_TSP_DST_FIFO_AUDIO, 148 E_TSP_DST_FIFO_AUDIO2, 149 E_TSP_DST_FIFO_AUDIO3, 150 E_TSP_DST_FIFO_AUDIO4, 151 E_TSP_DST_FIFO_AUDIO5, //Not support 152 E_TSP_DST_FIFO_AUDIO6, //Not support 153 154 E_TSP_DST_INVALID, 155 } TSP_DST_SEQ; 156 #else 157 #define TSP_FltType MS_U32 158 /// TS stream fifo type (Exclusive usage) 159 #define E_TSP_FLT_FIFO_MASK 0x000000FF 160 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 161 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 162 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 163 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 164 #endif 165 166 typedef enum _TSP_SRC_SEQ{ 167 E_TSP_SRC_PKTDMX0, 168 E_TSP_SRC_PKTDMX1, 169 E_TSP_SRC_PKTDMX2, 170 E_TSP_SRC_PKTDMX3, 171 E_TSP_SRC_PKTDMX4, //not used 172 E_TSP_SRC_PKTDMX5, //not used 173 E_TSP_SRC_MMFI0, 174 E_TSP_SRC_MMFI1, 175 176 E_TSP_SRC_INVALID, 177 } TSP_SRC_SEQ; 178 179 typedef enum _TSIF_CFG 180 { 181 // @NOTE should be Exclusive usage 182 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 183 E_TSP_TSIF_CFG_EN = 0x0001, 184 E_TSP_TSIF_CFG_PARA = 0x0002, 185 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 186 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 187 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 188 E_TSP_TSIF_CFG_3WIRE = 0x0010 189 } TSP_TSIF_CFG; 190 191 // for stream input source 192 typedef enum _HAL_TS_PAD 193 { 194 E_TSP_TS_PAD_EXT0, 195 E_TSP_TS_PAD_EXT1, 196 E_TSP_TS_PAD_EXT2, 197 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 198 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 199 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 200 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 201 E_TSP_TS_PAD_EXT7, // not support, 202 E_TSP_TS_PAD_INTER0, // not support, 203 E_TSP_TS_PAD_INTER1, // not support, 204 E_TSP_TS_PAD_TSOUT0, 205 E_TSP_TS_PAD_TSOUT1, //not support, 206 E_TSP_TS_PAD_TSIOOUT0, 207 E_TSP_TS_PAD_INVALID, 208 } TSP_TS_PAD; 209 210 // for ts pad mode 211 typedef enum _HAL_TS_PAD_MUX_MODE 212 { 213 E_TSP_TS_PAD_MUX_PARALLEL, // in 214 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 215 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 216 E_TSP_TS_PAD_MUX_TSO, // out 217 E_TSP_TS_PAD_MUX_S2P, // out 218 E_TSP_TS_PAD_MUX_S2P1, // out 219 E_TSP_TS_PAD_MUX_DEMOD, // out 220 221 E_TSP_TS_PAD_MUX_INVALID 222 } TSP_TS_PAD_MUX_MODE; 223 224 225 // for pkt converter mode 226 typedef enum _HAL_TS_PKT_CONVERTER_MODE 227 { 228 E_TSP_PKT_CONVERTER_188Mode = 0, 229 E_TSP_PKT_CONVERTER_CIMode = 1, 230 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 231 E_TSP_PKT_CONVERTER_ATSMode = 3, 232 E_TSP_PKT_CONVERTER_MxLMode = 4, 233 E_TSP_PKT_CONVERTER_NagraDongleMode = 5, 234 E_TSP_PKT_CONVERTER_Invalid, 235 } TSP_TS_PKT_CONVERTER_MODE; 236 237 typedef enum _HAL_TS_MXL_PKT_MODE 238 { 239 E_TSP_TS_MXL_PKT_192 = 4, 240 E_TSP_TS_MXL_PKT_196 = 8, 241 E_TSP_TS_MXL_PKT_200 = 12, 242 E_TSP_TS_MXL_PKT_INVALID, 243 } TSP_TS_MXL_PKT_MODE; 244 245 typedef enum _HAL_TSP_CLK_TYPE 246 { 247 E_TSP_HAL_TSP_CLK, 248 E_TSP_HAL_STC_CLK, 249 E_TSP_HAL_INVALID 250 } EN_TSP_HAL_CLK_TYPE; 251 252 typedef struct _HAL_TSP_CLK_STATUS 253 { 254 MS_BOOL bEnable; 255 MS_BOOL bInvert; 256 MS_U8 u8ClkSrc; 257 } ST_TSP_HAL_CLK_STATUS; 258 259 typedef enum _PCR_SRC 260 { 261 /* register setting for kaiser pcr 262 0: tsif0 263 1: tsif1 264 2: tsif2 265 3: tsif3 266 4: tsif4 267 5: tsif5 268 6: un-used 269 7: un-used 270 8: pkt merge 0 271 9: pkt merge 1 272 a: MM file in 1 273 b: MM file in 2 274 */ 275 E_TSP_PCR_SRC_TSIF0 = 0, 276 E_TSP_PCR_SRC_TSIF1, 277 E_TSP_PCR_SRC_TSIF2, 278 E_TSP_PCR_SRC_TSIF3, 279 E_TSP_PCR_SRC_TSIF4, 280 E_TSP_PCR_SRC_TSIF5, 281 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 282 E_TSP_PCR_SRC_PKT_MERGE1, 283 E_TSP_PCR_SRC_MMFI0, 284 E_TSP_PCR_SRC_MMFI1, 285 E_TSP_PCR_SRC_INVALID, 286 } TSP_PCR_SRC; 287 288 typedef enum _HAL_TSP_TSIF // for HW TSIF 289 { 290 E_TSP_HAL_TSIF_0 , 291 E_TSP_HAL_TSIF_1 , 292 E_TSP_HAL_TSIF_2 , 293 E_TSP_HAL_TSIF_3 , 294 E_TSP_HAL_TSIF_4 , // not support 295 E_TSP_HAL_TSIF_5 , // not support 296 E_TSP_HAL_TSIF_6 , // not support 297 298 E_TSP_HAL_TSIF_PVR0 , 299 E_TSP_HAL_TSIF_PVR1 , 300 E_TSP_HAL_TSIF_PVR2 , 301 E_TSP_HAL_TSIF_PVR3 , 302 E_TSP_HAL_TSIF_INVALID , 303 } TSP_HAL_TSIF; 304 305 306 typedef enum _TSP_HAL_FileState 307 { 308 /// Command Queue is Idle 309 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 310 /// Command Queue is Busy 311 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 312 /// Command Queue is Paused. 313 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 314 315 E_TSP_HAL_FILE_STATE_INVALID, 316 }TSP_HAL_FileState; 317 318 typedef enum 319 { 320 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 321 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 322 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 323 324 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 325 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 326 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 327 328 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 329 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 330 331 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 332 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 333 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 334 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 335 336 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 337 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 338 339 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 340 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 341 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 342 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 343 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 344 345 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 346 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 347 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 348 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 349 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 350 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 351 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 352 353 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 354 355 //27 is reserved, and can not be used 356 357 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 358 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 359 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 360 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 361 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 362 363 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 364 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 365 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 366 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 367 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 368 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 369 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 370 E_TSP_HAL_CAP_FIQ_NUM = 40, 371 E_TSP_HAL_CAP_TYPE_NULL, 372 } TSP_HAL_CAP_TYPE; 373 374 // @F_TODO remove unused enum member 375 typedef enum 376 { 377 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PCRFLT_END_ID - TSP_PIDFLT_START_ID), 378 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 379 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 380 381 E_TSP_HAL_CAP_VAL_RECENG_NUM = 4, 382 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 383 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 384 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 385 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 386 387 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 388 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 389 390 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 391 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 4, //internal demod // [ToDo] STC number... by MM problem Jason-YH.Sun 392 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 393 E_TSP_HAL_CAP_VAL_VQ_NUM = 4, 394 395 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 396 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 397 398 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 399 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 400 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 401 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 402 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 403 404 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 405 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 406 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 407 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 408 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 409 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 410 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 411 412 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 413 414 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 4, 415 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 4, 416 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 417 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 418 419 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 420 421 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 422 } TSP_HAL_CAP_VAL; 423 424 /// TSP TEI Remove Error Packet Infomation 425 typedef enum 426 { 427 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 428 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 429 430 }TSP_HAL_TEI_RmPktType; 431 432 /// TSP Packet Converter Input Mode 433 typedef enum 434 { 435 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 436 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 437 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 438 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 439 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 440 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 441 E_TSP_HAL_PKT_MODE_MXL_200, ///< MXL mode (200 bytes) 442 E_TSP_HAL_PKT_MODE_ND, ///< Nagra Dongle mode (192 bytes) 443 444 }TSP_HAL_PKT_MODE; 445 446 // TSP TimeStamp Clk Select 447 typedef enum 448 { 449 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 450 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 451 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 452 453 } TSP_HAL_TimeStamp_Clk; 454 455 //---------------------------------- 456 /// DMX debug table information structure 457 //---------------------------------- 458 459 typedef enum 460 { 461 E_TSP_HAL_FLOW_LIVE0, 462 E_TSP_HAL_FLOW_LIVE1, 463 E_TSP_HAL_FLOW_LIVE2, 464 E_TSP_HAL_FLOW_LIVE3, 465 E_TSP_HAL_FLOW_LIVE4, 466 E_TSP_HAL_FLOW_LIVE5, 467 E_TSP_HAL_FLOW_LIVE6, 468 469 E_TSP_HAL_FLOW_FILE0, 470 E_TSP_HAL_FLOW_FILE1, 471 E_TSP_HAL_FLOW_FILE2, 472 E_TSP_HAL_FLOW_FILE3, 473 E_TSP_HAL_FLOW_FILE4, 474 E_TSP_HAL_FLOW_FILE5, 475 E_TSP_HAL_FLOW_FILE6, 476 477 E_TSP_HAL_FLOW_MMFI0, 478 E_TSP_HAL_FLOW_MMFI1, 479 480 E_TSP_HAL_FLOW_INVALID, 481 482 } TSP_HAL_FLOW; 483 484 typedef enum 485 { 486 E_TSP_HAL_MIU_SEL_MMFI = 0, 487 E_TSP_HAL_MIU_SEL_FQ = 1, 488 489 E_TSP_HAL_MIU_SEL_INVALID, 490 491 } TSP_HAL_MIU_SEL_TYPE; 492 493 //-------------------------------------------------------------------------------------------------- 494 // PVR HAL API 495 //-------------------------------------------------------------------------------------------------- 496 // Static Register Mapping for external access 497 #define REG_PIDFLT_BASE0 (0x00240000UL) 498 #define REG_PIDFLT_BASE1 (0x00241000UL) 499 #define REG_SECFLT_BASE (0x00221000UL) 500 #define REG_SECBUF_BASE (0x00221024UL) 501 #define REG_CTRL_BASE (0x00210200UL) 502 503 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 504 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 505 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 506 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 507 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 508 509 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 510 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 511 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 512 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 513 514 //#define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 515 516 //#define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 517 518 519 520 //******************** PIDFLT DEFINE START ********************// 521 // PID 522 #define TSP_PIDFLT_PID_MASK 0x00001FFF 523 #define TSP_PIDFLT_PID_SHFT 0 524 525 // Continuous counter 526 #define TSP_PIDFLT_CC_MASK 0xFF000000 527 #define TSP_PIDFLT_CC_SHFT 24 528 529 // PIDFLT SRC 530 typedef enum _TSP_PIDFLT_SRC 531 { 532 E_TSP_PIDFLT_LIVE0, 533 E_TSP_PIDFLT_LIVE1, 534 E_TSP_PIDFLT_LIVE2, 535 E_TSP_PIDFLT_LIVE3, 536 E_TSP_PIDFLT_LIVE4, // not support 537 E_TSP_PIDFLT_LIVE5, // not support 538 E_TSP_PIDFLT_LIVE6, // not support 539 E_TSP_PIDFLT_FILE0, 540 E_TSP_PIDFLT_FILE1, 541 E_TSP_PIDFLT_FILE2, 542 E_TSP_PIDFLT_FILE3, 543 E_TSP_PIDFLT_FILE4, // not support 544 E_TSP_PIDFLT_FILE5, // not support 545 E_TSP_PIDFLT_FILE6, // not support 546 E_TSP_PIDFLT_INVALID, 547 } TSP_PIDFLT_SRC; 548 549 #define TSP_PIDFLT_IN_MASK 0x0000E000 550 #define TSP_PIDFLT_TSIF_SHFT 13 551 #define TSP_PIDFLT_TSIF0 0x00 552 #define TSP_PIDFLT_TSIF1 0x01 553 #define TSP_PIDFLT_TSIF2 0x02 554 #define TSP_PIDFLT_TSIF3 0x03 555 #define TSP_PIDFLT_TSIF_MAX 0x04 556 557 // Section filter Id (0~63) 558 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 559 #define TSP_PIDFLT_SECFLT_SHFT 0 560 561 // PIDFLT DST 562 typedef enum _TSP_PIDFLT_DST 563 { 564 E_TSP_PIDFLT_DST_VIDEO, 565 E_TSP_PIDFLT_DST_AUDIO, 566 E_TSP_PIDFLT_DST_PVR, 567 568 E_TSP_PIDFLT_DST_INVALID, 569 } TSP_PIDFLT_DST; 570 571 // AF/Sec/Video/V3D/V3/V4/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 572 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 573 #define TSP_PIDFLT_OUT_MASK 0x009FFF00 574 #define TSP_PIDFLT_OUT_SHFT 8 575 #define TSP_PIDFLT_OUT_NONE 0x00000000 576 #define TSP_PIDFLT_OUT_SECAF 0x00000100 577 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 578 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 579 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 580 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 581 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 582 #define TSP_PIDFLT_OUT_VFIFO3 0x00004000 583 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 584 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 585 #define TSP_PIDFLT_OUT_VFIFO4 0x00800000 586 587 588 // SRC ID 589 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 590 #define TSP_PIDFLT_SRCID_SHIFT 28 591 592 //enable LUT 593 #define TSP_PIDFLT_OUT_LUT 0x00000000 // K6 not suppor 594 595 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 596 #define TSP_PIDFLT_PVRFLT_SHFT 15 597 #define TSP_PIDFLT_OUT_PVR1 0x00008000 598 #define TSP_PIDFLT_OUT_PVR2 0x00010000 599 #define TSP_PIDFLT_OUT_PVR3 0x00020000 600 #define TSP_PIDFLT_OUT_PVR4 0x00040000 601 602 603 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 604 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 605 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 606 607 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 608 #define TSP_PIDFLT_TSOFLT_SHFT 22 609 #define TSP_PID_FLT_OUT_TSO0 0x00400000 610 611 //******************** PIDFLT DEFINE END ********************// 612 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 613 MS_U32 TSP32_IdrR(TSP32 *preg); 614 615 //=========================TSIF================================ 616 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 617 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 618 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 619 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 620 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 621 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 622 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 623 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 624 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 625 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 626 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 627 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 628 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 629 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 630 631 //=========================TSP================================ 632 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 633 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 634 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 635 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 636 void HAL_TSP_Reset(MS_BOOL bEn); 637 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 638 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 639 void HAL_TSP_Power(MS_BOOL bEn); 640 void HAL_TSP_CPU(MS_BOOL bEn); 641 void HAL_TSP_ResetCPU(MS_BOOL bReset); 642 void HAL_TSP_HwPatch(void); 643 void HAL_TSP_RestoreFltState(void); 644 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 645 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 646 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 647 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 648 void HAL_TSP_SaveFltState(void); 649 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 650 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 651 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 652 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 653 654 //=========================TSO================================ 655 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 656 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 657 658 //=========================Filein================================ 659 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 660 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 661 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 662 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 663 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 664 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 665 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 666 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 667 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 668 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 669 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 670 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 671 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 672 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 673 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 674 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 675 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 676 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass);// for PS mode A/V fifo pull back 677 678 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 679 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 680 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 681 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 682 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 683 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 684 /* 685 // Only used by [HW test code] 686 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 687 */ 688 689 //=========================PCR FLT================================ 690 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 691 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 692 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 693 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 694 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 695 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 696 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 697 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 698 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId); 699 700 //=========================STC================================ 701 void HAL_TSP_STC_Init(void); 702 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 703 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 704 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 705 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 706 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 707 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 708 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 709 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 710 711 //=========================FIFO================================ 712 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 713 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 714 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 715 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 716 void HAL_TSP_FIFO_ClearAll (void); 717 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 718 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 719 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 720 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 721 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 722 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 723 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 724 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 725 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 726 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 727 void HAL_TSP_PS_SRC(MS_U32 tsIf); 728 void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 729 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 730 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 731 void HAL_TSP_FIFO_ReadEn(MS_BOOL bEn); // 732 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 733 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 734 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 735 736 //=========================VQ================================ 737 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 738 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 739 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 740 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 741 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 742 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 743 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 744 745 //=========================Pid Flt================================ 746 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 747 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 748 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 749 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 750 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 751 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 752 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 753 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 754 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 755 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 756 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 757 758 //=========================SecFlt================================ 759 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 760 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 761 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 762 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 763 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 764 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 765 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 766 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 767 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 768 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 769 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 770 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 771 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 772 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 773 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 774 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 775 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 776 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 777 778 //=========================Sec Buf================================ 779 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 780 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 781 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 782 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 783 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 784 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 785 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 786 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 787 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 788 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 789 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart); 790 791 //=========================PVR================================ 792 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 793 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 794 void HAL_PVR_Exit(MS_U32 u32PVREng); 795 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 796 /* 797 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 798 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 799 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 800 */ 801 void HAL_PVR_FlushData(MS_U32 u32PVREng); 802 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 803 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 804 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 805 void HAL_PVR_Start(MS_U32 u32PVREng); 806 void HAL_PVR_Stop(MS_U32 u32PVREng); 807 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 808 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 809 void HAL_PVR_RecNull(MS_BOOL bSet); 810 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 811 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 812 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 813 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 814 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 815 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 816 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 817 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 818 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 819 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 820 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 821 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 822 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 823 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 824 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 825 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 826 /* 827 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 828 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 829 */ 830 831 //=========================FQ================================ 832 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 833 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 834 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 835 836 //=========================HCMD================================ 837 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 838 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 839 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 840 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 841 MS_BOOL HAL_TSP_HCMD_Alive(void); 842 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 843 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 844 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 845 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 846 847 //=========================INT================================ 848 void HAL_TSP_INT_Enable(MS_U32 u32Mask); 849 void HAL_TSP_INT_Disable(MS_U32 u32Mask); 850 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask); 851 MS_U32 HAL_TSP_INT_GetHW(void); 852 void HAL_TSP_INT_ClrSW(void); 853 MS_U32 HAL_TSP_INT_GetSW(void); 854 855 //=========================Mapping================================ 856 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 857 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 858 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 859 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 860 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 861 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 862 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 863 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng); 864 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 865 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 866 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 867 868 //========================DSCMB Functions=================================== 869 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 870 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 871 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 872 873 //========================MOBF Functions===================================== 874 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 875 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 876 877 //========================Protection range=================================== 878 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 879 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 880 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 881 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 882 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 883 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 884 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 885 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 886 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 887 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 888 889 //========================Debug table============================= 890 891 // @TODO Renaming Load and Get 892 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 893 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 894 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock); 895 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 896 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 897 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 898 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 899 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 900 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 901 902 // @TODO Implement Drop and Dis Hal 903 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 904 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 905 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 906 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 907 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 908 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 909 910 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 911 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 912 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 913 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 914 915 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 916 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 917 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 918 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 919 920 //========================MergeStream Functions============================= 921 void HAL_TSP_PktConverter_Init(void); 922 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 923 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 924 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 925 /* 926 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 927 */ 928 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 929 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable); 930 931 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 932 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 933 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path); 934 935 //==========================TSIO ============================================ 936 void HAL_TSP_Privilege_Enable(MS_BOOL bEnable); 937 938 #endif // #ifndef __HAL_PVR_H__ 939