1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 //@TODO check ENG PIDFLT TSIF number 138 139 #define TSO_ENGINE_NUM (1) 140 #define TSO_PIDFLT_NUM (256) 141 #define TSO_REP_PIDFLT_NUM (16) 142 #define TSO_FILE_IF_NUM (2) 143 #define TSO_TSIF_NUM (6) 144 145 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 146 147 #define TSO_PID_NULL (0x1FFF) 148 #define TSO_MIU_BUS (4) 149 #define TSO_SVQ_UNIT_SIZE (208) 150 151 //------------------------------------------------------------------------------------------------- 152 // Harware Capability 153 //------------------------------------------------------------------------------------------------- 154 #define TSO_CLKIN_TS0 0x00 155 #define TSO_CLKIN_TS1 0x01 156 #define TSO_CLKIN_TS2 0x02 157 #define TSO_CLKIN_TS3 0x03 158 #define TSO_CLKIN_TS4 0x04 159 #define TSO_CLKIN_TS5 0x05 160 #define TSO_CLKIN_TS6 0x06 161 #define TSO_CLKIN_TSO0_OUT_P 0x07 162 #define TSO_CLKIN_DMD 0xFFFF //not supported 163 164 //------------------------------------------------------------------------------------------------- 165 // Type and Structure 166 //------------------------------------------------------------------------------------------------- 167 #define REG_PIDFLT_BASE (0x210000UL) 168 #define TSO_PIDFLT_PID_MASK (0x1FFF) 169 #define TSO_PIDFLT_IN_MASK (0x7) 170 #define TSO_PIDFLT_IN_SHIFT (13) 171 172 #define REG_CTRL_BASE_TSO (0xE0C00UL) // 0x1706 173 #define REG_CTRL_BASE_TSO1 (0xC2400UL) // 0x1612 174 175 typedef struct _REG32_TSO 176 { 177 volatile MS_U16 L; 178 volatile MS_U16 empty_L; 179 volatile MS_U16 H; 180 volatile MS_U16 empty_H; 181 } REG32_TSO; 182 183 typedef struct _REG16_TSO 184 { 185 volatile MS_U16 data; 186 volatile MS_U16 _resv; 187 } REG16_TSO; 188 189 //TSO0 190 typedef struct _REG_Ctrl_TSO 191 { 192 //---------------------------------------------- 193 // 0xBF802A00 MIPS direct access 194 //---------------------------------------------- 195 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 196 REG16_TSO SW_RSTZ; //00 197 #define TSO_SW_RSTZ 0x0001 198 #define TSO_SW_RST_CLK_STAMP 0x0002 199 #define TSO_SW_RST_CMDQ1 0x0100 200 #define TSO_SW_RST_WB1 0x0200 201 #define TSO_SW_RST_WB_DMA1 0x0400 202 #define TSO_SW_RST_TS_FIN1 0x0800 203 #define TSO_SW_RST_CMDQ 0x1000 204 #define TSO_SW_RST_WB 0x2000 205 #define TSO_SW_RST_WB_DMA 0x4000 206 #define TSO_SW_RST_FIN 0x8000 207 #define TSO_SW_RST_ALL 0xF002 208 #define TSO_SW_RST_ALL1 0x0F02 209 210 211 REG16_TSO SW_RSTZ1; //01 212 #define TSO_SW_RST_CHANNEL_IF1 0x0001 213 #define TSO_SW_RST_CHANNEL_IF2 0x0002 214 #define TSO_SW_RST_CHANNEL_IF3 0x0004 215 #define TSO_SW_RST_CHANNEL_IF4 0x0008 216 #define TSO_SW_RST_CHANNEL_IF5 0x0010 217 #define TSO_SW_RST_CHANNEL_IF6 0x0020 218 219 REG16_TSO CFG_TSO_02_03[2]; 220 221 REG16_TSO CHANNEL0_IF1_CONFIG0; //04 222 #define TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF //for internal sync 223 #define TSO_CHANNEL0_IF1_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 224 #define TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 225 #define TSO_CHANNEL0_IF1_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 226 227 REG16_TSO CHANNEL0_IF1_CONFIG1; //05 228 #define TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_MASK 0x00FF 229 #define TSO_CHANNEL0_IF1_CONFIG1_SYNC_BYTE_SHIFT 0 230 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 231 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_INPUT_MODE_SHIFT 8 232 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 233 #define TSO_CHANNEL0_IF1_CONFIG1_PKT_HEADER_LEN_SHIFT 11 234 235 REG16_TSO CHANNEL0_IF1_CONFIG2; //06 236 //----- for TV comaptibility -----// 237 #define TSO_CHCFG_P_SEL 0x0001 238 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002 239 #define TSO_CHCFG_TS_SIN_C0 0x0004 240 #define TSO_CHCFG_TS_SIN_C1 0x0008 241 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010 242 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020 243 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040 244 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080 245 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100 246 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200 247 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400 248 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800 249 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000 250 #define TSO_CHCFG_TRC_CLK_CLR 0x2000 251 //--------------------------------// 252 253 REG16_TSO CHANNEL0_IF1_CONFIG3; //07 reserved 254 255 REG16_TSO CHANNEL0_IF2_CONFIG0; //08 256 #define TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 257 #define TSO_CHANNEL0_IF2_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 258 #define TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 259 #define TSO_CHANNEL0_IF2_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 260 261 REG16_TSO CHANNEL0_IF2_CONFIG1; //09 262 #define TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_MASK 0x00FF 263 #define TSO_CHANNEL0_IF2_CONFIG1_SYNC_BYTE_SHIFT 0 264 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 265 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_INPUT_MODE_SHIFT 8 266 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 267 #define TSO_CHANNEL0_IF2_CONFIG1_PKT_HEADER_LEN_SHIFT 11 268 269 REG16_TSO CHANNEL0_IF2_CONFIG2; //0a 270 #define TSO_CHANNEL0_IF2_CONFIG2_P_SEL 0x0001 271 #define TSO_CHANNEL0_IF2_CONFIG2_EXT_SYNC_SEL 0x0002 272 #define TSO_CHANNEL0_IF2_CONFIG2_TS_SIN_C0 0x0004 273 #define TSO_CHANNEL0_IF2_CONFIG2_TS_SIN_C1 0x0008 274 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL 0x0010 275 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_NULL 0x0020 276 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 277 #define TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 278 #define TSO_CHANNEL0_IF2_CONFIG2_FORCE_SYNC_BYTE 0x0100 279 #define TSO_CHANNEL0_IF2_CONFIG2_SKIP_TEI_PKT 0x0200 280 #define TSO_CHANNEL0_IF2_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 281 #define TSO_CHANNEL0_IF2_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 282 #define TSO_CHANNEL0_IF2_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 283 #define TSO_CHANNEL0_IF2_CONFIG2_TRACING_CLOCK_CLR 0x2000 284 285 REG16_TSO CHANNEL0_IF2_CONFIG3; //0b reserved 286 287 REG16_TSO CHANNEL0_IF3_CONFIG0; //0c 288 #define TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 289 #define TSO_CHANNEL0_IF3_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 290 #define TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 291 #define TSO_CHANNEL0_IF3_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 292 293 REG16_TSO CHANNEL0_IF3_CONFIG1; //0d 294 #define TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_MASK 0x00FF 295 #define TSO_CHANNEL0_IF3_CONFIG1_SYNC_BYTE_SHIFT 0 296 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 297 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_INPUT_MODE_SHIFT 8 298 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 299 #define TSO_CHANNEL0_IF3_CONFIG1_PKT_HEADER_LEN_SHIFT 11 300 301 REG16_TSO CHANNEL0_IF3_CONFIG2; //0e 302 #define TSO_CHANNEL0_IF3_CONFIG2_P_SEL 0x0001 303 #define TSO_CHANNEL0_IF3_CONFIG2_EXT_SYNC_SEL 0x0002 304 #define TSO_CHANNEL0_IF3_CONFIG2_TS_SIN_C0 0x0004 305 #define TSO_CHANNEL0_IF3_CONFIG2_TS_SIN_C1 0x0008 306 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL 0x0010 307 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_NULL 0x0020 308 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 309 #define TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 310 #define TSO_CHANNEL0_IF3_CONFIG2_FORCE_SYNC_BYTE 0x0100 311 #define TSO_CHANNEL0_IF3_CONFIG2_SKIP_TEI_PKT 0x0200 312 #define TSO_CHANNEL0_IF3_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 313 #define TSO_CHANNEL0_IF3_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 314 #define TSO_CHANNEL0_IF3_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 315 #define TSO_CHANNEL0_IF3_CONFIG2_TRACING_CLOCK_CLR 0x2000 316 317 REG16_TSO CHANNEL0_IF3_CONFIG3; //0f reserved 318 319 REG16_TSO CHANNEL0_IF4_CONFIG0; //10 320 #define TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 321 #define TSO_CHANNEL0_IF4_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 322 #define TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 323 #define TSO_CHANNEL0_IF4_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 324 325 REG16_TSO CHANNEL0_IF4_CONFIG1; //11 326 #define TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_MASK 0x00FF 327 #define TSO_CHANNEL0_IF4_CONFIG1_SYNC_BYTE_SHIFT 0 328 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 329 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_INPUT_MODE_SHIFT 8 330 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 331 #define TSO_CHANNEL0_IF4_CONFIG1_PKT_HEADER_LEN_SHIFT 11 332 333 REG16_TSO CHANNEL0_IF4_CONFIG2; //12 334 #define TSO_CHANNEL0_IF4_CONFIG2_P_SEL 0x0001 335 #define TSO_CHANNEL0_IF4_CONFIG2_EXT_SYNC_SEL 0x0002 336 #define TSO_CHANNEL0_IF4_CONFIG2_TS_SIN_C0 0x0004 337 #define TSO_CHANNEL0_IF4_CONFIG2_TS_SIN_C1 0x0008 338 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL 0x0010 339 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_NULL 0x0020 340 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 341 #define TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 342 #define TSO_CHANNEL0_IF4_CONFIG2_FORCE_SYNC_BYTE 0x0100 343 #define TSO_CHANNEL0_IF4_CONFIG2_SKIP_TEI_PKT 0x0200 344 #define TSO_CHANNEL0_IF4_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 345 #define TSO_CHANNEL0_IF4_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 346 #define TSO_CHANNEL0_IF4_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 347 #define TSO_CHANNEL0_IF4_CONFIG2_TRACING_CLOCK_CLR 0x2000 348 349 REG16_TSO CHANNEL0_IF4_CONFIG3; //13 reserved 350 351 REG16_TSO CHANNEL0_IF5_CONFIG0; //14 352 #define TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 353 #define TSO_CHANNEL0_IF5_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 354 #define TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 355 #define TSO_CHANNEL0_IF5_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 356 357 REG16_TSO CHANNEL0_IF5_CONFIG1; //15 358 #define TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_MASK 0x00FF 359 #define TSO_CHANNEL0_IF5_CONFIG1_SYNC_BYTE_SHIFT 0 360 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 361 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_INPUT_MODE_SHIFT 8 362 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 363 #define TSO_CHANNEL0_IF5_CONFIG1_PKT_HEADER_LEN_SHIFT 11 364 365 REG16_TSO CHANNEL0_IF5_CONFIG2; //16 366 #define TSO_CHANNEL0_IF5_CONFIG2_P_SEL 0x0001 367 #define TSO_CHANNEL0_IF5_CONFIG2_EXT_SYNC_SEL 0x0002 368 #define TSO_CHANNEL0_IF5_CONFIG2_TS_SIN_C0 0x0004 369 #define TSO_CHANNEL0_IF5_CONFIG2_TS_SIN_C1 0x0008 370 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL 0x0010 371 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_NULL 0x0020 372 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 373 #define TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 374 #define TSO_CHANNEL0_IF5_CONFIG2_FORCE_SYNC_BYTE 0x0100 375 #define TSO_CHANNEL0_IF5_CONFIG2_SKIP_TEI_PKT 0x0200 376 #define TSO_CHANNEL0_IF5_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 377 #define TSO_CHANNEL0_IF5_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 378 #define TSO_CHANNEL0_IF5_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 379 #define TSO_CHANNEL0_IF5_CONFIG2_TRACING_CLOCK_CLR 0x2000 380 381 REG16_TSO CHANNEL0_IF5_CONFIG3; //17 reserved 382 383 REG16_TSO CHANNEL0_IF6_CONFIG0; //18 384 #define TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_MASK 0x00FF 385 #define TSO_CHANNEL0_IF6_CONFIG0_PKT_SIZE_CHK_LIVE_SHIFT 0 386 #define TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_MASK 0xFF00 387 #define TSO_CHANNEL0_IF6_CONFIG0_PIDFLT_PKT_SIZE_SHIFT 8 388 389 REG16_TSO CHANNEL0_IF6_CONFIG1; //19 390 #define TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_MASK 0x00FF 391 #define TSO_CHANNEL0_IF6_CONFIG1_SYNC_BYTE_SHIFT 0 392 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_MASK 0x0700 393 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_INPUT_MODE_SHIFT 8 394 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_MASK 0xF800 395 #define TSO_CHANNEL0_IF6_CONFIG1_PKT_HEADER_LEN_SHIFT 11 396 397 REG16_TSO CHANNEL0_IF6_CONFIG2; //1a 398 #define TSO_CHANNEL0_IF6_CONFIG2_P_SEL 0x0001 399 #define TSO_CHANNEL0_IF6_CONFIG2_EXT_SYNC_SEL 0x0002 400 #define TSO_CHANNEL0_IF6_CONFIG2_TS_SIN_C0 0x0004 401 #define TSO_CHANNEL0_IF6_CONFIG2_TS_SIN_C1 0x0008 402 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL 0x0010 403 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_NULL 0x0020 404 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_OVERFLOW_INT_EN 0x0040 405 #define TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_OVERFLOW_CLR 0x0080 406 #define TSO_CHANNEL0_IF6_CONFIG2_FORCE_SYNC_BYTE 0x0100 407 #define TSO_CHANNEL0_IF6_CONFIG2_SKIP_TEI_PKT 0x0200 408 #define TSO_CHANNEL0_IF6_CONFIG2_DIS_LOCKED_PKT_CNT 0x0400 409 #define TSO_CHANNEL0_IF6_CONFIG2_CLR_LOCKED_PKT_CNT 0x0800 410 #define TSO_CHANNEL0_IF6_CONFIG2_TRACING_CLOCK_LD_DIS 0x1000 411 #define TSO_CHANNEL0_IF6_CONFIG2_TRACING_CLOCK_CLR 0x2000 412 413 REG16_TSO CHANNEL0_IF6_CONFIG3; //1b reserved 414 415 REG16_TSO TSO_CONFIG0; //1c 416 #define TSO_CONFIG0_S2P_EN 0x0001 417 #define TSO_CONFIG0_S2P_TS_SIN_C0 0x0002 418 #define TSO_CONFIG0_S2P_TS_SIN_C1 0x0004 419 #define TSO_CONFIG0_S2P_3WIRE_MODE 0x0008 420 #define TSO_CONFIG0_BYPASS_S2P 0x0010 421 #define TSO_CONFIG0_S2P1_EN 0x0100 422 #define TSO_CONFIG0_S2P1_TS_SIN_C0 0x0200 423 #define TSO_CONFIG0_S2P1_TS_SIN_C1 0x0400 424 #define TSO_CONFIG0_S2P1_3WIRE_MODE 0x0800 425 #define TSO_CONFIG0_BYPASS_S2P1 0x1000 426 427 REG16_TSO TSO_CONFIG1; //1d 428 //----- for TV comaptibility -----// 429 #define TSO_CFG1_TSO_OUT_EN 0x0001 430 #define TSO_CFG1_TSO_TSIF1_EN 0x0002 431 #define TSO_CFG1_TSO_TSIF2_EN 0x0004 432 #define TSO_CFG1_TSO_TSIF3_EN 0x0008 433 #define TSO_CFG1_TSO_TSIF4_EN 0x0010 434 #define TSO_CFG1_TSO_TSIF5_EN 0x0020 435 #define TSO_CFG1_TSO_TSIF6_EN 0x0040 436 //--------------------------------// 437 #define TSO_CONFIG1_PAUSE_OPIF 0x0080 438 #define TSO_CONFIG1_TURN_OFF_MCM 0x0100 439 #define TSO_CONFIG1_CLOCK_TRACING_SEL_MASK 0x0E00 440 #define TSO_CONFIG1_CLOCK_TRACING_SEL_SHIFT 9 441 #define TSO_CONFIG1_SERIAL_OUT_EN 0x1000 442 #define TSO_CONFIG1_PKT_LOCK_CLR 0x2000 443 #define TSO_CONFIG1_PKT_NULL_EN 0x4000 444 //----- for TV comaptibility -----// 445 #define TSO_CFG1_PKT_PARAM_LD 0x8000 446 //--------------------------------// 447 448 REG16_TSO TSO_CONFIG2; //1e 449 #define TSO_CONFIG2_VALID_BYTE_CNT_MASK 0x00FF 450 #define TSO_CONFIG2_VALID_BYTE_CNT_SHIFT 0 451 #define TSO_CONFIG2_INVALID_BYTE_CNT_MASK 0xFF00 452 #define TSO_CONFIG2_INVALID_BYTE_CNT_SHIFT 8 453 454 REG16_TSO TSO_CONFIG3; //1f 455 #define TSO_CONFIG3_OPIF_PKT_SIZE_MASK 0xFFFF 456 457 REG32_TSO PIDFLTS[16]; //20~3e PID00~0F 458 //FOR ALL PID 459 #define TSO_PID_ORIGINAL_PID_MASK 0x00001FFF 460 #define TSO_PID_ORIGINAL_PID_SHIFT 0 461 #define TSO_PID_SOURCE_SEL_MASK 0x0000E000 462 #define TSO_PID_SOURCE_SEL_SHIFT 13 463 #define TSO_PID_NEW_PID_MASK 0x1FFF0000 464 #define TSO_PID_NEW_PID_SHIFT 16 465 #define TSO_PID_REPLACE_EN 0x80000000 466 467 REG16_TSO CLR_BYTE_CNT; //40 468 #define TSO_CLR_BYTE_CNT_1 0x0001 469 #define TSO_CLR_BYTE_CNT_2 0x0002 470 #define TSO_CLR_BYTE_CNT_3 0x0004 471 #define TSO_CLR_BYTE_CNT_4 0x0008 472 #define TSO_CLR_BYTE_CNT_5 0x0010 473 #define TSO_CLR_BYTE_CNT_6 0x0020 474 475 REG16_TSO CFG_TSO_41_42[2]; //41~42 476 477 REG16_TSO TSO_CONFIG4; //43 478 #define TSO_CFG4_LOCK_RETURN_SYSTEM_TIMESTAMP 0x0001 479 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002 480 #define TSO_CFG4_SET_SYS_TIMESTAMP_TO_HW 0x0004 481 #define TSO_CFG4_TIMESTAMP_BASE 0x0008//0:90k 1:27m 482 #define TSO_CFG4_PDTABLE_SRAM_SD_EN 0x0010 483 #define TSO_CFG4_NULL_PKT_ID_MASK 0xFF00 484 #define TSO_CFG4_NULL_PKT_ID_SHIFT 8 485 486 REG16_TSO TSO_CONFIG5; //44 487 #define TSO_CONFIG5_3_WIRE_EN_1 0x0001 488 #define TSO_CONFIG5_3_WIRE_EN_2 0x0002 489 #define TSO_CONFIG5_3_WIRE_EN_3 0x0004 490 #define TSO_CONFIG5_3_WIRE_EN_4 0x0008 491 #define TSO_CONFIG5_3_WIRE_EN_5 0x0010 492 #define TSO_CONFIG5_3_WIRE_EN_6 0x0020 493 #define TSO_CONFIG5_DIS_MIU_RQ 0x0040 494 #define TSO_CONFIG5_FIXED_MIU_REG_FLUSH 0x0080 495 #define TSO_CONFIG5_TSIO_MODE 0x0400 496 #define TSO_CONFIG5_TSIO2OPIF 0x0800 497 498 REG16_TSO PDTABLE_ADDR_L; //45 ind R/W of L addr to pdtable 499 REG16_TSO PDTABLE_ADDR_H; //46 ind R/W of H addr to pdtable 500 501 REG16_TSO PDTABLE_WDATA_L; //47 ind R/W of L addr to pdtable 502 REG16_TSO PDTABLE_WDATA_H; //48 ind R/W of L addr to pdtable 503 504 REG16_TSO PDTABLE_RDATA; //49 ind of Rdata from pdtable 505 506 REG16_TSO PDTABLE_EN; //4a 507 #define TSO_PDTABLE_W_EN 0x0001//Ind W flag to pdtable 508 #define TSO_PDTABLE_R_EN 0x0002//Ind R flag to pdtable 509 510 REG16_TSO TSO_STATUS; //4b 511 #define TSO_STATUS_SVQ_MASK 0x7F00 512 #define TSO_STATUS_SVQ_SHIFT 8 513 #define TSO_STATUS_PDFLT 0x8000 514 515 REG16_TSO FILE_TIMER[2]; //4c ~ 4d 516 517 REG16_TSO TSO_STATUS1; //4e 518 #define TSO_STATUS1_EVEROVERFLOW_TSIF_1 0x0001 519 #define TSO_STATUS1_EVEROVERFLOW_TSIF_2 0x0002 520 #define TSO_STATUS1_EVEROVERFLOW_TSIF_3 0x0004 521 #define TSO_STATUS1_EVEROVERFLOW_TSIF_4 0x0008 522 #define TSO_STATUS1_EVEROVERFLOW_TSIF_5 0x0010 523 #define TSO_STATUS1_EVEROVERFLOW_TSIF_6 0x0020 524 525 REG16_TSO CFG_TSO_4F_5A[12]; //4f~5a 526 527 REG16_TSO TSO_TRACING_HIGH; //5b 528 REG16_TSO TSO_TRACING_LOW; //5c 529 REG16_TSO TSO_TRACING_1T; //5d 530 REG16_TSO TSO_BLOCK_SIZE_DB; //5e 531 REG16_TSO TSO_OPT_SZIE_DB; //5f 532 533 REG32_TSO CFG_TSO_60_63[2]; //60~63 534 REG16_TSO TSO_Filein_Ctrl; //64 535 REG32_TSO CFG_TSO_65_68[2]; //65~68 536 REG16_TSO TSO_Filein_Ctrl1; //69 537 #define TSO_FILEIN_CTRL_MASK 0x0007 538 #define TSO_FILEIN_RSTART 0x0001 539 #define TSO_FILEIN_ABORT 0x0002 540 #define TSO_FILEIN_TRUST 0x0004 541 542 REG16_TSO PKT_CNT_SEL; //6a 543 #define TSO_PKT_CNT_RETURN_SEL_MASK 0x000F 544 #define TSO_PKT_CNT_RETURN_SEL_SHIFT 0 545 #define TSO_PKT_CNT_DBG_LOCKED_PKT_CNT_MASK 0x00F0 546 #define TSO_PKT_CNT_DBG_LOCKED_PKT_CNT_SHIFT 4 547 #define TSO_PKT_CNT_DBG_PKT_CNTT_DBG_MASK 0xFF00 548 #define TSO_PKT_CNT_DBG_PKT_CNTT_DBG_SHIFT 8 549 550 REG16_TSO PKT_CHK_SIZE_FIN; //6b 551 #define TSO_PKT_CHK_SIZE_FIN_MASK 0x00FF 552 #define TSO_PKT_CHK_SIZE_FIN_SHIFT 0 553 #define TSO_PKT_CHK_SIZE_FIN1_MASK 0xFF00 554 #define TSO_PKT_CHK_SIZE_FIN1_SHIFT 8 555 556 REG32_TSO LPCR2_BUF; //6c~6d 557 REG32_TSO LPCR2_BUF1; //6e~6f 558 559 REG32_TSO TIMESTAMP; //70~71 560 REG32_TSO TIMESTAMP1; //72~73 561 562 REG32_TSO TSO2MI_RADDR; //74~75 563 REG32_TSO TSO2MI_RADDR1; //76~77 564 565 REG16_TSO CMD_QUEUE_STATUS; //78 566 #define TSO_CMDQ_SIZE 16 567 #define TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_MASK 0x000F 568 #define TSO_CMD_QUEUE_STATUS_CMD_WR_COUNT_SHIFT 0 569 #define TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_MASK 0x0030 570 #define TSO_CMD_QUEUE_STATUS_CMD_WR_LEVEL_SHIFT 4 571 #define TSO_CMD_QUEUE_STATUS_CMD_FIFO_FULL 0x0040 572 #define TSO_CMD_QUEUE_STATUS_CMD_FIFO_EMPTY 0x0080 573 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_MASK 0x0F00 574 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_COUNT_SHIFT 8 575 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_MASK 0x3000 576 #define TSO_CMD_QUEUE_STATUS1_CMD_WR_LEVEL_SHIFT 12 577 #define TSO_CMD_QUEUE_STATUS1_CMD_FIFO_FULL 0x4000 578 #define TSO_CMD_QUEUE_STATUS1_CMD_FIFO_EMPTY 0x8000 579 580 REG16_TSO TSO_FILE_CONFIG; //79 581 #define TSO_FILE_CONFIG_TSO2MI_RPRIORITY 0x0001 582 #define TSO_FILE_CONFIG_MEM_TS_DATA_ENDIAN 0x0002 583 #define TSO_FILE_CONFIG_MEM_TS_W_ORDER 0x0004 584 #define TSO_FILE_CONFIG_LPCR2_WLD 0x0008 585 #define TSO_FILE_CONFIG_LPCR2_LOAD 0x0010 586 #define TSO_FILE_CONFIG_DIS_MIU_RQ 0x0020 587 #define TSO_FILE_CONFIG_TSO_RADDR_READ 0x0040 588 #define TSO_FILE_CONFIG_TS_DATA_PORT_SEL 0x0080 589 #define TSO_FILE_CONFIG_TSO_FILE_IN 0x0100 590 #define TSO_FILE_CONFIG_TIMER_EN 0x0200 591 #define TSO_FILE_CONFIG_PKT_192_BLK_DISABLE 0x0400 592 #define TSO_FILE_CONFIG_PKT_192_EN 0x0800 593 #define TSO_FILE_CONFIG_TSP_FILE_SEGMENT 0x1000 594 #define TSO_FILE_CONFIG_CLK_STAMP_27_EN 0x2000 595 596 REG16_TSO TSO_FILE_CONFIG1; //7a 597 #define TSO_FILE_CONFIG1_TSO2MI_RPRIORITY 0x0001 598 #define TSO_FILE_CONFIG1_MEM_TS_DATA_ENDIAN 0x0002 599 #define TSO_FILE_CONFIG1_MEM_TS_W_ORDER 0x0004 600 #define TSO_FILE_CONFIG1_LPCR2_WLD 0x0008 601 #define TSO_FILE_CONFIG1_LPCR2_LOAD 0x0010 602 #define TSO_FILE_CONFIG1_DIS_MIU_RQ 0x0020 603 #define TSO_FILE_CONFIG1_TSO_RADDR_READ 0x0040 604 #define TSO_FILE_CONFIG1_TS_DATA_PORT_SEL 0x0080 605 #define TSO_FILE_CONFIG1_TSO_FILE_IN 0x0100 606 #define TSO_FILE_CONFIG1_TIMER_EN 0x0200 607 #define TSO_FILE_CONFIG1_PKT_192_BLK_DISABLE 0x0400 608 #define TSO_FILE_CONFIG1_PKT_192_EN 0x0800 609 #define TSO_FILE_CONFIG1_TSP_FILE_SEGMENT 0x1000 610 #define TSO_FILE_CONFIG1_CLK_STAMP_27_EN 0x2000 611 612 REG16_TSO INTERRUPT; //7b 613 #define TSO_INT_SRC_MASK 0x00FF 614 #define TSO_INT_STS_MASK 0xFF00 615 //----- for TV comaptibility -----// 616 #define TSO_INT_DMA_DONE 0x0001 617 #define TSO_INT_DMA_DONE1 0x0002 618 //--------------------------------// 619 #define TSO_INT_SRC_TRAC_CLK_UPDATE 0x0004 620 #define TSO_INT_STS_DMA_DONE 0x0100 621 #define TSO_INT_STS_DMA_DONE1 0x0200 622 #define TSO_INT_STS_TRAC_CLK_UPDATE 0x0400 623 624 REG16_TSO INTERRUPT1; //7c 625 #define TSO_INT_SRC_PIDFLT1_OVERFLOW 0x0001 626 #define TSO_INT_SRC_PIDFLT2_OVERFLOW 0x0002 627 #define TSO_INT_SRC_PIDFLT3_OVERFLOW 0x0004 628 #define TSO_INT_SRC_PIDFLT4_OVERFLOW 0x0008 629 #define TSO_INT_SRC_PIDFLT5_OVERFLOW 0x0010 630 #define TSO_INT_SRC_PIDFLT6_OVERFLOW 0x0020 631 632 #define TSO_INT_STS_PIDFLT1_OVERFLOW 0x0100 633 #define TSO_INT_STS_PIDFLT2_OVERFLOW 0x0200 634 #define TSO_INT_STS_PIDFLT3_OVERFLOW 0x0400 635 #define TSO_INT_STS_PIDFLT4_OVERFLOW 0x0800 636 #define TSO_INT_STS_PIDFLT5_OVERFLOW 0x1000 637 #define TSO_INT_STS_PIDFLT6_OVERFLOW 0x2000 638 639 REG32_TSO TSO_DEBUG; //7d~7e 640 641 REG16_TSO DBG_SEL; //7f 642 643 } REG_Ctrl_TSO; 644 645 646 //TSO1 647 typedef struct _REG_Ctrl_TSO1 648 { 649 //---------------------------------------------- 650 // 0xBF802C00 MIPS direct access 651 //---------------------------------------------- 652 653 REG16_TSO REG_PRE_HEADER_1_CONFIG_0; //00 654 #define TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 655 #define TSO1_REG_PRE_HEADER_1_CONFIG_0_LOCAL_STREAMID_SHIFT 0 656 657 REG16_TSO REG_PRE_HEADER_1_CONFIG_1; //01 658 REG16_TSO REG_PRE_HEADER_1_CONFIG_2; //02 659 REG16_TSO REG_PRE_HEADER_1_CONFIG_3; //03 660 661 REG16_TSO REG_PRE_HEADER_2_CONFIG_0; //04 662 #define TSO1_REG_PRE_HEADER_2_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 663 #define TSO1_REG_PRE_HEADER_2_CONFIG_0_LOCAL_STREAMID_SHIFT 0 664 665 REG16_TSO REG_PRE_HEADER_2_CONFIG_1; //05 666 REG16_TSO REG_PRE_HEADER_2_CONFIG_2; //06 667 REG16_TSO REG_PRE_HEADER_2_CONFIG_3; //07 668 669 REG16_TSO REG_PRE_HEADER_3_CONFIG_0; //08 670 #define TSO1_REG_PRE_HEADER_3_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 671 #define TSO1_REG_PRE_HEADER_3_CONFIG_0_LOCAL_STREAMID_SHIFT 0 672 673 REG16_TSO REG_PRE_HEADER_3_CONFIG_1; //09 674 REG16_TSO REG_PRE_HEADER_3_CONFIG_2; //0a 675 REG16_TSO REG_PRE_HEADER_3_CONFIG_3; //0b 676 677 REG16_TSO REG_PRE_HEADER_4_CONFIG_0; //0c 678 #define TSO1_REG_PRE_HEADER_4_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 679 #define TSO1_REG_PRE_HEADER_4_CONFIG_0_LOCAL_STREAMID_SHIFT 0 680 681 REG16_TSO REG_PRE_HEADER_4_CONFIG_1; //0d 682 REG16_TSO REG_PRE_HEADER_4_CONFIG_2; //0e 683 REG16_TSO REG_PRE_HEADER_4_CONFIG_3; //0f 684 685 REG16_TSO REG_PRE_HEADER_5_CONFIG_0; //10 686 #define TSO1_REG_PRE_HEADER_5_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 687 #define TSO1_REG_PRE_HEADER_5_CONFIG_0_LOCAL_STREAMID_SHIFT 0 688 689 REG16_TSO REG_PRE_HEADER_5_CONFIG_1; //11 690 REG16_TSO REG_PRE_HEADER_5_CONFIG_2; //12 691 REG16_TSO REG_PRE_HEADER_5_CONFIG_3; //13 692 693 REG16_TSO REG_PRE_HEADER_6_CONFIG_0; //14 694 #define TSO1_REG_PRE_HEADER_6_CONFIG_0_LOCAL_STREAMID_MASK 0x00FF 695 #define TSO1_REG_PRE_HEADER_6_CONFIG_0_LOCAL_STREAMID_SHIFT 0 696 697 REG16_TSO REG_PRE_HEADER_6_CONFIG_1; //15 698 REG16_TSO REG_PRE_HEADER_6_CONFIG_2; //16 699 REG16_TSO REG_PRE_HEADER_6_CONFIG_3; //17 700 701 REG32_TSO SVQ1_BASE; //18~19 702 #define TSO1_SVQ1_BASE_MASK 0x0FFFFFFF 703 #define TSO1_SVQ1_BASE_SHIFT 0 704 705 REG16_TSO SVQ1_SIZE_200BYTE; //1a 706 #define TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_MASK 0xFFFF 707 #define TSO1_SVQ1_SIZE_200BYTE_SVQ_SIZE_SHIFT 0 708 709 REG16_TSO SVQ1_TX_CONFIG; //1b 710 #define TSO1_SVQ1_TX_CONFIG_WR_THRESHOLD_MASK 0x000F 711 #define TSO1_SVQ1_TX_CONFIG_WR_THRESHOLD_SHIFT 0 712 #define TSO1_SVQ1_TX_CONFIG_PRIORITY_THRESHOLD_MASK 0x00F0 713 #define TSO1_SVQ1_TX_CONFIG_PRIORITY_THRESHOLD_SHIFT 4 714 #define TSO1_SVQ1_TX_CONFIG_FORCEFIRE_CNT_MASK 0x0F00 715 #define TSO1_SVQ1_TX_CONFIG_FORCEFIRE_CNT_SHIFT 8 716 #define TSO1_SVQ1_TX_CONFIG_TX_RESET 0x1000 717 #define TSO1_SVQ1_TX_CONFIG_OVERFLOW_INT_EN 0x2000 718 #define TSO1_SVQ1_TX_CONFIG_OVERFLOW_CLR 0x4000 719 #define TSO1_SVQ1_TX_CONFIG_SVQ_TX_ENABLE 0x8000 720 REG32_TSO SVQ2_BASE; //1C~1D 721 REG16_TSO SVQ2_SIZE_200BYTE; //1E 722 REG16_TSO SVQ2_TX_CONFIG; //1F 723 REG32_TSO SVQ3_BASE; //20~21 724 REG16_TSO SVQ3_SIZE_200BYTE; //22 725 REG16_TSO SVQ3_TX_CONFIG; //23 726 REG32_TSO SVQ4_BASE; //24~25 727 REG16_TSO SVQ4_SIZE_200BYTE; //26 728 REG16_TSO SVQ4_TX_CONFIG; //27 729 REG32_TSO SVQ5_BASE; //28~29 730 REG16_TSO SVQ5_SIZE_200BYTE; //2a 731 REG16_TSO SVQ5_TX_CONFIG; //2b 732 REG32_TSO SVQ6_BASE; //2C~2D 733 REG16_TSO SVQ6_SIZE_200BYTE; //2E 734 REG16_TSO SVQ6_TX_CONFIG; //2F 735 736 REG16_TSO SVQ_RX_CONFIG; //30 737 #define TSO1_SVQ_RX_CONFIG_MODE_MASK 0x0003 //00=open cable 01=CI+ 10=192 mode 738 #define TSO1_SVQ_RX_CONFIG_MODE_SHIT 0 739 //----- for TV comaptibility -----// 740 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000 741 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001 742 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002 743 //--------------------------------// 744 #define TSO1_SVQ_RX_CONFIG_RD_THRESHOLD_MASK 0x001C //000=1/6 empty 001=1/8 empty 010=1/4 empty 011=1/2 empty else empty 745 #define TSO1_SVQ_RX_CONFIG_RD_THRESHOLD_SHIT 2 746 #define TSO1_SVQ_RX_CONFIG_ARBITOR_MODE_MASK 0x0060 //00=Run-Robin. 01=fix priority by REG 0x31~33 mode 10=dynamic priority 747 #define TSO1_SVQ_RX_CONFIG_ARBITOR_MODE_SHIT 5 748 //----- for TV comaptibility -----// 749 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000 750 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0001 751 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0002 752 //--------------------------------// 753 #define TSO1_SVQ_RX_CONFIG_SRAM_SD_EN 0x0080 754 #define TSO1_SVQ_RX_CONFIG_SVQ_FORCE_RESET 0x0100 755 #define TSO1_SVQ_RX_CONFIG_SVQ_MIU_NS 0x0200 756 #define TSO1_SVQ_RX_CONFIG_SVQ_MOBF_INDEX_MASK 0x7C00 757 #define TSO1_SVQ_RX_CONFIG_SVQ_MOBF_INDEX_SHIFT 10 758 #define TSO1_SVQ_RX_CONFIG_SVQ_DYNAMIC_PRI 0x8000 759 760 REG16_TSO SVQ_RX_1_2_PRIORITY; //31 761 #define TSO1_SVQ_RX1_PRIORITY_MASK 0x003F 762 #define TSO1_SVQ_RX1_PRIORITY_SHIFT 0 763 #define TSO1_SVQ_RX2_PRIORITY_MASK 0x3F00 764 #define TSO1_SVQ_RX2_PRIORITY_SHIFT 8 765 766 REG16_TSO SVQ_RX_3_4_PRIORITY; //32 767 #define TSO1_SVQ_RX3_PRIORITY_MASK 0x003F 768 #define TSO1_SVQ_RX3_PRIORITY_SHIFT 0 769 #define TSO1_SVQ_RX4_PRIORITY_MASK 0x3F00 770 #define TSO1_SVQ_RX4_PRIORITY_SHIFT 8 771 772 REG16_TSO SVQ_RX_5_6_PRIORITY; //33 773 #define TSO1_SVQ_RX5_PRIORITY_MASK 0x003F 774 #define TSO1_SVQ_RX5_PRIORITY_SHIFT 0 775 #define TSO1_SVQ_RX6_PRIORITY_MASK 0x3F00 776 #define TSO1_SVQ_RX6_PRIORITY_SHIFT 8 777 778 REG32_TSO SVQ_STATUS; //34~35 779 //----- for TV comaptibility -----// 780 #define TSO_SVQ_STS_MASK 0x000F 781 #define TSO_SVQ1_STS_SHIFT 0 782 #define TSO_SVQ2_STS_SHIFT 4 783 #define TSO_SVQ3_STS_SHIFT 8 784 #define TSO_SVQ4_STS_SHIFT 12 785 #define TSO_SVQ5_STS_SHIFT 16 786 #define TSO_SVQ6_STS_SHIFT 20 787 #define TSO_SVQ_STS_EVER_FULL 0x0001 788 #define TSO_SVQ_STS_EVER_OVF 0x0002 789 #define TSO_SVQ_STS_EMPTY 0x0004 790 #define TSO_SVQ_STS_BUSY 0x0008 791 //--------------------------------// 792 #define TSO1_SVQ1_OVERFLOW_INT 0x01000000 793 #define TSO1_SVQ2_OVERFLOW_INT 0x02000000 794 #define TSO1_SVQ3_OVERFLOW_INT 0x04000000 795 #define TSO1_SVQ4_OVERFLOW_INT 0x08000000 796 #define TSO1_SVQ5_OVERFLOW_INT 0x10000000 797 #define TSO1_SVQ6_OVERFLOW_INT 0x20000000 798 799 REG32_TSO SVQ_STATUS2; //36~37 800 #define TSO1_SVQ1_TX_WATER_LEVEL_MASK 0x00000003 801 #define TSO1_SVQ1_TX_WATER_LEVEL_SHIFT 0 802 #define TSO1_SVQ1_TX_FULL_MASK 0x00000004 803 #define TSO1_SVQ1_TX_FULL_SHIFT 2 804 #define TSO1_SVQ1_TX_EMPTY_MASK 0x00000008 805 #define TSO1_SVQ1_TX_EMPTY_SHIFT 3 806 #define TSO1_SVQ2_TX_WATER_LEVEL_MASK 0x00000030 807 #define TSO1_SVQ2_TX_WATER_LEVEL_SHIFT 4 808 #define TSO1_SVQ2_TX_FULL_MASK 0x00000040 809 #define TSO1_SVQ2_TX_FULL_SHIFT 6 810 #define TSO1_SVQ2_TX_EMPTY_MASK 0x00000080 811 #define TSO1_SVQ2_TX_EMPTY_SHIFT 7 812 #define TSO1_SVQ3_TX_WATER_LEVEL_MASK 0x00000300 813 #define TSO1_SVQ3_TX_WATER_LEVEL_SHIFT 8 814 #define TSO1_SVQ3_TX_FULL_MASK 0x00000400 815 #define TSO1_SVQ3_TX_FULL_SHIFT 10 816 #define TSO1_SVQ3_TX_EMPTY_MASK 0x00000800 817 #define TSO1_SVQ3_TX_EMPTY_SHIFT 11 818 #define TSO1_SVQ4_TX_WATER_LEVEL_MASK 0x00003000 819 #define TSO1_SVQ4_TX_WATER_LEVEL_SHIFT 12 820 #define TSO1_SVQ4_TX_FULL_MASK 0x00004000 821 #define TSO1_SVQ4_TX_FULL_SHIFT 14 822 #define TSO1_SVQ4_TX_EMPTY_MASK 0x00008000 823 #define TSO1_SVQ4_TX_EMPTY_SHIFT 15 824 #define TSO1_SVQ5_TX_WATER_LEVEL_MASK 0x00030000 825 #define TSO1_SVQ5_TX_WATER_LEVEL_SHIFT 16 826 #define TSO1_SVQ5_TX_FULL_MASK 0x00040000 827 #define TSO1_SVQ5_TX_FULL_SHIFT 18 828 #define TSO1_SVQ5_TX_EMPTY_MASK 0x00080000 829 #define TSO1_SVQ5_TX_EMPTY_SHIFT 19 830 #define TSO1_SVQ6_TX_WATER_LEVEL_MASK 0x00300000 831 #define TSO1_SVQ6_TX_WATER_LEVEL_SHIFT 20 832 #define TSO1_SVQ6_TX_FULL_MASK 0x00400000 833 #define TSO1_SVQ6_TX_FULL_SHIFT 22 834 #define TSO1_SVQ6_TX_EMPTY_MASK 0x00800000 835 #define TSO1_SVQ6_TX_EMPTY_SHIFT 23 836 837 REG32_TSO DELTA; //38~39 838 839 REG16_TSO DELTA_CONFIG; //3a 840 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_MASK 0x0007 841 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_SHIFT 0 842 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_1 1 843 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_2 2 844 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_3 3 845 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_4 4 846 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_5 5 847 #define TSO1_DELTA_CONFIG_SEL_CHANNEL_6 6 848 #define TSO1_DELTA_CONFIG_DELTA_CLR 0x0008 849 #define TSO1_DELTA_CONFIG_MAX_ID_MASK 0x0070 850 #define TSO1_DELTA_CONFIG_MAX_ID_SHIFT 8 851 852 REG16_TSO REG_TSO1_CFG3B_52[24]; //3b~52 853 REG16_TSO REG_TSO_MIU_SEL_1; //53 854 #define REG_MIU_SEL_SVQTX1_MASK 0x0003 855 #define REG_MIU_SEL_SVQTX1_SHIFT 0 856 #define REG_MIU_SEL_SVQTX2_MASK 0x000C 857 #define REG_MIU_SEL_SVQTX2_SHIFT 2 858 #define REG_MIU_SEL_SVQTX3_MASK 0x0030 859 #define REG_MIU_SEL_SVQTX3_SHIFT 4 860 #define REG_MIU_SEL_SVQTX4_MASK 0x00C0 861 #define REG_MIU_SEL_SVQTX4_SHIFT 6 862 #define REG_MIU_SEL_SVQTX5_MASK 0x0300 863 #define REG_MIU_SEL_SVQTX5_SHIFT 8 864 #define REG_MIU_SEL_SVQTX6_MASK 0x0C00 865 #define REG_MIU_SEL_SVQTX6_SHIFT 10 866 #define REG_MIU_SEL_SVQRX_MASK 0x300 867 #define REG_MIU_SEL_SVQRX_SHIFT 12 868 #define REG_MIU_SEL_CH5FILEIN_MASK 0xC000 869 #define REG_MIU_SEL_CH5FILEIN_SHIFT 14 870 REG16_TSO REG_TSO_MIU_SEL_2; //54 871 #define REG_MIU_SEL_CH6FILEIN_MASK 0x0003 872 #define REG_MIU_SEL_CH6FILEIN_SHIFT 0 873 REG16_TSO REG_TSO1_CFG55_66[18]; //55~66 874 REG16_TSO REG_TSO_MIU_ABT_CONFIG_1; 875 #define REG_MIU_ABT_CONFIG_1_CHECK2MI_RDY 0x0040 //U02 876 #define REG_MIU_ABT_CONFIG_1_MIU_FIXED_LAST_WD_EN_DONE_Z 0x0080 //U02 877 } REG_Ctrl_TSO1; 878 879 #endif // _TSO_REG_H_ 880