1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSIO_REG_H_ 103 #define _TSIO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 #define TSIO_ENGINE_NUM (1) 138 #define TSIO_SERVICE_NUM (64) 139 #define TSIO_LOCKEY_LEN (16) 140 #define TSIO_MAX_SYNCTHRESHOLD (16) 141 #define TSIO_MIN_SYNCTHRESHOLD (1) 142 #define TSIO_SGDMAIN_PIDFLT_NUM (512) 143 #define TSIO_FILTER_NUM (32) 144 #define TSIO_MIU_BUS (4) 145 #define TSIO_SVQ_UNIT_SIZE (200) 146 147 #define TSIO_LOCDEC_KEY_LEN (16) 148 #define TSIO_PID_NULL (0x1FFF) 149 #define TSIO_SERVICE_NULL (0xFF) 150 151 //------------------------------------------------------------------------------------------------- 152 // Harware Capability 153 //------------------------------------------------------------------------------------------------- 154 #define BITTRAINING_SW_MODE_ENABLE (1) 155 156 //------------------------------------------------------------------------------------------------- 157 // Type and Structure 158 //------------------------------------------------------------------------------------------------- 159 #define REG_SGDMAIN_PIDFLT_BASE (0x220000UL) 160 161 #define REG_CTRL_BASE_TSIO0 (0xE3400UL) // 0x171A 162 #define REG_CTRL_BASE_TSIO1 (0xE3600UL) // 0x171B 163 #define REG_CTRL_BASE_TSIO2 (0xE3800UL) // 0x171C 164 #define REG_CTRL_BASE_TSIO3 (0xE7200UL) // 0x1739 165 #define REG_CTRL_BASE_TSIO_LOCDEC (0xE3C00UL) // 0x171E 166 #define REG_CTRL_BASE_TSIO_PHY (0xE3E00UL) // 0x171F 167 168 #define REG_CTRL_BASE_TSO0 (0xE0C00UL) // 0x1706 169 #define REG_CTRL_BASE_TSO2 (0xA7200UL) // 0x1539 170 #define REG_CTRL_BASE_TSO3 (0xE3A00UL) // 0x171D 171 172 #define REG_CTRL_BASE_CLOCKGEN0 (0x01600UL) // 0x100B 173 #define REG_CTRL_BASE_CHIPTOP (0x03C00UL) // 0x101E 174 #define REG_CTRL_BASE_STRLD (0x05200UL) // 0x1029 175 176 typedef struct _REG32_TSIO 177 { 178 volatile MS_U16 L; 179 volatile MS_U16 empty_L; 180 volatile MS_U16 H; 181 volatile MS_U16 empty_H; 182 } REG32_TSIO; 183 184 typedef struct _REG16_TSIO 185 { 186 volatile MS_U16 data; 187 volatile MS_U16 _resv; 188 } REG16_TSIO; 189 190 191 //CLOCKGEN0 192 typedef struct _REG_Ctrl_CLOCKGEN0 193 { 194 REG16_TSIO RESERVED_00_24[37]; //00~24 195 196 REG16_TSIO REG_CLKGEN0_TSIO; //25 197 #define REG_CLKGEN0_TSIO_DISABLE_CLOCK 0x0100 198 #define REG_CLKGEN0_TSIO_INVERT_CLOCK 0x0200 199 #define REG_CLKGEN0_TSIO_CLKSOURCE_MASK 0x1C00 200 #define REG_CLKGEN0_TSIO_CLKSOURCE_SHIFT 10 201 202 REG16_TSIO RESERVED_26_29[4]; //26~29 203 204 REG16_TSIO REG_CLKGEN0_TSP; //2A 205 #define REG_CLKGEN0_TSP_DISABLE_CLOCK 0x0001 206 #define REG_CLKGEN0_TSP_INVERT_CLOCK 0x0002 207 #define REG_CLKGEN0_TSP_CLKSOURCE_MASK 0x001C 208 #define REG_CLKGEN0_TSP_CLKSOURCE_SHIFT 2 209 210 }REG_Ctrl_CLOCKGEN0; 211 212 //CHIP TOP 213 typedef struct _REG_Ctrl_CHIPTOP 214 { 215 REG16_TSIO RESERVED_00_53[84]; //00~53 216 217 REG16_TSIO REG_TOP_TSIO; //54 218 #define REG_TOP_TSIO_TSP_BOOT_CLK_SEL 0x0100 219 220 }REG_Ctrl_CHIPTOP; 221 222 //STRLD 223 typedef struct _REG_Ctrl_STRLD 224 { 225 REG16_TSIO RESERVED_00_31[50]; //00~31 226 227 REG16_TSIO REG_STRLD_32; //32 228 #define TEST_SDLDO_SEL_MASK 0x0030 229 #define TEST_SDLDO_SEL_SHIFT 4 230 }REG_Ctrl_STRLD; 231 232 //TSIO0 233 typedef struct _REG_Ctrl_TSIO0 234 { 235 REG16_TSIO SW_RSTZ; //00 236 #define TSIO0_SW_RSTZ 0x0001 237 #define TSIO0_SW_RST_ANA_TX 0x0002 238 #define TSIO0_SW_RST_ANA_RX 0x0004 239 240 REG16_TSIO TX_CONFIG0; //01 241 #define TSIO0_STUFF_SVID_MASK 0x003F 242 #define TSIO0_STUFF_SVID_SHIFT 0 243 #define TSIO0_VALID_LOCKED_CLR 0x0040 244 #define TSIO0_PKT_OVERFLOW_CLR 0x0080 245 #define TSIO0_TSIO_TX_IDLE_CLR 0x0100 246 #define TSIO0_TX_DIRECT_RX_8 0x0200 247 #define TSIO0_CTS_DISABLE 0x0400 248 #define TSIO0_INSERT_CTS_IN_TX 0x0800 249 #define TSIO0_INSERT_EVEN_KEY_IN_TX 0x1000 250 #define TSIO0_INSERT_LE_EN_IN_TX 0x2000 251 #define TSIO0_TURN_OFF_MCM_TSIO 0x4000 252 #define TSIO0_BYOASS_TSIOTX_FIFO 0x8000 253 254 REG16_TSIO TX_STATUS; //02 255 256 REG16_TSIO ECO0; //03 257 258 REG16_TSIO ECO1; //04 259 260 REG16_TSIO CKG_TSP_TSIO; //05 261 #define TSIO0_CKG_TSP_TSIO 0x0001 262 263 REG16_TSIO TX_SOC_DEFINE_VAL[4]; //06~09 264 265 REG16_TSIO TX_CONFIG1; //0a 266 #define TSIO0_STUFF_WHEN_LOSE_LOCK_EN 0x0001 267 268 REG16_TSIO RESERVED_0B_0F[5]; //0b~0f 269 270 //C&C: h10~h3f 271 REG16_TSIO TX_CC_CNTRL; //10 272 #define TSIO0_TX_CC_INT_EN 0x0002 273 #define TSIO0_TX_CC_CLR 0x0004 274 #define TSIO0_TX_CC_INT_CLR 0x0008 275 #define TSIO0_TX_CC_START 0x8000 276 277 REG16_TSIO TX_CC_CNTRL2; //11 278 #define TSIO0_TX_ACPU_ST 0x0001 279 #define TSIO0_TX_ACPU_RW 0x0002 280 #define TSIO0_TX_ACPU_CONT 0x0004 281 #define TSIO0_TX_ACPU_ADDR_MASK 0xFF00 282 #define TSIO0_TX_ACPU_ADDR_SHIFT 8 283 284 REG32_TSIO TX_CC_WDATA; //12~13 285 286 REG16_TSIO TX_CC_SIZE; //14 287 #define TSIO0_CC_SIZE_MASK 0x01FF 288 #define TSIO0_CC_SIZE_SHIFT 0 289 290 REG16_TSIO RESERVED_15_17[3]; //15~17 291 292 REG16_TSIO TX_CC_STATUS; //18 293 #define TSIO0_TX_CC_STATUS_TX_ACPU_ADDR_MASK 0x00FF 294 #define TSIO0_TX_CC_STATUS_TX_ACPU_ADDR_SHIFT 0 295 #define TSIO0_TX_CC_STATUS_TX_CC_DONE 0x0100 296 #define TSIO0_TX_CC_STATUS_INT_TX_CC 0x8000 297 298 REG32_TSIO TX_CC_RDATA; //19~1a 299 300 REG16_TSIO RESERVED_1B_1F[5]; //1b~1f 301 302 REG16_TSIO RX_CC_CNTRL; //20 303 #define TSIO0_RX_CC_INT_EN 0x0002 304 #define TSIO0_RX_CC_CLR 0x0004 305 #define TSIO0_RX_CC_INT_CLR 0x0008 306 #define TSIO0_RX_ERR_INT_EN_MASK 0x0FF0 307 #define TSIO0_RX_ERR_INT_EN_SHIFT 4 308 #define TSIO0_RX_CC_RECEIVE_EN 0x8000 309 310 REG16_TSIO RX_CC_CNTRL2; //21 311 #define TSIO0_RX_ACPU_ST 0x0001 312 #define TSIO0_RX_ACPU_RW 0x0002 313 #define TSIO0_RX_ACPU_CONT 0x0004 314 #define TSIO0_RX_ACPU_ADDR_MASK 0x0FF0 315 #define TSIO0_RX_ACPU_ADDR_SHIFT 4 316 #define TSIO0_RX_ACPU_ADDR_CONT_TRI 0x8000 317 318 REG16_TSIO RESERVED_22_27[6]; //22~27 319 320 REG16_TSIO RX_CC_STATUS; //28 321 #define TSIO0_RX_CC_DONE 0x0001 322 #define TSIO0_FLAG_MID_IN_IDLE 0x0010 323 #define TSIO0_FLAG_LAST_IN_IDLE 0x0020 324 #define TSIO0_FLAG_FIRST_IN_MID 0x0040 325 #define TSIO0_RX_CC_PROTOCOL 0x0100 326 #define TSIO0_RX_CC_MISSED 0x0200 327 #define TSIO0_RX_CC_OVERFLOW 0x0400 328 #define TSIO0_ERR_FLAG_MASK 0x0770 329 #define TSIO0_INT_RX_CC 0x1000 330 331 REG32_TSIO RX_CC_RDATA; //29~2a 332 333 REG16_TSIO RX_CC_SIZE; //2b 334 #define TSIO0_RX_CC_SIZE_MASK 0x01FF 335 #define TSIO0_RX_CC_SIZE_SHIFT 0 336 337 REG16_TSIO RESERVED_2C_3F[20]; //2c~3f 338 339 //Power up handler: h40~h5f 340 REG16_TSIO PUH_CONFIG0; //40 341 342 REG16_TSIO PUH_CONFIG1; //41 343 #define TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT 0x0010 344 #define TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_LOW 0x0020 345 #define TSIO0_PUH_CONFIG1_TSIO_RX_DATA_VALID_SET_HIGH 0x0040 346 347 REG16_TSIO MIN_PERIOD_OF_IDLE; //42 348 349 REG16_TSIO MAX_PERIOD_OF_IDLE; //43 350 351 REG16_TSIO MIN_PERIOD_OF_RST_PWR; //44 352 353 REG16_TSIO MAX_PERIOD_OF_RST_PWR; //45 354 355 REG16_TSIO MIN_PERIOD_OF_RST_CLK_PRE; //46 356 357 REG16_TSIO MAX_PERIOD_OF_RST_CLK_PRE; //47 358 359 REG16_TSIO MIN_PERIOD_OF_RST_CLK; //48 360 361 REG16_TSIO MAX_PERIOD_OF_RST_CLK; //49 362 363 REG16_TSIO RESERVED_4A_4F[6]; //4a~4f 364 365 REG16_TSIO MIN_PERIOD_OF_SC_TRAINING; //50 366 367 REG16_TSIO MAX_PERIOD_OF_SC_TRAINING; //51 368 369 REG16_TSIO MIN_PERIOD_OF_SOC_TRAINING; //52 370 371 REG16_TSIO MAX_PERIOD_OF_SOC_TRAINING; //53 372 373 REG16_TSIO MIN_PERIOD_OF_PKT_SYNC; //54 374 375 REG16_TSIO MAX_PERIOD_OF_PKT_SYNC; //55 376 377 REG16_TSIO RETRY_THRESHOLD; //56 378 379 REG16_TSIO DELAY_CNT_SMALL; //57 380 381 REG16_TSIO DELAY_CNT_MID; //58 382 383 REG16_TSIO PUH_STATUS0; //59 384 #define TSIO0_PUH_STATUS0_OC_FLAG_TX_CH0 0x0001 385 #define TSIO0_PUH_STATUS0_OC_FLAG_TX_CH1 0x0002 386 #define TSIO0_PUH_STATUS0_NO_SUPPORT 0x0004 387 #define TSIO0_PUH_STATUS0_PKT_SYNC_TIMEOUT 0x0008 388 #define TSIO0_PUH_STATUS0_POWER_STATUS_MASK 0x00F0 389 #define TSIO0_PUH_STATUS0_POWER_STATUS_SHIFT 4 390 #define TSIO0_PUH_STATUS0_RETRY_TIMES 0x0100 391 #define TSIO0_PUH_STATUS0_OPERATION 0x0200 392 #define TSIO0_PUH_STATUS0_POWER_OFF 0x0400 393 #define TSIO0_PUH_STATUS0_POWER_ON 0x0800 394 395 REG16_TSIO PUH_CONFIG2; //5a 396 #define TSIO0_PUH_CONFIG2_OC_FLAG_TX_CH0_INT_CLR 0x0001 397 #define TSIO0_PUH_CONFIG2_OC_FLAG_TX_CH0_INT_EN 0x0002 398 #define TSIO0_PUH_CONFIG2_OC_FLAG_TX_CH1_INT_CLR 0x0004 399 #define TSIO0_PUH_CONFIG2_OC_FLAG_TX_CH1_INT_EN 0x0008 400 #define TSIO0_PUH_CONFIG2_NO_SUPPORT_CLR 0x0010 401 #define TSIO0_PUH_CONFIG2_NO_SUPPORT_EN 0x0020 402 #define TSIO0_PUH_CONFIG2_PKT_SYNC_TIMEOUT_CLR 0x0040 403 #define TSIO0_PUH_CONFIG2_PKT_SYNC_TIMEOUT_EN 0x0080 404 #define TSIO0_PUH_CONFIG2_RETRY_TIMES_CLR 0x0100 405 #define TSIO0_PUH_CONFIG2_RETRY_TIMES_EN 0x0200 406 #define TSIO0_PUH_CONFIG2_OPERATION_START_CLR 0x0400 407 #define TSIO0_PUH_CONFIG2_OPERATION_START_EN 0x0800 408 #define TSIO0_PUH_CONFIG2_POWER_OFF_CLR 0x1000 409 #define TSIO0_PUH_CONFIG2_POWER_OFF_EN 0x2000 410 #define TSIO0_PUH_CONFIG2_POWER_ON_CLR 0x4000 411 #define TSIO0_PUH_CONFIG2_POWER_ON_EN 0x8000 412 413 REG16_TSIO RESERVED_5B_5F[5]; //5b~5f 414 415 //AD_IF:h60~h6b 416 REG16_TSIO AD_TX_CONFIG0; //60 417 #define TSIO0_TX_DATA_PN_SWAP 0x0001 418 #define TSIO0_CLK_PN_SWAP 0x0002 419 #define TSIO0_CH_SWAP 0x0004 420 #define TSIO0_TX_BIG_ENDIAN 0x0008 421 #define TSIO0_TX2ATOP_STATUS_CLR 0x0010 422 #define TSIO0_BYPASS_AD_OUT_FIFO 0x0020 423 #define TSIO0_PRBS_TX_TSIO 0x0040 424 #define TSIO0_PBRS_TX_ATOP 0x0080 425 #define TSIO0_PD_SMC_LDO_FPGA 0x0100 426 #define TSIO0_TX_BYTE_SWAP 0x0200 427 428 REG16_TSIO AD_RX_CONFIG0; //61 429 430 REG16_TSIO AD_TX_ST; //62 431 432 REG16_TSIO PRBS_CONFIG0; //63 433 434 REG16_TSIO DP_PHY_PRBS_ERRCNT; //64 435 436 REG16_TSIO PRBS_CONFIG1; //65 437 438 REG16_TSIO RESERVED_66_6B[6]; //66~6b 439 440 //test mode:h6c~6f 441 REG16_TSIO PUH_TEST_CONFIG; //6c 442 443 REG16_TSIO BTRAIN_TEST_CONFIG0; //6d 444 445 REG16_TSIO BTRAIN_TEST_CONFIG1; //6e 446 447 REG16_TSIO BTRAIN_TEST_CONFIG2; //6f 448 449 //bit training status: h70~h7f 450 REG16_TSIO PH_INFO_0; //70 451 452 REG16_TSIO PH_INFO_1; //71 453 454 REG16_TSIO PH_INFO_2; //72 455 #define TSIO0_PH_INFO_2_REG_PHASE_MASK 0x003F 456 #define TSIO0_PH_INFO_2_REG_PHASE_SHIFT 0 457 458 REG16_TSIO EL_INFO[3]; //73~75 459 460 REG16_TSIO CH_INFO; //76 461 462 REG16_TSIO ATOP_IN; //77 463 464 REG16_TSIO FT_STATUS; //78 465 466 REG16_TSIO BTRAIN_ST_0; //79 467 #define TSIO0_BTRAIN_ST_0_SW_MODE_DONE 0x0001 468 #define TSIO0_BTRAIN_ST_0_SW_MODE_DONE_CH 0x0002 469 #define TSIO0_BTRAIN_ST_0_SW_REMAP_MODE 0x0004 470 #define TSIO0_BTRAIN_ST_0_CHG_PH_START_REMAP 0x0008 471 #define TSIO0_BTRAIN_ST_0_CHG_PH_START_REMAP_SHIFT 3 472 473 REG16_TSIO RESERVED_7A_7F[6]; //7a~7f 474 } REG_Ctrl_TSIO0; 475 476 //TSIO1 477 typedef struct _REG_Ctrl_TSIO1 478 { 479 REG16_TSIO SVID_SRCID[64]; //00~3f 480 #define TSIO1_SOURCE_ID_MASK 0x00FF 481 #define TSIO1_SOURCE_ID_SHIFT 0 482 #define TSIO1_SERVICE_ID_MASK 0x3F00 483 #define TSIO1_SERVICE_ID_SHIFT 8 484 #define TSIO1_ENABLE 0x8000 485 486 REG16_TSIO SVID_INFO[8]; //40~47 487 #define TSIO1_LIVE_0_ENABLE 0x0001 488 #define TSIO1_LIVE_1_ENABLE 0x0004 489 #define TSIO1_LIVE_2_ENABLE 0x0010 490 #define TSIO1_LIVE_3_ENABLE 0x0040 491 #define TSIO1_LIVE_4_ENABLE 0x0100 492 #define TSIO1_LIVE_5_ENABLE 0x0400 493 #define TSIO1_LIVE_6_ENABLE 0x1000 494 #define TSIO1_LIVE_7_ENABLE 0x4000 495 496 REG16_TSIO RESERVED_48_4F[8]; //48~4f 497 498 REG16_TSIO RX_CONFIG0; //50 499 #define TSIO1_DECRYPT_DISABLE 0x0001 500 #define TSIO1_SECURE_FLAG_DBG 0x0002 501 #define TSIO1_BIT_TRAINING_BYPASS 0x0004 502 #define TSIO1_TX_DIRECT_RX_16 0x0008 503 #define TSIO1_STUFF_RM_CLR 0x0010 504 #define TSIO1_BYPASS_TSIORX_FIFO 0x0080 505 #define TSIO1_BEST_PH_OFFSET_MASK 0x0700 506 #define TSIO1_BEST_PH_OFFSET_SHIFT 8 507 #define TSIO1_BEST_PH_ADD 0x0800 508 #define TSIO1_BEST_PH_MINUS 0x1000 509 #define TSIO1_MAX_CDR_CNT_MASK 0xE000 510 #define TSIO1_MAX_CDR_CNT_SHIFT 13 511 512 REG16_TSIO PKT_SYNC_CTRL; //51 513 #define TSIO1_PKT_SYNC_EN 0x0001 514 #define TSIO1_PKT_SYNC_CLR 0x0010 515 516 REG16_TSIO MATCH_PATTERN; //52 517 #define TSIO1_MATCH_PATTERN_MASK 0x00FF 518 #define TSIO1_MATCH_PATTERN_SHIFT 0 519 520 REG16_TSIO TSIO_SYNC_THRESHOLD; //53 521 #define TSIO1_TSIO_N_SYNC_MASK 0x000F 522 #define TSIO1_TSIO_N_SYNC_SHIFT 0 523 #define TSIO1_TSIO_SYNC_CNT_MASK 0x00F0 524 #define TSIO1_TSIO_SYNC_CNT_SHIFT 4 525 526 REG32_TSIO MISSED_NUMOFBYTES; //54~55 527 528 REG16_TSIO PKT_SYNC_STATUS; //56 529 #define TSIO1_ANAFIFO_OVERFLOW 0x0001 530 #define TSIO1_MISSED_MUCH_FLAG 0x0002 531 #define TSIO1_EVER_LOSE_LOCK 0x0004 532 #define TSIO1_PKT_SYNC_RX_DONE 0x0080 533 #define TSIO1_STUFF_RM_OVERFLOW 0x8000 534 535 REG32_TSIO TSIO_BIST_FAIL; //57~58 536 537 REG16_TSIO LOSE_LOCK_CNT; //59 538 539 REG16_TSIO RX_SOC_DEFINE_VAL[4]; //5a~5d 540 541 REG16_TSIO RXANA_TO_PVR; //5e 542 #define TSIO1_RXANA_TO_PVR_EN 0x0001 543 #define TSIO1_RXANA_WINDOW_INDEX_MASK 0x00F0 544 #define TSIO1_RXANA_WINDOW_INDEX_SHIFT 4 545 546 REG16_TSIO RESERVED_5F; //5f 547 548 //bit training: h60~h70 549 REG16_TSIO CHECK_PH_TIME; //60 550 551 REG16_TSIO CHG_PH_STABLE_TIME; //61 552 #define TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_MASK 0x0F00 553 #define TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_SHIFT 8 554 #define TSIO1_CHG_PH_STABLE_TIME_GUARD_PH_LOAD 0x1000 555 556 REG32_TSIO DYN_ADJ_TIMER_PERIOD; //62~63 557 558 REG16_TSIO BTRAIN_CONFIG0; //64 559 #define TSIO1_SW_JUMP_PH_CH 0x4000 560 561 REG16_TSIO BTRAIN_CONFIG1; //65 562 563 REG16_TSIO BTRAIN_CONFIG2; //66 564 565 REG16_TSIO BTRAIN_CONFIG3; //67 566 #define TSIO1_SW_PH_CHNAGE 0x0001 567 #define TSIO1_SW_PH_INCR 0x0002 568 #define TSIO1_SW_PH_DECR 0x0004 569 #define TSIO1_SW_PH_STEP_MODE 0x0008 570 #define TSIO1_SW_CH_PH_REMAP 0x0010 571 #define TSIO1_SW_REMAP_WHEN_STUCK 0x0020 572 #define TSIO1_SW_EARLY 0x0040 573 #define TSIO1_SW_LATE 0x0080 574 #define TSIO1_SW_CHG_PH_DONE 0x0100 575 #define TSIO1_BTRAIN_INT_CLR 0x0200 576 #define TSIO1_DONE_EVER_CLR 0x0400 577 #define TSIO1_CHANNEL_SEL_MASK 0x1800 578 #define TSIO1_CHANNEL_SEL_SHIFT 11 579 #define TSIO1_EL_INFO_SEL 0x2000 580 #define TSIO1_PH_INFO_SEL 0x4000 581 #define TSIO1_DEBUG_REG_LOAD 0x8000 582 583 REG16_TSIO BTRAIN_INT_EN; //68 584 #define TSIO1_BTRAIN_INT_EN 0x0001 585 586 REG16_TSIO BTRAIN_INT_STATUS; //69 587 #define TSIO1_GUARD_REACH_MIN 0x0001 588 589 REG32_TSIO MAX_DYN_CDR_EL_TIMER; //6a~6b 590 591 REG16_TSIO DYN_CDR_EL_CNT; //6c 592 593 REG16_TSIO BTRAIN_CONFIG4; //6d 594 #define TSIO1_BTRAIN_CONFIG4_SW_MODE_CH_READ_ST_DIS 0x0001 595 #define TSIO1_BTRAIN_CONFIG4_DISABLE_BITTRAIN 0x0020 596 597 REG16_TSIO FT_PRBS_TIMEOUT; //6e 598 599 REG16_TSIO BTRAIN_CONFIG5; //6f 600 #define TSIO1_BTRAIN_CONFIG5_MAX_EYE_REGION_MASK 0x003F 601 #define TSIO1_BTRAIN_CONFIG5_MAX_EYE_REGION_SHIFT 0 602 603 //unpack : h70 604 REG16_TSIO UNPACK_CTRL; //70 605 #define TSIO1_BYPASS_ERRPKT_TSBLK_LIVEDMA 0x0001 606 #define TSIO1_BYPASS_ERRPKT_WITHOUT_SERVICEID 0x0002 607 #define TSIO1_BYPASS_ERRPKT_DMAEND 0x0004 608 #define TSIO1_DMAEND_DISABLE 0x0010 609 #define TSIO1_CLR_ALL_ERR_FLAG 0x0080 610 #define TSIO1_UNPACK_CTS_DISABLE 0x0100 611 612 REG32_TSIO UNPACK_STATUS; //71~72 613 614 REG16_TSIO UNDECLARE_SVID[4]; //73~76 615 616 REG16_TSIO TSIORX_INT_EN; //77 617 618 REG16_TSIO DESYNC_CTRL; //78 619 620 REG16_TSIO RESERVED_79_7A[2]; //79~7a 621 622 REG32_TSIO TSIO_INT_STATUS; //7b~7c 623 624 REG32_TSIO TSIO_DEBUG; //7d~7e 625 #define D45_PH_INCR 0x00800000 626 #define D45_PH_DECR 0x00400000 627 #define D45_GUARD_PH_SMALL 0x00080000 628 #define D45_GUARD_PH_LARGE 0x00040000 629 630 REG16_TSIO TSIO_DBG_SEL; //7f 631 632 } REG_Ctrl_TSIO1; 633 634 //TSIO2 635 typedef struct _REG_Ctrl_TSIO2 636 { 637 REG16_TSIO TSIO_PVR_CONFIG; //00 638 #define TSIO2_PVR_STR2MI_EN 0x0001 639 #define TSIO2_PVR_STR2MI_RST_WADR 0x0002 640 #define TSIO2_PVR_STR2MI_PAUSE 0x0004 641 #define TSIO2_PVR_BURST_LEN_MASK 0x0018 642 #define TSIO2_PVR_BURST_LEN_SHIFT 3 643 #define TSIO2_PVR_SRAM_AD_EN 0x0020 644 #define TSIO2_PVR_STR2MI_WP_LD 0x0040 645 #define TSIO2_PVR_CLR 0x0080 646 #define TSIO2_PVR_DMA_FLUSH_EN 0x0100 647 #define TSIO2_PVR_MIU_HIGHPRI 0x0200 648 #define TSIO2_PVR_WRITE_POINTER_TO_NEXT_ADDR_EN 0x0400 649 #define TSIO2_PVR_DMAW_PROTECT_EN 0x0800 650 #define TSIO2_PVR_CLR_NO_HIT_INT 0x1000 651 #define TSIO2_FLUSH_DATA_TSIO_PVR_STATUS 0x2000 652 653 REG32_TSIO TSIO_PVR_DMAW_WADDR_ERR; //01~02 654 655 REG16_TSIO RESERVED_03; //03 656 657 REG32_TSIO TSIO_PVR_STR2MI_WADR_R; //04~05 658 659 REG16_TSIO TSIO_PVR_FIFO_STATUS; //06 660 661 REG32_TSIO TSIO_PVR_DMAW_LBND; //07~08 662 663 REG32_TSIO TSIO_PVR_DMAW_UBND; //09~0a 664 665 REG16_TSIO TSIO_PVR2MI_SEL; //0b 666 667 REG16_TSIO RESERVED_0C_1F[20]; //0c~1f 668 669 REG16_TSIO PVR_CTRL; //20 670 671 REG16_TSIO PVR_CTRL_STATUS; //21 672 673 REG16_TSIO RESERVED_22; //22 674 675 REG16_TSIO SW_RST_SG_TSIO; //23 676 #define TSIO2_SW_RST_SG_TSIO_ROUNDROBIN 0x0200 677 #define TSIO2_SW_RST_SG_TSIO_SG_FSM 0x0400 678 #define TSIO2_SW_RST_SG_TSIO_VC_TABLE 0x0800 679 #define TSIO2_SW_RST_SG_TSIO_VCDMA_READ_MIU 0x1000 680 #define TSIO2_SW_RST_SG_TSIO_VC_FSM 0x2000 681 682 REG16_TSIO RESERVED_24_3D[26]; //24~3d 683 684 REG32_TSIO SGDMAOUT_DBG; //3e~3f 685 #define TSIO2_SGDMAOUT_DBG_MASK 0x00FFFFFF 686 #define TSIO2_SGDMAOUT_DBG_SHIFT 0 687 #define TSIO2_SGDMAOUT_DBG_SEL_MASK 0xFF000000 688 #define TSIO2_SGDMAOUT_DBG_SEL_SHIFT 24 689 690 REG16_TSIO VCFSM_START; //40 691 #define TSIO2_VCFSM_START 0x0001 692 693 REG16_TSIO ACPU_ACTIVE; //41 694 #define TSIO2_ACPU_ACTIVE 0x0001 695 696 REG16_TSIO ACPU_CMD; //42 697 #define TSIO2_ACPU_CMD_VC_ID_MASK 0x003F 698 #define TSIO2_ACPU_CMD_VC_ID_SHIFT 0 699 #define TSIO2_ACPU_CMD_RD_POSITION_MASK 0x01C0 700 #define TSIO2_ACPU_CMD_RD_POSITION_SHIFT 6 701 #define TSIO2_ACPU_CMD_CLR 0x0200 702 #define TSIO2_ACPU_CMD_RW 0x0400 703 #define TSIO2_ACPU_CMD_ACTIVE 0x0800 704 #define TSIO2_ACPU_CMD_RD_ADDR_LSB 0x1000 705 706 REG32_TSIO ACPU_WDATA; //43~44 707 708 REG16_TSIO ACPU_FLAG; //45 709 #define TSIO2_ACPU_FLAG_INTERRUPT_ENABLE 0x0010 710 #define TSIO2_ACPU_FLAG_MOBF_MASK 0x03E0 711 #define TSIO2_ACPU_FLAG_MOBF_SHIFT 5 712 #define TSIO2_ACPU_FLAG_SECURE_FLAG 0x0400 713 #define TSIO2_ACPU_FLAG_DMA_END_MASK 0x0800 714 #define TSIO2_ACPU_FLAG_DMA_END_CONTINUE_DMA 0x1000 715 716 REG32_TSIO ACPU_RDATA; //46~47 717 718 REG16_TSIO SGDMA_OUT_CTRL; //48 719 #define TSIO2_SGDMA_OUT_INT_CLR 0x0001 720 #define TSIO2_SGDMA_OUT_PAUSE 0x0002 721 #define TSIO2_SGDMA_OUT_DBG_SEL_MASK 0x00FC 722 #define TSIO2_SGDMA_OUT_DBG_SEL_SHIFT 2 723 #define TSIO2_SGDMA_OUT_INT_MASK 0x0100 724 #define TSIO2_VCDMA_MIU_PRIORITY 0x0200 725 #define TSIO2_SGDMA_OUT_VC_INT_TRIGGER 0x0400 726 727 REG16_TSIO SGDMA_OUT_DBG; //49 728 729 REG16_TSIO SGDMA_OUT_VC_INT[4]; //4a~4d 730 731 REG16_TSIO SGDMA_OUT_INFO; //4e 732 #define TSIO2_SGDMA_OUT_VC_INT_VC_ID_MASK 0x003F 733 #define TSIO2_SGDMA_OUT_VC_INT_VC_ID_SHIFT 0 734 #define TSIO2_SGDMA_OUT_VC_INT_CLR 0x0040 735 #define TSIO2_SGDMA_OUT_VC_INT_MASK 0x0080 736 #define TSIO2_PACE_DBG_VCID_MASK 0x3F00 737 #define TSIO2_PACE_DBG_VCID_SHIFT 8 738 #define TSIO2_PACE_DBG_CLR 0x4000 739 #define TSIO2_PACE_DBG_EN 0x8000 740 741 REG16_TSIO RESERVED_4F; //4f 742 743 REG16_TSIO SGDMA_OUT_VC_STATUS_SEL; //50 744 #define TSIO2_SGDMA_OUT_VC_STATUS_SEL_MASK 0x00FC 745 #define TSIO2_SGDMA_OUT_VC_STATUS_SEL_SHIFT 2 746 747 REG16_TSIO SGDMA_OUT_VC_STATUS; //51 748 #define TSIO2_SGDMA_OUT_VC_STATUS_LASTNODE 0x0200 749 #define TSIO2_SGDMA_OUT_VC_STATUS_NODEINT 0x0400 750 #define TSIO2_SGDMA_OUT_VC_STATUS_DROP 0x0800 751 #define TSIO2_SGDMA_OUT_VC_STATUS_DMAEND 0x1000 752 753 REG16_TSIO SGDMA_OUT_CONFIG0; //52 754 755 REG16_TSIO SGDMA_OUT_CONFIG1; //53 756 757 REG16_TSIO RESERVED_54_5F[12]; //54~5f 758 759 REG32_TSIO TSIO_PVR_STR2MI_HEAD_DEBUG; //60~61 760 761 REG32_TSIO TSIO_PVR_STR2MI_TAIL_DEBUG; //62~63 762 763 REG16_TSIO TSIO_RXANA_TO_PVR_DEBUG; //64 764 #define TSIO2_TSIO_RXANA_TO_PVR_DEBG 0x0001 765 766 REG16_TSIO RESERVED_65_7F[27]; //65~7f 767 } REG_Ctrl_TSIO2; 768 769 //TSIO3 770 typedef struct _REG_Ctrl_TSIO3 771 { 772 REG32_TSIO TSIO_FILTER[32]; //00~3f 773 #define TSIO3_FILTER_ENABLE 0x00000001 774 #define TSIO3_FILTER_SERVICE_ID_MASK 0x0000007E 775 #define TSIO3_FILTER_SERVICE_ID_SHIFT 1 776 #define TSIO3_FILTER_PID_MASK 0x000FFF10 777 #define TSIO3_FILTER_PID_SHIFT 7 778 #define TSIO3_FILTER_USE_SERVICE_ID_IN_FILTERING 0x00100000 779 #define TSIO3_FILTER_USE_PID_IN_FILTERING 0x00200000 780 #define TSIO3_FILTER_DATA_TO_SM 0x00400000 781 #define TSIO3_FILTER_DATA_TO_TSIO_RX 0x00800000 782 783 REG16_TSIO TSIO_WHITE_LIST; //40 784 #define TSIO3_WHITE_LIST_SM_ENABLE 0x0001 785 #define TSIO3_WHITE_LIST_RX_ENABLE 0x0002 786 787 REG16_TSIO TSIO3_CONFIG0; //41 788 #define TSIO3_BULK_ALWAYS_TO_SM 0x0001 789 790 791 REG16_TSIO TSIO_PKT_MERGE_CONFIG; //42 792 #define TSIO3_NO_NEED_MERGE_BYPASS_SM 0x0001 793 #define TSIO3_CLR_PKT_LENGTH_FLAG 0x0020 794 795 REG16_TSIO TSIO_PKT_LENGTH; //43 796 #define TSIO3_PKT_LENGTH_MORE_212 0x0001 797 #define TSIO3_PKT_LENGTH_LESS_212 0x0002 798 799 REG16_TSIO TSIO_ONEWAY_MERGE; //44 800 #define TSIO3_TSIO_ONE_WAY_MERGRE 0x0001 801 802 REG16_TSIO TSIO_BYPASS_MERGE_DISABLE; //45 803 #define TSIO3_BYPASS_MERGE_DIABLE 0x0001 804 805 REG16_TSIO TSIO_SVID_BYPASS_SMC_EN[4]; //46~49 806 807 REG16_TSIO RESERVED_4A_7F[54]; //4A~7f 808 } REG_Ctrl_TSIO3; 809 810 //TSIO_LOCDEC 811 typedef struct _REG_Ctrl_TSIO_LOCDEC 812 { 813 REG16_TSIO SW_KEY[8]; //00~07 814 815 REG32_TSIO SW_KEY_PROPERTY; //08~09 816 817 REG16_TSIO CMD; //0a 818 #define TSIO_LOCDEC_CMD_SERVICE_ID_MASK 0x003F 819 #define TSIO_LOCDEC_CMD_SERVICE_ID_SHIFT 0 820 #define TSIO_LOCDEC_CMD_KEY_SEL 0x0100 821 #define TSIO_LOCDEC_CMD_CMD 0x0200 822 #define TSIO_LOCDEC_CMD_CMD_FPGA 0x0400 823 824 REG16_TSIO KT_GO; //0b 825 #define TSIO_LOCDEC_KT_GO 0x0001 826 827 REG16_TSIO KT_DONE; //0c 828 #define TSIO_LOCDEC_KT_DONE 0x0001 829 830 REG16_TSIO SCBFIXRULE; //0d 831 #define TSIO_LOCDEC_SCBFIXRULE 0x0001 832 833 REG16_TSIO XIU; //0e 834 #define TSIO_LOCDEC_XIU_ID_MASK 0x000F 835 #define TSIO_LOCDEC_XIU_ID_SHIFT 0 836 #define TSIO_LOCDEC_XIU_NS 0x0010 837 838 REG16_TSIO SECURE; //0f 839 #define TSIO_LOCDEC_TO_SECURE 0x0001 840 #define TSIO_LOCDEC_WRITE_SECURE_FORBID 0x0010 841 842 REG16_TSIO BYPASS_STATUS; //10 843 #define TSIO_LOCDEC_BPSTATUS_KEY_ENABLE_BIT 0x0001 844 #define TSIO_LOCDEC_BPSTATUS_EVEN_KEY_VLD 0x0002 845 #define TSIO_LOCDEC_BPSTATUS_EVEN_KEY_DECRYPT 0x0004 846 #define TSIO_LOCDEC_BPSTATUS_EVEN_KEY_ENTROPY 0x0008 847 #define TSIO_LOCDEC_BPSTATUS_EVEN_KEY_USAGE 0x0010 848 #define TSIO_LOCDEC_BPSTATUS_ODD_KEY_VLD 0x0020 849 #define TSIO_LOCDEC_BPSTATUS_ODD_KEY_DECRYPT 0x0040 850 #define TSIO_LOCDEC_BPSTATUS_ODD_KEY_ENTROPY 0x0080 851 #define TSIO_LOCDEC_BPSTATUS_ODD_KEY_USAGE 0x0100 852 #define TSIO_LOCDEC_BPSTATUS_AF_ONLY 0x0200 853 #define TSIO_LOCDEC_BPSTATUS_AF_LENGTH 0x0400 854 #define TSIO_LOCDEC_BPSTATUS_TS_MODE 0x0800 855 #define TSIO_LOCDEC_BPSTATUS_BULK_MODE 0x1000 856 #define TSIO_LOCDEC_BPSTATUS_BYPASS_EN 0x2000 857 #define TSIO_LOCDEC_BPSTATUS_BYPASS_VLD 0x8000 858 859 REG32_TSIO SCPU_CTRL; //11~12 860 861 REG16_TSIO RESERVED_13; //13 862 863 REG16_TSIO KEY_ENABLE_BIT[4]; //14~17 864 865 REG16_TSIO ODD_KEY_VLD[4]; //18~1b 866 867 REG16_TSIO EVEN_KEY_VLD[4]; //1c~1f 868 869 REG32_TSIO CHK_BANK_VERSION; //20~21 870 871 REG16_TSIO FORCESCB_BIT[4]; //22~25 872 873 REG16_TSIO RESERVED_26_2F[10]; //26~2f 874 875 REG16_TSIO DEBUG; //30 876 #define TSIO_LOCDEC_DEBUG_ID_MASK 0x003F 877 #define TSIO_LOCDEC_DEBUG_ID_SHIFT 0 878 #define TSIO_LOCDEC_DEBUG_CLR 0x0080 879 #define TSIO_LOCDEC_PKT_CNT_CLR 0x0100 880 #define TSIO_LOCDEC_BYPASS_CLR 0x0200 881 882 REG16_TSIO KT_ERROR; //31 883 #define TSIO_LOCDEC_KT_ERROR_NO_ENABLE 0x0001 884 #define TSIO_LOCDEC_KT_ERROR_NO_KEY 0x0002 885 #define TSIO_LOCDEC_KT_ERROR_ERR_ALGO 0x0010 886 #define TSIO_LOCDEC_KT_ERROR_ERR_ENTROPY 0x0020 887 #define TSIO_LOCDEC_KT_ERROR_ERR_ENCDEC 0x0040 888 889 REG16_TSIO KT_WARNING; //32 890 #define TSIO_LOCDEC_KT_WARNING_ERR_SYNC 0x0001 891 #define TSIO_LOCDEC_KT_WARNING_NONE_212 0x0002 892 893 REG16_TSIO RESERVED_33_37[5]; //33~37 894 895 REG16_TSIO PKT_CNT; //38 896 #define TSIO_LOCDEC_DEC_PKT_CNT_MASK 0x00FF 897 #define TSIO_LOCDEC_DEC_PKT_CNT_SHIFT 0 898 #define TSIO_LOCDEC_CLR_PKT_CNT_MASK 0xFF00 899 #define TSIO_LOCDEC_CLR_PKT_CNT_SHIFT 8 900 901 REG16_TSIO INPUT_PKT_CNT; //39 902 #define TSIO_LOCDEC_INPUT_PKT_CNT_MASK 0x00FF 903 #define TSIO_LOCDEC_INPUT_PKT_CNT_SHIFT 0 904 905 REG16_TSIO RESERVED_3A_3F[6]; //3a~3f 906 907 REG16_TSIO NO_EN_IRQ_EN[4]; //40~43 908 909 REG16_TSIO ERROR_IRQ_EN[4]; //44~47 910 911 REG16_TSIO RESERVED_48_4F[8]; //48~4f 912 913 REG16_TSIO NO_EN_IRQ_STA[4]; //50~53 914 915 REG16_TSIO ERROR_IRQ_STA[4]; //54~57 916 917 REG16_TSIO WARNING_STA[4]; //58~5b 918 919 REG16_TSIO RESERVED_5C_5F[4]; //5c~5f 920 921 REG16_TSIO FPGA_READ[8]; //60~67 922 923 REG16_TSIO SLOT_SECURE[4]; //68~6b 924 925 REG16_TSIO SLOT_PRIVILEGE[4]; //6c~6f 926 927 REG16_TSIO RESERVED_70_7F[16]; //70~7f 928 } REG_Ctrl_TSIO_LOCDEC; 929 930 typedef struct _REG_Ctrl_TSIO_PHY 931 { 932 REG16_TSIO TSIO_PHY_00; //0x00 933 #define TSIO_PHY_00_EN_RX_TERM 0x0001 934 #define TSIO_PHY_00_EN_TX_SKEWCLK 0x0002 935 #define TSIO_PHY_00_GCR_CKEN_RX 0x0004 936 #define TSIO_PHY_00_GCR_CKEN_RX_GUARD 0x0008 937 #define TSIO_PHY_00_GCR_CKEN_TX 0x0010 938 #define TSIO_PHY_00_EN_REG 0x0020 939 #define TSIO_PHY_00_EN_TX_SKEW 0x0040 940 #define TSIO_PHY_00_REG_REF_SEL 0x0080 941 #define TSIO_PHY_00_TX_CAL_EN 0x0100 942 #define TSIO_PHY_00_TX_CAL_SRC 0x0200 943 #define TSIO_PHY_00_PDN_TSIO_RX_PREAMP 0x0400 944 #define TSIO_PHY_00_PDN_TSIO_RX_TED 0x0800 945 #define TSIO_PHY_00_PD_IB_TSIO 0x1000 946 #define TSIO_PHY_00_PD_RX_REF 0x2000 947 #define TSIO_PHY_00_PD_TX_OCP 0x4000 948 #define TSIO_PHY_00_START_RX_CAL 0x8000 949 950 REG16_TSIO TSIO_PHY_01; //0x01 951 952 REG16_TSIO TSIO_PHY_02; //0x02 953 #define TSIO_PHY_02_TEST_REG_MASK 0x0300 954 #define TSIO_PHY_02_TEST_REG_SHIFT 8 955 956 REG16_TSIO TSIO_PHY_03; //0x03 957 958 REG16_TSIO RESERVED_04_05[2]; //0x04 ~0x05 959 960 REG16_TSIO TSIO_PHY_06; //0x06 961 #define TSIO_PHY_06_GCR_RX_CA_DA_OV_MASK 0x007F 962 #define TSIO_PHY_06_GCR_RX_CA_DA_OV_SHIFT 0 963 #define TSIO_PHY_06_GCR_RX_CA_DB_OV_MASK 0x7F00 964 #define TSIO_PHY_06_GCR_RX_CA_DB_OV_SHIFT 8 965 966 REG16_TSIO RESERVED_07_0A[4]; //0x07 ~0x0A 967 968 REG16_TSIO TSIO_PHY_0B; //0x0B 969 #define TSIO_PHY_0B_RX_CAL_DATA_A_MASK 0x003F 970 #define TSIO_PHY_0B_RX_CAL_DATA_A_SHIFT 0 971 #define TSIO_PHY_0B_RX_CAL_DATA_B_MASK 0x3F00 972 #define TSIO_PHY_0B_RX_CAL_DATA_B_SHIFT 8 973 #define TSIO_PHY_0B_RX_CAL_END 0x8000 974 #define TSIO_PHY_0B_RX_CAL_END_SHIFT 15 975 976 REG16_TSIO RESERVED_0C_0E[3]; //0x0C ~0x0E 977 978 REG16_TSIO TSIO_PHY_0F; //0x0F 979 #define TSIO_PHY_0F_HW_CAL_BIAS_CON_MASK 0x001F 980 #define TSIO_PHY_0F_HW_CAL_BIAS_CON_SHIFT 0 981 982 REG16_TSIO RESERVED_10_11[2]; //0x10~0x11 983 984 REG16_TSIO TSIO_PHY_12; //0x12 985 986 REG16_TSIO TSIO_PHY_13; //0x13 987 988 REG16_TSIO RESERVED_14_17[4]; //0x14~0x17 989 990 REG16_TSIO TSIO_PHY_18; //0x18 991 #define TSIO_PHY_18_TEST_TSIO_MASK 0x00FF 992 #define TSIO_PHY_18_TEST_TSIO_SHIFT 0 993 994 REG16_TSIO RESERVED_19_1A[2]; //0x19~0x1A 995 996 REG16_TSIO TSIO_PHY_1B; //0x1B 997 998 REG16_TSIO RESERVED_1C_1F[4]; //0x1C~0x1F 999 1000 REG16_TSIO TSIO_PHY_20; //0x20 1001 #define TSIO_PHY_20_LPLL_PD 0x0001 1002 #define TSIO_PHY_20_LPLL_DMY_SKEW2 0x0002 1003 #define TSIO_PHY_20_LPLL_DMY_SKEW3 0x0004 1004 #define TSIO_PHY_20_LPLL_DMY_SKEW4 0x0008 1005 #define TSIO_PHY_20_LPLL_PHDAC_RST 0x0010 1006 #define TSIO_PHY_20_LPLL_PHDAC_SELECT 0x0020 1007 #define TSIO_PHY_20_LPLL_PHDAC_UPDATE 0x0040 1008 #define TSIO_PHY_20_LPLL_DUAL_LP_EN 0x0080 1009 #define TSIO_PHY_20_LPLL_SEL_SKEW1_DELAYlt 0x0100 1010 #define TSIO_PHY_20_LPLL_SEL_SKEW2_DELAYlt 0x0200 1011 #define TSIO_PHY_20_LPLL_SEL_SKEW3_DELAYlt 0x0400 1012 #define TSIO_PHY_20_LPLL_SEL_SKEW4_DELAYlt 0x0800 1013 #define TSIO_PHY_20_LPLL_SKEW_EN_FIXCLK 0x1000 1014 #define TSIO_PHY_20_LPLL_SKEW_EN_SKEWCLK 0x2000 1015 #define TSIO_PHY_20_LPLL_SYN_CLKIN 0x4000 1016 #define TSIO_PHY_20_LPLL_XTAL_LV 0x8000 1017 1018 REG16_TSIO TSIO_PHY_21; //0x21 1019 #define TSIO_PHY_21_EN_DDR 0x0001 1020 #define TSIO_PHY_21_EN_MINI 0x0002 1021 #define TSIO_PHY_21_LPLL_RX_CLKIN_10 0x0004 1022 #define TSIO_PHY_21_LPLL_EN_FT_BACKUP 0x0008 1023 1024 REG16_TSIO TSIO_PHY_22; //0x22 1025 #define TSIO_PHY_22_LPLL_INPUT_DIV_FIRST_MASK 0x0003 1026 #define TSIO_PHY_22_LPLL_INPUT_DIV_FIRST_SHIFT 0 1027 #define TSIO_PHY_22_LPLL_LOOP_DIV_FIRST_MASK 0x000C 1028 #define TSIO_PHY_22_LPLL_LOOP_DIV_FIRST_SHIFT 2 1029 #define TSIO_PHY_22_LPLL_LOOP_DIV_SECOND_MASK 0x00F0 1030 #define TSIO_PHY_22_LPLL_LOOP_DIV_SECOND_SHIFT 4 1031 #define TSIO_PHY_22_LPLL_ICTRL_MASK 0x0700 1032 #define TSIO_PHY_22_LPLL_ICTRL_SHIFT 8 1033 #define TSIO_PHY_22_LPLL_SKEW_DIV_MASK 0x7000 1034 #define TSIO_PHY_22_LPLL_SKEW_DIV_SHIFT 12 1035 #define TSIO_PHY_22_LPLL_SW_DEBUG_EN 0x8000 1036 1037 REG16_TSIO TSIO_PHY_23; //0x23 1038 #define TSIO_PHY_23_LPLL_SKEW1_FINE_MASK 0x000F 1039 #define TSIO_PHY_23_LPLL_SKEW1_FINE_SHIFT 0 1040 #define TSIO_PHY_23_LPLL_SKEW4_FINE_MASK 0x00F0 1041 #define TSIO_PHY_23_LPLL_SKEW4_FINE_SHIFT 4 1042 #define TSIO_PHY_23_LPLL_SKEW2_FINE_MASK 0x0F00 1043 #define TSIO_PHY_23_LPLL_SKEW2_FINE_SHIFT 8 1044 #define TSIO_PHY_23_LPLL_SKEW3_FINE_MASK 0xF000 1045 #define TSIO_PHY_23_LPLL_SKEW3_FINE_SHIFT 12 1046 1047 REG16_TSIO TSIO_PHY_24; //0x24 1048 #define TSIO_PHY_24_LPLL_SKEW1_COARSE_MASK 0x001F 1049 #define TSIO_PHY_24_LPLL_SKEW1_COARSE_SHIFT 0 1050 #define TSIO_PHY_24_LPLL_SKEW2_COARSE_MASK 0x1F00 1051 #define TSIO_PHY_24_LPLL_SKEW2_COARSE_SHIFT 8 1052 1053 REG16_TSIO TSIO_PHY_25; //0x25 1054 #define TSIO_PHY_24_LPLL_SKEW4_COARSE_MASK 0x001F 1055 #define TSIO_PHY_24_LPLL_SKEW4_COARSE_SHIFT 0 1056 #define TSIO_PHY_24_LPLL_SKEW3_COARSE_MASK 0x1F00 1057 #define TSIO_PHY_24_LPLL_SKEW3_COARSE_SHIFT 8 1058 1059 REG16_TSIO RESERVED_26_2F[10]; //0x26~0x2F 1060 1061 REG32_TSIO TSIO_PHY_30_31; //0x30~31 1062 #define TSIO_PHY_30_31_LPLL_SYNTH_SET_MASK 0x00FFFFFF 1063 #define TSIO_PHY_30_31_LPLL_SYNTH_SET_SHIFT 0 1064 1065 }REG_Ctrl_TSIO_PHY; 1066 1067 1068 typedef struct _REG_Ctrl_TSO0 //for sgdmain pidflt 1069 { 1070 REG16_TSIO RESERVED_00_43[68]; //0x00~0x43 1071 1072 REG16_TSIO TSO_CONFIG5; //0x44 1073 #define TSO0_TSIO2OPIF 0x0800 1074 #define TSO0_TSIO_MODE 0x0400 1075 1076 REG16_TSIO PDTABLE_ADDR_L; //45 ind R/W of L addr to pdtable 1077 REG16_TSIO PDTABLE_ADDR_H; //46 ind R/W of H addr to pdtable 1078 1079 REG16_TSIO PDTABLE_WDATA_L; //47 ind R/W of L addr to pdtable 1080 REG16_TSIO PDTABLE_WDATA_H; //48 ind R/W of L addr to pdtable 1081 #define TSO0_PID_MASK 0x00001FFF 1082 #define TSO0_PID_SHIFT 0 1083 #define TSO0_ONE_MASK 0x0000E000 1084 #define TSO0_ONE_SHIFT 13 1085 #define TSO0_SVID_MASK 0x003F0000 1086 #define TSO0_SVID_SHIFT 16 1087 #define TSO0_ZERO_MASK 0xFFC00000 1088 #define TSO0_ZERO_SHIFT 22 1089 1090 REG16_TSIO PDTABLE_RDATA; //49 ind of Rdata from pdtable 1091 1092 REG16_TSIO PDTABLE_EN; //4A 1093 #define TSO0_PDTABLE_W_EN 0x0001 1094 #define TSO0_PDTABLE_R_EN 0x0002 1095 1096 REG16_TSIO RESERVED_4b_7F[53]; //4B~7F 1097 }REG_Ctrl_TSO0; 1098 1099 typedef struct _REG_Ctrl_TSO2 //Part of SGDMA_in 1100 { 1101 REG16_TSIO RESERVED_00_50[81]; //00~50 1102 1103 REG16_TSIO SG_PDFLT_SVID_EN[4]; //51~54 1104 REG16_TSIO SG_PDTABLE_RDATA; //55 ind of Rdata from pdtable 1105 REG16_TSIO SG_PDTABLE_RDATA_H; //56 ind of Rdata from pdtable 1106 #define TSO2_PDTABLE_RDATA_H_MASK 0x003F 1107 1108 REG16_TSIO RESERVED_57_7F[41]; //57~7F 1109 }REG_Ctrl_TSO2; 1110 1111 typedef struct _REG_Ctrl_TSO3 //SGDMA_in 1112 { 1113 REG16_TSIO TSO3_CTRL; //00 1114 #define TSO3_MEM_TS_W_ORDER 0x0001 1115 #define TSO3_FILE_PAUSE 0x0002 1116 #define TSO3_RADDR_LD 0x0004 1117 #define TSO3_DIS_MIU_RQ 0x0008 1118 #define TSO3_BYTE_TIMER_EN 0x0010 1119 #define TSO3_MEM_TS_DATA_ENDIAN 0x0020 1120 #define TSO3_SGFI2MI_PRIORITY 0x0040 1121 1122 REG16_TSIO BYTE_TIMER; //01 1123 #define TSO3_BYTE_TIMER_MASK 0x00FF 1124 #define TSO3_BYTE_TIMER_SHIFT 0 1125 1126 REG16_TSIO SGCTRL; //02 1127 #define TSO3_SGCTRL_RSTART 0x0001 1128 #define TSO3_SGCTRL_RDONE 0x0002 1129 #define TSO3_SGCTRL_BYTECNT_MASK 0xFF00 1130 #define TSO3_SGCTRL_BYTECNT_SHIFT 8 1131 1132 REG16_TSIO RESERVED_03_07[5]; //03~07 1133 1134 REG32_TSIO SGVQ1_BASE; //08~09 1135 1136 REG16_TSIO SGVQ1_SIZE_200BYTE; //0a 1137 1138 REG16_TSIO SGVQ1_TX_CONFIG; //0b 1139 #define TSO3_TX_CONFIG_WR_THRESHOLD_MASK 0x000F 1140 #define TSO3_TX_CONFIG_WR_THRESHOLD_SHIFT 0 1141 #define TSO3_TX_CONFIG_PRIORITY_THRESHOLD_MASK 0x00F0 1142 #define TSO3_TX_CONFIG_PRIORITY_THRESHOLD_SHIFT 4 1143 #define TSO3_TX_CONFIG_FORCEFIRE_CNT_MASK 0x0F00 1144 #define TSO3_TX_CONFIG_FORCEFIRE_CNT_SHIFT 8 1145 #define TSO3_TX_CONFIG_TX_RESET 0x1000 1146 #define TSO3_TX_CONFIG_OVERFLOW_INT_EN 0x2000 1147 #define TSO3_TX_CONFIG_OVERFLOW_CLR 0x4000 1148 #define TSO3_TX_CONFIG_SVQ_TX_ENABLE 0x8000 1149 1150 REG16_TSIO SGVQ1_TX_CONFIG_2; //0c 1151 #define TSO3_TX_CONFIG_2_FORCEFIRE_CNT_EXT_MASK 0x0003 1152 #define TSO3_TX_CONFIG_2_FORCEFIRE_CNT_EXT_SHIFT 0 1153 #define TSO3_TX_CONFIG_2_DISABLE_FORCEFIRE 0x0004 1154 #define TSO3_TX_CONFIG_2_FIX_MIU_REG_FLUSH_VQ 0x0008 1155 1156 REG16_TSIO SGVQ_RX_CONFIG; //0d 1157 #define TSO3_SGVQ_RX_CONFIG_MODE_MASK 0x0003 1158 #define TSO3_SGVQ_RX_CONFIG_MODE_SHIFT 0 1159 #define TSO3_SGVQ_RX_CONFIG_RD_THRESHOLD_MASK 0x001C 1160 #define TSO3_SGVQ_RX_CONFIG_RD_THRESHOLD_SHIFT 2 1161 #define TSO3_SGVQ_RX_CONFIG_ARBITOR_MODE_MASK 0x0060 1162 #define TSO3_SGVQ_RX_CONFIG_ARBITOR_MODE_SHIFT 5 1163 #define TSO3_SGVQ_RX_CONFIG_SRAM_SD_EN 0x0080 1164 #define TSO3_SGVQ_RX_CONFIG_SVQ_FORCE_RESET 0x0100 1165 #define TSO3_SGVQ_RX_CONFIG_SVQ_MIU_NS 0x0200 1166 #define TSO3_SGVQ_RX_CONFIG_SVQ_MOBF_INDEX_MASK 0x7C00 1167 #define TSO3_SGVQ_RX_CONFIG_SVQ_MOBF_INDEX_SHIFT 10 1168 #define TSO3_SGVQ_RX_CONFIG_SVQ_DYNAMIC_PRI 0x8000 1169 1170 REG16_TSIO SGVQ_STATUS; //0e 1171 1172 REG16_TSIO RESERVED_0F; //0f 1173 1174 REG16_TSIO PRE_HEADER_1_CONFIG[4]; //10~13 1175 1176 REG16_TSIO DBG_SEL; //14 1177 #define TSO3_DBG_SEL_MASK 0x00FF 1178 #define TSO3_DBG_SEL_SHIFT 0 1179 1180 REG16_TSIO LAST_PKT; //15 1181 #define TSO3_LAST_PKT_STR2MI_EN 0x0001 1182 #define TSO3_LAST_PKT_STR2MI_RST_WADR 0x0002 1183 #define TSO3_LAST_PKT_STR2MI_PAUSE 0x0004 1184 #define TSO3_LAST_PKT_BURST_LEN_MASK 0x0018 1185 #define TSO3_LAST_PKT_BURST_LEN_SHIFT 3 1186 #define TSO3_LAST_PKT_SRAM_SD_EN 0x0020 1187 #define TSO3_LAST_PKT_FLUSH_DATA 0x0040 1188 #define TSO3_LAST_PKT_STR2MI_WP_LD 0x0080 1189 #define TSO3_LAST_PKT_CLR 0x0100 1190 #define TSO3_LAST_PKT_DMA_FLUSH_EN 0x0200 1191 #define TSO3_LAST_PKT_MIU_HIGHPRI 0x0400 1192 #define TSO3_LAST_PKT_WRITE_POINTER_TO_NEXT_ADDR_EN 0x0800 1193 #define TSO3_LAST_PKT_DMAW_PROTECT_EN 0x1000 1194 #define TSO3_LAST_PKT_CLR_NO_HIT_INT 0x2000 1195 #define TSO3_LAST_PKT_FLUSH_DATA_LAST_PKT_STATUS 0x4000 1196 1197 REG32_TSIO LAST_PKT_STR2MI_HEAD; //16~17 1198 1199 REG32_TSIO LAST_PKT_STR2MI_TAIL; //18~19 1200 1201 REG32_TSIO LAST_PKT_DMAW_WADDR_ERR; //1a~1b 1202 1203 REG16_TSIO LAST_PKT_STR2MI_MOBF_INDEX0;//1c 1204 #define TSO3_LAST_PKT_STR2MI_MOBF_INDEX0_MASK 0x001F 1205 #define TSO3_LAST_PKT_STR2MI_MOBF_INDEX0_SHIFT 0 1206 1207 REG32_TSIO LAST_PKT_STR2MI_WADR_R; //1d~1e 1208 1209 REG16_TSIO LAST_PKT_STATUS; //1f 1210 #define TSO3_LAST_PKT_FIFO_STATUS_MASK 0x000F 1211 #define TSO3_LAST_PKT_FIFO_STATUS_SHIFT 0 1212 #define TSO3_ABT_STATUS_MASK 0x03F0 1213 #define TSO3_ABT_STATUS_SHIFT 4 1214 1215 REG32_TSIO SG_DEBUG_PORT; //20~21 1216 #define TSO3_SG_DEBUG_PORT_MASK 0x00FFFFFF 1217 #define TSO3_SG_DEBUG_PORT_SHIFT 1 1218 1219 REG16_TSIO REG_ABT; //22 1220 #define TSO3_MIU_RR_PRI_ABT 0x0001 1221 #define TSO3_DIS_MIU_RQ_ABT 0x0002 1222 #define TSO3_MERGE_EN_ABT 0x0004 1223 1224 REG16_TSIO SW_RSTZ; //23 1225 #define TSO3_SW_RSTZ 0x0001 1226 #define TSO3_SW_RST_SG_DMA_READ 0x0002 1227 #define TSO3_SW_RST_SG_DMA_READ_MIU 0x0004 1228 #define TSO3_SW_RST_SG_LAST_PKT 0x0008 1229 #define TSO3_SW_RST_SG_LAST_PKT_MIU 0x0010 1230 #define TSO3_SW_RST_SG_PINGPONG_FIFO 0x0020 1231 #define TSO3_SW_RST_SG_TSIF 0x0040 1232 #define TSO3_SW_RST_SG_VQ_TX 0x0080 1233 #define TSO3_SW_RST_SG_VQ_TX_MIU 0x0100 1234 #define TSO3_SW_RST_SG_TSO_ROUNDROBIN 0x0200 1235 #define TSO3_SW_RST_SG_TSO_SGDMA_CTRL 0x0400 1236 #define TSO3_SW_RST_SG_TSO_VC_TABLE 0x0800 1237 #define TSO3_SW_RST_SG_TSO_VCDMA_READ_MIU 0x1000 1238 #define TSO3_SW_RST_SG_TSO_PACE_TRANSFER 0x2000 1239 1240 REG32_TSIO LAST_PKT_DMAW_LBND; //24~25 1241 1242 REG32_TSIO LAST_PKT_DMAW_UBND; //26~27 1243 1244 REG16_TSIO RESERVED_28_29[2]; //28~29 1245 1246 REG16_TSIO SGDMA_IN_CONFIG0; //2a 1247 1248 REG16_TSIO SGDMA_IN_CONFIG1; //2b 1249 1250 REG16_TSIO SID_DISABLE[4]; //2c~2f 1251 1252 REG16_TSIO SGCTRL_START; //30 1253 #define TSO3_SGCTRL_START 0x0001 1254 1255 REG16_TSIO ACPU_ACTIVE; //31 1256 #define TSO3_ACPU_ACTIVE 0x0001 1257 1258 REG16_TSIO ACPU_CMD; //32 1259 #define TSO3_ACPU_CMD_ACPU_VC_ID_MASK 0x003F 1260 #define TSO3_ACPU_CMD_ACPU_VC_ID_SHIFT 0 1261 #define TSO3_ACPU_CMD_ACPU_POSITION_MASK 0x01C0 1262 #define TSO3_ACPU_CMD_ACPU_POSITION_SHIFT 6 1263 #define TSO3_ACPU_CMD_START_A_NEW_PACKAGE 0x0200 1264 #define TSO3_ACPU_CMD_ACPU_RW 0x0400 1265 #define TSO3_ACPU_CMD_ACPU_ACTIVE 0x0800 1266 #define TSO3_ACPU_CMD_M_PRIORITY 0x1000 1267 1268 REG32_TSIO ACPU_WDATA; //33~34 1269 1270 REG16_TSIO ACPU_FLAG; //35 1271 #define TSO3_ACPU_FLAG_MODE_INFO_MIU_SEL_MASK 0x0003 1272 #define TSO3_ACPU_FLAG_MODE_INFO_MIU_SEL_SHIFT 0 1273 #define TSO3_ACPU_FLAG_LAST_NODE_FLUSH 0x0004 1274 #define TSO3_ACPU_FLAG_PKT_MODE_188 0x0008 1275 #define TSO3_ACPU_FLAG_INTERRUPT_ENABLE 0x0010 1276 #define TSO3_ACPU_FLAG_MOBF_MASK 0x03E0 1277 #define TSO3_ACPU_FLAG_MOBF_SHIFT 5 1278 #define TSO3_ACPU_FLAG_SERVICE_ID_MASK 0xFC00 1279 #define TSO3_ACPU_FLAG_SERVICE_ID_SHIFT 10 1280 1281 REG32_TSIO ACPU_RDATA; //36~37 1282 1283 REG16_TSIO SGDMA_IN; //38 1284 #define TSO3_SGDMA_IN_INT_CLR 0x0001 1285 #define TSO3_SGDMA_IN_PAUSE 0x0002 1286 #define TSO3_SGDMA_IN_DBG_SEL_MASK 0x00FC 1287 #define TSO3_SGDMA_IN_DBG_SEL_SHIFT 2 1288 #define TSO3_SGDMA_IN_INT_MASK 0x0100 1289 #define TSO3_SGDMA_IN_VCDMA_MIU_PRIORITY 0x0200 1290 #define TSO3_SGDMA_IN_VC_INT_TRIGGER 0x0400 1291 1292 REG16_TSIO SGDMA_IN_DBG; //39 1293 1294 REG16_TSIO SGDMA_IN_VC_INT[4]; //3a~3d 1295 1296 REG16_TSIO PACE_DBG; //3e 1297 #define TSO3_SGDMA_IN_VC_INT_VC_ID_MASK 0x003F 1298 #define TSO3_SGDMA_IN_VC_INT_VC_ID_SHIFT 0 1299 #define TSO3_SGDMA_IN_VC_INT_CLR 0x0040 1300 #define TSO3_SGDMA_IN_VC_INT_MASK 0x0080 1301 #define TSO3_PACE_DBG_VCID_MASK 0x3F00 1302 #define TSO3_PACE_DBG_VCID_SHIFT 8 1303 #define TSO3_PACE_DBG_CLR 0x4000 1304 #define TSO3_PACE_DBG_EN 0x8000 1305 1306 REG16_TSIO GLOBAL_TICK_COUNT_SET; //3f 1307 #define TSO3_GLOBAL_TICK_COUNT_SET_MASK 0x00FF 1308 #define TSO3_GLOBAL_TICK_COUNT_SET_SHIFT 0 1309 1310 REG16_TSIO TICK_COUNT_SET[64]; //40~7f 1311 #define TSO3_TICK_COUNT_SET_MASK 0x03FF 1312 #define TSO3_TICK_COUNT_SET_SHIFT 0 1313 }REG_Ctrl_TSO3; 1314 1315 typedef struct _REG_Ctrl_TSP8 //TSP8 1316 { 1317 REG16_TSIO RESERVED_00_62[99]; //00~62 1318 REG16_TSIO HW8_CONFIG3; //63 1319 #define TSP_TSIF0_TSIO0_BLK_EN 0x0001 1320 #define TSP_TSIF0_TSIO1_BLK_EN 0x0002 1321 #define TSP_TSIF0_TSIO2_BLK_EN 0x0004 1322 #define TSP_TSIF0_TSIO3_BLK_EN 0x0008 1323 #define TSP_TSIF0_TSIO4_BLK_EN 0x0010 1324 #define TSP_TSIF0_TSIO5_BLK_EN 0x0020 1325 REG16_TSIO RESERVED_64_7F[28]; //64~7f 1326 }REG_Ctrl_TSP8; 1327 1328 #endif // _TSIO_REG_H_ 1329