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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: mmfilein.h 98 // Description: Multimedia File In (MMFILEIN) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _MMFILEIN_REG_H_ 103 #define _MMFILEIN_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define MMFI_ENGINE_NUM (2) 137 138 #define MMFI_PIDFLT0_NUM (4) 139 #define MMFI_PIDFLT1_NUM (4) 140 141 #define MMFI_PIDFLT_NUM_ALL (MMFI_PIDFLT0_NUM+MMFI_PIDFLT1_NUM) 142 143 #define MMFI_PID_NULL 0x1FFF 144 145 //------------------------------------------------------------------------------------------------- 146 // Harware Capability 147 //------------------------------------------------------------------------------------------------- 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 153 #define REG_CTRL_BASE_MMFI0 (0x27E00UL) // 0xBF800000+(13F00/2)*4 154 #define REG_CTRL_BASE_MMFI1 (0x27F00UL) // 0xBF800000+(13F80/2)*4 155 156 typedef struct _REG32_MM 157 { 158 volatile MS_U16 L; 159 volatile MS_U16 empty_L; 160 volatile MS_U16 H; 161 volatile MS_U16 empty_H; 162 } REG32_MM; 163 164 165 typedef struct _REG16_MM 166 { 167 volatile MS_U16 data; 168 volatile MS_U16 _resv; 169 } REG16_MM; 170 171 typedef struct _REG_Ctrl_MMFI 172 { 173 //---------------------------------------------- 174 // 0xBF802A00 MIPS direct access 175 //---------------------------------------------- 176 // Index(word) CPU(byte) MIPS(0x13F00/2+index)*4 177 REG32_MM PidFlt[4]; // 0xbf827E00 0x00 178 #define MMFI_PIDFLT_PID_MASK 0x00001FFF 179 #define MMFI_PIDFLT_EN_MASK 0x001FE000 180 #define MMFI_PIDFLT_AFIFOB_EN 0x00002000 181 #define MMFI_PIDFLT_AFIFO_EN 0x00004000 182 #define MMFI_PIDFLT_VFIFO_EN 0x00008000 183 #define MMFI_PIDFLT_V3DFIFO_EN 0x00010000 184 #define MMFI_PIDFLT_AFIFOC_EN 0x00020000 185 #define MMFI_PIDFLT_AFIFOD_EN 0x00040000 186 #define MMFI_PIDFLT_VFIFO3_EN 0x00080000 187 #define MMFI_PIDFLT_VFIFO4_EN 0x00100000 188 #define MMFI_PIDFLT_AFIFOE_EN 0x00000000 // not support 189 #define MMFI_PIDFLT_AFIFOF_EN 0x00000000 // not support 190 #define MMFI_PIDFLT_VFIFO5_EN 0x00000000 // not support 191 #define MMFI_PIDFLT_VFIFO6_EN 0x00000000 // not support 192 #define MMFI_PIDFLT_VFIFO7_EN 0x00000000 // not support 193 #define MMFI_PIDFLT_VFIFO8_EN 0x00000000 // not support 194 195 REG32_MM FileIn_RAddr; // 0xbf803820 0x08 //byte address 196 REG32_MM FileIn_RNum; // 0xbf803828 0x0a 197 198 REG16_MM FileIn_Ctrl; // 0xbf803830 0x0c 199 #define MMFI_FILEIN_CTRL_START 0x0001 200 #define MMFI_FILEIN_CTRL_MOBF_EN 0x0002 201 #define MMFI_FILEIN_CTRL_ABORT 0x0010 202 #define MMFI_FILEIN_CTRL_MASK 0x0013 203 #define MMFI_FILEIN_TIMER_MASK 0xFF00 204 #define MMFI_FILEIN_TIMER_SHIFT 8 205 206 REG16_MM CmdQSts; // 0xbf803834 0x0d 207 #define MMFI_CMDQ_SIZE 8 208 #define MMFI_CMDQSTS_WRCNT_MASK 0x001F 209 #define MMFI_CMDQSTS_FIFO_FULL 0x0040 210 #define MMFI_CMDQSTS_FIFO_EMPTY 0x0080 211 #define MMFI_CMDQSTS_FIFO_WRLEVEL_MASK 0x0300 212 #define MMFI_CMDQSTS_FIFO_WRLEVEL_SHIFT 8 213 214 REG32_MM Cfg; // 0xbf803838 0x0e 215 #define MMFI_CFG_LPCR2_LD 0x00000001 216 #define MMFI_CFG_LPCR2_WLD 0x00000002 217 #define MMFI_CFG_TEI_SKIP 0x00000004 218 #define MMFI_CFG_CLR_PIDFLT_BYTE_CNT 0x00000008 219 #define MMFI_CFG_APID_BYPASS 0x00000010 220 #define MMFI_CFG_APIDB_BYPASS 0x00000020 221 #define MMFI_CFG_VPID_BYPASS 0x00000040 222 #define MMFI_CFG_VPID3D_BYPASS 0x00000080 223 #define MMFI_CFG_AUD_ERR_EN 0x00000100 224 #define MMFI_CFG_AUDB_ERR_EN 0x00000200 225 #define MMFI_CFG_VD_ERR_EN 0x00000400 226 #define MMFI_CFG_V3D_ERR_EN 0x00000800 227 #define MMFI_CFG_APES_ERR_RM_EN 0x00001000 228 #define MMFI_CFG_APESB_ERR_RM_EN 0x00002000 229 #define MMFI_CFG_VPES_ERR_RM_EN 0x00004000 230 #define MMFI_CFG_VPES3D_ERR_RM_EN 0x00008000 231 #define MMFI_CFG_CLR_PKT_CNT 0x00010000 232 #define MMFI_CFG_DIS_MIU_RQ 0x00020000 233 #define MMFI_CFG_RADDR_READ 0x00040000 234 #define MMFI_CFG_BYTETIMER_EN 0x00080000 235 #define MMFI_CFG_PLY_FILE_INV_EN 0x00100000 236 #define MMFI_CFG_DUP_PKT_SKIP 0x00200000 237 #define MMFI_CFG_ALT_TS_SIZE 0x00400000 238 #define MMFI_CFG_2MI_RPRIORITY 0x00800000 239 #define MMFI_CFG_PS_AUD_EN 0x01000000 240 #define MMFI_CFG_PS_AUDB_EN 0x02000000 241 #define MMFI_CFG_PS_VD_EN 0x04000000 242 #define MMFI_CFG_PS_V3D_EN 0x08000000 243 #define MMFI_CFG_MEM_TS_ORDER 0x10000000 244 #define MMFI_CFG_MEM_TS_DATA_ENDIAN 0x20000000 245 #define MMFI_CFG_PKT192_EN 0x40000000 246 #define MMFI_CFG_PKT192_BLK_DISABLE 0x80000000 247 #define MMFI_CFG_FILEIN_MODE_MASK (MMFI_CFG_APID_BYPASS|MMFI_CFG_APIDB_BYPASS|MMFI_CFG_VPID_BYPASS|MMFI_CFG_VPID3D_BYPASS|MMFI_CFG_PS_AUD_EN|MMFI_CFG_PS_AUDB_EN|MMFI_CFG_PS_VD_EN|MMFI_CFG_PS_V3D_EN) 248 249 REG32_MM TsHeader; // 0xbf803840 0x10 250 #define MMFI_HD_CCNT_MASK 0x0000000F 251 #define MMFI_HD_AF_MASK 0x00000030 252 #define MMFI_HD_AF_SHIFT 4 253 #define MMFI_HD_SCRAMBLE_MASK 0x000000C0 254 #define MMFI_HD_SCRAMBLE_SHIFT 6 255 #define MMFI_HD_PID 0x001FFF00 256 #define MMFI_HD_PID_SHIFT 8 257 #define MMFI_HD_TS_PRIORITY_MASK 0x00200000 258 #define MMFI_HD_TS_PRIORITY_SHIFT 21 259 #define MMFI_HD_PAYLOAD_START_FLG_MASK 0x00400000 260 #define MMFI_HD_PAYLOAD_START_FLG_SHIFT 22 261 #define MMFI_HD_ERR_FLG_MASK 0x00800000 262 #define MMFI_HD_ERR_FLG_SHIFT 23 263 264 REG16_MM APid_Status; // 0xbf803848 0x12 265 #define MMFI_APID_MATCHED_MASK 0x00001FFF 266 #define MMFI_APID_CHANGE 0x00002000 267 REG16_MM APidB_Status; // 0xbf80384C 0x13 268 #define MMFI_APIDB_MATCHED_MASK 0x00001FFF 269 #define MMFI_APIDB_CHANGE 0x00002000 270 REG16_MM VPID_Status; // 0xbf803850 0x14 271 #define MMFI_VPID_MATCHED_MASK 0x00001FFF 272 #define MMFI_VPID_CHANGE 0x00002000 273 REG16_MM VPID3D_Status; // 0xbf803854 0x15 274 #define MMFI_VPID3D_MATCHED_MASK 0x00001FFF 275 #define MMFI_VPID3D_CHANGE 0x00002000 276 277 REG32_MM LPcr2_Buf; // 0xbf803858 0x16 278 REG32_MM TimeStamp_FIn; // 0xbf803860 0x18 279 280 REG16_MM SWRst; // 0xbf803868 0x1a 281 #define MMFI_SWRST_MASK 0x07FF 282 #define MMFI_SW_RSTZ_MMFILEIN_DISABLE 0x0001 // low active 283 #define MMFI_RST_WB_DMA0 0x0002 284 #define MMFI_RST_CMDQ0 0x0004 285 #define MMFI_RST_TSIF0 0x0008 286 #define MMFI_RST_WB0 0x0010 287 #define MMFI_RST_WB_DMA1 0x0020 288 #define MMFI_RST_CMDQ1 0x0040 289 #define MMFI_RST_TSIF1 0x0080 290 #define MMFI_RST_WB1 0x0100 291 #define MMFI_RST_PATH0 0x0200 292 #define MMFI_RST_PATH1 0x0400 293 #define MMFI_RST_ALL 0x07FE 294 #define MMFI_RST_LPCR_27M_EN_MMFI0 0x4000 295 #define MMFI_RST_LPCR_27M_EN_MMFI1 0x8000 296 297 REG16_MM HWInt; // 0xbf80386c 0x1b 298 #define MMFI_HWINT_SRC_MASK 0x00FF 299 #define MMFI_HWINT_SRC_FILEIN_DONE1 0x0004 300 #define MMFI_HWINT_SRC_FILEIN_DONE0 0x0008 301 #define MMFI_HWINT_SRC_VD3D_ERR1 0x0010 302 #define MMFI_HWINT_SRC_AUAUB_ERR1 0x0020 303 #define MMFI_HWINT_SRC_VD3D_ERR0 0x0040 304 #define MMFI_HWINT_SRC_AUAUB_ERR0 0x0080 305 #define MMFI_HWINT_STS_MASK 0xFF00 306 #define MMFI_HWINT_STS_SHIFT 8 307 #define MMFI_HWINT_STS_FILEIN_DONE1 0x0400 308 #define MMFI_HWINT_STS_FILEIN_DONE0 0x0800 309 #define MMFI_HWINT_STS_VD3D_ERR1 0x1000 310 #define MMFI_HWINT_STS_AUAUB_ERR1 0x2000 311 #define MMFI_HWINT_STS_VD3D_ERR0 0x4000 312 #define MMFI_HWINT_STS_AUAUB_ERR0 0x8000 313 314 REG16_MM PktChkSize; // 0xbf803870 0x1c 315 #define MMFI_PKTCHK_SIZE_MASK 0x00FF 316 #define MMFI_SYNC_BYTE_MASK 0xFF00 317 #define MMFI_SYNC_BYTE_SHIFT 8 318 319 REG16_MM MOBFKey; // 0xbf803874 0x1d 320 #define MMFI_MOBFKEY_MASK 0x001F 321 322 REG32_MM RAddr; // 0xbf803878 0x1e 323 #define MMFI_TSP2MI_RADDR_MASK 0x0FFFFFFF 324 } REG_Ctrl_MMFI; 325 326 typedef struct _REG_Ctrl_MMFI1 327 { 328 //---------------------------------------------- 329 // 0xBF827F00 MIPS direct access 330 //---------------------------------------------- 331 // Index(word) CPU(byte) MIPS(0x13F80/2+index)*4 332 REG16_MM CFG2[2]; // 0xbf827F00 0x40~0x41 333 #define MMFI_CFG2_MMFI_APIDC_BYPASS 0x00000001 334 #define MMFI_CFG2_APESC_ERR_RM_EN 0x00000002 335 #define MMFI_CFG2_MMFI_PS_AUDC_EN 0x00000004 336 #define MMFI_CFG2_FILEIN_PAUSE 0x00000008 337 #define MMFI_CFG2_MMFI_APIDD_BYPASS 0x00000010 338 #define MMFI_CFG2_APESD_ERR_RM_EN 0x00000020 339 #define MMFI_CFG2_MMFI_PS_AUDD_EN 0x00000040 340 #define MMFI_CFG2_WB_FSM_RESET 0x00000080 341 #define MMFI_CFG2_INIT_TIMESTAMP_TSIF 0x00000100 342 #define MMFI_CFG2_MMFI_PS_AUDE_EN 0x00000000 // not support 343 #define MMFI_CFG2_MMFI_PS_AUDF_EN 0x00000000 // not support 344 #define MMFI_CFG2_MMFI_PS_VD3_EN 0x00000000 // not support 345 #define MMFI_CFG2_MMFI_PS_VD4_EN 0x00000000 // not support 346 #define MMFI_CFG2_MMFI_PS_VD5_EN 0x00000000 // not support 347 #define MMFI_CFG2_MMFI_PS_VD6_EN 0x00000000 // not support 348 #define MMFI_CFG2_MMFI_PS_VD7_EN 0x00000000 // not support 349 #define MMFI_CFG2_MMFI_PS_VD8_EN 0x00000000 // not support 350 #define MMFI_CFG2_FILEIN_MODE_MASK (MMFI_CFG2_MMFI_APIDC_BYPASS | MMFI_CFG2_MMFI_APIDD_BYPASS | MMFI_CFG2_MMFI_PS_AUDC_EN | MMFI_CFG2_MMFI_PS_AUDD_EN) 351 352 REG16_MM CFG3[2]; // 0xbf827F08 0x42~0x43 353 #define MMFI_CFG3_RVU_PSI_EN 0x00000001 354 #define MMFI_CFG3_RVU_TEI_EN 0x00000002 355 #define MMFI_CFG3_RVU_ERR_CLR 0x00000004 356 #define MMFI_CFG3_RVU_EN 0x00000008 357 #define MMFI_CFG3_RVU_TIMESTAMP_EN 0x00000010 358 #define MMFI_CFG3_MMFI_VPID3_BYPASS 0x00000020 359 #define MMFI_CFG3_MMFI_PS_VD3_EN 0x00000040 360 #define MMFI_CFG3_VD3_ERR_EN 0x00000080 361 #define MMFI_CFG3_VD3_ERR_RM_EN 0x00000100 362 #define MMFI_CFG3_MMFI_VPID4_BYPASS 0x00000200 363 #define MMFI_CFG3_MMFI_PS_VD4_EN 0x00000400 364 #define MMFI_CFG3_VD4_ERR_EN 0x00000800 365 #define MMFI_CFG3_VD4_ERR_RM_EN 0x00001000 366 #define MMFI_CFG3_FILEIN_MODE_MASK (MMFI_CFG3_MMFI_VPID3_BYPASS | MMFI_CFG3_MMFI_VPID4_BYPASS | MMFI_CFG3_MMFI_PS_VD3_EN | MMFI_CFG3_MMFI_PS_VD4_EN) 367 368 REG16_MM VPid3_Status_MMFI0; // 0xbf827F10 0x44 369 REG16_MM VPid3_Status_MMFI1; // 0xbf827F14 0x45 370 #define MMFI_VPID3_MATCHED_MASK 0x00001FFF 371 #define MMFI_VPID3_CHANGE 0x00002000 372 373 REG16_MM VPid4_Status_MMFI0; // 0xbf827F18 0x46 374 REG16_MM VPid4_Status_MMFI1; // 0xbf827F1C 0x47 375 #define MMFI_VPID4_MATCHED_MASK 0x00001FFF 376 #define MMFI_VPID4_CHANGE 0x00002000 377 378 REG16_MM APidC_Status_MMFI0; // 0xbf827F20 0x48 379 REG16_MM APidC_Status_MMFI1; // 0xbf827F24 0x49 380 #define MMFI_APIDC_MATCHED_MASK 0x00001FFF 381 #define MMFI_APIDC_CHANGE 0x00002000 382 383 REG16_MM APidD_Status_MMFI0; // 0xbf827F28 0x4A 384 REG16_MM APidD_Status_MMFI1; // 0xbf827F2C 0x4B 385 #define MMFI_APIDD_MATCHED_MASK 0x00001FFF 386 #define MMFI_APIDD_CHANGE 0x00002000 387 388 } REG_Ctrl_MMFI1; 389 390 391 #endif // _MMFILEIN_REG_H_ 392