1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 2 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 //VQ define 36 #define VQ_NUM 3 37 #define VQ_PACKET_UNIT_LEN 208 38 39 #define TSP_TSIF0 0x00 40 #define TSP_TSIF1 0x01 41 #define TSP_TSIF2 0x02 42 #define TSP_TSIF3 0x03 43 #define TSP_TSIF4 0x04 // not support 44 #define TSP_TSIF5 0x05 // not support 45 #define TSP_TSIF6 0x06 // not support 46 47 //FQ define 48 #define TSP_FQ_NUM 1 49 50 //######################################################################### 51 //#### Software Capability Macro Start 52 //######################################################################### 53 54 #define TSP_CA_RESERVED_FLT_NUM 1 55 #define TSP_RECFLT_NUM 1 56 #define TSP_PIDFLT_REC_NUM (TSP_PIDFLT_NUM - TSP_PCRFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 96 -2 = 94 // 0~189 (0 for CA) 57 // 193 for Err 58 // 192 for REC 59 // 191 for PCR1 60 // 190 for PCR0 61 62 ///#if HW_PCRFLT_ENABLE 63 //#define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 64 //#else 65 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 66 //#endif 67 68 //######################################################################### 69 //#### Software Capability Macro End 70 //######################################################################### 71 72 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 73 #define TSP_CAFLT_START_ID 0 74 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) // 1 75 76 // section FLT ID 77 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID // 1 78 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID // 1 79 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM - TSP_PCRFLT_NUM) // 1 + 64 - 1 - 2 = 62 80 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM - TSP_PCRFLT_NUM) 81 82 // PID 83 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID // 1 84 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM - TSP_PCRFLT_NUM) // 1 + 96 - 1 - 2 = 94 85 86 // PCR 87 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID // 94 88 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 89 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) // 96 90 91 // REC 92 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID // 96 93 94 //-------------------------------------------------------------------------------------------------- 95 // Driver Compiler Option 96 //-------------------------------------------------------------------------------------------------- 97 98 99 //-------------------------------------------------------------------------------------------------- 100 // PVR Hardware Abstraction Layer 101 //-------------------------------------------------------------------------------------------------- 102 103 // HW characteristic 104 105 typedef enum _PVRENG_SEQ 106 { 107 E_TSP_PVR_PVRENG_START = 0, 108 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 109 E_TSP_PVR_PVRENG_1, 110 E_TSP_PVR_PVRENG_2, 111 E_TSP_PVR_PVRENG_3, 112 E_TSP_PVR_PVRENG_END, 113 E_TSP_PVR_RASPENG_START = E_TSP_PVR_PVRENG_END, 114 E_TSP_PVR_RASPENG_0 = E_TSP_PVR_RASPENG_START, 115 E_TSP_PVR_RASPENG_1, 116 E_TSP_PVR_RASPENG_END, 117 E_TSP_PVR_CBPVRENG_START = E_TSP_PVR_RASPENG_END, 118 E_TSP_PVR_ENG_INVALID, 119 } PVRENG_SEQ; 120 121 typedef enum _FILEENG_SEQ 122 { 123 E_FILEENG_TSIF0 = TSP_TSIF0, 124 E_FILEENG_TSIF1 = TSP_TSIF1, 125 E_FILEENG_TSIF2 = TSP_TSIF2, 126 E_FILEENG_TSIF3 = TSP_TSIF3, 127 E_FILEENG_INVALID, 128 129 } FILEENG_SEQ; 130 131 #if 1 // Destination type 132 typedef enum _TSP_DST_SEQ 133 { 134 E_TSP_DST_FIFO_VIDEO, 135 E_TSP_DST_FIFO_VIDEO3D, 136 E_TSP_DST_FIFO_VIDEO3, //Not support 137 E_TSP_DST_FIFO_VIDEO4, //Not support 138 E_TSP_DST_FIFO_VIDEO5, //Not support 139 E_TSP_DST_FIFO_VIDEO6, //Not support 140 E_TSP_DST_FIFO_VIDEO7, //Not support 141 E_TSP_DST_FIFO_VIDEO8, //Not support 142 143 E_TSP_DST_FIFO_AUDIO, 144 E_TSP_DST_FIFO_AUDIO2, 145 E_TSP_DST_FIFO_AUDIO3, 146 E_TSP_DST_FIFO_AUDIO4, 147 E_TSP_DST_FIFO_AUDIO5, //Not support 148 E_TSP_DST_FIFO_AUDIO6, //Not support 149 150 E_TSP_DST_INVALID, 151 } TSP_DST_SEQ; 152 #else 153 #define TSP_FltType MS_U32 154 /// TS stream fifo type (Exclusive usage) 155 #define E_TSP_FLT_FIFO_MASK 0x000000FF 156 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 157 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 158 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 159 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 160 #endif 161 162 typedef enum _TSP_SRC_SEQ{ 163 E_TSP_SRC_PKTDMX0, 164 E_TSP_SRC_PKTDMX1, 165 E_TSP_SRC_PKTDMX2, 166 E_TSP_SRC_PKTDMX3, 167 E_TSP_SRC_PKTDMX4, //not used 168 E_TSP_SRC_PKTDMX5, //not used 169 E_TSP_SRC_MMFI0, 170 E_TSP_SRC_MMFI1, 171 172 E_TSP_SRC_INVALID, 173 } TSP_SRC_SEQ; 174 175 typedef enum _TSIF_CFG 176 { 177 // @NOTE should be Exclusive usage 178 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 179 E_TSP_TSIF_CFG_EN = 0x0001, 180 E_TSP_TSIF_CFG_PARA = 0x0002, 181 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 182 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 183 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 184 E_TSP_TSIF_CFG_3WIRE = 0x0010 185 } TSP_TSIF_CFG; 186 187 // for stream input source 188 typedef enum _HAL_TS_PAD 189 { 190 E_TSP_TS_PAD_EXT0, 191 E_TSP_TS_PAD_EXT1, 192 E_TSP_TS_PAD_EXT2, 193 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 194 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 195 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 196 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 197 E_TSP_TS_PAD_EXT7, // not support, 198 E_TSP_TS_PAD_INTER0, 199 E_TSP_TS_PAD_INTER1, // not support, 200 E_TSP_TS_PAD_TSOUT0, 201 E_TSP_TS_PAD_TSOUT1, // not support, 202 E_TSP_TS_PAD_EXT0_3WIRE, 203 E_TSP_TS_PAD_EXT1_3WIRE, 204 E_TSP_TS_PAD_EXT2_3WIRE, 205 E_TSP_TS_PAD_EXT3_3WIRE, 206 E_TSP_TS_PAD_INVALID, 207 } TSP_TS_PAD; 208 209 // for ts pad mode 210 typedef enum _HAL_TS_PAD_MUX_MODE 211 { 212 E_TSP_TS_PAD_MUX_PARALLEL, 213 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, 214 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, 215 E_TSP_TS_PAD_MUX_TSO, // out 216 E_TSP_TS_PAD_MUX_S2P, // out 217 E_TSP_TS_PAD_MUX_S2P1, // out 218 E_TSP_TS_PAD_MUX_DEMOD, // out 219 E_TSP_TS_PAD_MUX_INVALID 220 } TSP_TS_PAD_MUX_MODE; 221 222 223 224 // for pkt converter mode 225 typedef enum _HAL_TS_PKT_CONVERTER_MODE 226 { 227 E_TSP_PKT_CONVERTER_188Mode = 0, 228 E_TSP_PKT_CONVERTER_CIMode = 1, 229 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 230 E_TSP_PKT_CONVERTER_ATSMode = 3, 231 E_TSP_PKT_CONVERTER_MxLMode = 4, 232 E_TSP_PKT_CONVERTER_Invalid, 233 } TSP_TS_PKT_CONVERTER_MODE; 234 235 typedef enum _HAL_TS_MXL_PKT_MODE 236 { 237 E_TSP_TS_MXL_PKT_192 = 4, 238 E_TSP_TS_MXL_PKT_196 = 8, 239 E_TSP_TS_MXL_PKT_200 = 12, 240 E_TSP_TS_MXL_PKT_INVALID, 241 } TSP_TS_MXL_PKT_MODE; 242 243 244 typedef enum _HAL_DMX_FLOW_DST 245 { 246 E_TSP_DMX_FLOW_PLAYBACK, 247 E_TSP_DMX_FLOW_PLAYBACK1, 248 E_TSP_DMX_FLOW_PLAYBACK2, 249 E_TSP_DMX_FLOW_PLAYBACK3, 250 }_HAL_DMX_FLOW_DST; 251 252 typedef enum _HAL_TSP_CLK_TYPE 253 { 254 E_TSP_HAL_TSP_CLK, 255 E_TSP_HAL_STC_CLK, 256 E_TSP_HAL_INVALID 257 } EN_TSP_HAL_CLK_TYPE; 258 259 260 typedef struct _HAL_TSP_CLK_STATUS 261 { 262 MS_BOOL bEnable; 263 MS_BOOL bInvert; 264 MS_U8 u8ClkSrc; 265 } ST_TSP_HAL_CLK_STATUS; 266 267 268 typedef enum _PCR_SRC 269 { 270 /* register setting for kaiser pcr 271 0: tsif0 272 1: tsif1 273 2: tsif2 274 3: tsif3 275 4: tsif4 276 5: tsif5 277 6: un-used 278 7: un-used 279 8: pkt merge 0 280 9: pkt merge 1 281 a: MM file in 1 282 b: MM file in 2 283 */ 284 E_TSP_PCR_SRC_TSIF0 = 0, 285 E_TSP_PCR_SRC_TSIF1, 286 E_TSP_PCR_SRC_TSIF2, 287 E_TSP_PCR_SRC_TSIF3, 288 E_TSP_PCR_SRC_TSIF4, 289 E_TSP_PCR_SRC_TSIF5, 290 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 291 E_TSP_PCR_SRC_PKT_MERGE1, 292 E_TSP_PCR_SRC_MMFI0, 293 E_TSP_PCR_SRC_MMFI1, 294 E_TSP_PCR_SRC_INVALID, 295 } TSP_PCR_SRC; 296 297 typedef enum _CLR_SRC 298 { 299 E_TSP_CLR_SRC_TSIF0, 300 E_TSP_CLR_SRC_TSIF1, 301 E_TSP_CLR_SRC_TSIF2, //not support 302 E_TSP_CLR_SRC_TSIF3, //not support 303 E_TSP_CLR_SRC_MMFI0, 304 E_TSP_CLR_SRC_MMFI1, 305 E_TSP_CLR_SRC_INVALID, 306 } TSP_CLR_SRC; 307 308 309 typedef enum _HAL_TSP_TSIF // for HW TSIF 310 { 311 E_TSP_HAL_TSIF_0 , 312 E_TSP_HAL_TSIF_1 , 313 E_TSP_HAL_TSIF_2 , 314 E_TSP_HAL_TSIF_3 , 315 E_TSP_HAL_TSIF_4 , // not support 316 E_TSP_HAL_TSIF_5 , // not support 317 E_TSP_HAL_TSIF_6 , // not support 318 319 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 320 E_TSP_HAL_TSIF_PVR0 , 321 E_TSP_HAL_TSIF_PVR1 , 322 E_TSP_HAL_TSIF_PVR2 , 323 E_TSP_HAL_TSIF_PVR3 , 324 E_TSP_HAL_TSIF_INVALID , 325 } TSP_HAL_TSIF; 326 327 328 typedef enum _TSP_HAL_FileState 329 { 330 /// Command Queue is Idle 331 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 332 /// Command Queue is Busy 333 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 334 /// Command Queue is Paused. 335 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 336 337 E_TSP_HAL_FILE_STATE_INVALID, 338 }TSP_HAL_FileState; 339 340 typedef enum 341 { 342 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 343 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 344 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 345 346 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 347 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 348 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 349 350 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 351 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 352 353 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 354 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 355 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 356 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 357 358 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 359 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 360 361 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 362 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 363 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 364 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 365 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 366 367 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 368 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 369 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 370 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 371 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 372 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 373 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 374 375 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 376 377 //27 is reserved, and can not be used 378 379 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 380 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 381 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 382 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 383 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 384 385 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 386 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 387 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 388 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 389 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 390 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 391 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 392 E_TSP_HAL_CAP_FIQ_NUM = 40, 393 E_TSP_HAL_CAP_TYPE_NULL, 394 } TSP_HAL_CAP_TYPE; 395 396 // @F_TODO remove unused enum member 397 typedef enum 398 { 399 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), // 94-1 = 93 400 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), // 62-1 = 61 401 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), // 62-1 = 61 402 403 E_TSP_HAL_CAP_VAL_RECENG_NUM = 2, 404 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, // 96-2 = 94 405 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, // 96 406 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, // 94 407 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 408 409 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 410 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 411 412 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 413 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 1, //internal demod 414 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 2, 415 E_TSP_HAL_CAP_VAL_VQ_NUM = 3, 416 417 E_TSP_HAL_CAP_VAL_CAFLT_NUM = 0xDEADBEEF, //@TODO don't know this value 418 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 419 420 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 421 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 422 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 423 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 424 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 425 426 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 427 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 428 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 429 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 430 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 431 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 432 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 433 434 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 435 436 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 2, 437 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 2, 438 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 439 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 440 441 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 442 443 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 444 } TSP_HAL_CAP_VAL; 445 446 /// TSP TEI Remove Error Packet Infomation 447 typedef enum 448 { 449 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 450 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 451 452 }TSP_HAL_TEI_RmPktType; 453 454 /// TSP Packet Converter Input Mode 455 typedef enum 456 { 457 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 458 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 459 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 460 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 461 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 462 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 463 E_TSP_HAL_PKT_MODE_MXL_200 ///< MXL mode (200 bytes) 464 465 }TSP_HAL_PKT_MODE; 466 467 // TSP TimeStamp Clk Select 468 typedef enum 469 { 470 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 471 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 472 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 473 474 } TSP_HAL_TimeStamp_Clk; 475 476 //---------------------------------- 477 /// DMX debug table information structure 478 //---------------------------------- 479 480 typedef enum 481 { 482 E_TSP_HAL_FLOW_LIVE0, 483 E_TSP_HAL_FLOW_LIVE1, 484 E_TSP_HAL_FLOW_LIVE2, 485 E_TSP_HAL_FLOW_LIVE3, 486 E_TSP_HAL_FLOW_LIVE4, // not support 487 E_TSP_HAL_FLOW_LIVE5, // not support 488 E_TSP_HAL_FLOW_LIVE6, // not support 489 490 E_TSP_HAL_FLOW_FILE0, 491 E_TSP_HAL_FLOW_FILE1, 492 E_TSP_HAL_FLOW_FILE2, 493 E_TSP_HAL_FLOW_FILE3, 494 E_TSP_HAL_FLOW_FILE4, // not support 495 E_TSP_HAL_FLOW_FILE5, // not support 496 E_TSP_HAL_FLOW_FILE6, // not support 497 498 E_TSP_HAL_FLOW_MMFI0, 499 E_TSP_HAL_FLOW_MMFI1, 500 501 E_TSP_HAL_FLOW_INVALID, 502 503 } TSP_HAL_FLOW; 504 505 506 //-------------------------------------------------------------------------------------------------- 507 // PVR HAL API 508 //-------------------------------------------------------------------------------------------------- 509 // Static Register Mapping for external access 510 #define REG_PIDFLT_BASE0 (0x00240000UL) 511 #define REG_PIDFLT_BASE1 (0x00241000UL) 512 #define REG_SECFLT_BASE (0x00221000UL) 513 #define REG_SECBUF_BASE (0x00221024UL) 514 #define REG_CTRL_BASE (0x00210200UL) 515 516 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 517 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 518 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 519 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 520 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 521 522 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 523 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 524 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE)->Flt[_fltid])) 525 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE)->Buf[_bufid])) 526 527 #define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 528 529 #define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 530 531 532 533 //******************** PIDFLT DEFINE START ********************// 534 // PID 535 #define TSP_PIDFLT_PID_MASK 0x00001FFF 536 #define TSP_PIDFLT_PID_SHFT 0 537 538 // Continuous counter 539 #define TSP_PIDFLT_CC_MASK 0xFF000000 540 #define TSP_PIDFLT_CC_SHFT 24 541 542 // PIDFLT SRC 543 typedef enum _TSP_PIDFLT_SRC 544 { 545 E_TSP_PIDFLT_LIVE0, 546 E_TSP_PIDFLT_LIVE1, 547 E_TSP_PIDFLT_LIVE2, 548 E_TSP_PIDFLT_LIVE3, 549 E_TSP_PIDFLT_LIVE4, 550 E_TSP_PIDFLT_LIVE5, 551 E_TSP_PIDFLT_LIVE6, 552 E_TSP_PIDFLT_FILE0, 553 E_TSP_PIDFLT_FILE1, 554 E_TSP_PIDFLT_FILE2, 555 E_TSP_PIDFLT_FILE3, 556 E_TSP_PIDFLT_FILE4, 557 E_TSP_PIDFLT_FILE5, 558 E_TSP_PIDFLT_FILE6, 559 E_TSP_PIDFLT_INVALID, 560 } TSP_PIDFLT_SRC; 561 562 #define TSP_PIDFLT_IN_MASK 0x0000E000 563 #define TSP_PIDFLT_TSIF_SHFT 13 564 #define TSP_PIDFLT_TSIF0 0x00 565 #define TSP_PIDFLT_TSIF1 0x01 566 #define TSP_PIDFLT_TSIF2 0x02 567 #define TSP_PIDFLT_TSIF3 0x03 568 #define TSP_PIDFLT_TSIF_MAX 0x04 569 570 // Section filter Id (0~63) 571 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 572 #define TSP_PIDFLT_SECFLT_SHFT 0 573 574 // PIDFLT DST 575 typedef enum _TSP_PIDFLT_DST 576 { 577 E_TSP_PIDFLT_DST_VIDEO, 578 E_TSP_PIDFLT_DST_AUDIO, 579 E_TSP_PIDFLT_DST_PVR, 580 581 E_TSP_PIDFLT_DST_INVALID, 582 } TSP_PIDFLT_DST; 583 584 // AF/Sec/Video/V3D/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 585 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 586 #define TSP_PIDFLT_OUT_MASK 0x001FBF00 587 #define TSP_PIDFLT_OUT_SHFT 8 588 #define TSP_PIDFLT_OUT_NONE 0x00000000 589 #define TSP_PIDFLT_OUT_SECAF 0x00000100 590 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 591 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 592 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 593 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 594 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 595 #define TSP_PIDFLT_OUT_VFIFO3 0x00000000 //Not Support 596 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 597 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 598 #define TSP_PIDFLT_OUT_VFIFO4 0x00000000 //Not Support 599 600 // SRC ID 601 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 602 #define TSP_PIDFLT_SRCID_SHIFT 28 603 604 //enable LUT 605 #define TSP_PIDFLT_OUT_LUT 0x00000000 //Not support 606 607 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 608 #define TSP_PIDFLT_PVRFLT_SHFT 15 609 #define TSP_PIDFLT_OUT_PVR1 0x00008000 610 #define TSP_PIDFLT_OUT_PVR2 0x00010000 611 #define TSP_PIDFLT_OUT_PVR3 0x00020000 612 #define TSP_PIDFLT_OUT_PVR4 0x00040000 613 614 615 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 616 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 617 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 618 619 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 620 #define TSP_PIDFLT_TSOFLT_SHFT 22 621 #define TSP_PID_FLT_OUT_TSO0 0x00400000 622 623 //******************** PIDFLT DEFINE END ********************// 624 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 625 MS_U32 TSP32_IdrR(TSP32 *preg); 626 627 //=========================TSIF================================ 628 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 629 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 630 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 631 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 632 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 633 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 634 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 635 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 636 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 637 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 638 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 639 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 640 void HAL_TSP_GetTSIF_Status(MS_U32 u32TsIfId, TSP_TS_PAD* pePad, MS_U16* pu16Clk, MS_BOOL* pbClkInv, MS_BOOL* pbExtSync, MS_BOOL* pbParl); 641 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 642 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 643 644 //=========================TSP================================ 645 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 646 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 647 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 648 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 649 void HAL_TSP_Reset(MS_BOOL bEn); 650 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 651 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 652 void HAL_TSP_Power(MS_BOOL bEn); 653 void HAL_TSP_CPU(MS_BOOL bEn); 654 void HAL_TSP_ResetCPU(MS_BOOL bReset); 655 void HAL_TSP_HwPatch(void); 656 void HAL_TSP_RestoreFltState(void); 657 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 658 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 659 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 660 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 661 void HAL_TSP_SaveFltState(void); 662 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 663 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 664 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 665 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 666 667 //=========================TSO================================ 668 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 669 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 670 671 //=========================Filein================================ 672 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 673 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 674 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 675 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 676 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 677 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 678 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 679 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 680 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 681 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 682 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 683 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 684 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 685 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 686 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 687 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 688 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 689 690 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 691 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 692 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 693 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 694 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 695 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 696 /* 697 // Only used by [HW test code] 698 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 699 */ 700 701 //=========================PCR FLT================================ 702 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 703 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 704 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 705 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 706 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 707 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 708 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 709 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 710 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId); 711 712 //=========================STC================================ 713 void HAL_TSP_STC_Init(void); 714 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 715 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 716 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 717 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 718 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 719 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 720 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 721 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 722 723 //=========================FIFO================================ 724 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 725 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 726 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 727 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 728 void HAL_TSP_FIFO_ClearAll (void); 729 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 730 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 731 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 732 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 733 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 734 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 735 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 736 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 737 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 738 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 739 void HAL_TSP_PS_SRC(MS_U32 tsIf); 740 //void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 741 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bEnable);// for PS mode A/V fifo pull back 742 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 743 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 744 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 745 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 746 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 747 748 //=========================VQ================================ 749 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 750 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 751 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 752 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 753 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 754 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 755 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 756 757 //=========================Pid Flt================================ 758 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 759 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 760 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 761 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 762 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 763 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 764 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 765 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 766 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 767 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 768 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 769 770 //=========================SecFlt================================ 771 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 772 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 773 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 774 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 775 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 776 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 777 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 778 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 779 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 780 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 781 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 782 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 783 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 784 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 785 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 786 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 787 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 788 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 789 790 //=========================Sec Buf================================ 791 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 792 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 793 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 794 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 795 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 796 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 797 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 798 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 799 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 800 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 801 802 //=========================PVR================================ 803 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 804 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 805 void HAL_PVR_Exit(MS_U32 u32PVREng); 806 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 807 /* 808 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 809 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 810 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 811 */ 812 void HAL_PVR_FlushData(MS_U32 u32PVREng); 813 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 814 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 815 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 816 void HAL_PVR_Start(MS_U32 u32PVREng); 817 void HAL_PVR_Stop(MS_U32 u32PVREng); 818 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 819 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 820 void HAL_PVR_RecNull(MS_BOOL bSet); 821 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 822 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 823 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 824 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 825 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 826 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 827 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 828 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 829 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 830 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 831 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 832 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 833 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 834 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 835 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 836 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 837 /* 838 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 839 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 840 */ 841 842 //=========================RASP================================ 843 MS_U32 HAL_RASP_Set_Source(MS_U32 u32RASPEng, MS_U32 pktDmxId); 844 MS_U32 HAL_RASP_Get_Source(MS_U32 u32RASPEng, TSP_SRC_SEQ *eSrc); 845 846 //=========================FQ================================ 847 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 848 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 849 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 850 851 //=========================HCMD================================ 852 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 853 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 854 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 855 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 856 MS_BOOL HAL_TSP_HCMD_Alive(void); 857 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 858 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 859 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 860 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 861 862 //=========================INT================================ 863 void HAL_TSP_INT_Enable(MS_U32 u16Mask); 864 void HAL_TSP_INT_Disable(MS_U32 u16Mask); 865 void HAL_TSP_INT_ClrHW(MS_U32 u16Mask); 866 MS_U32 HAL_TSP_INT_GetHW(void); 867 void HAL_TSP_INT_ClrSW(void); 868 MS_U32 HAL_TSP_INT_GetSW(void); 869 870 //=========================Mapping================================ 871 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 872 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 873 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 874 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 875 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 876 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 877 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 878 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng); 879 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 880 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 881 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 882 883 //========================DSCMB Functions=================================== 884 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 885 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 886 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 887 888 //========================MOBF Functions===================================== 889 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 890 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 891 892 //========================Protection range=================================== 893 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 894 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 895 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 896 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 897 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 898 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 899 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 900 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 901 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 902 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 903 904 //========================Debug table============================= 905 // @TODO Renaming Load and Get 906 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 907 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 908 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock); 909 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 910 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 911 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 912 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 913 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 914 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 915 916 // @TODO Implement Drop and Dis Hal 917 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 918 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 919 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 920 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 921 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 922 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 923 924 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 925 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 926 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 927 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 928 929 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 930 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 931 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 932 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 933 934 //========================MergeStream Functions============================= 935 void HAL_TSP_PktConverter_Init(void); 936 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 937 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SrcId, MS_BOOL bSet); 938 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SyncByte, MS_BOOL bSet); 939 /* 940 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 941 */ 942 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 943 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 944 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 945 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path); 946 947 948 #endif // #ifndef __HAL_PVR_H__ 949