1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halPVR.c
20 // @brief PVR HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "halCHIP.h"
25 #include "regTSP.h"
26 #include "halTSP.h"
27 #include "drvSYS.h"
28
29
30 //--------------------------------------------------------------------------------------------------
31 // Driver Compiler Option
32 //--------------------------------------------------------------------------------------------------
33
34
35 //--------------------------------------------------------------------------------------------------
36 // TSP Hardware Abstraction Layer
37 //--------------------------------------------------------------------------------------------------
38 MS_VIRT _u32RegBase = 0;
39
40 static REG_Ctrl* _RegCtrl = NULL;
41 static REG_Ctrl2* _RegCtrl2 = NULL;
42 static REG_Ctrl3* _RegCtrl3 = NULL;
43 static REG_Ctrl4* _RegCtrl4 = NULL;
44 static REG_Ctrl5* _RegCtrl5 = NULL;
45 static REG_Ctrl6* _RegCtrl6 = NULL;
46 static REG_Ctrl7* _RegCtrl7 = NULL;
47 static REG_Ctrl8* _RegCtrl8 = NULL;
48
49
50
51 // @F_TODO These parameters need to be combined with global variables in Utopia 2.0
52 static MS_U32 _u32PidFltReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
53 static MS_U32 _u32PidDstReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
54 static MS_U32 _u32SecReg[(TSP_SECFLT_NUM * ((sizeof(REG_SecFlt) - sizeof(((REG_SecFlt*)0)->_x50))/sizeof(TSP32)))];
55
56
57 //-------------------------------------------------------------------------------------------------
58 // Local Functions
59 //-------------------------------------------------------------------------------------------------
60 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value);
61
_delay(MS_U32 usec)62 static void _delay(MS_U32 usec)
63 {
64 MsOS_DelayTaskUs_Poll(usec);
65 }
66
REG32_R(REG32 * reg)67 static MS_U32 REG32_R(REG32 *reg)
68 {
69 MS_U32 value = 0;
70 value = (reg)->low;
71 value |= (reg)->high << 16;
72 return value;
73 }
74
75
REG16_R(REG16 * reg)76 static MS_U16 REG16_R(REG16 *reg)
77 {
78 MS_U16 value = 0;
79 value = (reg)->data;
80 return value;
81 }
82
83 static MS_BOOL _u32RegDump = 0;
84 static void _REG32_DUMP(REG32 * reg, MS_U32 value );
85 static void _REG16_DUMP(REG16 * reg, MS_U16 value);
86
87 #if 0
88 #define REG32_W(reg, value); { (reg)->low = ((value) & 0x0000FFFF); \
89 (reg)->high = ((value) >> 16);\
90 if(_u32RegDump)\
91 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n", (((MS_U32)(&(reg)->low) - _u32RegBase)>>(1+8)), ((((MS_U32)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1,(value) & 0x0000FFFF);\
92 printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)(&(reg)->high) - _u32RegBase)>>(1+8)),((((MS_U32)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1, (value) >> 16);}}
93
94 #define REG16_W(reg, value); {(reg)->data = ((value) & 0x0000FFFF);\
95 if(_u32RegDump)\
96 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)reg) - _u32RegBase)>>(1+8), ((((MS_U32)reg - _u32RegBase)>>1)&0xFF)>>1, (value) & 0x0000FFFF);}}
97 #endif
98 #define REG32_W(reg, value) { (reg)->low = ((value) & 0x0000FFFF); \
99 (reg)->high = ((value) >> 16);\
100 if(_u32RegDump){_REG32_DUMP(reg, value);}}
101
102 #define REG16_W(reg, value) {(reg)->data = ((value) & 0x0000FFFF);\
103 if(_u32RegDump){_REG16_DUMP(reg, value);}}
104
105
106 #define _AND_(flag, bit) ((flag) & (bit) )
107
108 #define _SET_(flag, bit) ((flag) | (bit) )
109 #define _CLR_(flag, bit) ((flag) & (~(bit)))
110
111 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value))
112 #define REG32_SET(reg, value) REG32_W(reg, _SET_(REG32_R(reg), value))
113 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value))
114 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value))
115
116 #define REG16_MSK_W(reg, mask, value) REG16_W((reg), _CLR_(REG16_R(reg), (mask)) | _AND_((value), (mask)))
117 #define REG32_MSK_W(reg, mask, value) REG32_W((reg), _CLR_(REG32_R(reg), (mask)) | _AND_((value), (mask)))
118
119 #define MIU_BUS (4)
120
121
122 //-------------------------------------------------------------------------------------------------
123 // Debug Message
124 //-------------------------------------------------------------------------------------------------
125 typedef enum
126 {
127 E_HAL_TSP_DBG_LEVEL_NONE, // no debug message shown
128 E_HAL_TSP_DBG_LEVEL_ERR, // only shows error message that can't be recover
129 E_HAL_TSP_DBG_LEVEL_WARN, // error case can be recover, like retry
130 E_HAL_TSP_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
131 E_HAL_TSP_DBG_LEVEL_INFO, // information for internal parameter
132 E_HAL_TSP_DBG_LEVEL_FUNC, // Function trace and input parameter trace
133 E_HAL_TSP_DBG_LEVEL_TRACE, // debug trace
134 } EN_HAL_TSP_DBGMSG_LEVEL;
135
136 typedef enum
137 {
138 E_HAL_TSP_DBG_MODEL_NONE, // @temporarily , need to refine
139 E_HAL_TSP_DBG_MODEL_ALL,
140 } EN_HAL_TSP_DBGMSG_MODEL;
141
142 #define HAL_TSP_DBGMSG(_level,_model,_f) do {if(_u32TSPDbgLevel >= (_level)&&((_u32TSPDbgModel&_model)!=0)) (_f);} while(0)
143 static MS_U32 _u32TSPDbgLevel = E_HAL_TSP_DBG_LEVEL_ERR;
144 static MS_U32 _u32TSPDbgModel = E_HAL_TSP_DBG_MODEL_ALL;
145
146
147 //--------------------------------------------------------------------------------------------------
148 // Implementation
149 //--------------------------------------------------------------------------------------------------
TSP32_IdrW(TSP32 * preg,MS_U32 value)150 void TSP32_IdrW(TSP32 *preg, MS_U32 value)
151 {
152 MS_U32 tempDump = _u32RegDump;
153 if(_u32RegDump)
154 {
155 //test_chip_top.write_ind32('h00221004, 32'hffffffff); //indirect .... (address,data)
156 _u32RegDump = 0;
157 printf("test_chip_top.write_ind32(\'h%08lx, 32\'h%08lx);\n", (long unsigned int)preg, (long unsigned int)value);
158 }
159 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
160 REG32_W(&_RegCtrl->Idr_Write, value);
161 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE);
162 _u32RegDump = tempDump;
163 }
164
TSP32_IdrR(TSP32 * preg)165 MS_U32 TSP32_IdrR(TSP32 *preg)
166 {
167 MS_U32 tempDump = _u32RegDump;
168 if(_u32RegDump)
169 {
170 _u32RegDump = 0;
171 }
172 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
173 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ);
174 _u32RegDump = tempDump;
175 return REG32_R(&_RegCtrl->Idr_Read);
176 }
177
HAL_TSP_SetBank(MS_VIRT u32BankAddr)178 void HAL_TSP_SetBank(MS_VIRT u32BankAddr)
179 {
180 _u32RegBase = u32BankAddr;
181 _RegCtrl = (REG_Ctrl*)(u32BankAddr + 0x2A00UL); //TSP0 0x1015, TSP1 0x1016
182 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); //TSP3 0x1702,
183 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); //TSP4 0x1703
184 _RegCtrl4 = (REG_Ctrl4*)(u32BankAddr + 0xC2000UL); //TSP6 0x1610
185 _RegCtrl5 = (REG_Ctrl5*)(u32BankAddr + 0xC2200UL); //TSP7 0x1611
186 _RegCtrl6 = (REG_Ctrl6*)(u32BankAddr + 0xC4E00UL); //TSP8 0x1627
187 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); //TSP9 0x170C
188 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); //TSP10 0x170D
189 }
190
HAL_TSP_RegDump(MS_BOOL bEnable)191 void HAL_TSP_RegDump(MS_BOOL bEnable)
192 {
193 _u32RegDump = bEnable;
194 }
195 #if 1
_REG32_DUMP(REG32 * reg,MS_U32 value)196 static void _REG32_DUMP(REG32* reg, MS_U32 value )
197 {
198 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7�h06 ....reg ,16�h400a ......
199 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7�h06 ....reg ,16�h400a ......
200 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
201 MS_U32 bank = ((MS_VIRT)(&(reg)->low) - _u32RegBase)>>(1+8);
202 MS_U32 addr_low = ((((MS_VIRT)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1;
203 MS_U32 addr_high = ((((MS_VIRT)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1;
204 MS_U32 val_low = (value) & 0x0000FFFF;
205 MS_U32 val_high = ((value) & 0xFFFF0000 )>>16;
206
207 if(bank == 0x15)
208 {
209 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
210 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
211 }
212 else if(bank == 0x16)
213 {
214 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
215 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
216 }
217 else if(bank == 0x38)
218 {
219 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
220 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
221 }
222 }
_REG16_DUMP(REG16 * reg,MS_U16 value)223 static void _REG16_DUMP(REG16* reg, MS_U16 value )
224 {
225 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7�h06 ....reg ,16�h400a ......
226 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7�h06 ....reg ,16�h400a ......
227 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
228 MS_U32 bank = ((MS_VIRT)(&(reg)) - _u32RegBase)>>(1+8);
229 MS_U32 addr = ((((MS_VIRT)(&(reg)) - _u32RegBase)>>1)&0xFF)>>1;
230 MS_U32 val = (value) & 0x0000FFFF;
231
232 if(bank == 0x15)
233 {
234 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
235 }
236 else if(bank == 0x16)
237 {
238 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
239 }
240 else if(bank == 0x38)
241 {
242 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
243 }
244 }
245 #endif
246
HAL_TSP_HwPatch(void)247 void HAL_TSP_HwPatch(void)
248 {
249 //For sram
250 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE);
251 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
252
253 // @F_TODO check these setting with Stephen
254 // TSP_HW_CFG4_WSTAT_CH_EN <--this is bit disable HW sync section buf id with section filter id
255 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WSTAT_CH_EN);
256
257 // Bad initial value of TSP_CTRL1
258 // Suppose Standby mode for TSP should NOT be enabled.
259 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
260 // Disable it by SW at this stage.
261 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);
262
263 //enable PVR record to bypass header
264 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2);
265 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC);
266 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC);
267
268 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
269
270 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN*/);
271
272 //Disable all live pathes block mechanism
273 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_VQTX3_BLOCK_DIS*/);
274 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH);
275
276 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode
277
278 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
279 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD);
280 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP);
281
282 //Disable pvr1 & pvr2 block mechanism
283 //DisableAV FIFO block mechanism for live path
284 //REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLOCK_DIS|TSP_V_BLOCK_DIS|TSP_A_BLOCK_DIS|TSP_AD_BLOCK_DIS); // by angie
285
286 //fix load fw secure issue (dma_start = 1 , polling dma_done , dma_start = 0)
287 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW);
288
289 //Internal Sync Patch
290 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T);
291
292 //Fixed filein_192+timer_en+byte_time=0 Error
293 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN);
294
295 //Fixed filein_192 timestamp & LPCR ring back first issue
296 //REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_TIMESTAMP_RING_BACK_EN | FIXED_LPCR_RING_BACK_EN);
297
298 //ECO bit for miu flush
299 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_DMA_WADDR_NEXT_OVF | FIXED_VQ_MIU_REQ_FLUSH);
300
301 //drop start code error
302 REG16_SET(&_RegCtrl6->CFG6_2A, TSP_DROP_ERR_START_CODE | TSP_DROP_TEI_ERR_START_CODE);
303
304 REG16_SET(&_RegCtrl6->CFG6_2A,TSP_FIQ_DMA_FLUSH_EN | TSP_FIND_LOSS_SYNC_PID_RVU);
305
306 //FIQ ECO and block-reverse
307 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_FIQ_INPUT | TSP_ECO_TS_SYNC_OUT_DELAY | TSP_ECO_TS_SYNC_OUT_REVERSE_BLOCK);
308
309 //serial mode config
310 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT | TSP_VALID_FALLING_DETECT);
311 }
312
313 // ------------ initial config ------------
314 // Sync Byte: 0x47 , 0x48 .... , 0x4e
315 // Source id : 0 , 1 , ... , 7
316 // User can use "HAL_TSP_PktConverter_SetSyncByte()" to change Sync Byte configuration
317 // , and use "HAL_TSP_PktConverter_SetSrcId()" to change Source id configuration
HAL_TSP_PktConverter_Init(void)318 void HAL_TSP_PktConverter_Init(void)
319 {
320 MS_U8 u8Path,u8Id;
321 MS_U8 u8SyncByte;
322
323 for(u8Path = 0; u8Path < TSP_TSIF_NUM; ++u8Path)
324 {
325 HAL_TSP_PktConverter_ForceSync(u8Path,TRUE);//default: FALSE
326
327 u8SyncByte = 0x47;
328 for(u8Id = 0; u8Id < TSP_MERGESTREAM_NUM; ++u8Id,++u8SyncByte)
329 {
330 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Id, &u8SyncByte, TRUE);
331 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Id, &u8Id, TRUE);
332 }
333 }
334 }
335
HAL_TSP_Reset(MS_BOOL bEn)336 void HAL_TSP_Reset(MS_BOOL bEn)
337 {
338 //MS_U16 reg;
339
340 if (bEn)
341 {
342 #if 0
343
344 // WB DMA source won't be reset by SW_RST bit so we use HWPATCH to make it's source to default
345 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
346 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
347
348 #endif
349 // reset CMDQ for tsif 0~3
350 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
351 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
352 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
353 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
354 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
355 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
356 }
357 else
358 {
359 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
360
361 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
362 // set CMDQ for tsif 0~3
363 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
364 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
365 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
366 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
367 }
368 }
369
370
HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)371 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)
372 {
373 switch(tsIf)
374 {
375 case 0: if(bEn)
376 {
377 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
378 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
379 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
380 }
381 else
382 {
383 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
384 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
385 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
386 }
387 break;
388 case 1: if(bEn)
389 {
390 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
391 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
392 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
393 }
394 else
395 {
396 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
397 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
398 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
399 }
400 break;
401 case 2: if(bEn)
402 {
403 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
404 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
405 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
406 }
407 else
408 {
409 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
410 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
411 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
412 }
413 break;
414 default: break;
415 }
416 }
417 /*****************/
418
HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType,MS_U8 u8Index,ST_TSP_HAL_CLK_STATUS * pstClkStatus)419 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus)
420 {
421 switch(eClkType)
422 {
423 case E_TSP_HAL_TSP_CLK:
424 pstClkStatus->bEnable = !(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_DISABLE);
425 pstClkStatus->bInvert = !!(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_INVERT);
426 pstClkStatus->u8ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_CLK_MASK) >> REG_CLKGEN0_TSP_SRC_SHIFT;
427 break;
428 default:
429 return FALSE;
430 }
431
432 return TRUE;
433 }
434
HAL_TSP_Power(MS_BOOL bEn)435 void HAL_TSP_Power(MS_BOOL bEn)
436 {
437 if(bEn)
438 {
439
440 //disable MCM
441 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE); //TSP
442 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_MMFI1_REQ_MCM_DISABLE); // disable MMFI1 MCM, and never enable it, only for Curry
443
444 // Enable TSP Clk
445 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & ~REG_CLKGEN0_TSP_CLK_MASK)
446 | (REG_CLKGEN0_TSP_SRC_192MHZ << REG_CLKGEN0_TSP_SRC_SHIFT);
447 // Enable STC1,2 Clk
448 // STC1
449 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) & ~REG_CLKGEN0_STC0_MASK)
450 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT));
451 // STC2
452 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) & ~REG_CLKGEN0_STC1_MASK)
453 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT));
454
455 // Stamp
456 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) & ~REG_CLKGEN0_STAMP_MASK);
457
458 // Parser
459 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = ((TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) & ~REG_CLKGEN0_PARSER_MASK) | REG_CLKGEN0_PARSER_192);
460
461 // Enable TSIF => Disable TSIF
462 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
463 //TS0
464 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK);
465
466 //TS1
467 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS1_SHIFT));
468
469 //TS2
470 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS2_SHIFT));
471 // TSP Boot clk sel
472 TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) = (TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) & ~REG_TOP_TSP_BOOT_CLK_SEL_MASK) | REG_TOP_TSP_BOOT_CLK_SEL_TSP;
473
474 // TSP SRAM sel
475 TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) = TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) | REG_MMFI_TSP_SEL_SRAM_EN;
476
477 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
478 }
479 else
480 {
481 // Disable TSP Clk
482 // [2016.03.10] Disable TSP clk for power problem. If AESDMA share clk with TSP. Need to do tsp init before using AESDMA.
483 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK),(REG_CLKGEN0_TSP_DISABLE << REG_CLKGEN0_TSP_SHIFT));
484
485 // Disable STC Clk
486 //STC0
487 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC0_SHIFT));
488 //STC1
489 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC1_SHIFT));
490
491 // Stamp
492 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK),(REG_CLKGEN0_STAMP_DISABLE << REG_CLKGEN0_STAMP_SHIFT));
493
494 // Parser
495 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK),(REG_CLKGEN0_PARSER_DISABLE << REG_CLKGEN0_PARSER_SHIFT));
496
497 // Disable TSIF clk
498 //TS0
499 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS0_SHIFT));
500 //TS1
501 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS1_SHIFT));
502 //TS2
503 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS2_SHIFT));
504
505 //enable MCM
506 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
507 }
508 }
509
HAL_TSP_CPU(MS_BOOL bEn)510 void HAL_TSP_CPU(MS_BOOL bEn)
511 {
512 if (bEn)
513 {
514 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
515 }
516 else
517 {
518 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
519 }
520 }
HAL_TSP_ResetCPU(MS_BOOL bReset)521 void HAL_TSP_ResetCPU(MS_BOOL bReset)
522 {
523 // @NOTE TRUE for stop cpu clock
524 if (bReset)
525 {
526 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
527 }
528 else
529 {
530 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
531 }
532 }
533
534
HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr,MS_U32 u32FwSize)535 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize)
536 {
537
538 #define _TSP_QMEM_I_MASK 0xffffc000 //code: 0x2000, data: 0x1000, total: 0x3000
539 #define _TSP_QMEM_I_ADDR_HIT 0x00000000
540 #define _TSP_QMEM_I_ADDR_MISS 0xffffffff
541 #define _TSP_QMEM_D_MASK 0xffffc000
542 #define _TSP_QMEM_D_ADDR_HIT 0x00000000
543 #define _TSP_QMEM_D_ADDR_MISS 0xffffffff
544 #define _TSP_QMEM_SIZE 0x1000 // 16K bytes, 32bit aligment //0x4000 this is 4 byte address
545
546 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit
547
548 MS_U32 u32DnldCtrl = 0;
549 MS_U32 u32DnldCtrl1 = 0;
550
551 u32DnldCtrl = (u32FwPhyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;
552 u32DnldCtrl1 = u32DnldCtrl >> 16;
553
554 REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register
555 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1);
556 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE);
557 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
558 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START);
559
560 //@TODO temprarily comment because of Secure Protect
561 #if 1
562 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE))
563 {
564 }
565 #endif
566
567
568 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
569
570 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK);
571 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT);
572 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK);
573 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT);
574
575 #undef _TSP_QMEM_I_MASK
576 #undef _TSP_QMEM_I_ADDR_HIT
577 #undef _TSP_QMEM_I_ADDR_MISS
578 #undef _TSP_QMEM_D_MASK
579 #undef _TSP_QMEM_D_ADDR_HIT
580 #undef _TSP_QMEM_D_ADDR_MISS
581 #undef _TSP_QMEM_SIZE
582
583 return TRUE;
584 }
585
HAL_TSP_RestoreFltState(void)586 void HAL_TSP_RestoreFltState(void)
587 {
588 MS_U32 u32Size;
589 TSP32 * pRegEnd;
590 TSP32 * pReg;
591 int i, j;
592
593 for (i = 0; i < TSP_PIDFLT_NUM; i++)
594 {
595 TSP32_IdrW(&(_REGPid0->Flt[i]), _u32PidFltReg[i]);
596 TSP32_IdrW(&(_REGPid1->Flt[i]), _u32PidDstReg[i]);
597 }
598
599 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
600
601 for (i = 0; i < TSP_SECFLT_NUM; i++)
602 {
603 pReg = (TSP32*)&(_REGSec->Flt[i]);
604 pRegEnd = pReg + u32Size;
605 j = 0;
606 for ( ; pReg < pRegEnd; pReg++)
607 {
608 TSP32_IdrW(pReg, _u32SecReg[i*u32Size+j]);
609 j++;
610 }
611 }
612
613 }
614
HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)615 void HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
616 {
617 if(bEn)
618 {
619 switch(pktDmxId)
620 {
621 case 0:
622 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
623 break;
624 case 1:
625 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
626 break;
627 case 2:
628 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
629 break;
630 default:
631 break;
632 }
633 }
634 else
635 {
636 switch(pktDmxId)
637 {
638 case 0:
639 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
640 break;
641 case 1:
642 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
643 break;
644 case 2:
645 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
646 break;
647 default:
648 break;
649 }
650 }
651 }
652
HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)653 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
654 {
655 if(bEn)
656 {
657 switch(pktDmxId)
658 {
659 case 0:
660 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
661 break;
662 case 1:
663 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
664 break;
665 case 2:
666 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
667 break;
668 default:
669 break;
670 }
671 }
672 else
673 {
674 switch(pktDmxId)
675 {
676 case 0:
677 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
678 break;
679 case 1:
680 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
681 break;
682 case 2:
683 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
684 break;
685 default:
686 break;
687 }
688 }
689 }
690
HAL_TSP_SetTSIF(MS_U16 u16TSIF,TSP_TSIF_CFG u16Cfg,MS_BOOL bFileIn)691 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn)
692 {
693 if(bFileIn)
694 {
695 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, TRUE); // this returns true only we don't check the return value
696 HAL_TSP_TSIF_LiveEn(u16TSIF, FALSE); // this returns true only we don't check the return value
697 }
698 else
699 {
700 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, FALSE);
701 HAL_TSP_TSIF_LiveEn(u16TSIF, TRUE);
702 }
703
704 if(bFileIn != TRUE)
705 {
706 HAL_TSP_TSIF_BitSwap(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_BITSWAP)?TRUE:FALSE));
707 HAL_TSP_TSIF_ExtSync(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_EXTSYNC)?TRUE:FALSE));
708 HAL_TSP_TSIF_Parl (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_PARA )?TRUE:FALSE));
709 HAL_TSP_TSIF_3Wire (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_3WIRE )?TRUE:FALSE));
710 }
711
712 return TRUE;
713 }
714
HAL_TSP_TSIF_LiveEn(MS_U32 tsIf,MS_BOOL bEnable)715 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable)
716 {
717 if(bEnable)
718 {
719 switch(tsIf)
720 {
721 case 0:
722 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
723 break;
724 case 1:
725 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
726 break;
727 case 2:
728 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
729 break;
730 default:
731 return FALSE;
732 }
733 }
734 else
735 {
736 switch(tsIf)
737 {
738 case 0:
739 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
740 break;
741 case 1:
742 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
743 break;
744 case 2:
745 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
746 break;
747 default:
748 return FALSE;
749 }
750 }
751
752 return TRUE;
753 }
754
HAL_TSP_TSIF_SelPad(MS_U32 tsIf,TSP_TS_PAD eTSPad)755 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad) // @FIXME modify this parameter to enum plz
756 {
757 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
758 MS_U32 pad_src = REG_TOP_TS_SRC_EXT0;
759
760 //@NOTE
761 //EX3~6 are serial mode and ts2_padmax_mode must be 2 or 3.
762
763
764 switch (eTSPad)
765 {
766 default:
767 case E_TSP_TS_PAD_EXT0:
768 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
769 pad_src = REG_TOP_TS_SRC_EXT0;
770 break;
771 case E_TSP_TS_PAD_EXT1:
772 clk_src = REG_CLKGEN0_TS_SRC_EXT1;
773 pad_src = REG_TOP_TS_SRC_EXT1;
774 break;
775 case E_TSP_TS_PAD_INTER0:
776 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
777 pad_src = REG_TOP_TS_SRC_EXT0;
778 printf("[%s][%d]Warning KANO not support Internal Demod\n",__FUNCTION__,__LINE__);
779 break;
780 }
781 //@FIXME use enum instead of constant
782 switch (tsIf)
783 {
784 case 0:
785 TSP_TOP_REG(REG_TOP_TS0_MUX) = (TSP_TOP_REG(REG_TOP_TS0_MUX) & ~REG_TOP_TS_SRC_MASK) | (pad_src<<REG_TOP_TS0_SHIFT);
786 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK) | (clk_src<<(REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
787 break;
788 case 1:
789 TSP_TOP_REG(REG_TOP_TS1_MUX) = (TSP_TOP_REG(REG_TOP_TS1_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS1_SHIFT))
790 | (pad_src<<REG_TOP_TS1_SHIFT);
791 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT))
792 | (clk_src<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
793 break;
794 case 2:
795 TSP_TOP_REG(REG_TOP_TS2_MUX) = (TSP_TOP_REG(REG_TOP_TS2_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS2_SHIFT))
796 | (pad_src<<REG_TOP_TS2_SHIFT);
797 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT))
798 | (clk_src<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
799 break;
800 default:
801 return FALSE;
802 }
803 return TRUE;
804 }
805
HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)806 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)
807 {
808 return ;
809 }
810
HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad,TSP_TS_PAD_MUX_MODE eOutPadMode,TSP_TS_PAD eInPad,TSP_TS_PAD_MUX_MODE eInPadMode,MS_BOOL bEnable)811 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable)
812 {
813 return FALSE;
814 }
815
_TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad,MS_U32 * pu32PADSrc,MS_U32 * pu32CLKSrc)816 static MS_BOOL _TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad, MS_U32* pu32PADSrc, MS_U32* pu32CLKSrc)
817 {
818 switch (eTSPad)
819 {
820 case E_TSP_TS_PAD_EXT0:
821 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
822 *pu32PADSrc = REG_TOP_TS_SRC_EXT0;
823 break;
824 case E_TSP_TS_PAD_EXT1:
825 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT1;
826 *pu32PADSrc = REG_TOP_TS_SRC_EXT1;
827 break;
828 case E_TSP_TS_PAD_INTER0:
829 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_DMD0;
830 *pu32PADSrc = REG_TOP_TS_SRC_DMD0;
831 break;
832 default:
833 return FALSE;
834 }
835
836 return TRUE;
837 }
838
HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng,TSP_TS_PAD eTSPad)839 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad)
840 {
841 MS_U32 u32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
842 MS_U32 u32PADSrc = REG_TOP_TS_SRC_EXT0;
843 _TSP_Hal_TSPAD2RelatedReg_Mapping(eTSPad, &u32PADSrc, &u32CLKSrc);
844
845 switch(u32TSOEng)
846 {
847 case 0:
848 TSP_TOP_REG(REG_TOP_TSO0_MUX) = (TSP_TOP_REG(REG_TOP_TSO0_MUX) & ~REG_TOP_TS_SRC_MASK) | u32PADSrc;
849 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK)
850 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
851 return TRUE;
852
853 default:
854 return FALSE;
855 }
856 }
857
858
HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf,MS_BOOL bClkInv)859 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv)
860 {
861 if (bClkInv)
862 {
863 switch (tsIf)
864 {
865 case 0:
866 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
867 break;
868 case 1:
869 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
870 break;
871 case 2:
872 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
873 break;
874 default:
875 return FALSE;
876 }
877 }
878 else
879 {
880 switch (tsIf)
881 {
882 case 0:
883 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
884 break;
885 case 1:
886 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
887 break;
888 case 2:
889 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
890 break;
891 default:
892 return FALSE;
893 }
894 }
895 return TRUE;
896 }
897
HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf,MS_BOOL bClkDis)898 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis)
899 {
900 if (bClkDis)
901 {
902 switch (tsIf)
903 {
904 case 0:
905 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
906 break;
907 case 1:
908 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
909 break;
910 case 2:
911 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
912 break;
913 default:
914 return FALSE;
915 }
916 }
917 else
918 {
919 switch (tsIf)
920 {
921 case 0:
922 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
923 break;
924 case 1:
925 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
926 break;
927 case 2:
928 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
929 break;
930 default:
931 return FALSE;
932 }
933 }
934 return TRUE;
935 }
936
937 // @NOTE tsif0 and tsif2 can do filein and livein simulatenously,so tsif0 tsif2's output are both live TS Data
HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng,MS_BOOL bEnable)938 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
939 {
940 if(bEnable)
941 {
942 switch(eFileEng)
943 {
944 case E_FILEENG_TSIF0:
945 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firmware or playback)
946 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS
947 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable
948 break;
949 case E_FILEENG_TSIF1:
950 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firmware or playback) we don't use this fileEng for FW
951 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
952 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
953 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable
954 break;
955 case E_FILEENG_TSIF2:
956 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
957 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
958 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
959 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
960 break;
961 default:
962 return FALSE;
963 }
964 }
965 else
966 {
967 switch(eFileEng)
968 {
969 case E_FILEENG_TSIF0:
970 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
971 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL);
972 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN);
973 break;
974 case E_FILEENG_TSIF1:
975 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1);
976 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
977 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
978 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN);
979 break;
980 case E_FILEENG_TSIF2:
981 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
982 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
983 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
984 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
985 break;
986 default:
987 return FALSE;
988 }
989 }
990
991 return TRUE;
992 }
993
HAL_TSP_TSIF_BitSwap(MS_U32 tsIf,MS_BOOL bEnable)994 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable)
995 {
996 if(bEnable)
997 {
998 switch(tsIf)
999 {
1000 case 0:
1001 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1002 break;
1003 case 1:
1004 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1005 break;
1006 case 2:
1007 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1008 break;
1009 default:
1010 return;
1011 }
1012 }
1013 else
1014 {
1015 switch(tsIf)
1016 {
1017 case 0:
1018 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1019 break;
1020 case 1:
1021 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1022 break;
1023 case 2:
1024 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1025 break;
1026 default:
1027 return;
1028 }
1029 }
1030 }
1031
HAL_TSP_TSIF_ExtSync(MS_U32 tsIf,MS_BOOL bEnable)1032 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable)
1033 {
1034 if(bEnable)
1035 {
1036 printf("External Sync\n");
1037
1038 switch(tsIf)
1039 {
1040 case 0:
1041 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1042 break;
1043 case 1:
1044 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1045 break;
1046 case 2:
1047 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1048 break;
1049 default:
1050 return;
1051 }
1052 }
1053 else
1054 {
1055 printf("Internal Sync\n");
1056
1057 switch(tsIf)
1058 {
1059 case 0:
1060 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1061 break;
1062 case 1:
1063 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1064 break;
1065 case 2:
1066 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1067 break;
1068 default:
1069 return;
1070 }
1071 }
1072 }
1073
1074 //void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable)
HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1075 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1076 {
1077 if(bEnable)
1078 {
1079 switch(eFileEng)
1080 {
1081 case 0:
1082 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1083 break;
1084 case 1:
1085 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1086 break;
1087 case 2:
1088 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1089 break;
1090 default:
1091 return;
1092 }
1093
1094 REG16_MSK_W(&_RegCtrl3->CFG3_10,CFG3_10_PS_MODE_SRC_MASK,(eFileEng << CFG3_10_PS_MODE_SRC_SHIFT));
1095 }
1096 else
1097 {
1098 switch(eFileEng)
1099 {
1100 case 0:
1101 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1102 break;
1103 case 1:
1104 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1105 break;
1106 case 2:
1107 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1108 break;
1109 default:
1110 return;
1111 }
1112
1113 }
1114 }
1115
HAL_TSP_TSIF_Parl(MS_U32 tsIf,MS_BOOL bEnable)1116 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable)
1117 {
1118 if(bEnable)
1119 {
1120 switch(tsIf)
1121 {
1122 case 0:
1123 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1124 break;
1125 case 1:
1126 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1127 break;
1128 case 2:
1129 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1130 break;
1131 default:
1132 return;
1133 }
1134 }
1135 else
1136 {
1137 switch(tsIf)
1138 {
1139 case 0:
1140 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1141 break;
1142 case 1:
1143 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1144 break;
1145 case 2:
1146 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1147 break;
1148 default:
1149 return;
1150 }
1151 }
1152 }
1153
HAL_TSP_PAD_3Wire(MS_U32 u32Pad,MS_BOOL bEnable)1154 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable)
1155 {
1156 #if 0 //@NOTE: Kano do NOT need to set
1157 if(bEnable)
1158 {
1159 switch(u32Pad)
1160 {
1161 case 0:
1162 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS0_3WIRE_EN;
1163 break;
1164 case 1:
1165 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS1_3WIRE_EN;
1166 break;
1167 case 2:
1168 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1)| REG_TOP_TSP_TS2_3WIRE_EN;
1169 break;
1170 case 3:
1171 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) | REG_TOP_TSP_TS3_3WIRE_EN;
1172 break;
1173
1174 default:
1175 return;
1176 }
1177 }
1178 else
1179 {
1180 switch(u32Pad)
1181 {
1182 case 0:
1183 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS0_3WIRE_EN;
1184 break;
1185 case 1:
1186 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS1_3WIRE_EN;
1187 break;
1188 case 2:
1189 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) & ~REG_TOP_TSP_TS2_3WIRE_EN;
1190 break;
1191 case 3:
1192 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE1) & ~REG_TOP_TSP_TS3_3WIRE_EN;
1193 break;
1194 default:
1195 return;
1196 }
1197 }
1198 #endif
1199 }
1200
HAL_TSP_TSIF_3Wire(MS_U32 tsIf,MS_BOOL bEnable)1201 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable)
1202 {
1203 if(bEnable)
1204 {
1205 switch(tsIf)
1206 {
1207 case 0:
1208 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1209 break;
1210 case 1:
1211 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1212 break;
1213 case 2:
1214 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1215 break;
1216 default:
1217 return;
1218 }
1219 }
1220 else
1221 {
1222 switch(tsIf)
1223 {
1224 case 0:
1225 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1226 break;
1227 case 1:
1228 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1229 break;
1230 case 2:
1231 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1232 break;
1233 default:
1234 return;
1235 }
1236 }
1237
1238 }
1239
HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId,MS_BOOL bEn)1240 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn)
1241 {
1242 if(bEn)
1243 {
1244 REG16_SET(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
1245 }
1246 else
1247 {
1248 REG16_CLR(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
1249 }
1250 }
1251
HAL_TSP_ReDirect_File(MS_U32 reDir,MS_U32 tsIf,MS_BOOL bEn)1252 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn)
1253 {
1254 //@NOTE Not support in KANO(K7)
1255 #if 0
1256 MS_U16 u16Src = 0;
1257
1258 if((reDir > 0) || (tsIf > 1))
1259 return;
1260
1261 if(bEn)
1262 {
1263 u16Src = (MS_U16)(tsIf + 1) << CFG_01_PDFLT2_FILE_SRC_SHIFT;
1264 }
1265
1266 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src);
1267 #endif
1268 }
1269
HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)1270 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)
1271 {
1272 if(bEn)
1273 {
1274 switch(u32Tsif)
1275 {
1276 case 0:
1277 switch (eFltType)
1278 {
1279 case E_TSP_DST_FIFO_VIDEO:
1280 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
1281 break;
1282 case E_TSP_DST_FIFO_VIDEO3D:
1283 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
1284 break;
1285 case E_TSP_DST_FIFO_AUDIO:
1286 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
1287 break;
1288 case E_TSP_DST_FIFO_AUDIO2:
1289 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
1290 break;
1291 default:
1292 break;
1293 }
1294 break;
1295 case 1:
1296 switch (eFltType)
1297 {
1298 case E_TSP_DST_FIFO_VIDEO:
1299 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
1300 break;
1301 case E_TSP_DST_FIFO_VIDEO3D:
1302 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
1303 break;
1304 case E_TSP_DST_FIFO_AUDIO:
1305 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
1306 break;
1307 case E_TSP_DST_FIFO_AUDIO2:
1308 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
1309 break;
1310 default:
1311 break;
1312 }
1313 break;
1314 case 2:
1315 switch (eFltType)
1316 {
1317 case E_TSP_DST_FIFO_VIDEO:
1318 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
1319 break;
1320 case E_TSP_DST_FIFO_VIDEO3D:
1321 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
1322 break;
1323 case E_TSP_DST_FIFO_AUDIO:
1324 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
1325 break;
1326 case E_TSP_DST_FIFO_AUDIO2:
1327 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
1328 break;
1329 default:
1330 break;
1331 }
1332 break;
1333 default:
1334 break;
1335 }
1336 }
1337 else
1338 {
1339 switch(u32Tsif)
1340 {
1341 case 0:
1342 switch (eFltType)
1343 {
1344 case E_TSP_DST_FIFO_VIDEO:
1345 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
1346 break;
1347 case E_TSP_DST_FIFO_VIDEO3D:
1348 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
1349 break;
1350 case E_TSP_DST_FIFO_AUDIO:
1351 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
1352 break;
1353 case E_TSP_DST_FIFO_AUDIO2:
1354 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
1355 break;
1356 default:
1357 break;
1358 }
1359 break;
1360 case 1:
1361 switch (eFltType)
1362 {
1363 case E_TSP_DST_FIFO_VIDEO:
1364 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
1365 break;
1366 case E_TSP_DST_FIFO_VIDEO3D:
1367 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
1368 break;
1369 case E_TSP_DST_FIFO_AUDIO:
1370 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
1371 break;
1372 case E_TSP_DST_FIFO_AUDIO2:
1373 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
1374 break;
1375 default:
1376 break;
1377 }
1378 break;
1379 case 2:
1380 switch (eFltType)
1381 {
1382 case E_TSP_DST_FIFO_VIDEO:
1383 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
1384 break;
1385 case E_TSP_DST_FIFO_VIDEO3D:
1386 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
1387 break;
1388 case E_TSP_DST_FIFO_AUDIO:
1389 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
1390 break;
1391 case E_TSP_DST_FIFO_AUDIO2:
1392 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
1393 break;
1394 default:
1395 break;
1396 }
1397 break;
1398 default:
1399 break;
1400 }
1401 }
1402 }
1403
HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)1404 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)
1405 {
1406
1407 if(bEn == TRUE)
1408 {
1409 switch(u32BD)
1410 {
1411 case 0:
1412 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
1413 break;
1414 case 1:
1415 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
1416 break;
1417 default:
1418 printf("Not support !!\n");
1419 break;
1420 }
1421 }
1422 else
1423 {
1424 switch(u32BD)
1425 {
1426 case 0:
1427 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
1428 break;
1429 case 1:
1430 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
1431 break;
1432 default:
1433 printf("Not support !!\n");
1434 break;
1435
1436 }
1437 }
1438
1439 }
1440
HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng,MS_U32 u32PktSize)1441 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize)
1442 {
1443 MS_U32 u32PktLen = u32PktSize;
1444
1445 if(u32PktSize == 130)
1446 {
1447 u32PktLen = 188;
1448 }
1449 else if(u32PktSize == 134)
1450 {
1451 u32PktLen = 192;
1452 }
1453
1454 if(u32PktSize == 130 || u32PktSize == 134) //RVU
1455 {
1456 MS_U16 u16value = 0;
1457
1458 if(u32PktSize == 134)
1459 {
1460 switch(eFileEng)
1461 {
1462 case E_FILEENG_TSIF0:
1463 u16value = HW4_CFG36_PKT130_TIMESTAMP_EN0;
1464 break;
1465 case E_FILEENG_TSIF1:
1466 u16value = HW4_CFG36_PKT130_TIMESTAMP_EN1;
1467 break;
1468 case E_FILEENG_TSIF2:
1469 u16value = CFG4_54_RVU_TIMESTAMP_EN2;
1470 break;
1471 default:
1472 printf("Not support !!\n");
1473 break;
1474 }
1475 }
1476
1477 switch(eFileEng)
1478 {
1479 case E_FILEENG_TSIF0:
1480 u16value |= HW4_CFG36_PKT130_PSI_EN0 | HW4_CFG36_PKT130_EN0;
1481 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
1482 break;
1483 case E_FILEENG_TSIF1:
1484 u16value |= HW4_CFG36_PKT130_PSI_EN1 | HW4_CFG36_PKT130_EN1;
1485 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
1486 break;
1487 case E_FILEENG_TSIF2:
1488 u16value |= CFG4_54_RVU_PSI_EN2 | CFG4_54_RVU_EN2;
1489 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
1490 break;
1491 default:
1492 return;
1493 }
1494
1495 }
1496
1497 switch(eFileEng)
1498 {
1499 case E_FILEENG_TSIF0:
1500 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE);
1501 REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) | (TSP_PKT_SIZE_MASK & (u32PktLen-1)));
1502 break;
1503 case E_FILEENG_TSIF1:
1504 REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PKT_CHK_SIZE_FIN1 & (u32PktLen-1)));
1505 break;
1506 case E_FILEENG_TSIF2:
1507 REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FILEIN2) | (CFG_07_PKT_CHK_SIZE_FILEIN2 & (u32PktLen-1)));
1508 break;
1509 default:
1510 break;
1511 }
1512 }
1513
HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng,MS_U32 addr)1514 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr)
1515 {
1516 switch(eFileEng)
1517 {
1518 case E_FILEENG_TSIF0:
1519 REG32_W(&_RegCtrl->TsDma_Addr, addr);
1520 break;
1521 case E_FILEENG_TSIF1:
1522 REG32_W(&_RegCtrl2->CFG_30_31, addr);
1523 break;
1524 case E_FILEENG_TSIF2:
1525 REG32_W(&_RegCtrl2->CFG_35_36, addr);
1526 break;
1527 default:
1528 break;
1529 }
1530 }
1531
HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng,MS_U32 size)1532 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size)
1533 {
1534 switch(eFileEng)
1535 {
1536 case E_FILEENG_TSIF0:
1537 REG32_W(&_RegCtrl->TsDma_Size, size);
1538 break;
1539 case E_FILEENG_TSIF1:
1540 REG32_W(&_RegCtrl2->CFG_32_33, size);
1541 break;
1542 case E_FILEENG_TSIF2:
1543 REG32_W(&_RegCtrl2->CFG_37_38, size);
1544 break;
1545 default:
1546 break;
1547 }
1548 }
1549
HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)1550 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)
1551 {
1552 switch(eFileEng)
1553 {
1554 case E_FILEENG_TSIF0:
1555 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START);
1556 break;
1557 case E_FILEENG_TSIF1:
1558 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START);
1559 break;
1560 case E_FILEENG_TSIF2:
1561 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START);
1562 break;
1563 default:
1564 break;
1565 }
1566 }
1567
HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)1568 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)
1569 {
1570 switch (eFileEng)
1571 {
1572 case E_FILEENG_TSIF0:
1573 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
1574 return TRUE;
1575 case E_FILEENG_TSIF1:
1576 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
1577 return TRUE;
1578 case E_FILEENG_TSIF2:
1579 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
1580 return TRUE;
1581 default:
1582 return FALSE;
1583 }
1584 }
1585
HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)1586 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)
1587 {
1588 switch (eFileEng)
1589 {
1590 case E_FILEENG_TSIF0:
1591 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
1592 return TRUE;
1593 case E_FILEENG_TSIF1:
1594 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
1595 return TRUE;
1596 case E_FILEENG_TSIF2:
1597 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
1598 return TRUE;
1599 default:
1600 return FALSE;
1601 }
1602 }
1603
HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)1604 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)
1605 {
1606 switch(eFileEng)
1607 {
1608 case E_FILEENG_TSIF0:
1609 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START));
1610 break;
1611 case E_FILEENG_TSIF1:
1612 REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START));
1613 break;
1614 case E_FILEENG_TSIF2:
1615 REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START));
1616 break;
1617 default:
1618 break;
1619 }
1620 }
1621
HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng,MS_BOOL bEn)1622 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn)
1623 {
1624 if(bEn)
1625 {
1626 switch(eFileEng)
1627 {
1628 case E_FILEENG_TSIF0:
1629 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
1630 break;
1631 case E_FILEENG_TSIF1:
1632 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
1633 break;
1634 case E_FILEENG_TSIF2:
1635 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
1636 break;
1637 default:
1638 break;
1639 }
1640 }
1641 else
1642 {
1643 switch(eFileEng)
1644 {
1645 case E_FILEENG_TSIF0:
1646 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
1647 break;
1648 case E_FILEENG_TSIF1:
1649 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
1650 break;
1651 case E_FILEENG_TSIF2:
1652 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
1653 break;
1654 default:
1655 break;
1656 }
1657 }
1658 }
1659
HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1660 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1661 {
1662 if(bEnable)
1663 {
1664 switch(eFileEng)
1665 {
1666 case E_FILEENG_TSIF0:
1667 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
1668 break;
1669 case E_FILEENG_TSIF1:
1670 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
1671 break;
1672 case E_FILEENG_TSIF2:
1673 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
1674 break;
1675 default:
1676 break;
1677 }
1678 }
1679 else
1680 {
1681 switch(eFileEng)
1682 {
1683 case E_FILEENG_TSIF0:
1684 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
1685 break;
1686 case E_FILEENG_TSIF1:
1687 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
1688 break;
1689 case E_FILEENG_TSIF2:
1690 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
1691 break;
1692 default:
1693 break;
1694 }
1695 }
1696 }
1697
HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)1698 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)
1699 {
1700 switch(eFileEng)
1701 {
1702 case E_FILEENG_TSIF0:
1703 return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT));
1704 case E_FILEENG_TSIF1:
1705 return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT));
1706 case E_FILEENG_TSIF2:
1707 return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT));
1708 default:
1709 return 0;
1710 }
1711 }
1712
HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)1713 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)
1714 {
1715 switch(eFileEng)
1716 {
1717 case E_FILEENG_TSIF0:
1718 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT);
1719 case E_FILEENG_TSIF1:
1720 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT);
1721 case E_FILEENG_TSIF2:
1722 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT);
1723 default:
1724 return 0;
1725 }
1726 }
1727
HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)1728 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)
1729 {
1730 switch(eFileEng)
1731 {
1732 case E_FILEENG_TSIF0:
1733 return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
1734 case E_FILEENG_TSIF1:
1735 return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
1736 case E_FILEENG_TSIF2:
1737 return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
1738 default:
1739 return 0;
1740 }
1741 }
1742
HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng,MS_U32 delay,MS_BOOL bEnable)1743 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable)
1744 {
1745 if(bEnable)
1746 {
1747 switch(eFileEng)
1748 {
1749 case E_FILEENG_TSIF0:
1750 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK);
1751 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
1752 break;
1753 case E_FILEENG_TSIF1:
1754 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1);
1755 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
1756 break;
1757 case E_FILEENG_TSIF2:
1758 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2);
1759 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
1760 break;
1761 default:
1762 break;
1763 }
1764 }
1765 else
1766 {
1767 switch(eFileEng)
1768 {
1769 case E_FILEENG_TSIF0:
1770 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
1771 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000);
1772 break;
1773 case E_FILEENG_TSIF1:
1774 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
1775 REG16_W(&_RegCtrl2->CFG_03, 0x0000);
1776 break;
1777 case E_FILEENG_TSIF2:
1778 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
1779 REG16_W(&_RegCtrl2->CFG_08, 0x0000);
1780 break;
1781 default:
1782 break;
1783 }
1784 }
1785 }
1786
HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)1787 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)
1788 {
1789 switch(eFileEng)
1790 {
1791 case E_FILEENG_TSIF0:
1792 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE);
1793 case E_FILEENG_TSIF1:
1794 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE);
1795 case E_FILEENG_TSIF2:
1796 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE);
1797 default:
1798 return 0;
1799 }
1800 }
1801
1802 // Only used by [HW test code]
1803 /*
1804 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng)
1805 {
1806 return !HAL_TSP_Filein_Status(eFileEng);
1807 }
1808 */
1809
1810 //To do : only tsif0 has pause functionality in Kaiser
HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)1811 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)
1812 {
1813 TSP_HAL_FileState state = E_TSP_HAL_FILE_STATE_INVALID;
1814 MS_U32 u32Status = HAL_TSP_Filein_Status(eFileEng);
1815
1816 // @FIXME in kaiser u01 only tsif0 file eng has pause function
1817 switch (eFileEng)
1818 {
1819 case E_FILEENG_TSIF0:
1820 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE )
1821 {
1822 state = E_TSP_HAL_FILE_STATE_PAUSE;
1823 }
1824 else if (u32Status)
1825 {
1826 state = E_TSP_HAL_FILE_STATE_BUSY;
1827 }
1828 else
1829 {
1830 state = E_TSP_HAL_FILE_STATE_IDLE;
1831 }
1832 break;
1833 case E_FILEENG_TSIF1:
1834 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF1_FILE_PAUSE)
1835 {
1836 state = E_TSP_HAL_FILE_STATE_PAUSE;
1837 }
1838 else if (u32Status)
1839 {
1840 state = E_TSP_HAL_FILE_STATE_BUSY;
1841 }
1842 else
1843 {
1844 state = E_TSP_HAL_FILE_STATE_IDLE;
1845 }
1846 break;
1847 case E_FILEENG_TSIF2:
1848 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF2_FILE_PAUSE)
1849 {
1850 state = E_TSP_HAL_FILE_STATE_PAUSE;
1851 }
1852 else if (u32Status)
1853 {
1854 state = E_TSP_HAL_FILE_STATE_BUSY;
1855 }
1856 else
1857 {
1858 state = E_TSP_HAL_FILE_STATE_IDLE;
1859 }
1860 break;
1861 default:
1862 state = E_TSP_HAL_FILE_STATE_INVALID;
1863 break;
1864 }
1865 return state;
1866 }
1867
HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)1868 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)
1869 {
1870 if(bSet)
1871 {
1872 switch(eFileEng)
1873 {
1874 case E_FILEENG_TSIF0:
1875 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
1876 break;
1877 case E_FILEENG_TSIF1:
1878 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
1879 break;
1880 case E_FILEENG_TSIF2:
1881 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
1882 break;
1883 default:
1884 break;
1885 }
1886 }
1887 else
1888 {
1889 switch(eFileEng)
1890 {
1891 case E_FILEENG_TSIF0:
1892 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
1893 break;
1894 case E_FILEENG_TSIF1:
1895 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
1896 break;
1897 case E_FILEENG_TSIF2:
1898 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
1899 break;
1900 default:
1901 break;
1902 }
1903 }
1904
1905 }
1906
HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng,MS_BOOL bEn)1907 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn)
1908 {
1909 if(bEn)
1910 {
1911 switch(eFileEng)
1912 {
1913 case E_FILEENG_TSIF0:
1914 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
1915 break;
1916 case E_FILEENG_TSIF1:
1917 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
1918 break;
1919 case E_FILEENG_TSIF2:
1920 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
1921 break;
1922 default:
1923 break;
1924 }
1925 }
1926 else
1927 {
1928 switch(eFileEng)
1929 {
1930 case E_FILEENG_TSIF0:
1931 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
1932 break;
1933 case E_FILEENG_TSIF1:
1934 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
1935 break;
1936 case E_FILEENG_TSIF2:
1937 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
1938 break;
1939 break;
1940 default:
1941 break;
1942 }
1943 }
1944 }
1945
_HAL_TSP_FILEIN_ResetPktTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32InitTimeStamp)1946 static void _HAL_TSP_FILEIN_ResetPktTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32InitTimeStamp)
1947 {
1948 switch(eFileEng)
1949 {
1950 case E_FILEENG_TSIF0:
1951 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
1952 REG32_W(&_RegCtrl6->CFG6_50_51, u32InitTimeStamp);
1953 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
1954 break;
1955 case E_FILEENG_TSIF1:
1956 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
1957 REG32_W(&_RegCtrl6->CFG6_52_53, u32InitTimeStamp);
1958 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
1959 break;
1960 case E_FILEENG_TSIF2:
1961 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
1962 REG32_W(&_RegCtrl6->CFG6_54_55, u32InitTimeStamp);
1963 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
1964 break;
1965 default:
1966 break;
1967 }
1968 }
1969
HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32Stamp)1970 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp)
1971 {
1972 switch(eFileEng)
1973 {
1974 case E_FILEENG_TSIF0:
1975 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
1976 REG32_W(&_RegCtrl->LPcr2, u32Stamp);
1977 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
1978 break;
1979 case E_FILEENG_TSIF1:
1980 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
1981 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp);
1982 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
1983 break;
1984 case E_FILEENG_TSIF2:
1985 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
1986 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp);
1987 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 _HAL_TSP_FILEIN_ResetPktTimeStamp(eFileEng, 0);
1994 }
1995
HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng,TSP_HAL_TimeStamp_Clk eTimeStampClk)1996 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk)
1997 {
1998 switch(eFileEng)
1999 {
2000 case E_FILEENG_TSIF0:
2001 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2002 {
2003 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
2004 }
2005 else
2006 {
2007 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
2008 }
2009 break;
2010 case E_FILEENG_TSIF1:
2011 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2012 {
2013 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
2014 }
2015 else
2016 {
2017 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
2018 }
2019 break;
2020 case E_FILEENG_TSIF2:
2021 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2022 {
2023 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
2024 }
2025 else
2026 {
2027 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
2028 }
2029 break;
2030 default:
2031 break;
2032 }
2033 }
2034
HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)2035 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)
2036 {
2037 MS_U32 u32Stamp = 0;
2038 switch(eFileEng)
2039 {
2040 case E_FILEENG_TSIF0:
2041 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
2042 u32Stamp = REG32_R(&_RegCtrl->LPcr2);
2043 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
2044 break;
2045 case E_FILEENG_TSIF1:
2046 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
2047 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51);
2048 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
2049 break;
2050 case E_FILEENG_TSIF2:
2051 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
2052 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53);
2053 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
2054 break;
2055 default:
2056 u32Stamp = 0;
2057 break;
2058 }
2059 return u32Stamp;
2060 }
2061
HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)2062 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)
2063 {
2064 switch(eFileEng)
2065 {
2066 case E_FILEENG_TSIF0:
2067 return REG32_R(&_RegCtrl->TimeStamp_FileIn);
2068 case E_FILEENG_TSIF1:
2069 return REG32_R(&_RegCtrl2->CFG_42_43);
2070 case E_FILEENG_TSIF2:
2071 return REG32_R(&_RegCtrl2->CFG_44_45);
2072 default:
2073 break;
2074 }
2075 return 0;
2076 }
2077
HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng,MS_PHY * pu32Addr)2078 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr)
2079 {
2080 switch(eFileEng)
2081 {
2082 case E_FILEENG_TSIF0:
2083 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK);
2084 break;
2085 case E_FILEENG_TSIF1:
2086 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1);
2087 break;
2088 case E_FILEENG_TSIF2:
2089 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2);
2090 break;
2091 default:
2092 break;
2093 }
2094
2095 }
2096
HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)2097 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
2098 {
2099 if(bEnable)
2100 {
2101 switch(eFileEng)
2102 {
2103 case E_FILEENG_TSIF0:
2104 REG16_SET(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_REST);
2105 break;
2106 case E_FILEENG_TSIF1:
2107 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
2108 break;
2109 case E_FILEENG_TSIF2:
2110 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
2111 break;
2112 default:
2113 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
2114 break;
2115 }
2116 }
2117 else
2118 {
2119 switch(eFileEng)
2120 {
2121 case E_FILEENG_TSIF0:
2122 REG16_CLR(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_REST);
2123 break;
2124 case E_FILEENG_TSIF1:
2125 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
2126 break;
2127 case E_FILEENG_TSIF2:
2128 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
2129 break;
2130 default:
2131 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
2132 break;
2133 }
2134 }
2135 }
2136
2137
HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng,MS_BOOL bEnable,MS_U32 u32Key)2138 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key)
2139 {
2140 if(bEnable)
2141 {
2142 switch(eFileEng)
2143 {
2144 case E_FILEENG_TSIF0:
2145 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK));
2146 break;
2147 case E_FILEENG_TSIF1:
2148 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK));
2149 break;
2150 case E_FILEENG_TSIF2:
2151 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK));
2152 break;
2153 default:
2154 break;
2155 }
2156 }
2157 else
2158 {
2159 switch(eFileEng)
2160 {
2161 case E_FILEENG_TSIF0:
2162 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0);
2163 break;
2164 case E_FILEENG_TSIF1:
2165 REG16_W(&_RegCtrl2->CFG_75, 0);
2166 break;
2167 case E_FILEENG_TSIF2:
2168 REG16_W(&_RegCtrl2->CFG_76, 0);
2169 break;
2170 default:
2171 break;
2172 }
2173 }
2174 }
2175
HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)2176 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
2177 {
2178 switch (ePidFltSrc)
2179 {
2180 case E_TSP_PIDFLT_LIVE0:
2181 return TSP_PIDFLT_TSIF0;
2182 case E_TSP_PIDFLT_LIVE1:
2183 return TSP_PIDFLT_TSIF2;
2184 case E_TSP_PIDFLT_LIVE2:
2185 return TSP_PIDFLT_TSIF1;
2186 case E_TSP_PIDFLT_FILE0:
2187 return TSP_PIDFLT_TSIF1;
2188 case E_TSP_PIDFLT_FILE1:
2189 return TSP_PIDFLT_TSIF2;
2190 case E_TSP_PIDFLT_FILE2:
2191 return TSP_PIDFLT_TSIF0;
2192 default:
2193 printf("[TSP_ERR][%s][%d] Wrong filter source!!!\n",__FUNCTION__, __LINE__);
2194 break;
2195 }
2196
2197 return 0;
2198 }
2199
HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId,MS_U32 u32FltIn)2200 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn)
2201 {
2202 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
2203 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_IN_MASK) | ((u32FltIn << TSP_PIDFLT_TSIF_SHFT) & TSP_PIDFLT_IN_MASK));
2204 }
2205
HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId,MS_U32 u32FltOut)2206 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut)
2207 {
2208 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
2209 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_OUT_MASK)) | (u32FltOut & TSP_PIDFLT_OUT_MASK)));
2210 }
2211
HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId,MS_U32 u32SrcID)2212 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID)
2213 {
2214 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
2215 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcID << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
2216 }
2217
HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId,MS_U32 u32SecFltId)2218 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId)
2219 {
2220 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
2221 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
2222 }
2223
HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId,MS_U32 u32PVREng,MS_BOOL bEn)2224 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn)
2225 {
2226 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
2227 if(bEn)
2228 {
2229 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK) | (((1 << u32PVREng) << TSP_PIDFLT_PVRFLT_SHFT) & TSP_PIDFLT_PVRFLT_MASK));
2230 }
2231 else
2232 {
2233 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK));
2234 }
2235 }
2236
HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId,MS_U8 u8Enable)2237 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable)
2238 {
2239 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
2240 if(u8Enable)
2241 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) | (TSP_PID_FLT_PKTPUSH_PASS));
2242 else
2243 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) & ~(TSP_PID_FLT_PKTPUSH_PASS));
2244 }
2245
HAL_TSP_PidFlt_SetPid(MS_U32 fltId,MS_U32 u32Pid)2246 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32Pid)
2247 {
2248 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
2249 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PID_MASK) | ((u32Pid << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
2250 }
2251
2252 //-------------------------------------------------------------------------------------------------
2253 // For section filter part
2254 //-------------------------------------------------------------------------------------------------
2255
HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)2256 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)
2257 {
2258 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN);
2259 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT));
2260 }
2261
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFlt,MS_U32 u32FltType)2262 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType)
2263 {
2264 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_USER_MASK) | (u32FltType << TSP_SECFLT_USER_SHFT));
2265 }
2266
2267
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFlt,MS_U32 u32SecFltMode)2268 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode)
2269 {
2270 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
2271 }
2272
2273
2274 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFlt,MS_U8 * pu8Mask)2275 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask)
2276 {
2277 MS_U32 i,j;
2278 MS_U32 u32Temp;
2279
2280 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
2281 {
2282 j = (i<< 2);
2283 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
2284 TSP32_IdrW((TSP32 *)&pSecFlt->Mask[i], u32Temp);
2285 }
2286 }
2287
2288
2289 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFlt,MS_U8 * pu8NMask)2290 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask)
2291 {
2292 MS_U32 i,j;
2293 MS_U32 u32Temp;
2294
2295 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
2296 {
2297 j = (i<< 2);
2298 u32Temp = (pu8NMask[j]) | (pu8NMask[j+ 1] << 8 ) | (pu8NMask[j+ 2] << 16 )| (pu8NMask[j+ 3] << 24);
2299 TSP32_IdrW((TSP32 *)&pSecFlt->NMask[i], u32Temp);
2300 }
2301 }
2302
2303
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFlt,MS_U8 * pu8Match)2304 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match)
2305 {
2306 MS_U32 i,j;
2307 MS_U32 u32Temp;
2308
2309 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
2310 {
2311 j = (i<< 2);
2312 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
2313 TSP32_IdrW((TSP32 *)&pSecFlt->Match[i], u32Temp);
2314 }
2315 }
2316
2317
2318 //[LIMIT] Is impossible to identify the pidfilter is assigned a secfilter/buffer or not
HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt * pSecFlt,MS_U16 u16BufId)2319 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId)
2320 {
2321 TSP32_IdrW( &pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_SECBUF_MASK)
2322 | ((u16BufId << TSP_SECFLT_SECBUF_SHFT) & TSP_SECFLT_SECBUF_MASK) );
2323 }
2324
2325
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFlt)2326 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt)
2327 {
2328 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_SECBUF_MASK) >> TSP_SECFLT_SECBUF_SHFT);
2329 }
2330
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFlt)2331 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt)
2332 {
2333 return (TSP32_IdrR(pPidFlt) & TSP_PIDFLT_OUT_MASK);
2334 }
2335
HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)2336 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)
2337 {
2338 // don't have to implement no reference
2339 }
2340
2341
2342 // @FIXME: Is it secflt or secbuf?
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFlt)2343 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt)
2344 {
2345 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
2346 }
2347
2348
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFlt)2349 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt)
2350 {
2351 TSP32_IdrW(&pSecFlt->Ctrl, 0);
2352 }
2353
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFlt)2354 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt)
2355 {
2356 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
2357 }
2358
2359
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFlt)2360 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFlt)
2361 {
2362 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
2363 }
2364
2365
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFlt)2366 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFlt)
2367 {
2368 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_PCRRST);
2369 }
2370
2371
HAL_TSP_SecFlt_TryAlloc(REG_SecFlt * pSecFlt,MS_U16 u16TSPId)2372 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId)
2373 {
2374 MS_U32 reg;
2375
2376 //_TSP_HW_Lock();
2377
2378 // rmn counter doesn't need 32bit (check 13818) so we use some of it to store owner and alloc info
2379 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & (TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
2380 if (reg & TSP_SECFLT_ALLOC_MASK)
2381 {
2382 //_TSP_HW_Unlock();
2383 return FALSE;
2384 }
2385 reg |= TSP_SECFLT_ALLOC_MASK | ((u16TSPId<<TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK);
2386 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
2387
2388 //_TSP_HW_Unlock();
2389 return TRUE;
2390 }
2391
2392
HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt * pSecFlt,MS_BOOL bSet)2393 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet)
2394 {
2395 if(bSet)
2396 {
2397 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_MODE_AUTO_CRCCHK);
2398 }
2399 else
2400 {
2401 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_AUTO_CRCCHK);
2402 }
2403 }
2404
2405
HAL_TSP_SecFlt_Free(REG_SecFlt * pSecFlt)2406 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt)
2407 {
2408 MS_U32 reg;
2409
2410 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
2411 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
2412 }
2413
HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt * pSecFlt)2414 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt)
2415 {
2416 TSP32_IdrW(&pSecFlt->RmnCnt, TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECBUF_RMNCNT_MASK));
2417 }
2418
2419 //-------------------------------------------------------------------------------------------------
2420 // For section buffer part
2421 //-------------------------------------------------------------------------------------------------
HAL_TSP_SecBuf_SetBuf(REG_SecBuf * pSecBuf,MS_U32 u32StartAddr,MS_U32 u32BufSize)2422 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize)
2423 {
2424 MS_U32 owner;
2425 // To avoid SW read hidden HW byte enable information.
2426 owner = TSP32_IdrR(&pSecBuf->Start); // @FIXME local variable but not used?
2427
2428 TSP32_IdrW(&pSecBuf->Start, u32StartAddr);
2429 TSP32_IdrW(&pSecBuf->End, u32StartAddr + u32BufSize);
2430 }
2431
2432
HAL_TSP_SecBuf_SetRead(REG_SecBuf * pSecBuf,MS_U32 u32ReadAddr)2433 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr)
2434 {
2435 TSP32_IdrW(&pSecBuf->Read, u32ReadAddr);
2436 }
2437
2438
HAL_TSP_SecBuf_GetStart(REG_SecBuf * pSecBuf)2439 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf)
2440 {
2441 return TSP32_IdrR(&pSecBuf->Start);
2442 }
2443
2444
HAL_TSP_SecBuf_GetEnd(REG_SecBuf * pSecBuf)2445 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf)
2446 {
2447 return TSP32_IdrR(&pSecBuf->End);
2448 }
2449
2450
HAL_TSP_SecBuf_GetBufCur(REG_SecBuf * pSecBuf)2451 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf)
2452 {
2453 //BufCur is control by firmware
2454 //we use Cur pointer to receive the newest data
2455 //and use write pointer to guarantee that the data between
2456 //read and write pointer is correct, so that user won't get
2457 //unverified data.
2458 return TSP32_IdrR(&pSecBuf->Cur);
2459 }
2460
2461
HAL_TSP_SecBuf_Reset(REG_SecBuf * pSecBuf)2462 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf)
2463 {
2464 MS_U32 start;
2465
2466 start = TSP32_IdrR(&pSecBuf->Start);
2467
2468 TSP32_IdrW(&pSecBuf->Cur, start);
2469 TSP32_IdrW(&pSecBuf->Read, start);
2470 TSP32_IdrW(&pSecBuf->Write, start);
2471
2472 start = ( (MS_VIRT)pSecBuf - (MS_VIRT)REG_SECBUF_BASE ) / sizeof(REG_SecBuf) ;
2473 HAL_TSP_HCMD_BufRst(start); // @FIXME seems we don't need to do this
2474 }
2475
2476
HAL_TSP_SecBuf_GetRead(REG_SecBuf * pSecBuf)2477 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf)
2478 {
2479 return TSP32_IdrR((TSP32*)&pSecBuf->Read);
2480 }
2481
2482
HAL_TSP_SecBuf_GetWrite(REG_SecBuf * pSecBuf)2483 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf)
2484 {
2485 return TSP32_IdrR((TSP32*)&pSecBuf->Write);
2486 }
2487
2488
HAL_TSP_SecBuf_TryAlloc(REG_SecBuf * pSecBuf,MS_U16 u16TSPId)2489 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId)
2490 {
2491 // @TODO make sure the owner and alloc info is necessary or not.
2492 MS_U32 reg;
2493
2494 //_TSP_HW_Lock();
2495
2496 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK);
2497 //if (reg & TSP_SECBUF_ALLOC_MASK)
2498 //{
2499 // //_TSP_HW_Unlock();
2500 // return FALSE;
2501 //}
2502 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK);
2503 //TSP32_IdrW(&pSecBuf->Start, reg);
2504
2505 //_TSP_HW_Unlock();
2506 return TRUE;
2507 }
2508
2509
HAL_TSP_SecBuf_Free(REG_SecBuf * pSecBuf)2510 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf)
2511 {
2512 // @TODO ref to HAL_TSP_SecBuf_TryAlloc
2513 TSP32_IdrW(&pSecBuf->Start, 0x0);
2514 }
2515
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFlt)2516 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt)
2517 {
2518 return ((TSP32_IdrR(pPidFlt) & TSP_PIDFLT_PID_MASK) >> TSP_PIDFLT_PID_SHFT);
2519 }
2520
HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId,MS_BOOL bEnable)2521 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable)
2522 {
2523 switch(pcrFltId)
2524 {
2525 case 0:
2526 if(bEnable)
2527 {
2528 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
2529 }
2530 else
2531 {
2532 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
2533 }
2534 break;
2535 case 1:
2536 if(bEnable)
2537 {
2538 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
2539 }
2540 else
2541 {
2542 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
2543 }
2544 break;
2545 default:
2546 break;
2547 }
2548 }
2549
HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId,MS_U32 u32Pid)2550 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid)
2551 {
2552 switch(pcrFltId)
2553 {
2554 case 0:
2555 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid);
2556 break;
2557 case 1:
2558 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid);
2559 break;
2560 default:
2561 break;
2562 }
2563
2564 }
2565
HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)2566 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)
2567 {
2568 switch(pcrFltId)
2569 {
2570 case 0:
2571 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK);
2572 case 1:
2573 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK);
2574 default:
2575 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
2576 return PVR_PIDFLT_DEF;
2577 }
2578 }
2579
HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId,TSP_PCR_SRC src)2580 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src)
2581 {
2582 switch(pcrFltId)
2583 {
2584 case 0:
2585 //src 0
2586 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT);
2587 break;
2588 case 1:
2589 //src 1
2590 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT);
2591 break;
2592 default:
2593 break;
2594 }
2595 }
2596
2597 //[Jason]
HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId,TSP_PCR_SRC * pPcrSrc)2598 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc)
2599 {
2600 //printf("[Jason][%s][%d] pcrFltId = %x\n", __FUNCTION__, __LINE__, pcrFltId);
2601
2602 switch(pcrFltId)
2603 {
2604 case 0:
2605 //src 0
2606 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT;
2607 break;
2608 case 1:
2609 //src 1
2610 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT;
2611 break;
2612 default:
2613 break;
2614 }
2615 }
2616
HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)2617 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
2618 {
2619 TSP_PCR_SRC ePcrSrc = E_TSP_PCR_SRC_INVALID;
2620 switch(ePidFltSrc)
2621 {
2622 case E_TSP_PIDFLT_LIVE0:
2623 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
2624 break;
2625 case E_TSP_PIDFLT_LIVE1:
2626 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
2627 break;
2628 case E_TSP_PIDFLT_LIVE2:
2629 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
2630 break;
2631 case E_TSP_PIDFLT_FILE0:
2632 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
2633 break;
2634 case E_TSP_PIDFLT_FILE1:
2635 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
2636 break;
2637 case E_TSP_PIDFLT_FILE2:
2638 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
2639 break;
2640 default:
2641 printf("[TSP_ERR][%s][%d] Wrong Flt Src type!!!\n",__FUNCTION__,__LINE__);
2642 break;
2643 }
2644 return ePcrSrc;
2645
2646 }
2647
2648
HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)2649 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
2650 {
2651 switch(pcrFltId)
2652 {
2653 case 0:
2654 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
2655 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L);
2656 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1;
2657 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
2658 break;
2659 case 1:
2660 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
2661 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L);
2662 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1;
2663 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
2664 break;
2665 default:
2666 break;
2667 }
2668 }
2669
HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)2670 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)
2671 {
2672 switch(pcrFltId)
2673 {
2674 case 0:
2675 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
2676 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
2677 break;
2678 case 1:
2679 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
2680 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
2681 break;
2682 default:
2683 break;
2684 }
2685 }
2686
2687
HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)2688 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)
2689 {
2690 switch(pcrFltId)
2691 {
2692 case 0:
2693 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L,TSP_HWINT2_PCR0_UPDATE_END);
2694 REG16_W(&_RegCtrl->SwInt_Stat1_L,
2695 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) |
2696 (~TSP_HWINT2_PCR0_UPDATE_END & TSP_HWINT2_STATUS_MASK));
2697 break;
2698 case 1:
2699 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L,TSP_HWINT2_PCR1_UPDATE_END);
2700 REG16_W(&_RegCtrl->SwInt_Stat1_L,
2701 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) |
2702 (~TSP_HWINT2_PCR1_UPDATE_END & TSP_HWINT2_STATUS_MASK));
2703 break;
2704 default:
2705 break;
2706 }
2707 }
2708
HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)2709 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)
2710 {
2711 switch(pcrFltId)
2712 {
2713 case 0:
2714 return (TSP_HWINT2_PCR0_UPDATE_END_EN << 8);
2715 case 1:
2716 return (TSP_HWINT2_PCR1_UPDATE_END_EN << 8);
2717 default:
2718 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
2719 return 0;
2720 }
2721 }
2722
HAL_TSP_STC_Init(void)2723 void HAL_TSP_STC_Init(void)
2724 {
2725 /////////////Set STC control by HK////////////////
2726 // select synth from chip top : bit 1 -> 0 -> controlled by HK
2727 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2728 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
2729
2730 // set HK STC synth CW
2731 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2732 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000;
2733 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800;
2734 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000;
2735 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = 0x2800;
2736
2737 // set STC synth
2738 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2739 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2740 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2741 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2742 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
2743 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2744
2745 #if 0 // we don't use TSP CPU to control STC anymmore, so we don't have to do the following
2746 /////////////Set STC control by TSP////////////////
2747 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
2748 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
2749 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL;
2750
2751 // set TSP STC synth CW
2752 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2753 TSP32_IdrW((TSP32 *)(0x0021024c<<1), 0x28000000);
2754 TSP32_IdrW((TSP32 *)(0x00210280<<1), 0x28000000); //STC1
2755
2756 // t2 , t3 had no 0x0021025c, it was add after t4, eanble synthesizer
2757 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x01);
2758 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x01);
2759 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x02); //STC1
2760 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x02);
2761 #endif
2762 }
2763
HAL_TSP_GetSTCSynth(MS_U32 Eng,MS_U32 * u32Sync)2764 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync)
2765 {
2766 switch (Eng)
2767 {
2768 case 0:
2769 // get HK STC synth CW
2770 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L);
2771 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ;
2772 break;
2773 case 1:
2774 // get HK STC synth CW
2775 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L);
2776 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) << 16 ;
2777 break;
2778 }
2779 }
2780
HAL_TSP_SetSTCSynth(MS_U32 Eng,MS_U32 u32Sync)2781 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync)
2782 {
2783 switch (Eng)
2784 {
2785 case 0:
2786 //set STC controller : HK or TSP CPU
2787 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2788
2789 // set HK STC synth CW
2790 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF;
2791 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16;
2792
2793 // set STC synth : toggle update bit
2794 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2795 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2796 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2797 break;
2798 case 1:
2799 //set STC controller : HK or TSP CPU
2800 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
2801
2802 // set HK STC synth CW
2803 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF;
2804 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = u32Sync >> 16;
2805
2806 // set STC synth : toggle update bit
2807 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2808 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
2809 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2810 break;
2811 }
2812 }
2813
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)2814 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
2815 {
2816 if (bEnable)
2817 {
2818 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
2819 }
2820 else
2821 {
2822 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
2823 }
2824 }
2825
HAL_TSP_STC64_Set(MS_U32 Eng,MS_U32 stcH,MS_U32 stcL)2826 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL)
2827 {
2828 switch (Eng)
2829 {
2830 case 0:
2831 REG32_W(&_RegCtrl->Pcr_L, stcL);
2832 REG32_W(&_RegCtrl->Pcr_H, stcH);
2833 break;
2834 case 1:
2835 REG32_W(&_RegCtrl->PCR64_2_L, stcL);
2836 REG32_W(&_RegCtrl->PCR64_2_H, stcH);
2837 break;
2838 }
2839 }
2840
HAL_TSP_STC64_Get(MS_U32 Eng,MS_U32 * pStcH,MS_U32 * pStcL)2841 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL)
2842 {
2843 switch (Eng)
2844 {
2845 case 0:
2846 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2847 *pStcH = REG32_R(&_RegCtrl->Pcr_H);
2848 *pStcL = REG32_R(&_RegCtrl->Pcr_L);
2849 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2850 break;
2851 case 1:
2852 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
2853 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H);
2854 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L);
2855 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
2856 break;
2857 }
2858 }
2859
HAL_TSP_STC33_CmdQSet(MS_U32 stcH,MS_U32 stcL)2860 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL)
2861 {
2862 // @TODO ask designer for the difference between 64bit STC and 33 Bit STC
2863 // and it's hw limit (like: cmdQ delay)
2864 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H);
2865 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL);
2866 }
2867
HAL_TSP_STC33_CmdQGet(MS_U32 * pStcH,MS_U32 * pStcL)2868 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL)
2869 {
2870 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2871 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H;
2872 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ);
2873 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2874 }
2875
HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType,MS_U32 pktDmxId)2876 void HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType, MS_U32 pktDmxId)
2877 {
2878 switch (eFltType)
2879 {
2880 case E_TSP_DST_FIFO_VIDEO :
2881 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT);
2882 break;
2883 case E_TSP_DST_FIFO_VIDEO3D :
2884 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT);
2885 break;
2886 case E_TSP_DST_FIFO_AUDIO :
2887 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT);
2888 break;
2889 case E_TSP_DST_FIFO_AUDIO2 :
2890 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT);
2891 break;
2892 default:
2893 break;
2894 }
2895 }
2896
HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType,TSP_SRC_SEQ * pktDmxId)2897 void HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId)
2898 {
2899 switch (eFltType)
2900 {
2901 case E_TSP_DST_FIFO_VIDEO :
2902 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT;
2903 break;
2904 case E_TSP_DST_FIFO_VIDEO3D:
2905 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT;
2906 break;
2907 case E_TSP_DST_FIFO_AUDIO :
2908 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT;
2909 break;
2910 case E_TSP_DST_FIFO_AUDIO2 :
2911 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT;
2912 break;
2913 default:
2914 break;
2915 }
2916 }
2917
HAL_TSP_FIFO_ClearAll()2918 void HAL_TSP_FIFO_ClearAll()
2919 {
2920 // clear ALL FIFO !!!
2921 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
2922 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
2923 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
2924 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
2925 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
2926 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
2927
2928 }
2929
2930
HAL_TSP_FIFO_Connect(MS_BOOL bEn)2931 void HAL_TSP_FIFO_Connect(MS_BOOL bEn)
2932 {
2933 if(bEn == TRUE)
2934 {
2935 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
2936 }
2937 else
2938 {
2939 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
2940 }
2941
2942 }
2943
2944
HAL_TSP_FIFO_ReadPkt(void)2945 MS_U16 HAL_TSP_FIFO_ReadPkt(void)
2946 {
2947 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK);
2948 }
2949
2950
2951
2952
HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)2953 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)
2954 {
2955 switch (eFltType)
2956 {
2957 case E_TSP_DST_FIFO_VIDEO:
2958 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
2959 break;
2960 case E_TSP_DST_FIFO_AUDIO:
2961 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_A) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
2962 break;
2963 case E_TSP_DST_FIFO_AUDIO2:
2964 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AB) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
2965 break;
2966 case E_TSP_DST_FIFO_VIDEO3D:
2967 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V3D) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
2968 break;
2969 default:
2970 break;
2971 }
2972 }
2973
2974
2975
2976
2977 //@NOTE for TS mode
2978 //@TODO need to rename (TS enable or PKTDMX_BYPASS)
HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)2979 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
2980 {
2981 if(bEn)
2982 {
2983 switch (eFltType)
2984 {
2985 case E_TSP_DST_FIFO_VIDEO:
2986 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
2987 break;
2988 case E_TSP_DST_FIFO_AUDIO:
2989 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
2990 break;
2991 case E_TSP_DST_FIFO_AUDIO2:
2992 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
2993 break;
2994 case E_TSP_DST_FIFO_VIDEO3D:
2995 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
2996 break;
2997 default:
2998 break;
2999 }
3000 }
3001 else
3002 {
3003 switch (eFltType)
3004 {
3005 case E_TSP_DST_FIFO_VIDEO:
3006 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
3007 break;
3008 case E_TSP_DST_FIFO_AUDIO:
3009 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
3010 break;
3011 case E_TSP_DST_FIFO_AUDIO2:
3012 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
3013 break;
3014 case E_TSP_DST_FIFO_VIDEO3D:
3015 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
3016 break;
3017 default:
3018 break;
3019
3020 }
3021 }
3022 }
3023
3024
HAL_TSP_PS_SRC(MS_U32 tsIf)3025 void HAL_TSP_PS_SRC(MS_U32 tsIf)
3026 {
3027 REG16_MSK_W(&_RegCtrl3->CFG3_10, CFG3_10_PS_MODE_SRC_MASK,(((MS_U16)tsIf)<< CFG3_10_PS_MODE_SRC_SHIFT));
3028 }
3029
3030
3031
3032 //PS MODE
3033 //NEED TO rename
HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)3034 void HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
3035 {
3036 if(bEn)
3037 {
3038 switch (eFltType)
3039 {
3040 case E_TSP_DST_FIFO_VIDEO:
3041 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
3042 break;
3043 case E_TSP_DST_FIFO_VIDEO3D:
3044 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
3045 break;
3046 case E_TSP_DST_FIFO_AUDIO:
3047 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
3048 break;
3049 case E_TSP_DST_FIFO_AUDIO2:
3050 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
3051 break;
3052 default:
3053 break;
3054 }
3055 }
3056 else
3057 {
3058 switch (eFltType)
3059 {
3060 case E_TSP_DST_FIFO_VIDEO :
3061 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
3062 break;
3063 case E_TSP_DST_FIFO_VIDEO3D:
3064 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
3065 break;
3066 case E_TSP_DST_FIFO_AUDIO :
3067 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
3068 break;
3069 case E_TSP_DST_FIFO_AUDIO2 :
3070 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
3071 break;
3072 default:
3073 break;
3074 }
3075 }
3076 }
3077
HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng,TSP_DST_SEQ eFltType)3078 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType)
3079 {
3080 // (K6 HW CL) Kano doesn't support
3081 // PS mode source sel need to be independent
3082 }
3083
HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)3084 MS_U32 HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)
3085 {
3086 switch (eFltType)
3087 {
3088 case E_TSP_DST_FIFO_VIDEO :
3089 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK;
3090 case E_TSP_DST_FIFO_VIDEO3D :
3091 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK;
3092 case E_TSP_DST_FIFO_AUDIO :
3093 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK;
3094 case E_TSP_DST_FIFO_AUDIO2 :
3095 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK;
3096 default:
3097 return 0x1FFF;
3098 }
3099 }
3100
HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType,MS_BOOL bReset)3101 void HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType, MS_BOOL bReset)
3102 {
3103 if (bReset)
3104 {
3105 switch (eFltType)
3106 {
3107 case E_TSP_DST_FIFO_VIDEO :
3108 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
3109 break;
3110 case E_TSP_DST_FIFO_VIDEO3D:
3111 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
3112 break;
3113
3114 case E_TSP_DST_FIFO_AUDIO :
3115 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
3116 break;
3117 case E_TSP_DST_FIFO_AUDIO2 :
3118 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
3119 break;
3120 default :
3121 break;
3122 }
3123 }
3124 else
3125 {
3126 switch (eFltType)
3127 {
3128 case E_TSP_DST_FIFO_VIDEO :
3129 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
3130 break;
3131 case E_TSP_DST_FIFO_VIDEO3D:
3132 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
3133 break;
3134
3135 case E_TSP_DST_FIFO_AUDIO :
3136 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
3137 break;
3138 case E_TSP_DST_FIFO_AUDIO2 :
3139 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
3140 break;
3141 default :
3142 break;
3143 }
3144 }
3145
3146 _delay(1);
3147 }
3148
HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)3149 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)
3150 {
3151 if(bSkip)
3152 {
3153 switch(eFltType)
3154 {
3155 case E_TSP_DST_FIFO_VIDEO:
3156 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
3157 break;
3158 case E_TSP_DST_FIFO_VIDEO3D:
3159 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
3160 break;
3161 case E_TSP_DST_FIFO_AUDIO:
3162 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
3163 break;
3164 case E_TSP_DST_FIFO_AUDIO2:
3165 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
3166 break;
3167 default:
3168 break;
3169 }
3170 }
3171 else
3172 {
3173 switch(eFltType)
3174 {
3175 case E_TSP_DST_FIFO_VIDEO:
3176 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
3177 break;
3178 case E_TSP_DST_FIFO_VIDEO3D:
3179 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
3180 break;
3181 case E_TSP_DST_FIFO_AUDIO:
3182 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
3183 break;
3184 case E_TSP_DST_FIFO_AUDIO2:
3185 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
3186 break;
3187 default:
3188 break;
3189 }
3190
3191 }
3192 }
3193
3194
HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType,MS_BOOL bDisable)3195 void HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType, MS_BOOL bDisable)
3196 {
3197 if(bDisable)
3198 {
3199 switch(eFltType)
3200 {
3201 case E_TSP_DST_FIFO_VIDEO:
3202 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
3203 break;
3204 case E_TSP_DST_FIFO_VIDEO3D:
3205 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
3206 break;
3207 case E_TSP_DST_FIFO_AUDIO :
3208 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
3209 break;
3210 case E_TSP_DST_FIFO_AUDIO2 :
3211 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
3212 break;
3213 default:
3214 break;
3215 }
3216 }
3217 else
3218 {
3219 switch(eFltType)
3220 {
3221 case E_TSP_DST_FIFO_VIDEO:
3222 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
3223 break;
3224 case E_TSP_DST_FIFO_VIDEO3D:
3225 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
3226 break;
3227 case E_TSP_DST_FIFO_AUDIO :
3228 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
3229 break;
3230 case E_TSP_DST_FIFO_AUDIO2 :
3231 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
3232 break;
3233 default:
3234 break;
3235 }
3236 }
3237 }
3238
HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)3239 MS_BOOL HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)
3240 {
3241 MS_U32 u32Matched = 0;
3242 switch (eFltType)
3243 {
3244 case E_TSP_DST_FIFO_VIDEO :
3245 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO;
3246 break;
3247 case E_TSP_DST_FIFO_VIDEO3D:
3248 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D;
3249 break;
3250 case E_TSP_DST_FIFO_AUDIO :
3251 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO;
3252 break;
3253 case E_TSP_DST_FIFO_AUDIO2 :
3254 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2;
3255 break;
3256 default :
3257 return FALSE;
3258 }
3259 return (u32Matched) ? TRUE: FALSE;
3260 }
3261
HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)3262 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)
3263 {
3264 #define E_TSP_FIFO_STATUS_ISRESET 0x80000000
3265 #define E_TSP_FIFO_STATUS_EMPTY 0x00000001
3266 #define E_TSP_FIFO_STATUS_OVERFLOW 0x00000002
3267 #define E_TSP_FIFO_STATUS_LEVEL 0x0000000C
3268 #define TSP_FIFO_STATUS_LEVEL_SHFT 2 //shift the value get from HAL_TSP_FIFO_Level to the u32Status level position
3269 // @NOTE please follow K2 like series to return this value
3270 // since API layer didn't define for each column
3271 // we only defined that 0x80000000 stands for this fifo reset is High
3272 // 0x00000001 stands for this fifo is empty
3273 // 0x00000002 stands for this fifo is overflow
3274 // 0x0000000C is a mask for this fifo level
3275 // this is exclusive usage
3276 MS_U32 u32Status = 0;
3277 if (HAL_TSP_FIFO_IsReset(eFltType))
3278 {
3279 u32Status |= E_TSP_FIFO_STATUS_ISRESET;
3280 }
3281 if (HAL_TSP_FIFO_Empty(eFltType))
3282 {
3283 u32Status |= E_TSP_FIFO_STATUS_EMPTY;
3284 }
3285 if (HAL_TSP_FIFO_Overflow(eFltType))
3286 {
3287 u32Status |= E_TSP_FIFO_STATUS_OVERFLOW;
3288 }
3289
3290 u32Status |= ((HAL_TSP_FIFO_Level(eFltType)<<TSP_FIFO_STATUS_LEVEL_SHFT)&E_TSP_FIFO_STATUS_LEVEL);
3291
3292 return u32Status;
3293 }
3294
HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)3295 MS_U32 HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)
3296 {
3297 switch (eFltType)
3298 {
3299 case E_TSP_DST_FIFO_VIDEO :
3300 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT;
3301 case E_TSP_DST_FIFO_VIDEO3D :
3302 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT;
3303 case E_TSP_DST_FIFO_AUDIO :
3304 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT;
3305 case E_TSP_DST_FIFO_AUDIO2 :
3306 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT;
3307 default :
3308 return 0;
3309 }
3310 }
3311
HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)3312 MS_BOOL HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)
3313 {
3314 switch (eFltType)
3315 {
3316 case E_TSP_DST_FIFO_VIDEO :
3317 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT;
3318 case E_TSP_DST_FIFO_VIDEO3D :
3319 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT;
3320 case E_TSP_DST_FIFO_AUDIO :
3321 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT;
3322 case E_TSP_DST_FIFO_AUDIO2 :
3323 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT;
3324 default :
3325 return FALSE;
3326 }
3327 }
3328
HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)3329 MS_BOOL HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)
3330 {
3331 switch (eFltType)
3332 {
3333 case E_TSP_DST_FIFO_VIDEO :
3334 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT;
3335 case E_TSP_DST_FIFO_VIDEO3D:
3336 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT;
3337 case E_TSP_DST_FIFO_AUDIO :
3338 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT;
3339 case E_TSP_DST_FIFO_AUDIO2 :
3340 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT;
3341 default :
3342 return FALSE;
3343 }
3344 }
3345
_HAL_TSP_VQ_TxConfig(MS_U32 vqId)3346 static MS_BOOL _HAL_TSP_VQ_TxConfig(MS_U32 vqId)
3347 {
3348 // reg_vq_wr_threshold = 0x8
3349 // reg_vq_forcefire_cnt_1k= 0xC
3350
3351 switch(vqId)
3352 {
3353 case 0:
3354 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ0_WR_THRESHOLD_SHIFT) & TSP_VQ0_WR_THRESHOLD_MASK));
3355 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT) & TSP_VQ0_FORCE_FIRE_CNT_1K_MASK));
3356 break;
3357 case 1:
3358 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ1_WR_THRESHOLD_SHIFT) & TSP_VQ1_WR_THRESHOLD_MASK));
3359 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ1_FORCEFIRE_CNT_1K_MASK));
3360 break;
3361 case 2:
3362 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ2_WR_THRESHOLD_SHIFT) & TSP_VQ2_WR_THRESHOLD_MASK));
3363 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ2_FORCEFIRE_CNT_1K_MASK));
3364 break;
3365 default:
3366 return FALSE;
3367 }
3368 return TRUE;
3369 }
3370
3371
HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr,MS_U32 u32BufLen)3372 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen)
3373 {
3374 MS_U32 vqId;
3375 MS_U32 u32VQ_PktNum = 0;
3376 MS_U32 u32Addr = u32BaseAddr;
3377 MS_U32 u32OneBufSize = 0;
3378
3379 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment
3380 u32VQ_PktNum = u32OneBufSize / VQ_PACKET_UNIT_LEN;
3381
3382 for(vqId = 0; vqId < VQ_NUM; vqId ++)
3383 {
3384 if(TRUE != _HAL_TSP_VQ_TxConfig(vqId))
3385 {
3386 return FALSE;
3387 }
3388
3389 // in kaiser we needs to set 6 VQ and the base unit is 208 so total vq size should be N*208*6
3390 if (TRUE != HAL_TSP_VQ_Buffer(vqId, u32Addr, u32VQ_PktNum))
3391 {
3392 return FALSE;
3393 }
3394 u32Addr += u32OneBufSize;
3395 }
3396
3397 HAL_TSP_VQ_Enable(TRUE);
3398 return TRUE;
3399
3400 }
3401
HAL_TSP_VQ_Buffer(MS_U32 vqId,MS_PHYADDR u32BaseAddr,MS_U32 u32VQ_PktNum)3402 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32VQ_PktNum)
3403 {
3404 switch(vqId)
3405 {
3406 case 0:
3407 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS));
3408 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum);
3409 break;
3410 case 1:
3411 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS));
3412 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum);
3413 break;
3414 case 2:
3415 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS));
3416 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum);
3417 break;
3418 default:
3419 return FALSE;
3420 }
3421 return TRUE;
3422 }
3423
HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)3424 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)
3425 {
3426 if(bDis == TRUE)
3427 {
3428 switch(vqId)
3429 {
3430 case 0:
3431 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
3432 break;
3433 case 1:
3434 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
3435 break;
3436 case 2:
3437 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
3438 break;
3439 default:
3440 return FALSE;
3441 }
3442 }
3443 else
3444 {
3445 switch(vqId)
3446 {
3447 case 0:
3448 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
3449 break;
3450 case 1:
3451 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
3452 break;
3453 case 2:
3454 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
3455 break;
3456 default:
3457 return FALSE;
3458 }
3459 }
3460
3461 return TRUE;
3462 }
3463
HAL_TSP_VQ_Enable(MS_BOOL bEn)3464 void HAL_TSP_VQ_Enable(MS_BOOL bEn)
3465 {
3466 if (bEn)
3467 {
3468 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
3469 }
3470 else
3471 {
3472 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
3473 }
3474 }
HAL_TSP_VQ_Reset(MS_U32 vqId,MS_BOOL bEn)3475 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn)
3476 {
3477 if(bEn)
3478 {
3479 switch(vqId)
3480 {
3481 case 0:
3482 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
3483 break;
3484 case 1:
3485 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
3486 break;
3487 case 2:
3488 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
3489 break;
3490 default:
3491 break;
3492 }
3493 }
3494 else
3495 {
3496 switch(vqId)
3497 {
3498 case 0:
3499 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
3500 break;
3501 case 1:
3502 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
3503 break;
3504 case 2:
3505 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
3506 break;
3507 default:
3508 break;
3509 }
3510 }
3511 }
3512
HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId,MS_BOOL bEn)3513 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn)
3514 {
3515 if(bEn)
3516 {
3517 switch(vqId)
3518 {
3519 case 0:
3520 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
3521 break;
3522 case 1:
3523 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
3524 break;
3525 case 2:
3526 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
3527 break;
3528 default:
3529 break;
3530 }
3531 }
3532 else
3533 {
3534 switch(vqId)
3535 {
3536 case 0:
3537 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
3538 break;
3539 case 1:
3540 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
3541 break;
3542 case 2:
3543 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
3544 break;
3545 default:
3546 break;
3547 }
3548 }
3549 }
3550
HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId,MS_BOOL bEn)3551 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn)
3552 {
3553 if(bEn)
3554 {
3555 switch(vqId)
3556 {
3557 case 0:
3558 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
3559 break;
3560 case 1:
3561 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
3562 break;
3563 case 2:
3564 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
3565 break;
3566 default:
3567 break;
3568 }
3569 }
3570 else
3571 {
3572 switch(vqId)
3573 {
3574 case 0:
3575 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
3576 break;
3577 case 1:
3578 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
3579 break;
3580 case 2:
3581 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
3582 break;
3583 default:
3584 break;
3585 }
3586 }
3587 }
3588
HAL_PVR_Init(MS_U32 u32PVREng,MS_U32 pktDmxId)3589 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId)
3590 {
3591 switch(u32PVREng)
3592 {
3593 case 0:
3594 // PVR 1
3595 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
3596 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)pktDmxId) << TSP_PVR1_SRC_SHIFT));
3597 break;
3598 case 1:
3599 // PVR 2
3600 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
3601 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U16)pktDmxId) & 0x01) << TSP_PVR2_SRC_SHIFT_L));
3602 REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)pktDmxId) >> 1) << TSP_PVR2_SRC_SHIFT_H));
3603 break;
3604 default:
3605 break;
3606 }
3607 }
3608
HAL_PVR_Exit(MS_U32 u32PVREng)3609 void HAL_PVR_Exit(MS_U32 u32PVREng)
3610 {
3611 switch(u32PVREng)
3612 {
3613 case 0:
3614 //reset pvr control registers
3615 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
3616 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK);
3617
3618 //reset write address
3619 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
3620 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
3621 break;
3622 case 1:
3623 //reset pvr control registers
3624 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
3625 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L);
3626 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H);
3627
3628 //reset write address
3629 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
3630 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
3631 break;
3632 default:
3633 break;
3634 }
3635
3636 //reset time-stamp
3637 HAL_PVR_SetPVRTimeStamp(u32PVREng,0);
3638
3639 }
3640
HAL_PVR_Start(MS_U32 u32PVREng)3641 void HAL_PVR_Start(MS_U32 u32PVREng)
3642 {
3643 switch(u32PVREng)
3644 {
3645 case 0:
3646 //reset write address
3647 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
3648 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
3649
3650 //enable string to miu
3651 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
3652 break;
3653 case 1:
3654 //reset write address
3655 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
3656 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
3657
3658 //enable string to miu
3659 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
3660 break;
3661 default:
3662 break;
3663 }
3664 }
3665
HAL_PVR_Stop(MS_U32 u32PVREng)3666 void HAL_PVR_Stop(MS_U32 u32PVREng)
3667 {
3668 switch(u32PVREng)
3669 {
3670 case 0:
3671 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
3672 break;
3673 case 1:
3674 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
3675 break;
3676 default:
3677 break;
3678 }
3679 }
3680
HAL_PVR_Pause(MS_U32 u32PVREng,MS_BOOL bPause)3681 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause)
3682 {
3683 if(bPause)
3684 {
3685 switch(u32PVREng)
3686 {
3687 case 0:
3688 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
3689 break;
3690 case 1:
3691 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
3692 break;
3693 default:
3694 break;
3695 }
3696 }
3697 else
3698 {
3699 switch(u32PVREng)
3700 {
3701 case 0:
3702 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
3703 break;
3704 case 1:
3705 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
3706 break;
3707 default:
3708 break;
3709 }
3710 }
3711 }
3712
HAL_PVR_RecPid(MS_U32 u32PVREng,MS_BOOL bSet)3713 void HAL_PVR_RecPid(MS_U32 u32PVREng , MS_BOOL bSet)
3714 {
3715 if(bSet)
3716 {
3717 switch(u32PVREng)
3718 {
3719 case 0:
3720 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
3721 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
3722 break;
3723 case 1:
3724 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
3725 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
3726 break;
3727 default:
3728 break;
3729 }
3730 }
3731 else
3732 {
3733 switch(u32PVREng)
3734 {
3735 case 0:
3736 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
3737 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
3738 break;
3739 case 1:
3740 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
3741 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
3742 break;
3743 default:
3744 break;
3745 }
3746 }
3747 }
3748
HAL_PVR_RecNull(MS_BOOL bSet)3749 void HAL_PVR_RecNull(MS_BOOL bSet)
3750 {
3751 if(bSet == TRUE)
3752 {
3753 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
3754 }
3755 else
3756 {
3757 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
3758 }
3759 }
3760
HAL_PVR_SetBuf(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0,MS_U32 u32StartAddr1,MS_U32 u32BufSize1)3761 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1)
3762 {
3763 MS_U32 u32EndAddr0 = u32StartAddr0 + u32BufSize0;
3764 MS_U32 u32EndAddr1 = u32StartAddr1 + u32BufSize1;
3765 //MS_U32 u32Temp;
3766 switch(u32PVREng)
3767 {
3768 case 0:
3769 //head1
3770 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3771 //end1
3772 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3773 //mid1
3774 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3775
3776 //head2
3777 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
3778 //end2
3779 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
3780 //mid2
3781 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32StartAddr1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK);
3782 break;
3783 case 1:
3784 //head1
3785 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3786 //end1
3787 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3788 //mid1
3789 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3790
3791 //head2
3792 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3793 //end2
3794 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3795 //mid2
3796 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32StartAddr1>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3797 break;
3798 default:
3799 break;
3800 }
3801 }
3802
HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32StartAddr1)3803 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
3804 {
3805 //MS_U32 u32Temp;
3806 switch(u32PVREng)
3807 {
3808 case 0:
3809 //head1
3810 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3811
3812 //head2
3813 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
3814 break;
3815 case 1:
3816 //head1
3817 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3818
3819 //head2
3820 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3821
3822 break;
3823 default:
3824 break;
3825 }
3826 }
3827
HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng,MS_U32 u32MidAddr0,MS_U32 u32MidAddr1)3828 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng , MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
3829 {
3830 switch(u32PVREng)
3831 {
3832 case 0:
3833 //mid1
3834 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
3835
3836 //mid2
3837 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK);
3838 break;
3839 case 1:
3840 //mid1
3841 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
3842
3843 //mid2
3844 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK);
3845 break;
3846 default:
3847 break;
3848 }
3849 }
3850
HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng,MS_U32 u32EndAddr0,MS_U32 u32EndAddr1)3851 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng , MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
3852 {
3853 switch(u32PVREng)
3854 {
3855 case 0:
3856 //end1
3857 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3858
3859 //end2
3860 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
3861 break;
3862 case 1:
3863 //end1
3864 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3865
3866 //end2
3867 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
3868 break;
3869 default:
3870 break;
3871 }
3872 }
3873
HAL_PVR_GetWritePtr(MS_U32 u32PVREng)3874 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng)
3875 {
3876 switch(u32PVREng)
3877 {
3878 case 0:
3879 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS);
3880 break;
3881 case 1:
3882 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS);
3883 break;
3884 default:
3885 break;
3886 }
3887 return 0;
3888 }
3889
3890
HAL_PVR_GetEngSrc(MS_U32 u32EngDst,TSP_SRC_SEQ * eSrc)3891 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc)
3892 {
3893 MS_U16 u16Value = 0;
3894
3895 switch(u32EngDst)
3896 {
3897 case 0:
3898 // PVR 1
3899 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT);
3900 break;
3901 case 1:
3902 // PVR 2
3903 u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L)>> TSP_PVR2_SRC_SHIFT_L;
3904 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1);
3905 *eSrc = (TSP_SRC_SEQ)u16Value;
3906 break;
3907 default:
3908 break;
3909 }
3910 }
3911
3912
3913 // kaiser Only!!!
HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)3914 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)
3915 {
3916 switch (u32FileEng)
3917 {
3918 case 0: //File in Eng 0
3919 return E_FILEENG_TSIF1;
3920 case 1: //File in Eng 1
3921 return E_FILEENG_TSIF2;
3922 case 2: //File in Eng 2
3923 return E_FILEENG_TSIF0;
3924 default:
3925 return E_FILEENG_INVALID;
3926 }
3927 }
3928
3929 // @NOTE for backward competible when calling flowset pvr
3930 // kaiser Only!!!
HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)3931 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)
3932 {
3933 switch(u32Eng)
3934 {
3935 case 0:
3936 return E_TSP_SRC_PKTDMX0;
3937 case 1:
3938 return E_TSP_SRC_PKTDMX1;
3939 case 2:
3940 return E_TSP_SRC_PKTDMX2;
3941 default:
3942 return E_TSP_SRC_INVALID;
3943 }
3944 }
3945
3946 // kaiser Only!!!
HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF,MS_BOOL bFileIn)3947 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF, MS_BOOL bFileIn)
3948 {
3949 MS_U32 u32PhyTSIF = 0;
3950 switch (eTSIF)
3951 {
3952 case E_TSP_HAL_TSIF_0:
3953 if(bFileIn)
3954 u32PhyTSIF = TSP_TSIF1; // @NOTE tsif1 is used for playback0 file-in
3955 else
3956 u32PhyTSIF = TSP_TSIF0;
3957 break;
3958 case E_TSP_HAL_TSIF_1:
3959 if(bFileIn)
3960 u32PhyTSIF = TSP_TSIF2;
3961 else
3962 u32PhyTSIF = TSP_TSIF2;
3963 break;
3964 case E_TSP_HAL_TSIF_2:
3965 if(bFileIn)
3966 u32PhyTSIF = TSP_TSIF0;
3967 else
3968 u32PhyTSIF = TSP_TSIF1;
3969 break;
3970 case E_TSP_HAL_TSIF_PVR0:
3971 u32PhyTSIF = TSP_TSIF0;
3972 break;
3973 case E_TSP_HAL_TSIF_PVR1:
3974 u32PhyTSIF = TSP_TSIF1;
3975 break;
3976 case E_TSP_HAL_TSIF_PVR2:
3977 u32PhyTSIF = TSP_TSIF2;
3978 break;
3979 default:
3980 printf("[PVR ERROR][%s][%d] mapping TSIF error\n",__FUNCTION__,__LINE__);
3981 break;
3982 }
3983
3984 return u32PhyTSIF;
3985 }
3986
3987
3988 // kaiser Only!!!
HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)3989 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)
3990 {
3991 // @NOTE we map hw pkt dmx setting to api layer flow at this function
3992
3993 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
3994
3995 switch (eSrc)
3996 {
3997 case E_TSP_SRC_PKTDMX0:
3998 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
3999 break;
4000 case E_TSP_SRC_PKTDMX1:
4001 ePidFltSrc = E_TSP_PIDFLT_FILE0;
4002 break;
4003 case E_TSP_SRC_PKTDMX2:
4004 ePidFltSrc = E_TSP_PIDFLT_LIVE1;
4005 break;
4006 default:
4007 // @TODO add assert
4008 printf ("[TSP_ERR][%s][%d] Wrong Engine Source!!\n", __FUNCTION__,__LINE__);
4009 break;
4010 }
4011
4012 return ePidFltSrc;
4013 }
4014
HAL_TSP_GetDefaultFileinEng(void)4015 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void)
4016 {
4017 return E_FILEENG_TSIF1;
4018 }
4019
HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType,MS_U32 u32Eng)4020 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng)
4021 {
4022 if(eDstType == E_TSP_PIDFLT_DST_VIDEO)
4023 {
4024 switch(u32Eng)
4025 {
4026 case 0:
4027 return TSP_PIDFLT_OUT_VFIFO;
4028 case 1:
4029 return TSP_PIDFLT_OUT_VFIFO3D;
4030 default:
4031 printf("[TSP ERROR][%s][%d] mapping Vfifo eng error\n", __FUNCTION__, __LINE__);
4032 return 0;
4033 }
4034 }
4035 else if(eDstType == E_TSP_PIDFLT_DST_AUDIO)
4036 {
4037 switch(u32Eng)
4038 {
4039 case 0:
4040 return TSP_PIDFLT_OUT_AFIFO;
4041 case 1:
4042 return TSP_PIDFLT_OUT_AFIFO2;
4043 case 2:
4044 return TSP_PIDFLT_OUT_AFIFO3;
4045 case 3:
4046 return TSP_PIDFLT_OUT_AFIFO4;
4047 default:
4048 printf("[TSP ERROR][%s][%d] mapping Afifo eng error\n", __FUNCTION__, __LINE__);
4049 return 0;
4050 }
4051 }
4052 else if(eDstType == E_TSP_PIDFLT_DST_PVR)
4053 {
4054 switch(u32Eng)
4055 {
4056 case 0:
4057 return TSP_PIDFLT_OUT_PVR1;
4058 case 1:
4059 return TSP_PIDFLT_OUT_PVR2;
4060 default:
4061 printf("[TSP ERROR][%s][%d] mapping PVR eng error\n", __FUNCTION__, __LINE__);
4062 return 0;
4063 }
4064 }
4065 else
4066 {
4067 printf("[TSP ERROR][%s][%d] pid filter destination type error\n", __FUNCTION__, __LINE__);
4068 return 0;
4069 }
4070 }
4071
HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)4072 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif) //TODO: fiq mux
4073 {
4074 MS_U32 u32Fq = 0;
4075
4076 switch (u32Tsif)
4077 {
4078 case 0:
4079 case 1:
4080 case 2:
4081 u32Fq = 0;
4082 break;
4083 default:
4084 printf("[PVR ERROR][%s][%d] mapping TSIF:%u error\n",__FUNCTION__,__LINE__,(unsigned int)u32Tsif);
4085 break;
4086 }
4087
4088 return u32Fq;
4089 }
4090
HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)4091 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)
4092 {
4093 switch(u8Pad3WireId)
4094 {
4095 case 0:
4096 return E_TSP_TS_PAD_EXT3;
4097 case 1:
4098 return E_TSP_TS_PAD_EXT4;
4099 case 2:
4100 return E_TSP_TS_PAD_EXT5;
4101 case 3:
4102 return E_TSP_TS_PAD_EXT6;
4103 default:
4104 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] mapping 3WirePad:%u error\n",__FUNCTION__,__LINE__,u8Pad3WireId));
4105 return E_TSP_TS_PAD_INVALID;
4106 }
4107 }
4108
HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng,MS_BOOL bSet)4109 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng , MS_BOOL bSet)
4110 {
4111 if(bSet)
4112 {
4113 switch(u32PVREng)
4114 {
4115 case 0:
4116 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN);
4117 break;
4118 case 1:
4119 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
4120 break;
4121 default:
4122 break;
4123 }
4124 }
4125 else
4126 {
4127 switch(u32PVREng)
4128 {
4129 case 0:
4130 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN);
4131 break;
4132 case 1:
4133 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
4134 break;
4135 default:
4136 break;
4137 }
4138 }
4139 }
4140
HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)4141 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)
4142 {
4143 MS_U32 u32lpcr = 0;
4144 switch(u32PVREng)
4145 {
4146 case 0:
4147 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
4148
4149 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1);
4150
4151 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
4152
4153 return u32lpcr;
4154 case 1:
4155 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
4156
4157 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1);
4158
4159 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
4160 return u32lpcr;
4161 default:
4162 break;
4163 }
4164 return 0;
4165 }
4166
HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32Stamp)4167 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng , MS_U32 u32Stamp)
4168 {
4169 switch(u32PVREng)
4170 {
4171 case 0:
4172 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
4173
4174 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp);
4175
4176 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
4177 break;
4178 case 1:
4179 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
4180
4181 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp);
4182
4183 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
4184 break;
4185 default:
4186 break;
4187 }
4188 }
4189
HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng,MS_U32 u32Stamp)4190 void HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng , MS_U32 u32Stamp)
4191 {
4192 switch(u32PVREng)
4193 {
4194 case 0:
4195 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
4196
4197 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp);
4198
4199 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
4200 break;
4201 case 1:
4202 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
4203
4204 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp);
4205
4206 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
4207 break;
4208 default:
4209 break;
4210 }
4211 }
4212
HAL_PVR_Alignment_Enable(MS_U32 u32PVREng,MS_BOOL bEnable)4213 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable)
4214 {
4215 if(bEnable)
4216 {
4217 switch(u32PVREng)
4218 {
4219 case 0:
4220 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
4221 break;
4222 case 1:
4223 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
4224 break;
4225 default:
4226 break;
4227 }
4228 }
4229 else
4230 {
4231 switch(u32PVREng)
4232 {
4233 case 0:
4234 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
4235 break;
4236 case 1:
4237 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
4238 break;
4239 default:
4240 break;
4241 }
4242 }
4243 }
4244
HAL_PVR_FlushData(MS_U32 u32PVREng)4245 void HAL_PVR_FlushData(MS_U32 u32PVREng)
4246 {
4247 switch(u32PVREng)
4248 {
4249 case 0:
4250 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
4251 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
4252 break;
4253 case 1:
4254 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
4255 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
4256 break;
4257 default:
4258 break;
4259 }
4260 }
4261
HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)4262 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)
4263 {
4264 if(bSkip)
4265 {
4266 switch(u32PVREng)
4267 {
4268 case 0:
4269 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
4270 break;
4271 case 1:
4272 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
4273 break;
4274 default:
4275 break;
4276 }
4277 }
4278 else
4279 {
4280 switch(u32PVREng)
4281 {
4282 case 0:
4283 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
4284 break;
4285 case 1:
4286 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
4287 break;
4288 default:
4289 break;
4290 }
4291 }
4292 }
4293
4294
HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)4295 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)
4296 {
4297 if(bDisable)
4298 {
4299 switch(u32PVREng)
4300 {
4301 case 0:
4302 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
4303 break;
4304 case 1:
4305 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
4306 break;
4307 default:
4308 break;
4309 }
4310 }
4311 else
4312 {
4313 switch(u32PVREng)
4314 {
4315 case 0:
4316 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
4317 break;
4318 case 1:
4319 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
4320 break;
4321 default:
4322 break;
4323 }
4324
4325 }
4326 }
4327
HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)4328 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)
4329 {
4330 switch(u32PVREng)
4331 {
4332 case 0:
4333 REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT));
4334 break;
4335 case 1:
4336 REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_SHIFT));
4337 break;
4338 default:
4339 break;
4340 }
4341 }
4342
HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng,MS_BOOL bLocal_Stream)4343 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream)
4344 {
4345 if (u32PVREng>=TSP_PVRENG_NUM)
4346 {
4347 return;
4348 }
4349
4350 if (bLocal_Stream) //Stream
4351 {
4352 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
4353 }
4354 else //local
4355 {
4356 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
4357 }
4358 }
4359
HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)4360 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)
4361 {
4362 if(bEnable)
4363 {
4364 switch(u32PVREng)
4365 {
4366 case 0:
4367 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
4368 break;
4369 case 1:
4370 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
4371 break;
4372 default:
4373 break;
4374 }
4375 }
4376 else
4377 {
4378 switch(u32PVREng)
4379 {
4380 case 0:
4381 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
4382 break;
4383 case 1:
4384 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
4385 break;
4386 default:
4387 break;
4388 }
4389 }
4390 }
4391
HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)4392 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)
4393 {
4394 switch(u32PVREng)
4395 {
4396 case 0:
4397 REG32_W(&_RegCtrl3->CFG3_44_45, u32PauseTime);
4398 break;
4399 case 1:
4400 REG32_W(&_RegCtrl3->CFG3_46_47, u32PauseTime);
4401 break;
4402 default:
4403 break;
4404 }
4405 }
4406
HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId,MS_BOOL bEnable)4407 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId, MS_BOOL bEnable)
4408 {
4409 if (bEnable)
4410 {
4411 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
4412 }
4413 else
4414 {
4415 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
4416 }
4417 }
4418
HAL_PVR_MOBF_Enable(MS_U32 u32PVREng,MS_BOOL bEnable,MS_U32 u32Key)4419 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key)
4420 {
4421 switch(u32PVREng)
4422 {
4423 case 0:
4424 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK));
4425 break;
4426 case 1:
4427 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK));
4428 break;
4429 default:
4430 break;
4431 }
4432 }
4433
4434 /*
4435 void HAL_PVR_SetTSIF(MS_U32 u32PVREng , MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
4436 {
4437 if (bPara)
4438 {
4439 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
4440 }
4441 else
4442 {
4443 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
4444 }
4445
4446 if (bExtSync)
4447 {
4448 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
4449 }
4450 else
4451 {
4452 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
4453 }
4454
4455 if (bDataSWP)
4456 {
4457 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4458 }
4459 else
4460 {
4461 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4462 }
4463 }
4464
4465 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis)
4466 {
4467 if(bDis)
4468 {
4469 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
4470 }
4471 else
4472 {
4473 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
4474 }
4475 }
4476
4477 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn)
4478 {
4479 if(bEn)
4480 {
4481 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4482 }
4483 else
4484 {
4485 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4486 }
4487 }
4488 */
4489
HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)4490 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)
4491 {
4492 MS_U32 u32Data;
4493
4494 //reserved
4495 switch (u32Type)
4496 {
4497
4498 case INFO_FW_VERSION:
4499 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
4500 break;
4501 case INFO_FW_DATE:
4502 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE);
4503 break;
4504 default:
4505 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
4506 break;
4507
4508 }
4509
4510 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO);
4511
4512 _delay(10); // supposed TSP is able to respond in 10us
4513 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4514 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4515
4516 return u32Data;
4517 }
4518
HAL_TSP_HCMD_BufRst(MS_U32 u32Value)4519 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value)
4520 {
4521 // MS_U32 u32Data;
4522
4523 REG32_W(&_RegCtrl->MCU_Data0 , u32Value);
4524 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST);
4525 _delay(10); // supposed TSP is able to respond in 10us
4526
4527 return TRUE;
4528 }
4529
HAL_TSP_HCMD_Read(MS_U32 u32Addr)4530 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr)
4531 {
4532 MS_U32 u32Data;
4533
4534 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
4535 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ);
4536
4537 _delay(10); // supposed TSP is able to respond in 10us
4538 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4539 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4540
4541 return u32Data;
4542 }
4543
4544
HAL_TSP_HCMD_Write(MS_U32 u32Addr,MS_U32 u32Value)4545 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value)
4546 {
4547 MS_U32 u32Data;
4548
4549 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
4550 REG32_W(&_RegCtrl->MCU_Data1, u32Value);
4551 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE);
4552
4553 _delay(10); // supposed TSP is able to respond in 10us
4554 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4555 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4556
4557 return TRUE;
4558 }
4559
4560
HAL_TSP_HCMD_Alive(void)4561 MS_BOOL HAL_TSP_HCMD_Alive(void)
4562 {
4563 MS_U32 u32Data;
4564
4565 REG32_W(&_RegCtrl->MCU_Data1, 0);
4566 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD
4567 _delay(10); // supposed TSP is able to respond in 10us
4568 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4569 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4570
4571 return (u32Data == TSP_MCU_DATA_ALIVE)? TRUE : FALSE;
4572 }
4573
HAL_TSP_HCMD_SET(MS_U32 mcu_cmd,MS_U32 mcu_data0,MS_U32 mcu_data1)4574 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1)
4575 {
4576 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0);
4577 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1);
4578 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd);
4579 }
4580
HAL_TSP_HCMD_GET(MS_U32 * pmcu_cmd,MS_U32 * pmcu_data0,MS_U32 * pmcu_data1)4581 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1)
4582 {
4583 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd);
4584 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0);
4585 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1);
4586 }
4587
HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId,MS_BOOL bDis)4588 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis)
4589 {
4590 MS_U32 u32Data = bDis ;
4591
4592 REG32_W(&_RegCtrl->MCU_Data0, FltId);
4593 REG32_W(&_RegCtrl->MCU_Data1,u32Data);
4594 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here
4595 _delay(10); // supposed TSP is able to respond in 10us
4596 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4597
4598 return ;
4599 }
4600
HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)4601 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)
4602 {
4603 MS_U32 u32Data;
4604
4605 REG32_W(&_RegCtrl->MCU_Data0, u32Enable);
4606 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG);
4607
4608 _delay(10); // supposed TSP is able to respond in 10us
4609 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4610 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4611
4612 return REG32_R(&_RegCtrl->MCU_Data1);
4613 }
4614
HAL_TSP_GetDBGStatus(MS_U16 u16Sel)4615 MS_U32 HAL_TSP_GetDBGStatus(MS_U16 u16Sel)
4616 {
4617 REG16_CLR(&_RegCtrl->PKT_CNT, TSP_DBG_SEL_MASK);
4618 REG16_SET(&_RegCtrl->PKT_CNT, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK));
4619
4620 return REG32_R(&_RegCtrl->TSP_Debug);
4621 }
4622
HAL_TSP_INT_Enable(MS_U32 u32Mask)4623 void HAL_TSP_INT_Enable(MS_U32 u32Mask)
4624 {
4625 // Low byte for bank 0x15 7e bit[0:7]
4626 /*
4627 7: audio/video packet error
4628 6: DMA read done
4629 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15]
4630 4: TSP_FILE_RP meets TSP_FILE_TAIL.
4631 3: TSP_FILE_RP meets TSP_FILE_MID.
4632 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15]
4633 1: STR2MI_WADR meets STR2MI_MID.
4634 0: STR2MI_WADR meets STR2MI_TAIL."
4635 */
4636 REG16_SET(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask);
4637
4638 // High byte for bank 0x16 6c bit[0:7]
4639 /*
4640 [7] : PVR2 meet_tail or PVR2_meet_mid
4641 [6] : vq0, vq1, vq2, vq3 overflow interrupt
4642 [5] : all DMA write address not in the protect zone interrupt
4643 [4] : PVR_cb meet the mid or PVR_cb meet the tail
4644 [3] : pcr filter 0 update finish
4645 [2] : pcr filter 1 update finish
4646 [1: 0] : reserved
4647 */
4648 REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK);
4649 }
4650
4651
HAL_TSP_INT_Disable(MS_U32 u32Mask)4652 void HAL_TSP_INT_Disable(MS_U32 u32Mask)
4653 {
4654 REG16_CLR(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask);
4655 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L, TSP_HWINT2_EN_MASK & (u32Mask >> 8));
4656 REG16_W(&_RegCtrl->SwInt_Stat1_L,
4657 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) |
4658 TSP_HWINT2_STATUS_MASK);
4659 }
4660
4661
HAL_TSP_INT_ClrHW(MS_U32 u32Mask)4662 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask)
4663 {
4664 REG16_CLR(&_RegCtrl->HwInt_Stat, (u32Mask & 0x00FF) << 8);
4665 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L, u32Mask & 0xFF00);
4666 REG16_W(&_RegCtrl->SwInt_Stat1_L,
4667 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) |
4668 (~(u32Mask & 0xFF00) & TSP_HWINT2_STATUS_MASK));
4669 }
4670
4671
HAL_TSP_INT_GetHW(void)4672 MS_U32 HAL_TSP_INT_GetHW(void)
4673 {
4674 MS_U32 status;
4675
4676 status = (MS_U32)(((REG16_R(&_RegCtrl->SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STATUS_SHIFT)<<8);
4677
4678 status |= (MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_SHIFT);
4679
4680 return (status & 0xFFFF);
4681 }
4682
4683
HAL_TSP_INT_ClrSW(void)4684 void HAL_TSP_INT_ClrSW(void)
4685 {
4686 REG32_W(&_RegCtrl->SwInt_Stat, 0);
4687 }
4688
4689
HAL_TSP_INT_GetSW(void)4690 MS_U32 HAL_TSP_INT_GetSW(void)
4691 {
4692 return REG32_R(&_RegCtrl->SwInt_Stat);
4693 }
4694
HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx,MS_U32 inputSrc)4695 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc)
4696 {
4697 switch (bufIdx)
4698 {
4699 case 0:
4700 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2));
4701 break;
4702 case 1:
4703 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2));
4704 break;
4705 case 2:
4706 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2));
4707 break;
4708 default:
4709 break;
4710 }
4711 }
4712
HAL_RASP_Set_Source(MS_U32 u32RASPEng,MS_U32 pktDmxId)4713 MS_U32 HAL_RASP_Set_Source(MS_U32 u32RASPEng, MS_U32 pktDmxId)
4714 {
4715 return 0;
4716 }
4717
HAL_RASP_Get_Source(MS_U32 u32RASPEng,TSP_SRC_SEQ * eSrc)4718 MS_U32 HAL_RASP_Get_Source(MS_U32 u32RASPEng, TSP_SRC_SEQ *eSrc)
4719 {
4720 return 0;
4721 }
4722
HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)4723 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)
4724 {
4725 if (bByPassEn)
4726 {
4727 REG16_SET(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
4728 }
4729 else
4730 {
4731 REG16_CLR(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
4732 }
4733 }
4734
4735 //@TODO
4736 #if 1
HAL_TSP_FileIn_SPDConfig(MS_U32 tsif,MS_BOOL CTR_mode)4737 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode)
4738 {
4739 if(CTR_mode == TRUE)
4740 {
4741 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05));
4742 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable
4743 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV
4744 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000);
4745 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000);
4746 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000);
4747 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld
4748 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV
4749 }
4750
4751 switch(tsif)
4752 {
4753 case 0: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI0_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
4754 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
4755 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
4756 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
4757 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
4758 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
4759 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
4760 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
4761 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
4762 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY0);
4763 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF0_BYPASS);//bypass SPD
4764 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET); //TSIF SPD reset
4765 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET);
4766 break;
4767 case 1: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI1_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
4768 /*
4769 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x2222); //file-in SPD key
4770 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x2222);
4771 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x2222);
4772 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x2222);
4773 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x3333);
4774 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x3333);
4775 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x3333);
4776 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x3333);
4777 */
4778 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
4779 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
4780 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
4781 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
4782 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
4783 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
4784 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
4785 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
4786 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY1);
4787 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF1_BYPASS);//bypass SPD
4788 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET); //TSIF SPD reset
4789 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET);
4790 break;
4791 case 2: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI2_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
4792 /*
4793 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x4444); //file-in SPD key
4794 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x4444);
4795 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x4444);
4796 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x4444);
4797 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x5555);
4798 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x5555);
4799 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x5555);
4800 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x5555);
4801 */
4802 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
4803 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
4804 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
4805 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
4806 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
4807 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
4808 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
4809 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
4810 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY2);
4811 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF2_BYPASS);//bypass SPD
4812 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET); //TSIF SPD reset
4813 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET);
4814 break;
4815 default:printf("Not Support !!\n");
4816 break;
4817 }
4818 }
4819 #endif
4820
4821 // for TSO
HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId,MS_U32 u32TSOEng,MS_BOOL bEn)4822 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn)
4823 {
4824 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
4825 if(bEn)
4826 {
4827 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_TSOFLT_MASK) | (((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK));
4828 }
4829 else
4830 {
4831 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~(((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK)));
4832 }
4833 }
4834
HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap,MS_U32 * pu32CapInfo)4835 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo)
4836 {
4837 switch (eCap)
4838 {
4839 case E_TSP_HAL_CAP_TYPE_PIDFLT_NUM :
4840 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PIDFLT_NUM;
4841 break;
4842 case E_TSP_HAL_CAP_TYPE_SECFLT_NUM :
4843 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECFLT_NUM;
4844 break;
4845 case E_TSP_HAL_CAP_TYPE_SECBUF_NUM :
4846 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_NUM;
4847 break;
4848 case E_TSP_HAL_CAP_TYPE_RECENG_NUM :
4849 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECENG_NUM;
4850 break;
4851 case E_TSP_HAL_CAP_TYPE_RECFLT_NUM :
4852 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_NUM;
4853 break;
4854 case E_TSP_HAL_CAP_TYPE_TSIF_NUM :
4855 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSIF_NUM;
4856 break;
4857 case E_TSP_HAL_CAP_TYPE_DEMOD_NUM :
4858 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_DEMOD_NUM;
4859 break;
4860 case E_TSP_HAL_CAP_TYPE_TSPAD_NUM :
4861 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSPAD_NUM;
4862 break;
4863 case E_TSP_HAL_CAP_TYPE_VQ_NUM :
4864 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_NUM;
4865 break;
4866 case E_TSP_HAL_CAP_TYPE_CAFLT_NUM :
4867 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAFLT_NUM;
4868 break;
4869 case E_TSP_HAL_CAP_TYPE_CAKEY_NUM :
4870 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAKEY_NUM;
4871 break;
4872 case E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN :
4873 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_ALIGN;
4874 break;
4875 case E_TSP_HAL_CAP_TYPE_PVR_ALIGN:
4876 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PVR_ALIGN;
4877 break;
4878 case E_TSP_HAL_CAP_TYPE_FW_ALIGN :
4879 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_ALIGN;
4880 break;
4881 case E_TSP_HAL_CAP_TYPE_VQ_ALIGN :
4882 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_ALIGN;
4883 break;
4884 case E_TSP_HAL_CAP_TYPE_VQ_PITCH :
4885 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_PITCH;
4886 break;
4887 case E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM:
4888 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM;
4889 break;
4890 case E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM:
4891 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM;
4892 break;
4893 case E_TSP_HAL_CAP_TYPE_HW_TYPE:
4894 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HW_TYPE;
4895 break;
4896 case E_TSP_HAL_CAP_TYPE_RECFLT_IDX :
4897 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_IDX;
4898 break;
4899 case E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX :
4900 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX;
4901 break;
4902 case E_TSP_HAL_CAP_TYPE_VFIFO_NUM:
4903 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VFIFO_NUM;
4904 break;
4905 case E_TSP_HAL_CAP_TYPE_AFIFO_NUM:
4906 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_AFIFO_NUM;
4907 break;
4908 case E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT:
4909 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT;
4910 break;
4911 case E_TSP_HAL_CAP_FIQ_NUM:
4912 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FIQ_NUM;
4913 break;
4914 case E_TSP_HAL_CAP_FW_BUF_SIZE:
4915 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_BUF_SIZE;
4916 break;
4917 case E_TSP_HAL_CAP_FW_BUF_RANGE:
4918 *(pu32CapInfo) = TSP_FW_BUF_LOW_BUD;
4919 *(pu32CapInfo + 1) = TSP_FW_BUF_UP_BUD;
4920 break;
4921 case E_TSP_HAL_CAP_VQ_BUF_RANGE:
4922 *(pu32CapInfo) = TSP_VQ_BUF_LOW_BUD;
4923 *(pu32CapInfo + 1) = TSP_VQ_BUF_UP_BUD;
4924 break;
4925 case E_TSP_HAL_CAP_SEC_BUF_RANGE:
4926 *(pu32CapInfo) = TSP_SEC_BUF_LOW_BUD;
4927 *(pu32CapInfo + 1) = TSP_SEC_BUF_UP_BUD;
4928 break;
4929 default:
4930 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_NULL;
4931 return FALSE;
4932 }
4933 return TRUE;
4934 }
4935
_HAL_TSP_PadMapping(MS_U16 u16Pad)4936 static TSP_TS_PAD _HAL_TSP_PadMapping(MS_U16 u16Pad)
4937 {
4938 MS_U16 u16Ts2_Mode = (TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) >> REG_TOP_TS2MODE_SHIFT) & REG_TOP_TS2MODE_MASK;
4939
4940 switch (u16Pad)
4941 {
4942 case REG_TOP_TS_SRC_EXT0:
4943 return E_TSP_TS_PAD_EXT0;
4944 case REG_TOP_TS_SRC_EXT1:
4945 return E_TSP_TS_PAD_EXT1;
4946 case REG_TOP_TS_SRC_EXT2:
4947 return E_TSP_TS_PAD_EXT2;
4948 case REG_TOP_TS_SRC_EXT3:
4949 if(u16Ts2_Mode == REG_TOP_TS2MODE_3WIRED)
4950 {
4951 return E_TSP_TS_PAD_EXT0_3WIRE;
4952 }
4953 else
4954 {
4955 return E_TSP_TS_PAD_EXT3;
4956 }
4957 case REG_TOP_TS_SRC_EXT4:
4958 if(u16Ts2_Mode == REG_TOP_TS2MODE_3WIRED)
4959 {
4960 return E_TSP_TS_PAD_EXT1_3WIRE;
4961 }
4962 else
4963 {
4964 return E_TSP_TS_PAD_EXT4;
4965 }
4966 case REG_TOP_TS_SRC_EXT5:
4967 if(u16Ts2_Mode == REG_TOP_TS2MODE_3WIRED)
4968 {
4969 return E_TSP_TS_PAD_EXT2_3WIRE;
4970 }
4971 else
4972 {
4973 return E_TSP_TS_PAD_EXT5;
4974 }
4975 case REG_TOP_TS_SRC_EXT6:
4976 if(u16Ts2_Mode == REG_TOP_TS2MODE_3WIRED)
4977 {
4978 return E_TSP_TS_PAD_EXT3_3WIRE;
4979 }
4980 else
4981 {
4982 return E_TSP_TS_PAD_EXT6;
4983 }
4984 case REG_TOP_TS_SRC_TSO0:
4985 return E_TSP_TS_PAD_TSOUT0;
4986
4987 default:
4988 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported Pad Enum: %d !\n",__FILE__,__FUNCTION__,__LINE__,u16Pad));
4989 return E_TSP_TS_PAD_INVALID;
4990 }
4991 }
4992
HAL_TSP_GetTSIF_Status(MS_U32 u32TsIfId,TSP_TS_PAD * pePad,MS_U16 * pu16Clk,MS_BOOL * pbClkInv,MS_BOOL * pbExtSync,MS_BOOL * pbParl)4993 void HAL_TSP_GetTSIF_Status(MS_U32 u32TsIfId, TSP_TS_PAD* pePad, MS_U16* pu16Clk, MS_BOOL* pbClkInv, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
4994 {
4995 MS_U16 u16pad, u16clk;
4996 *pbExtSync = FALSE;
4997 *pbParl = FALSE;
4998 *pbClkInv = FALSE;
4999 *pePad = 0;
5000 *pu16Clk = 0;
5001
5002 switch (u32TsIfId)
5003 {
5004 case 0:
5005 u16pad = TSP_TOP_REG(REG_TOP_TS0_MUX) & ((REG_TOP_TS_SRC_MASK) << REG_TOP_TS0_SHIFT);
5006 u16pad >>= REG_TOP_TS0_SHIFT;
5007 *pePad = _HAL_TSP_PadMapping(u16pad);
5008 u16clk = TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ((REG_CLKGEN0_TS_SRC_MASK)<<(REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
5009 u16clk >>= (REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT);
5010 *pu16Clk = u16clk;
5011 *pbExtSync = ((REG16_R(&_RegCtrl->Hw_Config0) & TSP_HW_CFG0_TSIF0_EXTSYNC) == TSP_HW_CFG0_TSIF0_EXTSYNC);
5012 *pbParl = ((REG16_R(&_RegCtrl->Hw_Config0) & TSP_HW_CFG0_TSIF0_PARL) == TSP_HW_CFG0_TSIF0_PARL);
5013 *pbClkInv =(((TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) >> REG_CLKGEN0_TS0_SHIFT)& REG_CLKGEN0_TS_INVERT) == REG_CLKGEN0_TS_INVERT);
5014 break;
5015 case 1:
5016 u16pad = TSP_TOP_REG(REG_TOP_TS1_MUX) & ((REG_TOP_TS_SRC_MASK) << REG_TOP_TS1_SHIFT);
5017 u16pad >>= REG_TOP_TS1_SHIFT;
5018 *pePad = _HAL_TSP_PadMapping(u16pad);
5019 u16clk = TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ((REG_CLKGEN0_TS_SRC_MASK)<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
5020 u16clk >>= (REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT);
5021 *pu16Clk = u16clk;
5022 *pbExtSync = ((REG16_R(&_RegCtrl->Hw_Config2) & TSP_HW_CFG2_TSIF1_EXTSYNC) == TSP_HW_CFG2_TSIF1_EXTSYNC);
5023 *pbParl = ((REG16_R(&_RegCtrl->Hw_Config2) & TSP_HW_CFG2_TSIF1_PARL) == TSP_HW_CFG2_TSIF1_PARL);
5024 *pbClkInv =(((TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) >> REG_CLKGEN0_TS1_SHIFT)& REG_CLKGEN0_TS_INVERT) == REG_CLKGEN0_TS_INVERT);
5025 break;
5026 case 2:
5027 u16pad = TSP_TOP_REG(REG_TOP_TS2_MUX) & ((REG_TOP_TS_SRC_MASK) << REG_TOP_TS2_SHIFT);
5028 u16pad >>= REG_TOP_TS2_SHIFT;
5029 *pePad = _HAL_TSP_PadMapping(u16pad);
5030 u16clk = TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ((REG_CLKGEN0_TS_SRC_MASK)<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
5031 u16clk >>= (REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT);
5032 *pu16Clk = u16clk;
5033 *pbExtSync = ((REG32_R(&_RegCtrl->PVR2_Config) & TSP_EXT_SYNC_SEL2) == TSP_EXT_SYNC_SEL2);
5034 *pbParl = ((REG32_R(&_RegCtrl->PVR2_Config) & TSP_P_SEL2) == TSP_P_SEL2);
5035 *pbClkInv =(((TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) >> REG_CLKGEN0_TS2_SHIFT)& REG_CLKGEN0_TS_INVERT) == REG_CLKGEN0_TS_INVERT);
5036 break;
5037 default:
5038 break;
5039 }
5040
5041 }
5042
HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)5043 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)
5044 {
5045 if(bEnable)
5046 {
5047 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
5048 }
5049 else
5050 {
5051 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
5052 }
5053 }
5054
HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType,MS_BOOL bEnable)5055 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable)
5056 {
5057 if(bEnable)
5058 {
5059 switch (eHalPktType)
5060 {
5061 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
5062 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
5063 break;
5064 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
5065 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
5066 break;
5067 default:
5068 break;
5069 }
5070 }
5071 else
5072 {
5073 switch (eHalPktType)
5074 {
5075 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
5076 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
5077 break;
5078 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
5079 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
5080 break;
5081 default:
5082 break;
5083 }
5084 }
5085 }
5086
HAL_TSP_TEI_SKIP(MS_U32 tsIf,MS_BOOL bEnable)5087 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable)
5088 {
5089 if(bEnable)
5090 {
5091 switch (tsIf)
5092 {
5093 case 0:
5094 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
5095 break;
5096 case 1:
5097 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
5098 break;
5099 case 2:
5100 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
5101 break;
5102 default:
5103 break;
5104 }
5105 }
5106 else
5107 {
5108 switch (tsIf)
5109 {
5110 case 0:
5111 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
5112 break;
5113 case 1:
5114 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
5115 break;
5116 case 2:
5117 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
5118 break;
5119 default:
5120 break;
5121 }
5122 }
5123
5124 }
5125
HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)5126 void HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)
5127 {
5128 switch (eFltType)
5129 {
5130 case E_TSP_DST_FIFO_VIDEO :
5131 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
5132 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
5133 break;
5134 case E_TSP_DST_FIFO_VIDEO3D:
5135 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
5136 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
5137 break;
5138 case E_TSP_DST_FIFO_AUDIO :
5139 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
5140 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
5141 break;
5142 case E_TSP_DST_FIFO_AUDIO2 :
5143 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
5144 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
5145 break;
5146 default :
5147 printf("[%s][%s][%d] Clear AVPktNum Error\n",__FILE__,__FUNCTION__,__LINE__);
5148 break;
5149 }
5150 }
5151
_HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)5152 static MS_PHY _HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)
5153 {
5154 #ifdef HAL_MIU2_BASE
5155 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
5156 return (MS_PHY)HAL_MIU2_BASE;
5157 else
5158 #endif //HAL_MIU2_BUS_BASE
5159 #ifdef HAL_MIU1_BASE
5160 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
5161 return (MS_PHY)HAL_MIU1_BASE;
5162 else
5163 #endif //HAL_MIU1_BUS_BASE
5164 return (MS_PHY)HAL_MIU0_BASE;
5165 }
5166
HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)5167 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)
5168 {
5169 if(bEn == TRUE)
5170 {
5171 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
5172 }
5173 else
5174 {
5175 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
5176 }
5177 }
5178
HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH,MS_PHY u32AddrL)5179 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL)
5180 {
5181 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
5182
5183 REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK));
5184 REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK));
5185 }
5186
HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)5187 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)
5188 {
5189
5190 if(bEn == TRUE)
5191 {
5192 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
5193 }
5194 else
5195 {
5196 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
5197 }
5198 }
5199
HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID,MS_PHY u32AddrH,MS_PHY u32AddrL)5200 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL)
5201 {
5202 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
5203 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK);
5204 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK);
5205
5206 switch(u8SecID)
5207 {
5208 case 0:
5209 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd);
5210 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd);
5211 break;
5212 case 1:
5213 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd);
5214 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd);
5215 break;
5216 default:
5217 break;
5218 }
5219 }
5220
HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)5221 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)
5222 {
5223 if(bEnable)
5224 {
5225 switch(u32PVREng)
5226 {
5227 case 0:
5228 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
5229 break;
5230 case 1:
5231 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
5232 break;
5233 default:
5234 break;
5235 }
5236 }
5237 else
5238 {
5239 switch(u32PVREng)
5240 {
5241 case 0:
5242 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
5243 break;
5244 case 1:
5245 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
5246 break;
5247 default:
5248 break;
5249 }
5250 }
5251 }
5252
HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32AddrH,MS_PHY u32AddrL)5253 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32AddrH, MS_PHY u32AddrL)
5254 {
5255 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
5256 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK);
5257 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK);
5258
5259 switch(u32PVREng)
5260 {
5261 case 0:
5262 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd);
5263 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd);
5264 break;
5265 case 1:
5266 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd);
5267 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd);
5268 break;
5269 default:
5270 break;
5271 }
5272 }
5273
HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)5274 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)
5275 {
5276 if(bEnable)
5277 {
5278 switch(eFileEng)
5279 {
5280 case E_FILEENG_TSIF0:
5281 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
5282 break;
5283 case E_FILEENG_TSIF1:
5284 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
5285 break;
5286 case E_FILEENG_TSIF2:
5287 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
5288 break;
5289 default:
5290 break;
5291 }
5292 }
5293 else
5294 {
5295 switch(eFileEng)
5296 {
5297 case E_FILEENG_TSIF0:
5298 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
5299 break;
5300 case E_FILEENG_TSIF1:
5301 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
5302 break;
5303 case E_FILEENG_TSIF2:
5304 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
5305 break;
5306 default:
5307 break;
5308 }
5309 }
5310 }
5311
HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH,MS_PHY u32AddrL)5312 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL)
5313 {
5314 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
5315 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
5316 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
5317
5318 switch(eFileEng)
5319 {
5320 case E_FILEENG_TSIF0:
5321 REG32_W(&_RegCtrl6->CFG6_30_31, u32LBnd);
5322 REG32_W(&_RegCtrl6->CFG6_32_33, u32UBnd);
5323 break;
5324 case E_FILEENG_TSIF1:
5325 REG32_W(&_RegCtrl6->CFG6_34_35, u32LBnd);
5326 REG32_W(&_RegCtrl6->CFG6_36_37, u32UBnd);
5327 break;
5328 case E_FILEENG_TSIF2:
5329 REG32_W(&_RegCtrl6->CFG6_38_39, u32LBnd);
5330 REG32_W(&_RegCtrl6->CFG6_3A_3B, u32UBnd);
5331 break;
5332 default:
5333 break;
5334 }
5335 }
5336
HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)5337 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)
5338 {
5339 if(bEnable)
5340 {
5341 switch(u32MMFIEng)
5342 {
5343 case 0:
5344 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
5345 break;
5346 case 1:
5347 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
5348 break;
5349 default:
5350 break;
5351 }
5352 }
5353 else
5354 {
5355 switch(u32MMFIEng)
5356 {
5357 case 0:
5358 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
5359 break;
5360 case 1:
5361 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
5362 break;
5363 default:
5364 break;
5365 }
5366 }
5367 }
5368
HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH,MS_PHY u32AddrL)5369 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL)
5370 {
5371 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
5372 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
5373 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
5374
5375 switch(u32MMFIEng)
5376 {
5377 case 0:
5378 REG32_W(&_RegCtrl6->CFG6_48_49, u32LBnd);
5379 REG32_W(&_RegCtrl6->CFG6_4A_4B, u32UBnd);
5380 break;
5381 case 1:
5382 REG32_W(&_RegCtrl6->CFG6_4C_4D, u32LBnd);
5383 REG32_W(&_RegCtrl6->CFG6_4E_4F, u32UBnd);
5384 break;
5385 default:
5386 break;
5387 }
5388 }
5389
5390
HAL_TSP_SaveFltState(void)5391 void HAL_TSP_SaveFltState(void)
5392 {
5393 MS_U32 u32Size;
5394 TSP32 * pRegEnd;
5395 TSP32 * pReg;
5396 int i, j;
5397
5398 for (i = 0; i < TSP_PIDFLT_NUM; i++)
5399 {
5400 _u32PidFltReg[i] = TSP32_IdrR(&(_REGPid0->Flt[i]));
5401 _u32PidDstReg[i] = TSP32_IdrR(&(_REGPid1->Flt[i]));
5402 }
5403
5404 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
5405 for (i = 0; i < TSP_SECFLT_NUM; i++)
5406 {
5407 pReg = (TSP32*)&(_REGSec->Flt[i]);
5408 pRegEnd = pReg + u32Size;
5409 j = 0;
5410 for ( ; pReg < pRegEnd; pReg++)
5411 {
5412 _u32SecReg[i*u32Size+j] = TSP32_IdrR(pReg);
5413 j++;
5414 }
5415 }
5416 }
5417
5418
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)5419 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
5420 {
5421 //@TODO not implement yet
5422 return TRUE;
5423 }
5424
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_BOOL bEnable)5425 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable)
5426 {
5427 printf("[%s] not support!!\n",__FUNCTION__);
5428 return FALSE;
5429 }
5430
HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng,MS_U16 u16CaPvrMode,MS_BOOL bEnable)5431 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable)
5432 {
5433 MS_U16 u16value = REG16_R(&_RegCtrl3->CFG3_38);
5434
5435 switch(u32Eng)
5436 {
5437 case 0:
5438 u16value &= ~(HW4_CFG38_CA_PVR1_SEL_MASK|HW4_CFG38_PKT192_SPS_EN1);
5439 break;
5440 case 1:
5441 u16value &= ~(HW4_CFG38_CA_PVR2_SEL_MASK|HW4_CFG38_PKT192_SPS_EN2);
5442 break;
5443 default:
5444 return FALSE;
5445 }
5446
5447 if(bEnable)
5448 {
5449 switch(u32Eng)
5450 {
5451 case 0:
5452 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR1_SEL_SHIFT);
5453 u16value |= HW4_CFG38_PKT192_SPS_EN1;
5454 break;
5455 case 1:
5456 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR2_SEL_SHIFT);
5457 u16value |= HW4_CFG38_PKT192_SPS_EN2;
5458 break;
5459 default:
5460 return FALSE;
5461 }
5462 }
5463
5464 REG16_W(&_RegCtrl3->CFG3_38, u16value);
5465
5466 return TRUE;
5467
5468 }
5469
5470 //@TODO
5471 #if 1
HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng,MS_BOOL CTR_mode)5472 void HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng, MS_BOOL CTR_mode)
5473 {
5474 switch(u32Eng)
5475 {
5476 case 0: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN1);
5477 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR1_KEY);
5478 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
5479 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
5480 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
5481 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
5482 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
5483 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
5484 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
5485 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
5486 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY1);
5487 break;
5488 case 1: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN2);
5489 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR2_KEY);
5490 /*
5491 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x2222);//PVR SPS key
5492 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x2222);
5493 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x2222);
5494 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x2222);
5495 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x3333);
5496 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x3333);
5497 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x3333);
5498 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x3333);
5499 */
5500 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
5501 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
5502 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
5503 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
5504 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
5505 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
5506 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
5507 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
5508 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY2);
5509 break;
5510 default: printf("Not Support !!\n");
5511 break;
5512 }
5513
5514 if(CTR_mode == TRUE)
5515 {
5516 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05));
5517 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode
5518 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV
5519 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000);
5520 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000);
5521 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000);
5522 REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld
5523 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV
5524 }
5525 }
5526 #endif
5527
5528 // u32GroupId: 0 -> filter0 ~ filter31
5529 // u32GroupId: 1 -> filter32 ~ filter63
5530 // u32GroupId: 2 -> filter64 ~ filter95
5531 // u32GroupId: 3 -> filter96 ~ filter127
5532 // u32GroupId: 4 -> filter128 ~ filter159
5533 // u32GroupId: 5 -> filter160 ~ filter191
5534
5535
HAL_DSCMB_GetStatus(MS_U32 u32PktDmx,MS_U32 u32GroupId,MS_U32 u32PidFltId,MS_U32 * pu32ScmbSts)5536 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts)
5537 {
5538 MS_U16 u16PktDmxSrc;
5539 MS_U16 u16WordId;
5540 MS_U32 u32PIDFltMask = u32PidFltId;
5541
5542 if(u32PidFltId != 0xFFFFFFFF)
5543 {
5544 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
5545 }
5546
5547 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK);
5548
5549 switch(u32PktDmx)
5550 {
5551 case 0:
5552 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX0 << TSP_MATCH_PID_SRC_SHIFT);
5553 break;
5554 case 1:
5555 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX1 << TSP_MATCH_PID_SRC_SHIFT);
5556 break;
5557 case 2:
5558 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX2 << TSP_MATCH_PID_SRC_SHIFT);
5559 break;
5560 case 3:
5561 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX3 << TSP_MATCH_PID_SRC_SHIFT);
5562 break;
5563 default:
5564 break;
5565 }
5566
5567 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc);
5568
5569 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to load match_pid_num
5570
5571 // get status
5572 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze
5573
5574 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK);
5575
5576 if (u32GroupId < 6)
5577 {
5578 u16WordId = _SET_(u16WordId, u32GroupId << TSP_MATCH_PID_SEL_SHIFT);
5579 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId);
5580 }
5581 else
5582 {
5583 printf("[TSP_ERR][%s][%d] Unsupported u32GroupId (%lu)!!!\n",__FUNCTION__, __LINE__, (long unsigned int)u32GroupId);
5584 }
5585
5586 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask);
5587
5588 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable
5589
5590 if(u32PIDFltMask != 0xFFFFFFFF)
5591 {
5592 *pu32ScmbSts = ((*pu32ScmbSts > 0) ? 1: 0);
5593 }
5594
5595 return TRUE;
5596 }
5597
5598 // -------------------------------------------------------------
5599 // Merge Stream
5600 // -------------------------------------------------------------
HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path,MS_U8 u8Id,MS_U8 * pu8SyncByte,MS_BOOL bSet)5601 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SyncByte, MS_BOOL bSet)
5602 {
5603 REG16 *SynReg=0;
5604 MS_U16 u16Mask = 0x00FF, u16Sync = 0, u16Shift = 0;
5605
5606 switch(u8Path)
5607 {
5608 case TSP_TSIF0:
5609 SynReg = &(_RegCtrl6[0].SyncByte_tsif0[u8Id>>1]);
5610 break;
5611 case TSP_TSIF1:
5612 SynReg = &(_RegCtrl6[0].SyncByte_tsif1[u8Id>>1]);
5613 break;
5614 case TSP_TSIF2:
5615 SynReg = &(_RegCtrl6[0].SyncByte_tsif2[u8Id>>1]);
5616 break;
5617 default:
5618 return FALSE;
5619 }
5620
5621
5622 if(u8Id & 0x1)
5623 {
5624 u16Shift = 8;
5625 }
5626
5627 if(bSet == TRUE)
5628 {
5629 u16Sync = (MS_U16)(*pu8SyncByte & 0xFF);
5630 REG16_W(SynReg,((REG16_R(SynReg) & ~(u16Mask << u16Shift)) | (u16Sync << u16Shift)));
5631 }
5632 else
5633 {
5634 u16Sync = (REG16_R(SynReg) & (u16Mask << u16Shift)) >> u16Shift;
5635 *pu8SyncByte = (MS_U8)u16Sync;
5636 }
5637
5638 return TRUE;
5639
5640 }
5641
HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path,MS_U8 u8Id,MS_U8 * pu8SrcId,MS_BOOL bSet)5642 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SrcId, MS_BOOL bSet)
5643 {
5644 REG16 *SrcIdReg =0;
5645 MS_U16 u16SrcId = 0, u16Mask = 0x000F, u16Shift = 0;
5646
5647 switch(u8Path)
5648 {
5649 case TSP_TSIF0:
5650 SrcIdReg = &(_RegCtrl6[0].SourceId_tsif0[u8Id>>2]);
5651 break;
5652 case TSP_TSIF1:
5653 SrcIdReg = &(_RegCtrl6[0].SourceId_tsif1[u8Id>>2]);
5654 break;
5655 case TSP_TSIF2:
5656 SrcIdReg = &(_RegCtrl6[0].SourceId_tsif2[u8Id>>2]);
5657 break;
5658 default:
5659 return FALSE;
5660 }
5661
5662 switch(u8Id & 0x3)
5663 {
5664 case 0x1:
5665 u16Shift = 4;
5666 u16SrcId <<= 4;
5667 u16Mask <<= 4;
5668 break;
5669 case 0x2:
5670 u16Shift = 8;
5671 u16SrcId <<= 8;
5672 u16Mask <<= 8;
5673 break;
5674 case 0x3:
5675 u16Shift = 12;
5676 u16SrcId <<= 12;
5677 u16Mask <<= 12;
5678 break;
5679 }
5680
5681 if(bSet == TRUE)
5682 {
5683 u16SrcId = (MS_U16)(*pu8SrcId & 0xFF);
5684 REG16_W(SrcIdReg,((REG16_R(SrcIdReg) & ~(u16Mask << u16Shift)) | (u16SrcId << u16Shift)));
5685 }
5686 else
5687 {
5688 u16SrcId = (REG16_R(SrcIdReg) & (u16Mask << u16Shift)) >> u16Shift;
5689 *pu8SrcId = (MS_U8)u16SrcId;
5690 }
5691
5692 return TRUE;
5693 }
5694
HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path,MS_U8 u8PktHeaderLen)5695 static void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen)
5696 {
5697 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
5698
5699 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_MXL_PKT_HEADER_MASK)) | ((u8PktHeaderLen << TSP_MXL_PKT_HEADER_SHIFT) & TSP_MXL_PKT_HEADER_MASK)));
5700 }
5701
HAL_TSP_PktConverter_PktMode(MS_U8 u8Path,TSP_HAL_PKT_MODE ePktMode)5702 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode)
5703 {
5704 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
5705
5706 switch(ePktMode)
5707 {
5708 case E_TSP_HAL_PKT_MODE_NORMAL:
5709 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_188Mode));
5710 break;
5711 case E_TSP_HAL_PKT_MODE_CI:
5712 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_CIMode));
5713 break;
5714 case E_TSP_HAL_PKT_MODE_OPEN_CABLE:
5715 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_OpenCableMode));
5716 break;
5717 case E_TSP_HAL_PKT_MODE_ATS:
5718 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_ATSMode));
5719 break;
5720 case E_TSP_HAL_PKT_MODE_MXL_192:
5721 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
5722 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,4);
5723 break;
5724 case E_TSP_HAL_PKT_MODE_MXL_196:
5725 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
5726 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,8);
5727 break;
5728 case E_TSP_HAL_PKT_MODE_MXL_200:
5729 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
5730 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,12);
5731 break;
5732 default:
5733 printf("[TSP_ERR][%s][%d] Wrong PktConverter Packet Mode!!!\n",__FUNCTION__,__LINE__);
5734 return FALSE;
5735 }
5736
5737 return TRUE;
5738 }
5739
HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path,MS_BOOL bEnable)5740 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable)
5741 {
5742 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
5743
5744 if(bEnable)
5745 {
5746 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47)); // Set 1 to force sync byte be 0x47
5747 }
5748 else
5749 {
5750 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47));
5751 }
5752 }
5753
HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId,MS_U32 u32SrcId)5754 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId)
5755 {
5756 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
5757 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcId << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
5758 }
5759
HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId,MS_U32 u32SrcId)5760 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId)
5761 {
5762 switch(pcrFltId)
5763 {
5764 case 0:
5765 //src 0
5766 REG16_MSK_W(&_RegCtrl3->CFG3_72,CFG3_72_PIDFLT_PCR_SCR_ID_MASK,(u32SrcId << CFG3_72_PIDFLT_PCR0_SCR_ID_SHIFT));
5767 break;
5768 case 1:
5769 //src 1
5770 REG16_MSK_W(&_RegCtrl3->CFG3_72,CFG3_72_PIDFLT_PCR_SCR_ID_MASK<<CFG3_72_PIDFLT_PCR1_SCR_ID_SHIFT,(u32SrcId << CFG3_72_PIDFLT_PCR1_SCR_ID_SHIFT));
5771
5772 break;
5773 default:
5774 break;
5775 }
5776 }
5777
HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)5778 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)
5779 {
5780 MS_U8 u8Id;
5781 MS_U8 u8SyncByte;
5782
5783 u8SyncByte = 0x47;
5784 for(u8Id = 0; u8Id < TSP_MERGESTREAM_NUM; u8Id++,u8SyncByte++)
5785 {
5786 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Id, &u8SyncByte, TRUE);
5787 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Id, &u8Id, TRUE);
5788 }
5789 HAL_TSP_PktConverter_PktMode(u8Path,E_TSP_HAL_PKT_MODE_NORMAL);
5790 }
5791
5792
5793 //-------------------------------------------------------------------------------------------------
5794 // For Debug Table
5795 //-------------------------------------------------------------------------------------------------
5796
HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)5797 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)
5798 {
5799 switch (eFlow)
5800 {
5801 case E_TSP_HAL_FLOW_LIVE0:
5802 return E_TSP_SRC_PKTDMX0;
5803 case E_TSP_HAL_FLOW_LIVE1:
5804 return E_TSP_SRC_PKTDMX2;
5805 case E_TSP_HAL_FLOW_LIVE2:
5806 return E_TSP_SRC_PKTDMX1;
5807 case E_TSP_HAL_FLOW_FILE0:
5808 return E_TSP_SRC_PKTDMX1;
5809 case E_TSP_HAL_FLOW_FILE1:
5810 return E_TSP_SRC_PKTDMX2;
5811 case E_TSP_HAL_FLOW_FILE2:
5812 return E_TSP_SRC_PKTDMX0;
5813 case E_TSP_HAL_FLOW_MMFI0:
5814 return E_TSP_SRC_MMFI0;
5815 case E_TSP_HAL_FLOW_MMFI1:
5816 return E_TSP_SRC_MMFI1;
5817 default:
5818 printf("[TSP_ERR][%s][%d] UnSupported Debug Flow : %d !!!\n",__FUNCTION__, __LINE__,eFlow);
5819 return E_TSP_SRC_INVALID;
5820 }
5821 }
5822
HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)5823 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)
5824 {
5825 MS_U16 u16TSIF = 0;;
5826
5827 switch(u32TsIf)
5828 {
5829 case 0:
5830 u16TSIF = TSIF_SRC_SEL_TSIF0;
5831 break;
5832 case 1:
5833 u16TSIF = TSIF_SRC_SEL_TSIF1;
5834 break;
5835 case 2:
5836 u16TSIF = TSIF_SRC_SEL_TSIF2;
5837 break;
5838 default:
5839 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
5840 break;
5841 }
5842
5843 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_TSIF_SRC_SEL_MASK,(u16TSIF << CFG5_7F_TSIF_SRC_SEL_SHIFT));
5844 }
5845
HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)5846 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
5847 {
5848 if(bEn == TRUE)
5849 {
5850 switch(u32TsIf)
5851 {
5852 case 0:
5853 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
5854 break;
5855 case 1:
5856 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
5857 break;
5858 case 2:
5859 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
5860 break;
5861 default:
5862 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
5863 break;
5864 }
5865 }
5866 else
5867 {
5868 switch(u32TsIf)
5869 {
5870 case 0:
5871 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
5872 break;
5873 case 1:
5874 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
5875 break;
5876 case 2:
5877 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
5878 break;
5879 default:
5880 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
5881 break;
5882 }
5883 }
5884
5885 }
5886
HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf,MS_BOOL bLock)5887 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock)
5888 {
5889 if(bLock) // 188 mode
5890 {
5891 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
5892 }
5893 else // Non 188 mode
5894 {
5895 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
5896 }
5897
5898 return REG16_R(&_RegCtrl5->Locked_PKT_Cnt);
5899 }
5900
HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)5901 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)
5902 {
5903 switch (u32Tsif)
5904 {
5905 case 0 :
5906 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
5907 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
5908 break;
5909 case 1:
5910 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
5911 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
5912 break;
5913 case 2:
5914 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
5915 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
5916 break;
5917 default :
5918 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
5919 break;
5920 }
5921 }
5922
HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)5923 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)
5924 {
5925 switch (eClrSrc)
5926 {
5927 case E_TSP_SRC_PKTDMX0:
5928 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX0 << CFG5_7F_CLR_SRC_SHIFT);
5929 break;
5930 case E_TSP_SRC_PKTDMX1:
5931 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX1 << CFG5_7F_CLR_SRC_SHIFT);
5932 break;
5933 case E_TSP_SRC_PKTDMX2:
5934 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX2 << CFG5_7F_CLR_SRC_SHIFT);
5935 break;
5936 case E_TSP_SRC_PKTDMX3:
5937 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX3 << CFG5_7F_CLR_SRC_SHIFT);
5938 break;
5939 case E_TSP_SRC_MMFI0:
5940 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI0 << CFG5_7F_CLR_SRC_SHIFT);
5941 break;
5942 case E_TSP_SRC_MMFI1:
5943 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI1 << CFG5_7F_CLR_SRC_SHIFT);
5944 break;
5945 default:
5946 printf("[%s][%s][%d] UnSupported Clear Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,eClrSrc);
5947 break;
5948 }
5949 }
5950
HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)5951 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId)
5952 {
5953 MS_U16 u16AvSrc = 0;
5954
5955 switch(ePktDmxId)
5956 {
5957 case E_TSP_SRC_PKTDMX0:
5958 u16AvSrc = AV_PKT_SRC_PKTDMX0;
5959 break;
5960 case E_TSP_SRC_PKTDMX1:
5961 u16AvSrc = AV_PKT_SRC_PKTDMX1;
5962 break;
5963 case E_TSP_SRC_PKTDMX2:
5964 u16AvSrc = AV_PKT_SRC_PKTDMX2;
5965 break;
5966 case E_TSP_SRC_PKTDMX3:
5967 u16AvSrc = AV_PKT_SRC_PKTDMX3;
5968 break;
5969 case E_TSP_SRC_MMFI0:
5970 u16AvSrc = AV_PKT_SRC_MMFI0;
5971 break;
5972 case E_TSP_SRC_MMFI1:
5973 u16AvSrc = AV_PKT_SRC_MMFI1;
5974 break;
5975 default:
5976 printf("[%s][%s][%d] UnSupported AV Source : %d!\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
5977 break;
5978 }
5979
5980 switch (eAvType)
5981 {
5982 case E_TSP_DST_FIFO_VIDEO :
5983 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_SRC_MASK, u16AvSrc << CFG5_7E_VID_SRC_SHIFT);
5984 break;
5985 case E_TSP_DST_FIFO_VIDEO3D :
5986 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_3D_SRC_MASK, u16AvSrc << CFG5_7E_VID_3D_SRC_SHIFT);
5987 break;
5988 case E_TSP_DST_FIFO_AUDIO :
5989 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDA_SRC_MASK, u16AvSrc << CFG5_7E_AUDA_SRC_SHIFT);
5990 break;
5991 case E_TSP_DST_FIFO_AUDIO2 :
5992 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDB_SRC_MASK, u16AvSrc << CFG5_7E_AUDB_SRC_SHIFT);
5993 break;
5994 default:
5995 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
5996 break;
5997 }
5998 }
5999
HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)6000 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn)
6001 {
6002 if(bEn == TRUE)
6003 {
6004 switch (eAvType)
6005 {
6006 case E_TSP_DST_FIFO_VIDEO :
6007 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
6008 break;
6009 case E_TSP_DST_FIFO_VIDEO3D :
6010 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
6011 break;
6012 case E_TSP_DST_FIFO_AUDIO :
6013 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
6014 break;
6015 case E_TSP_DST_FIFO_AUDIO2 :
6016 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
6017 break;
6018 default :
6019 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6020 break;
6021 }
6022 }
6023 else
6024 {
6025 switch (eAvType)
6026 {
6027 case E_TSP_DST_FIFO_VIDEO :
6028 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
6029 break;
6030 case E_TSP_DST_FIFO_VIDEO3D :
6031 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
6032 break;
6033 case E_TSP_DST_FIFO_AUDIO :
6034 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
6035 break;
6036 case E_TSP_DST_FIFO_AUDIO2 :
6037 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
6038 break;
6039 default :
6040 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6041 break;
6042 }
6043 }
6044 }
6045
HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)6046 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)
6047 {
6048 switch (eAvType)
6049 {
6050 case E_TSP_DST_FIFO_VIDEO :
6051 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
6052 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
6053 case E_TSP_DST_FIFO_VIDEO3D:
6054 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
6055 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
6056 case E_TSP_DST_FIFO_AUDIO :
6057 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
6058 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
6059 case E_TSP_DST_FIFO_AUDIO2 :
6060 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
6061 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
6062 default :
6063 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6064 return 0;
6065 }
6066 }
6067
HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)6068 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)
6069 {
6070 switch (eAvType)
6071 {
6072 case E_TSP_DST_FIFO_VIDEO :
6073 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
6074 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
6075 break;
6076 case E_TSP_DST_FIFO_VIDEO3D :
6077 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
6078 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
6079 break;
6080 case E_TSP_DST_FIFO_AUDIO :
6081 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
6082 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
6083 break;
6084 case E_TSP_DST_FIFO_AUDIO2 :
6085 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
6086 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
6087 break;
6088 default :
6089 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6090 break;
6091 }
6092 }
6093
HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)6094 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)
6095 {
6096 MS_U16 u16AvType = 0;
6097
6098 switch(eAvType)
6099 {
6100 case E_TSP_DST_FIFO_VIDEO:
6101 u16AvType = DIS_DROP_CNT_V;
6102 break;
6103 case E_TSP_DST_FIFO_VIDEO3D:
6104 u16AvType = DIS_DROP_CNT_V3D;
6105 break;
6106 case E_TSP_DST_FIFO_AUDIO:
6107 u16AvType = DIS_DROP_CNT_A;
6108 break;
6109 case E_TSP_DST_FIFO_AUDIO2:
6110 u16AvType = DIS_DROP_CNT_AD;
6111 break;
6112 default:
6113 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6114 break;
6115 }
6116
6117 switch(ePktDmxId)
6118 {
6119 case E_TSP_SRC_PKTDMX0:
6120 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL_SHIFT));
6121 break;
6122 case E_TSP_SRC_PKTDMX1:
6123 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL1_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL1_SHIFT));
6124 break;
6125 case E_TSP_SRC_PKTDMX2:
6126 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL2_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL2_SHIFT));
6127 break;
6128 case E_TSP_SRC_MMFI0:
6129 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT));
6130 break;
6131 case E_TSP_SRC_MMFI1:
6132 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT));
6133 break;
6134 default:
6135 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
6136 break;
6137 }
6138 }
6139
HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)6140 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)
6141 {
6142 if(bEn == TRUE)
6143 {
6144 switch (eAvType)
6145 {
6146 case E_TSP_DST_FIFO_VIDEO :
6147 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
6148 break;
6149 case E_TSP_DST_FIFO_VIDEO3D :
6150 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
6151 break;
6152 case E_TSP_DST_FIFO_AUDIO :
6153 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
6154 break;
6155 case E_TSP_DST_FIFO_AUDIO2 :
6156 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
6157 break;
6158 default :
6159 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6160 break;
6161 }
6162 }
6163 else
6164 {
6165 switch (eAvType)
6166 {
6167 case E_TSP_DST_FIFO_VIDEO :
6168 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
6169 break;
6170 case E_TSP_DST_FIFO_VIDEO3D :
6171 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
6172 break;
6173 case E_TSP_DST_FIFO_AUDIO :
6174 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
6175 break;
6176 case E_TSP_DST_FIFO_AUDIO2 :
6177 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
6178 break;
6179 default :
6180 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6181 break;
6182 }
6183 }
6184 }
6185
HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)6186 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)
6187 {
6188 if(bPayload)
6189 {
6190 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
6191 }
6192 else
6193 {
6194 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
6195 }
6196
6197 if(bEn == TRUE)
6198 {
6199 switch (eAvType)
6200 {
6201 case E_TSP_DST_FIFO_VIDEO :
6202 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
6203 break;
6204 case E_TSP_DST_FIFO_VIDEO3D :
6205 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD);
6206 break;
6207 case E_TSP_DST_FIFO_AUDIO :
6208 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
6209 break;
6210 case E_TSP_DST_FIFO_AUDIO2 :
6211 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
6212 break;
6213 default :
6214 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6215 break;
6216 }
6217 }
6218 else
6219 {
6220 switch (eAvType)
6221 {
6222 case E_TSP_DST_FIFO_VIDEO :
6223 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
6224 break;
6225 case E_TSP_DST_FIFO_VIDEO3D :
6226 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V3D_LOAD);
6227 break;
6228 case E_TSP_DST_FIFO_AUDIO :
6229 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
6230 break;
6231 case E_TSP_DST_FIFO_AUDIO2 :
6232 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
6233 break;
6234 default :
6235 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6236 break;
6237 }
6238 }
6239 }
6240
HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId,MS_BOOL bDrop)6241 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop)
6242 {
6243 if(bDrop)
6244 {
6245 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
6246 }
6247 else
6248 {
6249 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
6250 }
6251
6252 switch (ePktDmxId)
6253 {
6254 case E_TSP_SRC_PKTDMX0:
6255 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_0);
6256 case E_TSP_SRC_PKTDMX1:
6257 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_1);
6258 case E_TSP_SRC_PKTDMX2:
6259 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_2);
6260 case E_TSP_SRC_PKTDMX3:
6261 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_3);
6262 case E_TSP_SRC_MMFI0:
6263 return REG16_R(&_RegCtrl5->CFG5_0B);
6264 case E_TSP_SRC_MMFI1:
6265 return REG16_R(&_RegCtrl5->CFG5_0C);
6266 default :
6267 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
6268 return 0;
6269 }
6270 }
6271
HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)6272 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)
6273 {
6274 switch (eAvType)
6275 {
6276 case E_TSP_DST_FIFO_VIDEO :
6277 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
6278 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
6279 break;
6280 case E_TSP_DST_FIFO_VIDEO3D :
6281 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
6282 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
6283 break;
6284 case E_TSP_DST_FIFO_AUDIO :
6285 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
6286 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
6287 break;
6288 case E_TSP_DST_FIFO_AUDIO2 :
6289 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
6290 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
6291 break;
6292 default :
6293 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6294 break;
6295 }
6296 }
6297
HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)6298 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)
6299 {
6300 switch (eAvType)
6301 {
6302 case E_TSP_DST_FIFO_VIDEO :
6303 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
6304 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
6305 break;
6306 case E_TSP_DST_FIFO_VIDEO3D :
6307 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
6308 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
6309 break;
6310 case E_TSP_DST_FIFO_AUDIO :
6311 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
6312 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
6313 break;
6314 case E_TSP_DST_FIFO_AUDIO2 :
6315 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
6316 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
6317 break;
6318 default :
6319 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
6320 break;
6321 }
6322 }
6323
HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)6324 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)
6325 {
6326 MS_U16 u16TSIF = 0;;
6327
6328 switch(u32TsIf)
6329 {
6330 case 0:
6331 u16TSIF = TSIF_SRC_SEL_TSIF0;
6332 break;
6333 case 1:
6334 u16TSIF = TSIF_SRC_SEL_TSIF1;
6335 break;
6336 case 2:
6337 u16TSIF = TSIF_SRC_SEL_TSIF2;
6338 break;
6339 default:
6340 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
6341 break;
6342 }
6343
6344 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_ERR_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_ERR_PKT_SRC_SEL_SHIFT));
6345 }
6346
HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)6347 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
6348 {
6349 if(bEn == TRUE)
6350 {
6351 switch(u32TsIf)
6352 {
6353 case 0:
6354 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
6355 break;
6356 case 1:
6357 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
6358 break;
6359 case 2:
6360 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
6361 break;
6362 default:
6363 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
6364 break;
6365 }
6366 }
6367 else
6368 {
6369 switch(u32TsIf)
6370 {
6371 case 0:
6372 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
6373 break;
6374 case 1:
6375 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
6376 break;
6377 case 2:
6378 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
6379 break;
6380 default:
6381 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
6382 break;
6383 }
6384 }
6385
6386 }
6387
HAL_TSP_Debug_ErrPktCnt_Get(void)6388 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void)
6389 {
6390 return REG16_R(&_RegCtrl5->Err_PKT_Cnt);
6391 }
6392
HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)6393 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)
6394 {
6395 switch (u32Tsif)
6396 {
6397 case 0 :
6398 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
6399 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
6400 break;
6401 case 1:
6402 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
6403 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
6404 break;
6405 case 2 :
6406 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
6407 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
6408 break;
6409 default :
6410 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
6411 break;
6412 }
6413 }
6414
HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)6415 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)
6416 {
6417 MS_U16 u16TSIF = 0;;
6418
6419 switch(u32TsIf)
6420 {
6421 case 0:
6422 u16TSIF = TSIF_SRC_SEL_TSIF0;
6423 break;
6424 case 1:
6425 u16TSIF = TSIF_SRC_SEL_TSIF1;
6426 break;
6427 case 2:
6428 u16TSIF = TSIF_SRC_SEL_TSIF2;
6429 break;
6430 default:
6431 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
6432 break;
6433 }
6434
6435 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_INPUT_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_INPUT_PKT_SRC_SEL_SHIT));
6436 }
6437
HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)6438 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
6439 {
6440 if(bEn == TRUE)
6441 {
6442 switch(u32TsIf)
6443 {
6444 case 0:
6445 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
6446 break;
6447 case 1:
6448 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
6449 break;
6450 case 2:
6451 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
6452 break;
6453 default:
6454 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
6455 break;
6456 }
6457 }
6458 else
6459 {
6460 switch(u32TsIf)
6461 {
6462 case 0:
6463 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
6464 break;
6465 case 1:
6466 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
6467 break;
6468 case 2:
6469 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
6470 break;
6471 default:
6472 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
6473 break;
6474 }
6475 }
6476 }
6477
HAL_TSP_Debug_InputPktCnt_Get(void)6478 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void)
6479 {
6480 return REG16_R(&_RegCtrl5->Input_PKT_Cnt);
6481 }
6482
HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)6483 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)
6484 {
6485 switch (u32Tsif)
6486 {
6487 case 0 :
6488 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
6489 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
6490 break;
6491 case 1:
6492 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
6493 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
6494 break;
6495 case 2 :
6496 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
6497 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
6498 break;
6499 default :
6500 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
6501 break;
6502 }
6503
6504 }
6505
HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng,MS_U32 u32FQSrc)6506 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc)
6507 {
6508 MS_U32 u32Src = 0xFF;
6509
6510 if(u32FQEng != 0)
6511 return FALSE;
6512
6513 switch(u32FQSrc)
6514 {
6515 case 0: // @NOTE : mapping for Playback0 (LIVE0)
6516 u32Src = TSP_FIQ_SRC_PATH0;
6517 break;
6518 case 1: // @NOTE : mapping for Playback1 (LIVE1)
6519 u32Src = TSP_FIQ_SRC_PATH1;
6520 break;
6521 case 2: // @NOTE : mapping for Playback2 (LIVE2)
6522 u32Src = TSP_FIQ_SRC_PATH2;
6523 break;
6524 default:
6525 return FALSE;
6526 }
6527
6528 REG16_MSK_W(&_RegCtrl6->CFG6_60, TSP_FIQ_MUX_MASK, (MS_U16)u32Src);
6529
6530 return TRUE;
6531 }
6532
HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)6533 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)
6534 {
6535 MS_U32 u32Src = 0xFF;
6536 MS_U32 u32Ret = 0xFF;
6537
6538 if(u32FQEng != 0)
6539 return FALSE;
6540
6541 u32Src = (MS_U32)(REG16_R(&_RegCtrl6->CFG6_60) & TSP_FIQ_MUX_MASK);
6542
6543 switch(u32Src)
6544 {
6545 case TSP_FIQ_SRC_PATH0:
6546 u32Ret = 0; // @NOTE : mapping for Playback0 (LIVE0)
6547 break;
6548 case TSP_FIQ_SRC_PATH1:
6549 u32Ret = 1; // @NOTE : mapping for Playback2 (LIVE2)
6550 break;
6551 case TSP_FIQ_SRC_PATH2:
6552 u32Ret = 2; // @NOTE : mapping for Playback1 (LIVE1)
6553 break;
6554 default:
6555 return FALSE;
6556 }
6557 return u32Ret;
6558 }
6559
HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng,MS_BOOL bFltNull)6560 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull)
6561 {
6562 // not implement yet
6563 return TRUE;
6564 }
6565