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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP_tee.h 98 // Description: Transport Stream Processor (TSP) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSP_TEE_REG_H_ 103 #define _TSP_TEE_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //-------------------------------------------------------------------------------------------------- 139 // Compliation Option 140 //-------------------------------------------------------------------------------------------------- 141 142 //------------------------------------------------------------------------------------------------- 143 // Harware Capability 144 //------------------------------------------------------------------------------------------------- 145 #define MIU_BUS 4 146 #define TSP_VQ_PITCH 208 147 #define TSP_VQ_NUM 4 //VQ0, VQ_file, VQ1, VQ_2 148 #define TSP_PVR_ENG_NUM 2 149 150 #define TSP_QMEM_SIZES 0x1000 // 16K bytes, 32bit aligment //0x4000 151 152 //------------------------------------------------ 153 // TS0 Bank 154 //------------------------------------------------ 155 #define REG_TSP0_FW_DMA_ADDR_L 0x78 156 #define TSP_FW_DMA_ADDR_MASK 0xFFFFFF 157 #define TSP_DNLD_ADDR_ALI_SHIFT 4 158 #define REG_TSP1_FW_DMA_ADDR_H 0x0A 159 #define TSP_FW_DMA_ADDR_H_MASK 0xFF 160 #define REG_TSP0_FW_DMA_NUM 0x79 161 162 #define REG_TSP1_ONEWAY 0x42 163 #define TSP_FW_ONEWAY 0x0008 164 165 #define REG_TSP0_PVR_HEAD1_L 0x50 166 #define REG_TSP0_PVR_HEAD1_H 0x51 167 #define REG_TSP0_PVR_MID1_L 0x52 168 #define REG_TSP0_PVR_MID1_H 0x53 169 #define REG_TSP0_PVR_TAIL1_L 0x54 170 #define REG_TSP0_PVR_TAIL1_H 0x55 171 172 #define REG_TSP0_PVR_HEAD2_L 0x01 173 #define REG_TSP0_PVR_HEAD2_H 0x02 174 #define REG_TSP0_PVR_MID2_L 0x03 175 #define REG_TSP0_PVR_MID2_H 0x04 176 #define REG_TSP0_PVR_TAIL2_L 0x05 177 #define REG_TSP0_PVR_TAIL2_H 0x06 178 179 #define REG_TSP0_PVR1_HEAD1_L 0x12 180 #define REG_TSP0_PVR1_HEAD1_H 0x13 181 #define REG_TSP0_PVR1_MID1_L 0x14 182 #define REG_TSP0_PVR1_MID1_H 0x15 183 #define REG_TSP0_PVR1_TAIL1_L 0x16 184 #define REG_TSP0_PVR1_TAIL1_H 0x17 185 186 #define REG_TSP0_PVR1_HEAD2_L 0x18 187 #define REG_TSP0_PVR1_HEAD2_H 0x19 188 #define REG_TSP0_PVR1_MID2_L 0x1A 189 #define REG_TSP0_PVR1_MID2_H 0x1B 190 #define REG_TSP0_PVR1_TAIL2_L 0x1C 191 #define REG_TSP0_PVR1_TAIL2_H 0x1D 192 193 #define REG_TSP0_FILE_ADDR_L 0x3A 194 #define REG_TSP0_FILE_ADDR_H 0x3B 195 #define REG_TSP0_FILE_SIZE_L 0x3C 196 #define REG_TSP0_FILE_SIZE_H 0x3D 197 198 //------------------------------------------------ 199 // TS1 Bank 200 //------------------------------------------------ 201 #define REG_TSP1_VQ0_BASE_L 0x20 202 #define REG_TSP1_VQ0_BASE_H 0x21 203 #define REG_TSP1_VQ0_SIZE 0x22 204 #define REG_TSP1_VQ1_BASE_L 0x56 205 #define REG_TSP1_VQ1_BASE_H 0x57 206 #define REG_TSP1_PVR_CFG 0x5A 207 #define REG_TSP1_CH_BW_WP_LD 0x0100 208 #define REG_TSP1_VQ1_SIZE 0x5C 209 #define REG_TSP1_VQ2_BASE_L 0x5E 210 #define REG_TSP1_VQ2_BASE_H 0x5F 211 #define REG_TSP1_VQ2_SIZE 0x64 212 #define REG_TSP1_VQ3_BASE_L 0x74 213 #define REG_TSP1_VQ3_BASE_H 0x75 214 #define REG_TSP1_VQ3_SIZE 0x76 215 216 //------------------------------------------------ 217 // MMFI Bank 218 //------------------------------------------------ 219 #define REG_MMFI_FILE_ADDR_L 0x08 220 #define REG_MMFI_FILE_ADDR_H 0x09 221 #define REG_MMFI_FILE_SIZE_L 0x0A 222 #define REG_MMFI_FILE_SIZE_H 0x0B 223 224 #define REG_MMFI1_FILE_ADDR_L 0x28 225 #define REG_MMFI1_FILE_ADDR_H 0x29 226 #define REG_MMFI1_FILE_SIZE_L 0x2A 227 #define REG_MMFI1_FILE_SIZE_H 0x2B 228 229 #endif // _TSP_TEE_REG_H_ 230