1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //////////////////////////////////////////////////////////////////////////////////////////////////// 78 // 79 // File name: regFQ.h 80 // Description: FQ Register Definition 81 // 82 //////////////////////////////////////////////////////////////////////////////////////////////////// 83 84 #ifndef _FQ_REG_H_ 85 #define _FQ_REG_H_ 86 87 //-------------------------------------------------------------------------------------------------- 88 // Global Definition 89 //-------------------------------------------------------------------------------------------------- 90 91 //-------------------------------------------------------------------------------------------------- 92 // Compliation Option 93 //-------------------------------------------------------------------------------------------------- 94 95 //------------------------------------------------------------------------------------------------- 96 // Harware Capability 97 //------------------------------------------------------------------------------------------------- 98 99 //------------------------------------------------------------------------------------------------- 100 // Type and Structure 101 //------------------------------------------------------------------------------------------------- 102 // Software 103 #define FQ_REG_CTRL_BASE (0x60A80UL * 2UL) 104 105 typedef struct _REG32_FQ 106 { 107 volatile MS_U16 L; 108 volatile MS_U16 empty_L; 109 volatile MS_U16 H; 110 volatile MS_U16 empty_H; 111 } REG32_FQ; 112 113 typedef struct _REG16_FQ 114 { 115 volatile MS_U16 data; 116 volatile MS_U16 _resv; 117 } REG16_FQ; 118 119 typedef struct _REG_FIQ 120 { 121 REG16_FQ Reg_fiq_config0; //0x40 122 #define FIQ_CFG0_SW_RSTZ 0x0001 //sw_rstz 123 #define FIQ_CFG0_PVR_ENABLE 0x0002 //stream2miu_en 124 #define FIQ_CFG0_RESET_WR_PTR 0x0004 //str2miu_rst_wadr 125 #define FIQ_CFG0_FIQ2MI_DSWAP 0x0008 126 #define FIQ_CFG0_FIQ2MI_BITORD_BIG 0x0010 127 #define FIQ_CFG0_PVR_PAUSE 0x0020 128 #define FIQ_CFG0_LOAD_WR_PTR 0x0040 //strm2mi2_wp_ld 129 #define FIQ_CFG0_MIU_HIGH_PRI 0x0080 130 #define FIQ_CFG0_FORCE_SYNC_EN 0x0100 131 #define FIQ_CFG0_REC_AT_SYNC_DIS 0x0200 132 #define FIQ_CFG0_CLR_PVR_OVERFLOW 0x0400 133 #define FIQ_CFG0_FIQ2MI_R_PRT_HIGHT 0x0800 134 #define FIQ_CFG0_BURST_LEN_MASK 0x3000 135 #define FIQ_CFG0_BURST_LEN_8BYTE 0x0000 136 #define FIQ_CFG0_BURST_LEN_4BYTE 0x1000 137 #define FIQ_CFG0_BURST_LEN_1BYTE 0x3000 138 #define FIQ_CFG0_RUSH_ENABLE 0x4000 //rush_en 139 #define FIQ_CFG0_ADDR_MODE 0x8000 //addr_mode 140 141 #define FIQ_STR2MI2_ADDR_MASK 0x0FFFFFFF 142 REG32_FQ str2mi_head; //0x41 143 REG32_FQ str2mi_tail; //0x43 144 REG32_FQ str2mi_mid; //0x45 145 REG32_FQ rush_addr; //0x47 146 REG32_FQ cur_pkt_start_wadr_offset; //0x49 147 148 REG16_FQ Reg_fiq_config11; //0x4b 149 #define FIQ_CFG11_FIQ_BYPASS 0x0001 //FIQ_bypass 150 #define FIQ_CFG11_BURST_LEVEL_MASK 0x0006 151 #define FIQ_CFG11_BURST_LEVEL_25 0x0000 152 #define FIQ_CFG11_BURST_LEVEL_50 0x0002 153 #define FIQ_CFG11_BURST_LEVEL_75 0x0004 154 #define FIQ_CFG11_BURST_LEVEL_100 0x0006 155 #define FIQ_CFG11_SKIP_RUSH_DATA_PATH_MASK 0x13F8 156 #define FIQ_CFG11_SKIP_RUSH_DATA_PATH_NON 0x0000 157 #define FIQ_CFG11_SKIP_APES_RUSH_DATA 0x0008 //skip_apes_rush_data 158 #define FIQ_CFG11_SKIP_APES_B_RUSH_DATA 0x0010 //skip_apes_b_rush_data 159 #define FIQ_CFG11_SKIP_VPES_RUSH_DATA 0x0020 //skip_vpes_rush_data 160 #define FIQ_CFG11_SKIP_SEC_RUSH_DATA 0x0040 //skip_sec_rush_data 161 #define FIQ_CFG11_SKIP_ADP_RUSH_DATA 0x0080 //skip_adp_rush_data 162 #define FIQ_CFG11_SKIP_PCR_RUSH_DATA 0x0100 //skip_pcr_rush_data 163 #define FIQ_CFG11_SKIP_RASP_RUSH_DATA 0x0000 164 #define FIQ_CFG11_SKIP_PVR1_RUSH_DATA 0x0200 //skip_PVR1_rush_data 165 #define FIQ_CFG11_LPCR1_WLD 0x0400 166 #define FIQ_CFG11_LPCR1_LOAD 0x0800 167 #define FIQ_CFG11_SKIP_PCR1_RUSH_DATA 0x1000 168 #define FIQ_CFG11_TIMESTAMP_SRC_SEL 0x2000 169 #define FIQ_CFG11_C27M_EN_FIQ 0x4000 170 171 #define FIQ_CFG11_SKIP_RUSH_DATA_PATH1_MASK 0x0238 172 #define FIQ_CFG11_SKIP_RUSH_DATA_PATH1_NON 0x0000 173 #define FIQ_CFG11_SKIP_APES_C_RUSH_DATA 0x0008 174 #define FIQ_CFG11_SKIP_APES_D_RUSH_DATA 0x0010 175 #define FIQ_CFG11_SKIP_V3DPES_RUSH_DATA 0x0020 176 #define FIQ_CFG11_SKIP_PVR2_RUSH_DATA 0x0200 177 #define FIQ_CFG11_SKIP_PVR3_RUSH_DATA 0x0000 178 179 REG32_FQ pkt_addr_offset; //0x4c 180 REG16_FQ REG_FIQ0_CFG2; //0x4e 181 REG16_FQ REG_FIQ0_CFG3; //0x4f 182 183 REG16_FQ Reg_fiq_config16; //0x50 184 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF 185 #define FIQ_CFG16_INT_ENABLE_RUSH_DONE 0x0001 186 #define FIQ_CFG16_INT_ENABLE_PVR_MEET_BUFTAIL 0x0002 187 #define FIQ_CFG16_INT_ENABLE_PVR_MEET_BUFMID 0x0004 188 #define FIQ_CFG16_INT_STATUS_MASK 0xFF00 189 #define FIQ_CFG16_INT_STATUS_RUSH_DONE 0x0100 190 191 REG32_FQ str2mi2_wadr_r; //0x51 192 REG32_FQ Fiq2mi2_radr_r; //0x53 193 REG16_FQ Fiq_status; //0x55 194 #define FIQ_STATUS_PVRFIFO_EMPTY 0x0001 195 #define FIQ_STATUS_PVRFIFO_FULL 0x0002 196 #define FIQ_STATUS_PVRFIFO_WLEVEL_MASK 0x000C 197 #define FIQ_STATUS_PVRFIFO_EVEN_OVF 0x0010 198 REG32_FQ lpcr1; //0x56 199 200 REG32_FQ REG18_1F_RESERVED[4]; //0x58~0x5F 201 202 }REG_FIQ; 203 204 205 #endif // _FQ_REG_H_ 206