1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP.h 98 // Description: Transport Stream Processor (TSP) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSP_REG_H_ 103 #define _TSP_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TS_PACKET_SIZE 188UL 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 #define TSP_LIVE_AV_BLOCK_EN //for maserati , live path should enable AV fifo block, since dscmb behavior change 143 144 145 //[CMODEL][FWTSP] 146 // When enable, interrupt will not lost, CModel will block next packet 147 // and FwTSP will block until interrupt status is clear by MIPS. 148 // (For firmware and cmodel only) 149 #define TSP_DBG_SAFE_MODE_ENABLE 0UL 150 151 //------------------------------------------------------------------------------------------------- 152 // Harware Capability 153 //------------------------------------------------------------------------------------------------- 154 #define TSP_PIDFLT_NUM 128UL 155 156 #define TSP_PVR_IF_NUM 2UL 157 #define TSP_MMFI0_FILTER_NUM 4UL 158 #define TSP_MMFI1_FILTER_NUM 4UL 159 #define TSP_IF_NUM 4UL 160 #define TSP_DEMOD_NUM 2UL 161 #define TSP_VFIFO_NUM 2UL 162 #define TSP_AFIFO_NUM 4UL 163 #define TSP_TS_PAD_NUM 5UL // 2P(IN) + 2P(IN/OUT) + 1S 164 #define TSP_VQ_NUM 4UL //VQ0, VQ_file, VQ1, VQ_2 165 #define TSP_VQ_PITCH 208UL 166 #define TSP_CA_ENGINE_NUM 3UL 167 #define TSP_CA_KEY_NUM 8UL 168 #define TSP_CA0_FLT_NUM 128UL 169 #define TSP_CA1_FLT_NUM 128UL 170 #define TSP_CA_FLT_NUM 128UL 171 #define TSP_MERGESTR_MUM 8UL 172 #define TSP_ENGINE_NUM 1UL 173 #define TSP_SECFLT_NUM 128UL 174 #define TSP_PCRFLT_NUM 4UL 175 #define TSP_STC_NUM 4UL 176 177 #ifdef HWPCR_ENABLE 178 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+TSP_PCRFLT_NUM) 179 #else 180 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM) 181 #endif 182 183 #define TSP_SECBUF_NUM TSP_SECFLT_NUM 184 #define TSP_FILTER_DEPTH 16UL 185 186 #define TSP_WP_SET_NUM 4UL 187 188 #define DSCMB_FLT_START_ID 16UL 189 #define DSCMB_FLT_END_ID 31UL 190 #define DSCMB_FLT_NUM 16UL 191 192 #define DSCMB1_FLT_START_ID 32UL 193 #define DSCMB1_FLT_END_ID 47UL 194 #define DSCMB1_FLT_NUM 16UL 195 196 #define DSCMB2_FLT_START_ID 48UL 197 #define DSCMB2_FLT_END_ID 63UL 198 #define DSCMB2_FLT_NUM 16UL 199 200 #define DSCMB_FLT_SHAREKEY_START_ID 64UL 201 #define DSCMB_FLT_SHAREKEY_END_ID 127UL 202 #define DSCMB_FLT_SHAREKEY_NUM 128UL 203 204 #define DSCMB_FLT_SHAREKEY1_START_ID 64UL 205 #define DSCMB_FLT_SHAREKEY1_END_ID 127UL 206 #define DSCMB_FLT_SHAREKEY1_NUM 128UL 207 208 #define DSCMB_FLT_SHAREKEY2_START_ID 64UL 209 #define DSCMB_FLT_SHAREKEY2_END_ID 127UL 210 #define DSCMB_FLT_SHAREKEY2_NUM 128UL 211 212 #define TSP_NMATCH_FLTID 17UL 213 214 215 //PAD MUX definition 216 #define TSP_MUX_TS0 0UL 217 #define TSP_MUX_TS1 1UL 218 #define TSP_MUX_TS2 2UL 219 #define TSP_MUX_TS3 3UL 220 #define TSP_MUX_TS4 4UL 221 #define TSP_MUX_TSO 6UL 222 #define TSP_MUX_INDEMOD 7UL 223 #define TSP_MUX_3WIRE_MASK 0x80UL 224 #define TSP_MUX_TSCB 0xFFUL //not support 225 #define TSP_MUX_NONE 0xFF 226 227 //Clk source definition 228 #define TSP_CLK_DISABLE 0x01UL 229 #define TSP_CLK_INVERSE 0x02UL 230 #define TSP_CLK_TS0 0x00UL 231 #define TSP_CLK_TS1 0x04UL 232 #define TSP_CLK_TS2 0x08UL 233 #define TSP_CLK_TS3 0x0CUL 234 #define TSP_CLK_TS4 0x10UL 235 #define TSP_CLK_TSOOUT 0x18UL 236 #define TSP_CLK_INDEMOD 0x1CUL 237 #define CLKGEN0_TSP_CLK_MASK 0x1CUL 238 #define TSP_CLK_TSCB 0xFFUL //not support 239 240 //PIDFLT1,2 source definition 241 #define TSP_PIDFLT1_USE_TSIF1 0UL 242 #define TSP_PIDFLT2_USE_TSIF2 1UL 243 #define TSP_PIDFLT1_USE_TSIF_MMFI0 2UL 244 #define TSP_PIDFLT2_USE_TSIF_MMFI1 3UL 245 246 247 #define TSP_FW_DEVICE_ID 0x67UL 248 249 #define STC_SYNTH_DEFAULT 0x28000000UL 250 251 #define DRAM_SIZE (0x80000000UL) 252 #define TSP_FW_BUF_SIZE (0x4000UL) 253 #define TSP_FW_BUF_LOW_BUD 0UL 254 #define TSP_FW_BUF_UP_BUD DRAM_SIZE 255 256 #define TSP_VQ_BUF_LOW_BUD 0UL 257 #define TSP_VQ_BUF_UP_BUD (0xFFFFFFFFUL) 258 259 #define TSP_SEC_BUF_LOW_BUD 0UL 260 #define TSP_SEC_BUF_UP_BUD (0xFFFFFFFFUL) 261 #define TSP_SEC_FLT_DEPTH 32UL 262 #define TSP_FIQ_NUM 1UL 263 264 //QMEM Setting 265 #define _TSP_QMEM_I_MASK 0xffff8000UL //total: 0x4000 266 #define _TSP_QMEM_I_ADDR_HIT 0x00000000UL 267 #define _TSP_QMEM_I_ADDR_MISS 0xffffffffUL 268 #define _TSP_QMEM_D_MASK 0xffff8000UL 269 #define _TSP_QMEM_D_ADDR_HIT 0x00000000UL 270 #define _TSP_QMEM_D_ADDR_MISS 0xffffffffUL 271 #define _TSP_QMEM_SIZE 0x1000UL // 16K bytes, 32bit aligment //0x4000 272 273 //------------------------------------------------------------------------------------------------- 274 // Type and Structure 275 //------------------------------------------------------------------------------------------------- 276 277 // Software 278 #define REG_PIDFLT_L_BASE (0x00210000UL << 1UL) // Fit the size of REG32, 0~127 279 #define REG_PIDFLT_H_BASE (0x00210800UL << 1UL) // Fit the size of REG32, 0~127 280 281 #define REG_PIDFLT_L_EXT_BASE (0x00210400UL << 1UL) // Fit the size of REG32, 128~143 282 #define REG_PIDFLT_H_EXT_BASE (0x00210C00UL << 1UL) // Fit the size of REG32, 128~143 283 284 #define REG_SECFLT_BASE1 (0x00211000UL << 1UL) // Fix the size of REG32 285 #define REG_SECFLT_BASE2 (0x00215000UL << 1UL) // Fix the size of REG32 286 287 #define REG_CTRL_BASE (0x2A00UL) // 0xBF800000+(1500/2)*4 288 #define REG_CTRL_MMFIBASE (0x39C0UL) // 0xBF800000+(3800/2)*4 (TSP2: debug table), from 0x70 289 #define REG_CTRL_TSP3 (0xC1440UL) // 0xBF800000+(60a20/2)*4 290 #define REG_CTRL_TSP4 (0xC2E00UL) // 0xBF800000+(61700/2)*4 291 #define REG_CTRL_TSP5 (0xC7600UL) // 0xBF800000+(63b00/2)*4 292 #define REG_CTRL_TSP6 (0xC3E00UL) // 0xBF800000+(61f00/2)*4 293 #define REG_CTRL_TS_SAMPLE (0x21400UL) // 0xBF800000+(10A00/2)*4 294 295 typedef struct _REG32 296 { 297 volatile MS_U16 L; 298 volatile MS_U16 empty_L; 299 volatile MS_U16 H; 300 volatile MS_U16 empty_H; 301 } REG32; 302 303 typedef struct _REG32_L 304 { 305 volatile MS_U32 data; 306 volatile MS_U32 _resv; 307 } REG32_L; 308 309 typedef struct _REG16 310 { 311 volatile MS_U16 u16data; 312 volatile MS_U16 _null; 313 } REG16; 314 315 typedef REG32 REG_PidFlt; 316 317 //******************** PIDFLT DEFINE START ********************// 318 // PID 319 #define TSP_PIDFLT_PID_MASK 0x00001FFFUL 320 #define TSP_PIDFLT_PID_SHFT 0UL 321 322 // PIDFLT SRC 323 #define TSP_PIDFLT_IN_MASK 0x0000E000UL 324 #define TSP_PIDFLT_IN_NONE 0x00000000UL 325 #define TSP_PIDFLT_IN_PIDFLT0 0x00002000UL 326 #define TSP_PIDFLT_IN_PIDFLT_FILE 0x00004000UL 327 #define TSP_PIDFLT_IN_PIDFLT1 0x00006000UL 328 #define TSP_PIDFLT_IN_PIDFLT2 0x00008000UL 329 #define TSP_PIDFLT_IN_PIDFLT_CB 0UL //not support 330 #define TSP_PIDFLT_IN_SHIFT 13UL 331 332 // Section filter Id (0~128) 333 #define TSP_PIDFLT_SECFLT_MASK 0x000007F0UL // [38:32] secflt id 334 #define TSP_PIDFLT_SECFLT_SHFT 4UL 335 336 // Stream source ID 337 #define TSP_PIDFLT_IN_SRC_MASK 0x0000000FUL // [42:39] stream source id 338 #define TSP_PIDFLT_IN_SRC_SHFT 0UL 339 340 // AF/Sec/Video/V3D/Audio/Audio-second/PVR1/PVR2 341 #define TSP_PIDFLT_OUT_MASK 0xFFE00000UL 342 #define TSP_PIDFLT_OUT_NONE 0x00000000UL 343 #define TSP_PIDFLT_RUSH_PASS 0x00100000UL 344 #define TSP_PIDFLT_OUT_AFIFO4 0x00200000UL 345 #define TSP_PIDFLT_OUT_AFIFO3 0x00400000UL 346 #define TSP_PIDFLT_OUT_SECFLT_AF 0x01000000UL 347 #define TSP_PIDFLT_OUT_SECFLT 0x02000000UL 348 #define TSP_PIDFLT_OUT_VFIFO 0x04000000UL 349 #define TSP_PIDFLT_OUT_VFIFO3D 0x08000000UL 350 #define TSP_PIDFLT_OUT_AFIFO 0x10000000UL 351 #define TSP_PIDFLT_OUT_AFIFO2 0x20000000UL 352 #define TSP_PIDFLT_OUT_PVR1 0x80000000UL 353 #define TSP_PIDFLT_OUT_PVR2 0x40000000UL 354 355 #define TSP_PIDFLT_SECFLT_NULL 0x7FUL // software usage clean selected section filter 356 //******************** PIDFLT DEFINE END ********************// 357 358 typedef struct _REG_SecFlt 359 { 360 REG32 Ctrl; 361 // SW flag 362 #define TSP_SECFLT_TYPE_MASK 0x01000007UL 363 #define TSP_SECFLT_TYPE_SHFT 0UL 364 #define TSP_SECFLT_TYPE_SEC 0x00000000UL 365 #define TSP_SECFLT_TYPE_PES 0x00000001UL 366 #define TSP_SECFLT_TYPE_PKT 0x00000002UL 367 #define TSP_SECFLT_TYPE_PCR 0x00000003UL 368 #define TSP_SECFLT_TYPE_TTX 0x00000004UL 369 #define TSP_SECFLT_TYPE_VER 0x00000005UL 370 #define TSP_SECFLT_TYPE_EMM 0x00000006UL 371 #define TSP_SECFLT_TYPE_ECM 0x00000007UL 372 #define TSP_SECFLT_TYPE_SEC_NO_PUSI 0x01000000UL 373 374 #define TSP_SECFLT_PCRRST 0x00000010UL // for TSP_SECFLT_TYPE_PCR 375 376 #define TSP_SECFLT_MODE_MASK 0x00000030UL // software implementation 377 #define TSP_SECFLT_MODE_SHFT 4UL 378 #define TSP_SECFLT_MODE_CONTI 0x0UL 379 #define TSP_SECFLT_MODE_ONESHOT 0x1UL 380 #define TSP_SECFLT_MODE_CRCCHK 0x2UL 381 #define TSP_SECFLT_MODE_PESSCMCHK 0x3UL //Only for PES type checking SCMB status 382 383 #define TSP_SECFLT_STATE_MASK 0x000000C0UL // software implementation 384 #define TSP_SECFLT_STATE_SHFT 6UL 385 #define TSP_SECFLT_STATE_OVERFLOW 0x1UL 386 #define TSP_SECFLT_STATE_DISABLE 0x2UL 387 388 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 389 390 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 391 392 REG32 BufStart; 393 #define TSP_SECFLT_BUFSTART_MASK 0xFFFFFFFFUL 394 395 REG32 BufEnd; 396 397 REG32 BufRead; 398 399 REG32 BufWrite; 400 401 REG32 BufCur; 402 403 REG32 RmnReqCnt; 404 #define TSP_SECFLT_OWNER_MASK 0x80000000UL 405 #define TSP_SECFLT_OWNER_SHFT 31UL 406 #define TSP_SECFLT_REQCNT_MASK 0x7FFF0000UL 407 #define TSP_SECFLT_REQCNT_SHFT 16UL 408 #define TSP_SECFLT_RMNCNT_MASK 0x0000FFFFUL 409 #define TSP_SECFLT_RMNCNT_SHFT 0UL 410 411 REG32 CRC32; 412 413 REG32 _x50[16]; // (0x210080-0x210050)/4 414 } REG_SecFlt; 415 416 417 typedef struct _REG_Stc 418 { 419 REG32 ML; 420 REG32_L H32; 421 } REG_Stc; 422 423 typedef struct _REG_Pid 424 { // Index(word) CPU(byte) Default 425 REG_PidFlt Flt[TSP_PIDFLT_NUM]; 426 } REG_Pid; 427 428 typedef struct _REG_Sec 429 { // Index(word) CPU(byte) Default 430 REG_SecFlt Flt[TSP_SECFLT_NUM]; 431 } REG_Sec; 432 433 typedef struct _REG_Ctrl 434 { 435 //---------------------------------------------- 436 // 0xBF802A00 MIPS direct access 437 //---------------------------------------------- 438 // Type Name Index(word) CPU(byte) MIPS(0x1500/2+index)*4 439 REG32 TsRec_Head20; // 0xbf802a00 0x00 440 #define TSP_HW_PVR_BUF_HEAD20_MASK 0xFFFF0000UL 441 #define TSP_HW_PVR_BUF_HEAD20_SHFT 16UL 442 443 REG32 TsRec_Head21_Mid20_Wptr; // 0xbf802a08 0x02 ,wptr & mid share same register 444 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x00000FFFUL 445 #define TSP_HW_PVR_BUF_HEAD21_SHFT 0UL 446 #define TSP_HW_PVR_BUF_MID20_MASK 0xFFFF0000UL 447 #define TSP_HW_PVR_BUF_MID20_SHFT 16UL 448 449 REG32 TsRec_Mid21_Tail20; // 0xbf802a10 0x04 450 #define TSP_HW_PVR_BUF_MID21_MASK 0x00000FFFUL 451 #define TSP_HW_PVR_BUF_MID21_SHFT 0UL 452 #define TSP_HW_PVR_BUF_TAIL20_MASK 0xFFFF0000UL 453 #define TSP_HW_PVR_BUF_TAIL20_SHFT 16UL 454 455 REG32 TsRec_Tail2_Pcr1; // 0xbf802a18 0x06 456 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x00000FFFUL 457 #define TSP_HW_PVR_BUF_TAIL21_SHFT 0UL // PCR64 L16 458 #define TSP_PCR64_L16_MASK 0xFFFF0000UL 459 #define TSP_PCR64_L16_SHFT 16UL 460 461 REG32 Pcr1; // 0xbf802a20 0x08 462 #define TSP_PCR64_MID32_MASK 0xFFFFFFFFUL // PCR64 Middle 64 463 #define TSP_PCR64_MID32_SHFT 0UL 464 465 REG32 Pcr64_H; // 0xbf802a28 0x0a 466 #define TSP_PCR64_H16_MASK 0x0000FFFFUL 467 #define TSP_PCR64_H16_SHFT 0UL 468 #define TSP_MOBF_FILE_INDEX_MASK 0x001F0000UL // MOBF file index 469 #define TSP_MOBF_FILE_INDEX_SHIFT 16UL 470 471 REG16 _xbf202a30; // 0xbf802a30 0x0c 472 473 REG16 SW_Mail_Box0; // 0xbf802a34 0x0d 474 475 REG32 PVR2_Config; // 0xbf802a38 0x0e 476 #define TSP_PVR2_LPCR1_WLD 0x00000001UL 477 #define TSP_PVR2_LPCR1_RLD 0x00000002UL 478 #define TSP_PVR2_STR2MIU_DSWAP 0x00000004UL 479 #define TSP_PVR2_STR2MIU_EN 0x00000008UL 480 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL 481 #define TSP_PVR2_STR2MIU_BT_ORDER 0x00000020UL 482 #define TSP_PVR2_STR2MIU_PAUSE 0x00000040UL 483 #define TSP_PVR2_REG_PINGPONG_EN 0x00000080UL 484 #define TSP_PVR2_PVR_ALIGN_EN 0x00000100UL 485 #define TSP_PVR2_DMA_FLUSH_EN 0x00000200UL 486 #define TSP_PVR2_PKT192_EN 0x00000400UL 487 #define TSP_PVR2_BURST_LEN_MASK 0x00001800UL 488 #define TSP_PVR2_BURST_LEN_4 0x00000800UL 489 #define TSP_REC_DATA2_INV 0x00002000UL 490 #define TSP_V_BLOCK_DIS 0x00004000UL 491 #define TSP_V3D_BLOCK_DIS 0x00008000UL 492 #define TSP_AUD_BLOCK_DIS 0x00010000UL 493 #define TSP_AUDB_BLOCK_DIS 0x00020000UL 494 #define TSP_PVR1_BLOCK_DIS 0x00040000UL 495 #define TSP_PVR2_BLOCK_DIS 0x00080000UL 496 #define TSP_TSIF2_ENABLE 0x00100000UL 497 #define TSP_TSIF2_DATASWAP 0x00200000UL 498 #define TSP_TSIF2_SERL 0x00000000UL 499 #define TSP_TSIF2_PARL 0x00400000UL 500 #define TSP_TSIF2_EXTSYNC 0x00800000UL 501 #define TSP_TSIF2_BYPASS 0x01000000UL 502 #define TSP_TEI_SKIP_PKT2 0x02000000UL 503 #define TSP_AUDC_BLOCK_DIS 0x04000000UL 504 #define TSP_AUDD_BLOCK_DIS 0x08000000UL 505 #define TSP_DIS_LOCKED_PKT_CNT 0x10000000UL 506 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000UL 507 #define TSP_CLR_AV_PKT_CNT 0x40000000UL 508 #define TSP_CLR_PVR_OVERFLOW 0x80000000UL 509 510 REG32 PVR2_LPCR1; // 0xbf802a40 0x10 511 512 #define TSP_STR2MI2_ADDR_MASK 0x0FFFFFFFUL 513 REG32 Str2mi_head1_pvr2; // 0xbf802a48 0x12 514 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 515 REG32 Str2mi_tail1_pvr2; // 0xbf802a58 0x16 516 REG32 Str2mi_head2_pvr2; // 0xbf802a60 0x18 517 REG32 Str2mi_mid2_pvr2; // 0xbf802a68 0x1a, PVR2 mid address & write point 518 REG32 Str2mi_tail2_pvr2; // 0xbf802a70 0x1c 519 REG32 SyncByte2_ChkSize; // 0xbf802a78 0x1e 520 #define TSP_SYNC_BYTE2_MASK 0x000000FFUL 521 #define TSP_PKT_SIZE2_MASK 0x0000FF00UL 522 #define TSP_PKT_SIZE2_SHIFT 8UL 523 #define TSP_PKT_CHK_SIZE2_MASK 0x00FF0000UL 524 #define TSP_PKT_CHK_SIZE2_SHIFT 16UL 525 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 526 527 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 528 529 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 530 531 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 532 533 REG32_L Pkt_CacheIdx; // 0xbf802aa0 0x28 534 535 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 536 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FFUL 537 #define TSP_SEC_DMAFIL_NUM_SHIFT 0UL 538 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 539 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8UL 540 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 541 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000UL 542 #define TSP_SEC_DMADES_LEN_SHIFT 16UL 543 544 REG32 Hw_Config0; // 0xbf802ab0 0x2c 545 #define TSP_HW_CFG0_DATA_PORT_EN 0x00000001UL 546 #define TSP_HW_CFG0_TSIFO_SERL 0x00000000UL 547 #define TSP_HW_CFG0_TSIF0_PARL 0x00000002UL 548 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x00000004UL 549 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x00000008UL 550 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x00000010UL 551 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x00000020UL 552 #define TSP_HW_CFG0_WB_DMA_RESET 0x00000040UL 553 #define TSP_HW_CFG0_TSIF0_APID_B_BYPASS 0x00000080UL 554 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0x0000FF00UL 555 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8UL 556 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF0000UL 557 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 16UL 558 #define TSP_HW_CFG0_PACKET_CHK_SIZE_MASK 0xFF000000UL 559 #define TSP_HW_CFG0_PACKET_CHK_SIZE_SHFT 24UL 560 561 REG32 TSP_DBG_PORT; // 0xbf802ab8 0x2e 562 #define TSP_PCR64_3_SET 0x00000001UL 563 #define TSP_PCR64_3_EN 0x00000002UL 564 #define TSP_PCR64_3_LD 0x00000004UL 565 #define TSP_PCR64_4_SET 0x00000010UL 566 #define TSP_PCR64_4_EN 0x00000020UL 567 #define TSP_PCR64_4_LD 0x00000040UL 568 #define TSP_DNG_DATA_PORT_MASK 0x00FF0000UL 569 #define TSP_DNG_DATA_PORT_SHIFT 16UL 570 571 REG_Stc Pcr; // 0xbf802ac0 0x30 & 0x32 572 573 REG32 Pkt_Info; // 0xbf802ad0 0x34 574 #define TSP_APID_L_MASK 0x000000FFUL 575 #define TSP_APID_L_SHIFT 0UL 576 #define TSP_APID_H_MASK 0x00001F00UL 577 #define TSP_APID_H_SHIFT 8UL 578 #define TSP_PKT_PID_8_12_CP_MASK 0x001F0000UL 579 #define TSP_PKT_PID_8_12_CP_SHIFT 16UL 580 #define TSP_PKT_PRI_MASK 0x00200000UL 581 #define TSP_PKT_PRI_SHIFT 21UL 582 #define TSP_PKT_PLST_MASK 0x00400000UL 583 #define TSP_PKT_PLST_SHIFT 22UL 584 #define TSP_PKT_ERR 0x00800000UL 585 #define TSP_PKT_ERR_SHIFT 23UL 586 #define TSP_DMAW_NO_HIT_INT 0x0F000000UL 587 #define TSP_DMAW_NO_HIT_INT_SHIFT 24UL 588 589 REG32 Pkt_Info2; // 0xbf802ad8 0x36 590 #define TSP_PKT_INFO_CC_MASK 0x0000000FUL 591 #define TSP_PKT_INFO_CC_SHFT 0UL 592 #define TSP_PKT_INFO_ADPCNTL_MASK 0x00000030UL 593 #define TSP_PKT_INFO_ADPCNTL_SHFT 4UL 594 #define TSP_PKT_INFO_SCMB 0x000000C0UL 595 #define TSP_PKT_INFO_SCMB_SHFT 6UL 596 #define TSP_PKT_PID_0_7_CP_MASK 0x0000FF00UL 597 #define TSP_PKT_PID_0_7_CP_SHIFT 8UL 598 #define TSP_VFIFO3D_STATUS 0x000F0000UL 599 #define TSP_VFIFO3D_STATUS_SHFT 16UL 600 #define TSP_VFIFO_STATUS 0x00F00000UL 601 #define TSP_VFIFO_STATUS_SHFT 20UL 602 #define TSP_AFIFO_STATUS 0x0F000000UL 603 #define TSP_AFIFO_STATUS_SHFT 24UL 604 #define TSP_AFIFOB_STATUS 0xF0000000UL 605 #define TSP_AFIFOB_STATUS_SHFT 28UL 606 607 REG32 SwInt_Stat; // 0xbf802ae0 0x38 608 #define TSP_SWINT_INFO_SEC_MASK 0x000000FFUL 609 #define TSP_SWINT_INFO_SEC_SHFT 0UL 610 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00UL 611 #define TSP_SWINT_INFO_ENG_SHFT 8UL 612 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000UL 613 #define TSP_SWINT_STATUS_CMD_SHFT 16UL 614 #define TSP_SWINT_STATUS_SEC_RDY 0x0001UL 615 #define TSP_SWINT_STATUS_REQ_RDY 0x0002UL 616 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006UL 617 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007UL 618 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008UL 619 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010UL 620 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020UL 621 #define TSP_SWINT_STATUS_DEBUG 0x0030UL 622 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100UL 623 #define TSP_SWINT_CMD_DMA_RESUME 0x0200UL 624 #define TSP_SWINT_STATUS_SEC_GROUP 0x000FUL 625 #define TSP_SWINT_STATUS_GROUP 0x00FFUL 626 #define TSP_SWINT_CMD_GROUP 0x7F00UL 627 #define TSP_SWINT_CMD_STC_UPD 0x0400UL 628 #define TSP_SWINT_CTRL_FIRE 0x80000000UL 629 630 REG32 TsDma_Addr; // 0xbf802ae8 0x3a 631 632 REG32 TsDma_Size; // 0xbf802af0 0x3c 633 634 REG32 TsDma_Ctrl_CmdQ; // 0xbf802af8 0x3e 635 636 #define TSP_TSDMA_CTRL_VPES0 0x00000004UL 637 #define TSP_TSDMA_CTRL_APES0 0x00000008UL 638 #define TSP_TSDMA_CTRL_A2PES0 0x00000010UL 639 #define TSP_TSDMA_CTRL_V3DPES0 0x00000020UL 640 #define TSP_TSDMA_CTRL_A3PES0 0x00000040UL 641 #define TSP_TSDMA_CTRL_A4PES0 0x00000080UL 642 643 #define TSP_TSDMA_CTRL_START 0x00000001UL 644 #define TSP_TSDMA_CTRL_DONE 0x00000002UL 645 #define TSP_TSDMA_STAT_ABORT 0x00000080UL 646 #define TSP_CMDQ_CNT_MASK 0x001F0000UL 647 #define TSP_CMDQ_CNT_SHFT 16UL 648 #define TSP_CMDQ_FULL 0x00400000UL 649 #define TSP_CMDQ_EMPTY 0x00800000UL 650 #define TSP_CMDQ_SIZE 16UL 651 #define TSP_CMDQ_WR_LEVEL_MASK 0x03000000UL 652 #define TSP_CMDQ_WR_LEVEL_SHFT 24UL 653 654 REG32 MCU_Cmd; // 0xbf802b00 0x40 655 #define TSP_MCU_CMD_MASK 0xFF000000UL 656 #define TSP_MCU_CMD_NULL 0x00000000UL 657 #define TSP_MCU_CMD_ALIVE 0x01000000UL 658 #define TSP_MCU_CMD_NMATCH 0x02000000UL 659 #define TSP_MCU_CMD_NMATCH_FLT_MASK 0x000000FFUL 660 #define TSP_MCU_CMD_NMATCH_FLT_SHFT 0x00000000UL 661 #define TSP_MCU_CMD_PCR_GET 0x03000000UL 662 #define TSP_MCU_CMD_VER_RESET 0x04000000UL 663 #define TSP_MCU_CMD_VER_RESET_FLT_MASK 0x000000FFUL 664 #define TSP_MCU_CMD_VER_RESET_FLT_SHFT 0x00000000UL 665 #define TSP_MCU_CMD_MEM_HIGH_ADDR 0x05000000UL 666 #define TSP_MCU_CMD_MEM_LOW_ADDR 0x06000000UL 667 #define TSP_MCU_CMD_MEM_ADDR_SHFT 0x00000000UL 668 #define TSP_MCU_CMD_MEM_ADDR_MASK 0x0000FFFFUL 669 #define TSP_MCU_CMD_VERSION_GET 0x07000000UL 670 #define TSP_MCU_CMD_DBG_MEM 0x08000000UL 671 #define TSP_MCU_CMD_DBG_WORD 0x09000000UL 672 #define TSP_MCU_CMD_HWPCR_REG_SET 0x0A000000UL 673 #define TSP_MCU_CMD_SCMSTS_GET 0x0B000000UL 674 #define TSP_MCU_CMD_CTRL_STC_UPDATE 0x0C000000UL 675 #define TSP_MCU_CMD_CTRL_STC1_UPDATE 0x0D000000UL 676 #define TSP_MCU_CMD_CTRL_STC_UPDATE_OPTION_MASK 0x00FF0000UL 677 #define TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE 0x00010000UL 678 #define TSP_MCU_CMD_TEI_COUNT_GET 0x0E000000UL 679 #define TSP_MCU_CMD_TEI_COUNT_SRC_MASK 0x0000FFFFUL 680 #define TSP_MCU_CMD_TEI_COUNT_SRC_LIVE 0x00000000UL 681 #define TSP_MCU_CMD_TEI_COUNT_SRC_FILE 0x00000001UL 682 #define TSP_MCU_CMD_TEI_COUNT_OPTION_MASK 0x00FF0000UL 683 #define TSP_MCU_CMD_TEI_COUNT_OPTION_RESET 0x00800000UL 684 #define TSP_MCU_CMD_DISCONT_COUNT_GET 0x0F000000UL 685 #define TSP_MCU_CMD_DISCONT_COUNT_FLT_MASK 0x0000FFFFUL 686 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_MASK 0x00FF0000UL 687 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET 0x00800000UL 688 #define TSP_MCU_CMD_SET_STC_OFFSET 0x10000000UL 689 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_MASK 0x00FF0000UL 690 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT 16UL 691 #define TSP_MCU_CMD_SEL_STC_ENG 0x20000000UL 692 #define TSP_MCU_SEL_STC_ENG_ID_MASK 0x000000FFUL 693 #define TSP_MCU_SEL_STC_ENG_ID_SHIFT 0UL 694 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_MASK 0x0000FF00UL 695 #define TSP_MCU_CMD_SEL_STC_ENG_FLTSRC_SHIFT 8UL 696 697 REG32 Hw_Config2; // 0xbf802b08 0x42 698 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x000000FFUL 699 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0UL 700 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0x0000FF00UL 701 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8UL 702 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF0000UL 703 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 16UL 704 #define TSP_HW_CFG2_TSIF1_SERL 0x00000000UL 705 #define TSP_HW_CFG2_TSIF1_PARL 0x01000000UL 706 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x02000000UL 707 #define TSP_HW_CFG2_PIDFLT1_SOURCE_TSIF_MMFI0 0x20000000UL // Switch source of PIDFLT1 to MMFI0 708 #define TSP_HW_CFG2_PIDFLT2_SOURCE_TSIF_MMFI1 0x40000000UL // Switch source of PIDFLT2 to MMFI1 709 710 REG32 Hw_Config4; // 0xbf802b10 0x44 711 #define TSP_HW_CFG4_PVR_ENABLE 0x00000002UL 712 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x00000004UL // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 713 #define TSP_HW_CFG4_TSIF1_ENABLE 0x00000008UL // 1: enable ts interface 1 and vice versa 714 #define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_miu_head 715 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x00000020UL // Byte order of 8-byte recoding buffer to MIU. 716 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL 717 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x00000080UL // 32-bit data byte order read from 8x64 FIFO when playing file. 718 #define TSP_HW_CFG4_TSIF0_ENABLE 0x00000100UL // 1: enable ts interface 0 and vice versa 719 #define TSP_VALID_FALLING_DETECT 0x00000200UL // Reset bit count when data valid signal of TS interface is low. 720 #define TSP_SYNC_RISING_DETECT 0x00000400UL // Reset bit count on the rising sync signal of TS interface. 721 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x00000800UL // Set 1 to swap the bit order of TS0 DATA bus 722 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x00001000UL // Set 1 to swap the bit order of TS1 DATA bus 723 #define TSP_HW_TSP2OUTAEON_INT_EN 0x00004000UL // Set 1 to force interrupt to outside AEON 724 #define TSP_HW_HK_INT_FORCE 0x00008000UL // Set 1 to force interrupt to HK_MCU 725 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000F0000UL // prevent from byte enable bug, bit1~3 must enable togather 726 #define TSP_HW_CFG4_ALT_TS_SIZE 0x00010000UL // enable TS packets in 204 mode 727 #define TSP_HW_DMA_MODE_MASK 0x00300000UL // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 728 #define TSP_HW_DMA_MODE_SHIFT 20UL 729 #define TSP_HW_CFG4_WSTAT_CH_EN 0x00400000UL 730 #define TSP_HW_CFG4_PS_VID_EN 0x00800000UL // program stream video enable 731 #define TSP_HW_CFG4_PS_AUD_EN 0x01000000UL // program stream audio enable 732 #define TSP_HW_CFG4_PS_AUD2_EN 0x02000000UL // program stream audioB enable 733 #define TSP_HW_CFG4_APES_ERR_RM_EN 0x04000000UL // Set 1 to enable removing APES error packet 734 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x08000000UL // Set 1 to enable removing VPES error packet 735 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x10000000UL // Set 1 to enable removing section error packet 736 #define TSP_HW_CFG4_VID_ERR 0x20000000UL // Set 1 to mask the error packet interrupt 737 #define TSP_HW_CFG4_AUD_ERR 0x40000000UL // Set 1 to mask the error packet interrupt 738 #define TSP_HW_CFG4_ISYNC_PATCH_EN 0x80000000UL // Set 1 to enable the patch of internal sync in "tsif" 739 740 REG32 NOEA_PC; // 0xbf802b18 0x46 741 742 REG32 Idr_Ctrl_Addr0; // 0xbf802b20 0x48 743 #define TSP_IDR_START 0x00000001UL 744 #define TSP_IDR_READ 0x00000000UL 745 #define TSP_IDR_WRITE 0x00000002UL 746 #define TSP_IDR_WR_ENDIAN_BIG 0x00000004UL 747 #define TSP_IDR_WR_ADDR_AUTO_INC 0x00000008UL // Set 1 to enable address auto-increment after finishing read/write 748 #define TSP_IDR_WDAT0_TRIG_EN 0x00000010UL // WDAT0_TRIG_EN 749 #define TSP_IDR_MCUWAIT 0x00000020UL 750 #define TSP_IDR_SOFT_RST 0x00000080UL // Set 1 to soft-reset the IND32 module 751 #define TSP_IDR_AUTO_INC_VAL_MASK 0x00000F00UL 752 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8UL 753 #define TSP_IDR_ADDR_MASK0 0xFFFF0000UL 754 #define TSP_IDR_ADDR_SHFT0 16UL 755 756 REG32 Idr_Addr1_Write0; // 0xbf802b28 0x4a 757 #define TSP_IDR_ADDR_MASK1 0x0000FFFFUL 758 #define TSP_IDR_ADDR_SHFT1 0UL 759 #define TSP_IDR_WRITE_MASK0 0xFFFF0000UL 760 #define TSP_IDR_WRITE_SHFT0 16UL 761 762 REG32 Idr_Write1_Read0; // 0xbf802b30 0x4c 763 #define TSP_IDR_WRITE_MASK1 0x0000FFFFUL 764 #define TSP_IDR_WRITE_SHFT1 0UL 765 #define TSP_IDR_READ_MASK0 0xFFFF0000UL 766 #define TSP_IDR_READ_SHFT0 16UL 767 768 REG32 Idr_Read1; // 0xbf802b38 0x4e 769 #define TSP_IDR_READ_MASK1 0x0000FFFFUL 770 #define TSP_IDR_READ_SHFT1 0UL 771 #define TSP_V3D_FIFO_DISCON 0x00100000UL 772 #define TSP_V3D_FIFO_OVERFLOW 0x00200000UL 773 #define TSP_VD_FIFO_DISCON 0x02000000UL 774 #define TSP_VD_FIFO_OVERFLOW 0x08000000UL 775 #define TSP_AUB_FIFO_OVERFLOW 0x10000000UL 776 #define TSP_AU_FIFO_OVERFLOW 0x20000000UL 777 #define TSP_AUD_FIFO_OVERFLOW 0x40000000UL 778 #define TSP_AUC_FIFO_OVERFLOW 0x80000000UL 779 780 REG32 TsRec_Head; // 0xbf802b40 0x50 781 REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid address & write point 782 REG32 TsRec_Tail; // 0xbf802b50 0x54 783 784 REG16 SW_Mail_Box1; // 0xbf802b58 0x56 785 REG16 SW_Mail_Box2; // 0xbf802b5C 0x57 786 REG32 _xbf802b60; // 0xbf802b60 ~ 0xbf802b64 0x58~0x59 787 788 REG32 reg15b4; // 0xbf802b68 0x5a 789 #define TSP_SEC_DMAW_PROTECT_EN 0x00000001UL 790 #define TSP_PVR1_DAMW_PROTECT_EN 0x00000002UL 791 #define TSP_PVR2_DAMW_PROTECT_EN 0x00000004UL 792 #define TSP_PVR_PID_BYPASS 0x00000008UL // Set 1 to bypass PID in record 793 #define TSP_PVR_PID_BYPASS2 0x00000010UL // Set 1 to bypass PID in record2 794 #define TSP_BD_AUD_EN 0x00000020UL // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) to Audio A/B 795 #define TSP_BD_AUD_EN2 0x00000040UL // Set 1 to enable the BD audio stream recognization ( core /extend audio stream) to Audio C/D 796 #define TSP_AVFIFO_RD_EN 0x00000080UL // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 797 #define TSP_AVFIFO_RD 0x00000100UL // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 798 #define TSP_AVFIFO_SEL_VIDEO 0x00000000UL 799 #define TSP_AVFIFO_SEL_AUDIO 0x00000200UL 800 #define TSP_AVFIFO_SEL_AUDIOB 0x00000400UL 801 #define TSP_AVFIFO_SEL_V3D 0x00000600UL 802 #define TSP_PVR_INVERT 0x00001000UL // Set 1 to enable data payload invert for PVR record 803 #define TSP_PLY_FILE_INV_EN 0x00002000UL // Set 1 to enable data payload invert in pidflt0 file path 804 #define TSP_PLY_TS_INV_EN 0x00004000UL // Set 1 to enable data payload invert in pidflt0 TS path 805 #define TSP_FILEIN_BYTETIMER_ENABLE 0x00008000UL // Set 1 to enable byte timer in ts_if0 TS path 806 #define TSP_PVR1_PINGPONG 0x00010000UL // Set 1 to enable MIU addresses with pinpon mode 807 #define TSP_TEI_SKIPE_PKT_PID0 0x00040000UL // Set 1 to skip error packets in pidflt0 TS path 808 #define TSP_TEI_SKIPE_PKT_FILE 0x00080000UL // Set 1 to skip error packets in pidflt0 file path 809 #define TSP_TEI_SKIPE_PKT_PID1 0x00100000UL // Set 1 to skip error packets in pidflt1 TS path 810 #define TSP_DUP_PKT_SKIP 0x00400000UL 811 #define TSP_64bit_PCR2_ld 0x00800000UL // Set 1 to load CNT_64B_2 (the second STC) 812 #define TSP_cnt_33b_ld 0x01000000UL // Set 1 to load cnt_33b 813 #define TSP_FORCE_SYNCBYTE 0x02000000UL // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 814 #define TSP_SERIAL_EXT_SYNC_LT 0x04000000UL // Set 1 to detect serial-in sync without 8-cycle mode 815 #define TSP_BURST_LEN_MASK 0x18000000UL // 00,01: burst length = 4; 10,11: burst length = 1 816 #define TSP_BURST_LEN_4 0x08000000UL 817 #define TSP_BURST_LEN_SHIFT 27UL 818 #define TSP_MATCH_PID_SRC_MASK 0x60000000UL // Select the source of pid filter number with hit pid and match pid number with scramble information, 00 : from pkt_demux0, 01 : from pkt_demux_file, 10 : from pkt_demux1, 11 : from pkt_demux2 819 #define TSP_MATCH_PID_SRC_SHIFT 29UL 820 #define TSP_MATCH_PID_SRC_PKTDMX0 0UL 821 #define TSP_MATCH_PID_SRC_PKTDMXFL 1UL 822 #define TSP_MATCH_PID_SRC_PKTDMX1 2UL 823 #define TSP_MATCH_PID_SRC_PKTDMX2 3UL 824 #define TSP_MATCH_PID_LD 0x80000000UL 825 826 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 827 828 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 829 830 REG32 Cpu_Base; // 0xbf802b80 0x60 831 #define TSP_CPU_BASE_ADDR_MASK 0x01FFFFFFUL 832 833 REG32 Qmem_Ibase; // 0xbf802b88 0x62 834 835 REG32 Qmem_Imask; // 0xbf802b90 0x64 836 837 REG32 Qmem_Dbase; // 0xbf802b98 0x66 838 839 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 840 841 REG32 TSP_Debug; // 0xbf802ba8 0x6a 842 #define TSP_DEBUG_MASK 0x00FFFFFFUL 843 844 REG32 _xbf802bb0; // 0xbf802bb0 0x6c 845 846 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 847 848 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 849 #define TSP_FILE_TIMER_MASK 0x00FFFFFFUL 850 REG32 TsFileIn_Head; // 0xbf802bc8 0x72 851 #define TSP_FILE_ADDR_MASK 0x07FFFFFFUL 852 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 853 854 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 855 856 REG32 Dnld_Ctrl; // 0xbf802be0 0x78 857 #define TSP_DNLD_ADDR_MASK 0x0000FFFFUL 858 #define TSP_DNLD_ADDR_SHFT 0UL 859 #define TSP_DNLD_ADDR_ALI_SHIFT 4UL // Bit [11:4] of DMA_RADDR[19:0] 860 #define TSP_DNLD_NUM_MASK 0xFFFF0000UL 861 #define TSP_DNLD_NUM_SHFT 16UL 862 863 REG32 TSP_Ctrl; // 0xbf802be8 0x7a 864 #define TSP_CTRL_CPU_EN 0x00000001UL 865 #define TSP_CTRL_SW_RST 0x00000002UL 866 #define TSP_CTRL_DNLD_START 0x00000004UL 867 #define TSP_CTRL_DNLD_DONE 0x00000008UL // See 0x78 for related information 868 #define TSP_CTRL_TSFILE_EN 0x00000010UL 869 #define TSP_CTRL_R_PRIO 0x00000020UL 870 #define TSP_CTRL_W_PRIO 0x00000040UL 871 #define TSP_CTRL_ICACHE_EN 0x00000100UL 872 #define TSP_CTRL_CPU2MI_R_PRIO 0x00000400UL 873 #define TSP_CTRL_CPU2MI_W_PRIO 0x00000800UL 874 #define TSP_CTRL_I_EL 0x00000000UL 875 #define TSP_CTRL_I_BL 0x00001000UL 876 #define TSP_CTRL_D_EL 0x00000000UL 877 #define TSP_CTRL_D_BL 0x00002000UL 878 #define TSP_CTRL_NOEA_QMEM_ACK_DIS 0x00004000UL 879 #define TSP_CTRL_MEM_TS_WORDER 0x00008000UL 880 #define TSP_SYNC_BYTE_MASK 0x00FF0000UL 881 #define TSP_SYNC_BYTE_SHIFT 16UL 882 883 REG32 PKT_CNT; // 0xbf802bf0 0x7c 884 #define TSP_PKT_CNT_MASK 0x000000FFUL 885 #define TSP_DBG_SEL_MASK 0xFFFF0000UL 886 #define TSP_DBG_SEL_SHIFT 16UL 887 888 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 889 #define TSP_HWINT_STATUS_MASK 0xFF00UL // Tsp2hk_int enable bits. 890 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100UL 891 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200UL 892 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400UL 893 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800UL 894 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000UL 895 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000UL 896 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000UL 897 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000UL 898 899 #define TSP_HWINT_HW_PVR1_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS | TSP_HWINT_TSP_PVR_MID0_STATUS) 900 #define TSP_HWINT_ALL (TSP_HWINT_HW_PVR1_MASK | TSP_HWINT_TSP_SW_INT_STATUS) 901 902 // 0x7f: TSP_CTRL1: hidden in HwInt_Stat 903 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 904 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001UL 905 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002UL //Set 1 to enable TSP file data read without timer check 906 #define TSP_CTRL1_FILEIN_PAUSE 0x0004UL 907 #define TSP_CTRL1_STANDBY 0x0080UL 908 #define TSP_CTRL1_INT2NOEA 0x0100UL 909 #define TSP_CTRL1_INT2NOEA_FORCE 0x0200UL 910 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400UL 911 #define TSP_CTRL1_CMDQ_RESET 0x0800UL 912 #define TSP_CTRL1_DLEND_EN 0x1000UL // Set 1 to enable little-endian mode in TSP CPU 913 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000UL 914 #define TSP_CTRL1_DMA_RST 0x8000UL 915 916 //---------------------------------------------- 917 // 0xBF802C00 MIPS direct access 918 //---------------------------------------------- 919 REG32 MCU_Data0; // 0xbf802c00 0x00 920 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 921 922 REG32 PVR1_LPcr1; // 0xbf802c08 0x02 923 924 REG32 LPcr2; // 0xbf802c10 0x04 925 926 REG32 reg160C; // 0xbf802c18 0x06 927 #define TSP_PVR1_LPCR1_WLD 0x00000001UL // Set 1 to load LPCR1 value 928 #define TSP_PVR1_LPCR1_RLD 0x00000002UL // Set 1 to read LPCR1 value (Default: 1) 929 #define TSP_LPCR2_WLD 0x00000004UL // Set 1 to load LPCR2 value 930 #define TSP_LPCR2_RLD 0x00000008UL // Set 1 to read LPCR2 value (Default: 1) 931 #define TSP_RECORD192_EN 0x00000010UL // 160C bit(5)enable TS packets with 192 bytes on record mode 932 #define TSP_FILEIN192_EN 0x00000020UL // 160C bit(5)enable TS packets with 192 bytes on file-in mode 933 #define TSP_RVU_TIMESTAMP_EN 0x00000040UL 934 #define TSP_ORZ_DMAW_PROT_EN 0x00000080UL // 160C bit(7) open RISC DMA write protection 935 #define TSP_CLR_PIDFLT_BYTE_CNT 0x00000100UL // Clear pidflt0_file byte counter 936 #define TSP_DOUBLE_BUF_DESC 0x00004000UL // 160d bit(6) remove buffer limitation, Force pinpong buffer to flush 937 #define TSP_TIMESTAMP_RESET 0x00008000UL // 160d bit(7) reset timestamp, reset all file in path 938 #define TSP_VQTX0_BLOCK_DIS 0x00010000UL 939 #define TSP_VQTX1_BLOCK_DIS 0x00020000UL 940 #define TSP_VQTX2_BLOCK_DIS 0x00040000UL 941 #define TSP_VQTX3_BLOCK_DIS 0x00080000UL 942 #define TSP_DIS_MIU_RQ 0x00100000UL // Disable miu R/W request for reset TSP usage 943 #define TSP_RM_DMA_GLITCH 0x00800000UL // Fix sec_dma overflow glitch 944 #define TSP_RESET_VFIFO 0x01000000UL // Reset VFIFO -- ECO Done 945 #define TSP_RESET_AFIFO 0x02000000UL // Reset AFIFO -- ECO Done 946 #define TSP_RESET_GDMA 0x04000000UL // Set 1 to reset GDMA bridge 947 #define TSP_CLR_ALL_FLT_MATCH 0x08000000UL // Set 1 to clean all flt_match in a packet 948 #define TSP_RESET_AFIFO2 0x10000000UL 949 #define TSP_RESET_VFIFO3D 0x20000000UL 950 #define TSP_PVR_WPRI_HIGH 0x20000000UL 951 #define TSP_OPT_ORACESS_TIMING 0x80000000UL 952 953 REG32 PktChkSizeFilein; // 0xbf802c20 0x08 954 #define TSP_PKT_SIZE_MASK 0x000000ffUL 955 #define TSP_PKT192_BLK_DIS_FIN 0x00000100UL // Set 1 to disable file-in timestamp block scheme 956 #define TSP_AV_CLR 0x00000200UL // Clear AV FIFO overflow flag and in/out counter 957 #define TSP_HW_STANDBY_MODE 0x00000400UL // Set 1 to disable all SRAM in TSP for low power mode automatically 958 #define TSP_CNT_34B_DEFF_EN 0x00020000UL // Switch STC DIFF Mode (Output STC+DIFF to MVD and MAD) 959 #define TSP_SYSTIME_MODE_STC64 0x00080000UL // Switch normal STC or STC diff 960 #define TSP_SEC_DMA_BURST_EN 0x00800000UL // ECO bit for section DMA burst mode 961 #define TSP_REMOVE_DUP_VIDEO_PKT 0x02000000UL // Set 1 to remove duplicate video packet 962 #define TSP_REMOVE_DUP_VIDEO3D_PKT 0x04000000UL // Set 1 to remove duplicate video 3D packet 963 #define TSP_REMOVE_DUP_AUDIO_PKT 0x08000000UL // Set 1 to remove duplicate audio packet 964 #define TSP_REMOVE_DUP_AUDIOB_PKT 0x10000000UL // Set 1 to remove duplicate audio description packet 965 #define TSP_REMOVE_DUP_AUDIOC_PKT 0x20000000UL // Set 1 to remove duplicate third audio fifo packet 966 #define TSP_REMOVE_DUP_AUDIOD_PKT 0x40000000UL // Set 1 to remove duplicate fourth audio fifo packet 967 968 #define TSP_REMOVE_DUP_AV_PKT (TSP_REMOVE_DUP_VIDEO_PKT | \ 969 TSP_REMOVE_DUP_VIDEO3D_PKT | \ 970 TSP_REMOVE_DUP_AUDIO_PKT | \ 971 TSP_REMOVE_DUP_AUDIOB_PKT ) 972 973 REG32 Dnld_Ctrl2; // 0xbf802c28 0x0a 974 #define TSP_DMA_RADDR_MSB_MASK 0x000000FFUL 975 #define TSP_DMA_RADDR_MSB_SHIFT 0UL 976 //#define TSP_CMQ_WORD_EN 0x00400000UL // Set 1 to access CMDQ related registers in word. 977 //#define TSP_RESET_PVR_MOBF 0x04000000UL 978 //#define TSP_RESET_FILEIN_MOBF 0x08000000UL 979 #define TSP_TSIF0_VPID_3D_BYPASS 0x08000000UL // bypass TS for matched video 3D pid 980 #define TSP_VPID_3D_ERR_RM_EN 0x10000000UL // enable removing v3d err pkt 981 #define TSP_PS_VID3D_EN 0x40000000UL 982 983 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 984 985 REG32 _xbf802c38; // 0xbf802c38 0x0e 986 987 REG32 PCR64_2_L; // 0xbf802c40 0x10 988 989 REG32 PCR64_2_H; // 0xbf802c48 0x12 990 991 #define TSP_DMAW_BND_MASK 0xFFFFFFFFFUL 992 REG32 DMAW_LBND0; // 0xbf802c50 0x14 993 994 REG32 DMAW_UBND0; // 0xbf802c58 0x16 995 996 REG32 DMAW_LBND1; // 0xbf802c60 0x18 997 998 REG32 DMAW_UBND1; // 0xbf802c68 0x1A 999 1000 REG32 DMAW_ERR_WADDR_SRC_SEL; // 0xbf802c70 0x1C 1001 #define TSP_CLR_NO_HIT_INT 0x00000001UL // set 1 clear all dma write function not hit interrupt 1002 #define DMAW_ERR_WADDR_SRC_SEL_MASK 0x0000001EUL 1003 #define DMAW_ERR_WADDR_SRC_SEL_SHIFT 1UL 1004 #define TSP_PVR1_DWMA_WADDR_ERR 0x0UL 1005 #define TSP_SEC_DWMA_WADDR_ERR 0x1UL 1006 #define TSP_PVR_CB_DWMA_WADDR_ERR 0x2UL 1007 #define TSP_VQTX0_DWMA_WADDR_ERR 0x3UL 1008 #define TSP_VQTX1_DWMA_WADDR_ERR 0x4UL 1009 #define TSP_ORZ_DWMA_WADDR_ERR 0x5UL 1010 #define TSP_VQTX2_DWMA_WADDR_ERR 0x6UL 1011 #define TSP_VQTX3_DWMA_WADDR_ERR 0x7UL 1012 #define TSP_PVR2_DWMA_WADDR_ERR 0x8UL 1013 #define TSP_CLR_SEC_DMAW_OVERFLOW 0x00000040UL 1014 #define TSP_APES_B_ERR_RM_EN 0x00000080UL 1015 #define TSP_BLK_AF_SCRMB_BIT 0x00000400UL 1016 1017 REG32 reg163C; // 0xbf802c78 0x1e 1018 #define TSP_AUDC_SRC_MASK 0x00000007UL 1019 #define TSP_AUDC_SRC_SHIFT 0UL 1020 #define TSP_AUDD_SRC_MASK 0x00000038UL 1021 #define TSP_AUDD_SRC_SHIFT 3UL 1022 #define TSP_CLR_SRC_MASK 0x00070000UL 1023 #define TSP_CLR_SRC_SHIFT 16UL 1024 #define TSP_DISCONTI_VD_CLR 0x00080000UL //Set 1 to clear video discontinuity count 1025 #define TSP_DISCONTI_V3D_CLR 0x00100000UL //Set 1 to clear v3D discontinuity count 1026 #define TSP_DISCONTI_AUD_CLR 0x00200000UL //Set 1 to clear audio discontinuity count 1027 #define TSP_DISCONTI_AUDB_CLR 0x00400000UL //Set 1 to clear videoB discontinuity count 1028 #define TSL_CLR_SRAM_COLLISION 0x02000000UL 1029 #define TSP_TS_OUT_EN 0x04000000UL //set 1 to enable ts_out 1030 1031 #define TSP_ALL_VALID_EN 0x08000000UL 1032 #define TSP_PKT130_PUSI_EN 0x10000000UL 1033 #define TSP_PKT130_TEI_EN 0x20000000UL 1034 #define TSP_PKT130_ERR_CLR 0x40000000UL 1035 #define TSP_PKT130_EN 0x80000000UL // file in only 1036 1037 REG32 VQ0_BASE; // 0xbf802c80 0x20 1038 REG32 VQ0_CTRL; // 0xbf802c88 0x22 1039 #define TSP_VQ0_SIZE_208PK_MASK 0x0000FFFFUL 1040 #define TSP_VQ0_SIZE_208PK_SHIFT 0UL 1041 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F0000UL 1042 #define TSP_VQ0_WR_THRESHOLD_SHIFT 16UL 1043 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F00000UL 1044 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 20UL 1045 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F000000UL 1046 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 24UL 1047 #define TSP_VQ0_RESET 0x10000000UL 1048 #define TSP_VQ0_OVERFLOW_INT_EN 0x40000000UL // Enable the interrupt for overflow happened on Virtual Queue path 1049 #define TSP_VQ0_CLR_OVERFLOW_INT 0x80000000UL // Clear the interrupt and the overflow flag 1050 1051 REG32 VQ_PIDFLT_CTRL; // 0xbf802c90 0x24 1052 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x000E0000UL 1053 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 17UL 1054 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x00000000UL 1055 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x00020000UL 1056 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x00040000UL 1057 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x00060000UL 1058 #define TSP_PIDFLT0_OVF_INT_EN 0x00400000UL 1059 #define TSP_PIDFLT0_CLR_OVF_INT 0x00800000UL 1060 #define TSP_PIDFLT0_FILE_OVF_INT_EN 0x01000000UL 1061 #define TSP_PIDFLT0_FILE_CLR_OVF_INT 0x02000000UL 1062 #define TSP_PIDFLT1_OVF_INT_EN 0x04000000UL 1063 #define TSP_PIDFLT1_CLR_OVF_INT 0x08000000UL 1064 #define TSP_PIDFLT2_OVF_INT_EN 0x10000000UL 1065 #define TSP_PIDFLT2_CLR_OVF_INT 0x20000000UL 1066 1067 REG32 MOBF_PVR1_Index; // 0xbf3a2c98 0x26 1068 #define TSP_MOBF_PVR1_INDEX0_MASK 0x0000000FUL 1069 #define TSP_MOBF_PVR1_INDEX0_SHIFT 0UL 1070 #define TSP_MOBF_PVR1_INDEX1_MASK 0x000F0000UL 1071 #define TSP_MOBF_PVR1_INDEX1_SHIFT 16UL 1072 1073 REG32 MOBF_PVR2_Index; // 0xbf3a2cA0 0x28 1074 #define TSP_MOBF_PVR2_INDEX0_MASK 0x0000000FUL 1075 #define TSP_MOBF_PVR2_INDEX0_SHIFT 0UL 1076 #define TSP_MOBF_PVR2_INDEX1_MASK 0x000F0000UL 1077 #define TSP_MOBF_PVR2_INDEX1_SHIFT 16UL 1078 1079 REG32 DMAW_LBND2; // 0xbf802ca8 0x2a 1080 1081 REG32 DMAW_UBND2; // 0xbf802cb0 0x2c 1082 1083 REG32 DMAW_LBND3; // 0xbf802cb8 0x2e //reserved 1084 1085 REG32 DMAW_UBND3; // 0xbf802cc0 0x30 //reserved 1086 1087 REG32 DMAW_LBND4; // 0xbf802cc8 0x32 1088 1089 REG32 DMAW_UBND4; // 0xbf802cd0 0x34 1090 1091 REG32 ORZ_DMAW_LBND; // 0xbf802cd8 0x36 1092 #define TSP_ORZ_DMAW_LBND_MASK 0xffffffffUL 1093 REG32 ORZ_DMAW_UBND; // 0xbf802ce0 0x38 1094 #define TSP_ORZ_DMAW_UBND_MASK 0xffffffffUL 1095 REG32 _xbf802ce8_xbf802cec; // 0xbf802ce8_0xbf802cec 0x3a~0x3b 1096 1097 REG32 HWPCR0_L; // 0xbf802cf0 0x3c 1098 REG32 HWPCR0_H; // 0xbf802cf8 0x3e 1099 1100 REG32 CA_CTRL; // 0xbf802d00 0x40 1101 #define TSP_CA_CTRL_MASK 0xffffffffUL 1102 #define TSP_CA0_CTRL_MASK 0x00007077UL 1103 #define TSP_CA0_INPUT_TSIF0_LIVEIN 0x00000001UL 1104 #define TSP_CA0_INPUT_TSIF0_FILEIN 0x00000002UL 1105 #define TSP_CA0_INPUT_TSIF1 0x00000004UL 1106 #define TSP_CA0_OUTPUT_PKTDMX0_LIVE 0x00000010UL 1107 #define TSP_CA0_OUTPUT_PKTDMX0_FILE 0x00000020UL 1108 #define TSP_CA0_OUTPUT_PKTDMX1 0x00000040UL 1109 #define TSP_CA0_INPUT_TSIF2 0x00001000UL 1110 #define TSP_CA0_OUTPUT_PKTDMX2 0x00002000UL 1111 1112 #define TSP_CA1_CTRL_MASK 0x77300000UL 1113 #define TSP_CA1_INPUT_TSIF2 0x00100000UL 1114 #define TSP_CA1_OUTPUT_PKTDMX2 0x00200000UL 1115 1116 #define TSP_CA2_CTRL_MASK_L 0x00C00000UL 1117 #define TSP_CA2_INPUT_TSIF2 0x00400000UL 1118 #define TSP_CA2_OUTPUT_PKTDMX2 0x00800000UL 1119 1120 #define TSP_CA1_INPUT_TSIF0_LIVEIN 0x01000000UL 1121 #define TSP_CA1_INPUT_TSIF0_FILEIN 0x02000000UL 1122 #define TSP_CA1_INPUT_TSIF1 0x04000000UL 1123 #define TSP_CA1_OUTPUT_PKTDMX0_LIVE 0x10000000UL 1124 #define TSP_CA1_OUTPUT_PKTDMX0_FILE 0x20000000UL 1125 #define TSP_CA1_OUTPUT_PKTDMX1 0x40000000UL 1126 1127 REG32 REG_ONEWAY; // 0xbf802d08 0x42 1128 #define TSP_ONEWAY_PVR1_PORT 0x00000002UL // Oneway for PVR1 buffer 1129 #define TSP_ONEWAY_PVR2_PORT 0x00000004UL // Oneway for PVR2 buffer 1130 #define TSP_ONEWAY_LOAD_FW_PORT 0x00000008UL // Oneway for f/w load address 1131 #define TSP_ONEWAY_QMEM 0x00000010UL 1132 #define TSP_ONEWAY_AV_NOT_TO_SEC 0x00000020UL // Oneway for block av packet to section 1133 1134 #define TSP_CA2_CTRL_MASK_H 0x00770000UL 1135 #define TSP_CA2_CTRL_SHIFT_H 16UL 1136 #define TSP_CA2_INPUT_TSIF0_LIVEIN 0x00000001UL 1137 #define TSP_CA2_INPUT_TSIF0_FILEIN 0x00000002UL 1138 #define TSP_CA2_INPUT_TSIF1 0x00000004UL 1139 #define TSP_CA2_OUTPUT_PKTDMX0_LIVE 0x00000010UL 1140 #define TSP_CA2_OUTPUT_PKTDMX0_FILE 0x00000020UL 1141 #define TSP_CA2_OUTPUT_PKTDMX1 0x00000040UL 1142 1143 #define TSP_CA3_CTRL_MASK 0x7F800000UL 1144 #define TSP_CA3_INPUT_TSIF0_LIVEIN 0x00800000UL 1145 #define TSP_CA3_INPUT_TSIF0_FILEIN 0x01000000UL 1146 #define TSP_CA3_INPUT_TSIF1 0x02000000UL 1147 #define TSP_CA3_INPUT_TSIF2 0x04000000UL 1148 #define TSP_CA3_OUTPUT_PKTDMX0_LIVE 0x08000000UL 1149 #define TSP_CA3_OUTPUT_PKTDMX0_FILE 0x10000000UL 1150 #define TSP_CA3_OUTPUT_PKTDMX1 0x20000000UL 1151 #define TSP_CA3_OUTPUT_PKTDMX2 0x40000000UL 1152 1153 1154 REG32 HWPCR1_L; // 0xbf802d10 0x44 1155 REG32 HWPCR1_H; // 0xbf802d18 0x46 1156 1157 REG32 _xbf802d20[4]; // 0xbf802d20~0xbf802d3c 0x48~0x4f //LPCR_CB 1158 1159 REG32 FIFO_Src; // 0xbf802d40 0x50 1160 #define TSP_AUD_SRC_MASK 0x00000007UL 1161 #define TSP_AUD_SRC_SHIFT 0UL 1162 #define TSP_SRC_FROM_PKTDMX0 0x00000001UL 1163 #define TSP_SRC_FROM_PKTDMXFL 0x00000002UL 1164 #define TSP_SRC_FROM_PKTDMX1 0x00000003UL 1165 #define TSP_SRC_FROM_PKTDMX2 0x00000004UL 1166 #define TSP_SRC_FROM_MMFI0 0x00000006UL 1167 #define TSP_SRC_FROM_MMFI1 0x00000007UL 1168 #define TSP_AUDB_SRC_MASK 0x00000038UL 1169 #define TSP_AUDB_SRC_SHIFT 3UL 1170 #define TSP_VID_SRC_MASK 0x000001C0UL 1171 #define TSP_VID_SRC_SHIFT 6UL 1172 #define TSP_VID3D_SRC_MASK 0x00000E00UL 1173 #define TSP_VID3D_SRC_SHIFT 9UL 1174 #define TSP_PVR1_SRC_MASK 0x00007000UL 1175 #define TSP_PVR1_SRC_SHIFT 12UL 1176 #define TSP_PCR0_SRC_MASK 0x001C0000UL 1177 #define TSP_PCR0_SRC_SHIFT 18UL 1178 #define TSP_PCR1_SRC_MASK 0x00E00000UL 1179 #define TSP_PCR1_SRC_SHIFT 21UL 1180 #define TSP_TEI_SKIP_PKT_PCR0 0x01000000UL 1181 #define TSP_PCR0_RESET 0x02000000UL 1182 #define TSP_PCR0_READ 0x08000000UL 1183 #define TSP_TEI_SKIP_PKT_PCR1 0x10000000UL 1184 #define TSP_PCR1_RESET 0x20000000UL 1185 #define TSP_PCR1_READ 0x80000000UL 1186 1187 REG32 STC_DIFF_BUF; // 0xbf802d48 0x52 1188 1189 REG32 STC_DIFF_BUF_H; // 0xbf802d50 0x54 1190 #define TSP_STC_DIFF_BUF_H_MASK 0x0000007FUL 1191 #define TSP_STC_DIFF_BUF_H_AHIFT 0UL 1192 #define TSP_PVR2_SRC_MASK 0x00070000UL 1193 #define TSP_PVR2_SRC_SHIFT 16UL 1194 1195 1196 REG32 VQ1_Base; // 0xbf802d58 0x56 1197 1198 REG32 _rbf802d60; // 0xbf802d60 0x58 1199 1200 REG32 CH_BW_CTRL; // 0xbf802d68 0x5a 1201 #define TSP_CH_BW_WP_LD 0x00000100UL 1202 1203 REG32 VQ1_Config; // 0xbf802d70 0x5C 1204 #define TSP_VQ1_SIZE_208BYTE_MASK 0x0000ffffUL 1205 #define TSP_VQ1_SIZE_208BYTE_SHIFT 0UL 1206 #define TSP_VQ1_WR_THRESHOLD_MASK 0x000F0000UL 1207 #define TSP_VQ1_WR_THRESHOLD_SHIFT 16UL 1208 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x00F00000UL 1209 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 20UL 1210 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1211 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 24UL 1212 #define TSP_VQ1_RESET 0x10000000UL 1213 #define TSP_VQ1_OVF_INT_EN 0x40000000UL 1214 #define TSP_VQ1_CLR_OVF_INT 0x80000000UL 1215 1216 REG32 VQ2_Base; // 0xbf802d78 0x5E 1217 1218 REG32 Pkt_Info3; // 0xbf802d80 0x60 1219 #define TSP_AFIFOC_STATUS 0x0000000FUL 1220 #define TSP_AFIFOC_STATUS_SHFT 0UL 1221 #define TSP_AFIFOD_STATUS 0x000000F0UL 1222 #define TSP_AFIFOD_STATUS_SHFT 4UL 1223 1224 REG32 Bist_Fail; // 0xbf802d88 0x62 1225 #define TSP_BIST_FAIL_STATUS_MASK 0x00FF0000UL 1226 #define TSP_BIST_FAIL_STATUS_SRAM1P192x8_MASK 0x00070000UL 1227 #define TSP_BIST_FAIL_STATUS_SRAM2P512x32w8 0x00080000UL 1228 #define TSP_BIST_FAIL_STATUS_SRAM2P16x128_MASK 0x00600000UL 1229 #define TSP_BIST_FAIL_STATUS_SRAM1P2048x32w8 0x00800000UL 1230 #define TSP_BIST_FAIL_STATUS_SRAM1P1024x32w8 0x01000000UL 1231 #define TSP_BIST_FAIL_STATUS_SRAM1P512x20 0x00200000UL 1232 1233 REG32 VQ2_Config; // 0xbf802d90 0x64 1234 #define TSP_VQ2_SIZE_208BYTE_MASK 0x0000ffffUL 1235 #define TSP_VQ2_SIZE_208BYTE_SHIFT 0UL 1236 #define TSP_VQ2_WR_THRESHOLD_MASK 0x000F0000UL 1237 #define TSP_VQ2_WR_THRESHOLD_SHIFT 16UL 1238 #define TSP_VQ2_PRI_THRESHOLD_MASK 0x00F00000UL 1239 #define TSP_VQ2_PRI_THRESHOLD_SHIFT 20UL 1240 #define TSP_VQ2_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1241 #define TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT 24UL 1242 #define TSP_VQ2_RESET 0x10000000UL 1243 #define TSP_VQ2_OVF_INT_EN 0x40000000UL 1244 #define TSP_VQ2_CLR_OVF_INT 0x80000000UL 1245 1246 REG32 VQ_STATUS; // 0xbf802d98 0x66 1247 #define TSP_VQ_STATUS_MASK 0xFFFFFFFFUL 1248 #define TSP_VQ_STATUS_SHIFT 0UL 1249 #define TSP_VQ0_STATUS_READ_EVER_FULL 0x00001000UL 1250 #define TSP_VQ0_STATUS_READ_EVER_OVERFLOW 0x00002000UL 1251 #define TSP_VQ0_STATUS_EMPTY 0x00004000UL 1252 #define TSP_VQ0_STATUS_READ_BUSY 0x00008000UL 1253 #define TSP_VQ1_STATUS_READ_EVER_FULL 0x00010000UL 1254 #define TSP_VQ1_STATUS_READ_EVER_OVERFLOW 0x00020000UL 1255 #define TSP_VQ1_STATUS_EMPTY 0x00040000UL 1256 #define TSP_VQ1_STATUS_READ_BUSY 0x00080000UL 1257 #define TSP_VQ2_STATUS_READ_EVER_FULL 0x00100000UL 1258 #define TSP_VQ2_STATUS_READ_EVER_OVERFLOW 0x00200000UL 1259 #define TSP_VQ2_STATUS_EMPTY 0x00400000UL 1260 #define TSP_VQ2_STATUS_READ_BUSY 0x00800000UL 1261 #define TSP_VQ3_STATUS_READ_EVER_FULL 0x01000000UL 1262 #define TSP_VQ3_STATUS_READ_EVER_OVERFLOW 0x02000000UL 1263 #define TSP_VQ3_STATUS_EMPTY 0x04000000UL 1264 #define TSP_VQ3_STATUS_READ_BUSY 0x08000000UL 1265 #define TSP_VQ0_STATUS_TX_OVERFLOW 0x10000000UL 1266 #define TSP_VQ1_STATUS_TX_OVERFLOW 0x20000000UL 1267 #define TSP_VQ2_STATUS_TX_OVERFLOW 0x40000000UL 1268 #define TSP_VQ3_STATUS_TX_OVERFLOW 0x80000000UL 1269 1270 REG32 DM2MI_WAddr_Err; // 0xbf802da0 0x68 , DM2MI_WADDR_ERR0 1271 1272 REG32 ORZ_DMAW_WAddr_Err; // 0xbf802da8 0x6a , ORZ_WADDR_ERR0 1273 1274 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 1275 #define TSP_HWINT2_EN_MASK 0x00FFUL 1276 #define TSP_HWINT2_EN_SHIFT 0UL 1277 #define TSP_HWINT2_STATUS_MASK 0xFF00UL 1278 #define TSP_HWINT2_STATUS_SHIFT 8UL 1279 #define TSP_HWINT2_PCR1_UPDATE_END 0x0400UL 1280 #define TSP_HWINT2_PCR0_UPDATE_END 0x0800UL 1281 #define TSP_HWINT2_PVRCB_MEET_MID_TAIL 0x1000UL 1282 #define TSP_HWINT2_ALL_DMA_WADDR_NOT_IN_PROCT_Z 0x2000UL 1283 #define TSP_HWINT2_VQ0_VQ1_VQ2_VQ3_OVERFLOW 0x4000UL 1284 #define TSP_HWINT2_PVR2_MID_TAIL_STATUS 0x8000UL 1285 1286 #define TSP_HWINT_HW_PVRCB_MASK TSP_HWINT2_PVRCB_MEET_MID_TAIL 1287 #define TSP_HWINT_HW_PVR2_MASK TSP_HWINT2_PVR2_MID_TAIL_STATUS 1288 #define TSP_HWINT2_ALL (TSP_HWINT_HW_PVRCB_MASK|TSP_HWINT_HW_PVR2_MASK|TSP_HWINT2_PCR0_UPDATE_END|TSP_HWINT2_PCR1_UPDATE_END) 1289 1290 #define TSP_SWINT1_L_SHFT 16UL 1291 #define TSP_SWINT1_L_MASK 0xFFFF0000UL 1292 1293 REG16 SwInt_Stat1_M; 1294 REG32 SwInt_Stat1_H; // 0xbf802dB8 0x6e 1295 #define TSP_SWINT1_H_SHFT 0UL 1296 #define TSP_SWINT1_H_MASK 0x0000FFFFUL 1297 1298 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 1299 1300 REG32 HW2_Config3; // 0xbf802dC0 0x72 1301 #define TSP_RM_OVF_GLITCH 0x00000008UL 1302 #define TSP_FILEIN_RADDR_READ 0x00000010UL 1303 #define TSP_DUP_PKT_CNT_CLR 0x00000040UL 1304 #define TSP_REC_AT_SYNC_DIS 0x00000100UL 1305 #define TSP_PVR1_ALIGN_EN 0x00000200UL 1306 #define TSP_REC_FORCE_SYNC_EN 0x00000400UL 1307 #define TSP_RM_PKT_DEMUX_PIPE 0x00000800UL 1308 #define TSP_VQ_EN 0x00004000UL 1309 #define TSP_VQ2PINGPONG_EN 0x00008000UL 1310 #define TSP_PVR1_REC_ALL_EN 0x00010000UL 1311 #define TSP_PVR2_REC_ALL_EN 0x00020000UL 1312 #define TSP_DMA_FLUSH_EN 0x00040000UL //PVR1, PVR2 dma flush 1313 #define TSP_REC_ALL_OLD 0x00080000UL 1314 #define TSP_RESET_AFIFO3 0x00400000UL 1315 #define TSP_RESET_AFIFO4 0x00800000UL 1316 #define TSP_TSIF0_CLK_STAMP_27_EN 0x01000000UL 1317 #define TSP_PVR1_CLK_STAMP_27_EN 0x02000000UL 1318 #define TSP_PVR2_CLK_STAMP_27_EN 0x04000000UL 1319 #define TSP_HW_CFG3_PS_AUDC_EN 0x10000000UL 1320 #define TSP_HW_CFG3_PS_AUDD_EN 0x20000000UL 1321 #define TSP_REC_NULL 0x40000000UL // No used 1322 1323 1324 REG32 VQ3_BASE; // 0xbf802dC0 0x74 1325 1326 REG32 VQ3_Config; // 0xbf802dC0 0x76 1327 #define TSP_VQ3_SIZE_208BYTE_MASK 0x0000ffffUL 1328 #define TSP_VQ3_SIZE_208BYTE_SHIFT 0UL 1329 #define TSP_VQ3_WR_THRESHOLD_MASK 0x000F0000UL 1330 #define TSP_VQ3_WR_THRESHOLD_SHIFT 16UL 1331 #define TSP_VQ3_PRI_THRESHOLD_MASK 0x00F00000UL 1332 #define TSP_VQ3_PRI_THRESHOLD_SHIFT 20UL 1333 #define TSP_VQ3_FORCEFIRE_CNT_1K_MASK 0x0F000000UL 1334 #define TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT 24UL 1335 #define TSP_VQ3_RESET 0x10000000UL 1336 #define TSP_VQ3_OVF_INT_EN 0x40000000UL 1337 #define TSP_VQ3_CLR_OVF_INT 0x80000000UL 1338 1339 REG32 VQ_RX_Status; // 0xbf802dC0 0x78 1340 #define VQ_RX_ARBITER_MODE_MASK 0x0000000FUL 1341 #define VQ_RX_ARBITER_MODE_SHIFT 0UL 1342 #define VQ_RX0_PRI_MASK 0x000000F0UL 1343 #define VQ_RX0_PRI_SHIFT 4UL 1344 #define VQ_RX1_PRI_MASK 0x00000F00UL 1345 #define VQ_RX1_PRI_SHIFT 8UL 1346 #define VQ_RX2_PRI_MASK 0x0000F000UL 1347 #define VQ_RX2_PRI_SHIFT 12UL 1348 #define VQ_RX3_PRI_MASK 0x000F0000UL 1349 #define VQ_RX3_PRI_SHIFT 16UL 1350 1351 REG32 _xbf802dC0; // 0xbf802dC0 0x7a 1352 1353 REG32 MCU_Data1; // 0xbf802dC0 0x7c 1354 } REG_Ctrl; 1355 1356 // TSP part 2 1357 typedef struct _REG_Ctrl2 1358 { 1359 REG16 Qmem_Dbg; // 0xbf803ac0 0x70 1360 #define QMEM_DBG_MODE 0x0001 1361 #define QMEM_DBG_TSP_SEL_SRAM 0x0002 1362 REG16 Qmem_Dbg_RAddr; // 0xbf803ac4 0x71 1363 #define QMEM_DBG_RADDR_MASK 0xFFFF 1364 REG32 Qmem_Dbg_RD ; // 0xbf803ac8~0xbf803acc 0x72~0x73 1365 1366 } REG_Ctrl2; 1367 1368 typedef struct _REG_Ctrl3 1369 { 1370 REG16 PktConverterCfg[4]; // 0x10~13 1371 #define INPUT_MODE_MASK 0x0007UL 1372 #define INPUT_MODE_SHIF 0UL 1373 // input mode of pkt_converter0(need to turn on reg_eco_fiq_input(TSP5,0c[7]) when flow through FIQ) 1374 // 0: normal 188 1375 // 1:CI+1.4 188 1376 // 2.Opencable 1377 // 3:192 mode 1378 // 4:MxL mode (192 / 196 / 200 bytes, but flexible by pkt_header_len) 1379 // 3. reg_filter_null_pkt(TSP5,06[2]) 1380 // 5:Nagra Dongle mode (192 bytes, but flexible by pkt_header_len & sync_byte_position) 1381 #define FORCE_SYNC_0X47 0x0008UL 1382 #define BYPASS_PKT_CONVERTER 0x0010UL 1383 #define BYPASS_SRC_ID_PARSER 0x0020UL 1384 #define SRC_ID_FLT_EN 0x0040UL 1385 #define MXL_TS_HEADER_LEN_MASK 0x0F80UL 1386 #define MXL_TS_HEADER_LEN_SHFT 0x7UL 1387 // 4 : Mxl 192 or Nagra Dongle 192 1388 // 8 : Mxl 196 1389 // 12 : Mxl 200 1390 #define SYNC_BYTE_POS_MASK 0xF000UL 1391 #define SYNC_BYTE_POS_SHFT 0x12UL 1392 // 1 : Nagra Dongle 192 1393 1394 REG16 HW3_Cfg0; //0x14 1395 #define PREVENT_SRAM_COLLISION 0x0001UL 1396 #define PUSI_THREE_BYTE_MODE 0x0002UL 1397 #define PVR1_TIMESTAMP_SRC 0x0004UL // 1: FIQ 0: LPCR 1398 #define PVR2_TIMESTAMP_SRC 0x0004UL 1399 #define PCR0_SRC_MASK 0x0F00UL 1400 #define PCR0_SRC_SHIFT 8UL 1401 #define PCR1_SRC_MASK 0xF000UL 1402 #define PCR1_SRC_SHIFT 12UL 1403 1404 REG16 HW3_Cfg1; //0x15 1405 #define MASK_SCR_VID_EN 0x0001UL 1406 #define MASK_SCR_VID_3D_EN 0x0002UL 1407 #define MASK_SCR_AUD_EN 0x0004UL 1408 #define MASK_SCR_AUD_B_EN 0x0008UL 1409 #define MASK_SCR_AUD_C_EN 0x0010UL 1410 #define MASK_SCR_AUD_D_EN 0x0020UL 1411 #define MASK_SCR_PVR1_EN 0x0040UL 1412 #define MASK_SCR_PVR2_EN 0x0080UL 1413 #define RST_CC_MODE 0x0100UL 1414 #define DIS_CNTR_INC_BY_PL 0x0200UL 1415 #define BYPASS_TIMESTAMP_SEL0 0x0400UL 1416 #define BYPASS_TIMESTAMP_SEL1 0x0800UL 1417 #define APID_C_BYPASS 0x1000UL 1418 #define APID_D_BYPASS 0x2000UL 1419 REG32 PauseTime[2]; // 0x16~17, 0x18~19 1420 REG32 PIDFLR_PCR[2]; 1421 #define TSP_PIDFLT_PCR_PID_MASK 0x00001fffUL 1422 #define TSP_PIDFLT_PCR_EN 0x00008000UL 1423 #define TSP_PIDFLT_PCR_SOURCE_MASK 0x000F0000UL 1424 #define TSP_PIDFLT_PCR_SOURCE_SHIFT 16UL 1425 REG32 Reserve; // 0x1e 1426 REG16 HW_Semaphore0; // 0x20 1427 REG16 HW_Semaphore1; // 0x21 1428 REG16 HW_Semaphore2; // 0x22 1429 1430 REG16 HWeco0; // 0x23 1431 #define HW_ECO_RVU 0x0001UL //RVU, reg_start_read_bypass_en, set 1 to fix start_read hang when unexpected writes 1432 #define HW_ECO_NEW_SYNCP_IN_ECO 0x0002UL // fixed_rm_pinpong_limation_en 1433 #define HW_ECO_SEC_DMA_BURST_NEWMODE 0x000CUL // fixed bust length 2 /4 issue 1434 #define HW_ECO_FIQ_REVERSE_DEADLOCK 0x0010UL // fix FIQ will be deadlock when reverse block 1435 #define HW_ECO_FIX_SEC_NULLPKT_ERR 0x0020UL // fix section can't receive pid 1ffb pkt 1436 #define HW_ECO_INIT_TIMESTAMP 0x0400UL // set 1 to init timestamp when filein start 1437 1438 REG16 HWeco1; // 0x24 1439 REG16 ModeCfg; // 0x25 1440 #define TSP_3WIRE_SERIAL_MODE_MASK 0x001FUL //set 1 to enable 3 wire serial in mode: Combine valid and clk.Valid always 1 and gated clk when no data in 1441 #define TSP_3WIRE_SERIAL_TSIF0 0x0001UL 1442 #define TSP_3WIRE_SERIAL_TSIF1 0x0002UL 1443 #define TSP_3WIRE_SERIAL_TSIF2 0x0004UL 1444 #define TSP_3WIRE_SERIAL_TSIFFI 0x0010UL 1445 #define TSP_NEW_OVERFLOW_MODE 0x0100UL // 1: new dma_overflow 0:old dma_overflow 1446 #define TSP_NON_188_CNT_MODE 0x0200UL 1447 #define TSP_STREAMID_CHK_DISABLE 0x0400UL // 1 : for nagra dongle, sync byte = 0x00, 0x80 or 0x81 1448 #define TSP_FILTER_STREAMID_0_TO_1F 0x0800UL 1449 1450 REG16 NAGRA_DONGLE_SYNCBYTE; // 0x26 1451 #define SYNC_BYTE0_MASK 0x00FFUL 1452 #define SYNC_BYTE0_SHFT 0UL 1453 #define SYNC_BYTE1_MASK 0xFF00UL 1454 #define SYNC_BYTE1_SHFT 8UL 1455 1456 REG16 dummy; // 0x27 1457 1458 REG16 SyncByte_tsif0[4]; // 0x28~2b 1459 #define TSP_SYNC_BYTE0_MAASK0 0x00FFUL 1460 #define TSP_SYNC_BYTE0_MAASK1 0xFF00UL 1461 REG16 SourceId_tsif0[2]; // 0x2c~2d 1462 #define TSP_SRCID_MASK0 0x000FUL 1463 #define TSP_SRCID_MASK1 0x00F0UL 1464 #define TSP_SRCID_MASK2 0x0F00UL 1465 #define TSP_SRCID_MASK3 0xF000UL 1466 REG16 SyncByte_file[4]; // 0x2e~31 1467 REG16 SourceId_file[2]; // 0x32~33 1468 REG16 SyncByte_tsif1[4]; // 0x34~37 1469 REG16 SourceId_tsif1[2]; // 0x38~39 1470 REG16 SyncByte_tsif2[4]; // 0x3a~3d 1471 REG16 SourceId_tsif2[2]; // 0x3e~3f 1472 } REG_Ctrl3; 1473 1474 // TSP part 4 1475 typedef struct _REG_Ctrl4 1476 { 1477 REG16 Overflow0; // 0xbf803900 0x00 1478 #define PID_HIT_0_EVER_OVERFLOW 0x0001UL 1479 #define PID_HIT_1_EVER_OVERFLOW 0x0002UL 1480 #define PID_HIT_2_EVER_OVERFLOW 0x0004UL 1481 #define PID_HIT_FILE_EVER_OVERFLOW 0x0008UL 1482 #define PID_HIT_CB_EVER_OVERFLOW 0x0010UL 1483 #define AFIFO_EVER_OVERFLOW 0x0020UL 1484 #define AFIFOB_EVER_OVERFLOW 0x0040UL 1485 #define VFIFO_EVER_OVERFLOW 0x0080UL 1486 #define V3DFIFO_EVER_OVERFLOW 0x0100UL 1487 #define PVR_1_EVER_OVERFLOW 0x0200UL 1488 #define PVR_2_EVER_OVERFLOW 0x0400UL 1489 #define VQ_TX0_EVER_OVERFLOW 0x1000UL 1490 #define VQ_TX1_EVER_OVERFLOW 0x2000UL 1491 #define VQ_TX2_EVER_OVERFLOW 0x4000UL 1492 #define VQ_TX3_EVER_OVERFLOW 0x8000UL 1493 1494 REG16 Overflow1; // 0xbf803904 0x01 1495 #define AFIFOD_EVER_OVERFLOW 0x0010UL 1496 #define AFIFOC_EVER_OVERFLOW 0x0008UL 1497 #define SEC_DMAW_OVERFLOW 0x0004UL 1498 #define SEC_SINGLE_EVER_OVERFLOW 0x0002UL 1499 #define SEC_PINGPONG_EVER_OVERFLOW 0x0001UL 1500 1501 REG16 FifoStatus; // 0xbf803908 0x02 1502 #define AFIFO_STATUS_MASK 0x000FUL 1503 #define AFIFO_STATUS_SHFT 0UL 1504 #define AFIFOC_STATUS_MASK 0x000FUL 1505 #define AFIFOC_STATUS_SHFT 0UL 1506 #define AFIFOB_STATUS_MASK 0x00F0UL 1507 #define AFIFOB_STATUS_SHFT 4UL 1508 #define AFIFOD_STATUS_MASK 0x00F0UL 1509 #define AFIFOD_STATUS_SHFT 4UL 1510 #define VFIFO_STATUS_MASK 0x0F00UL 1511 #define VFIFO_STATUS_SHFT 8UL 1512 #define V3DFIFO_STATUS_MASK 0xF000UL 1513 #define V3DFIFO_STATUS_SHFT 12UL 1514 1515 REG16 PvrFifoStatus; // 0xbf80390C 0x03 1516 #define PVR_1_STATUS_MASK 0x000FUL 1517 #define PVR_1_STATUS_SHFT 0UL 1518 1519 REG16 VQTxFifoStatus; // 0xbf803910 0x04 1520 #define VQ_TX0_STATUS_MASK 0x000FUL 1521 #define VQ_TX0_STATUS_SHFT 0UL 1522 #define VQ_TX1_STATUS_MASK 0x0F00UL 1523 #define VQ_TX1_STATUS_SHFT 8UL 1524 1525 REG16 PktCnt_video; // 0xbf803914 0x05 1526 REG16 PktCnt_v3d; // 0xbf803918 0x06 1527 REG16 PktCnt_aud; // 0xbf80391C 0x07 1528 REG16 PktCnt_audB; // 0xbf803920 0x08 1529 REG16 PktCnt_audC; // 0xbf803924 0x09 1530 REG16 PktCnt_audD; // 0xbf803928 0x0a 1531 1532 REG32 _bf803924[1]; // 0xbf80392C~0xbf803930 0x0b~0x0c 1533 1534 REG16 LockedPktCnt; // 0x0d 1535 REG16 AVPktCnt; // 0x0e 1536 1537 REG16 PktErrStatus; // 0xbf80392C 0x0x0f 1538 REG16 PidMatched0; // 0xbf803930 0x10 1539 REG16 PidMatched1; // 0xbf803934 0x11 1540 REG16 PidMatched2; // 0xbf803938 0x12 1541 REG16 PidMatched3; // 0xbf80393C 0x13 1542 REG16 dummy[2]; // 0x14~0x15 1543 REG16 Sram2p_collision; // 0x16 1544 #define SRAM_COLLISION_BY_SW 0x1000UL 1545 #define SRAM_COLLISION_BY_HW 0x2000UL 1546 #define SECFLT_SRAM1_EVER_COLLISION 0x4000UL 1547 #define SECFLT_SRAM0_EVER_COLLISION 0x8000UL 1548 REG16 AVPktCnt1; //for vid_3d/audb 0x17 1549 REG16 ErrPktCnt; //use reg_err_pkt_src_sel 0x18 1550 REG16 AVPktCnt2; //for audc/audd 0x19 1551 1552 REG16 EverUnlockStatus; // 0x1a 1553 #define EVER_UNLOCK_TS0 0x0001UL // set 1 mean there are unlock pkts 1554 #define EVER_UNLOCK_TS1 0x0002UL 1555 #define EVER_UNLOCK_TS2 0x0004UL 1556 #define EVER_UNLOCK_TS_FI 0x0008UL 1557 1558 REG16 Overflow2; // 0xbf803904 0x1b 1559 #define PC_EVER_OVERFLOW_0 0x0001UL 1560 #define PC_EVER_OVERFLOW_FILE 0x0002UL 1561 #define PC_EVER_OVERFLOW_1 0x0004UL 1562 #define PC_EVER_OVERFLOW_2 0x0008UL 1563 1564 REG16 dummy1[0x70-0x1c]; //0x1C~0x6f 1565 REG16 ErrPktSrcSel; //select source of ErrPktCnt 0x70 1566 #define ERR_PKT_SRC_TS0 0x0001UL 1567 #define ERR_PKT_SRC_FILE 0x0002UL 1568 #define ERR_PKT_SRC_TS1 0x0003UL 1569 #define ERR_PKT_SRC_TS2 0x0004UL 1570 #define ERR_PKT_SRC_MMFI0 0x0005UL 1571 #define ERR_PKT_SRC_MMFI1 0x0006UL 1572 1573 REG16 ErrPktCntLoad; // 0x71 1574 #define ERR_PKT_CNT_0_LOAD 0x0001UL 1575 #define ERR_PKT_CNT_FILE_LOAD 0x0002UL 1576 #define ERR_PKT_CNT_1_LOAD 0x0004UL 1577 #define ERR_PKT_CNT_2_LOAD 0x0008UL 1578 #define ERR_PKT_CNT_MMFI0_LOAD 0x0010UL 1579 #define ERR_PKT_CNT_MMFI1_LOAD 0x0020UL 1580 1581 REG16 ErrPktCntClr; // 0x72 1582 #define ERR_PKT_CNT_0_CLR 0x0001UL 1583 #define ERR_PKT_CNT_FILE_CLR 0x0002UL 1584 #define ERR_PKT_CNT_1_CLR 0x0004UL 1585 #define ERR_PKT_CNT_2_CLR 0x0008UL 1586 #define ERR_PKT_CNT_MMFI0_CLR 0x0010UL 1587 #define ERR_PKT_CNT_MMFI1_CLR 0x0020UL 1588 1589 REG16 dummy2[0x78-0x73]; // 0x73~0x78 1590 1591 REG16 PktCntSrc2; // 0x78 1592 #define AUDC_SRC_MASK 0x0007UL 1593 #define AUDC_SRC_SHIFT 0UL 1594 #define AUDD_SRC_MASK 0x0038UL 1595 #define AUDD_SRC_SHIFT 3UL 1596 1597 REG16 dummy3; // 0x79 1598 REG16 PktCntLoad; // 0x7a 1599 #define LOCK_PKT_CNT_0_LOAD 0x0001UL 1600 #define LOCK_PKT_CNT_1_LOAD 0x0002UL 1601 #define LOCK_PKT_CNT_2_LOAD 0x0004UL 1602 #define LOCK_PKT_CNT_FI_LOAD 0x0010UL 1603 #define V_PKT_CNT_LOAD 0x0100UL 1604 #define V3D_PKT_CNT_LOAD 0x0200UL 1605 #define AUD_PKT_CNT_LOAD 0x0400UL 1606 #define AUDB_PKT_CNT_LOAD 0x0800UL 1607 #define AUDC_PKT_CNT_LOAD 0x1000UL 1608 #define AUDD_PKT_CNT_LOAD 0x2000UL 1609 1610 REG16 PktCntLoad1; // 0x7b 1611 #define V_DROP_PKT_CNT_LOAD 0x0001UL 1612 #define V3D_DROP_PKT_CNT_LOAD 0x0002UL 1613 #define AUD_DROP_PKT_CNT_LOAD 0x0004UL 1614 #define AUDB_DROP_PKT_CNT_LOAD 0x0008UL 1615 #define AUDC_DROP_PKT_CNT_LOAD 0x0010UL 1616 #define AUDD_DROP_PKT_CNT_LOAD 0x0020UL 1617 #define V_DIS_CNTR_PKT_CNT_LOAD 0x0100UL 1618 #define V3D_DIS_CNTR_PKT_CNT_LOAD 0x0200UL 1619 #define AUD_DIS_CNTR_PKT_CNT_LOAD 0x0400UL 1620 #define AUDB_DIS_CNTR_PKT_CNT_LOAD 0x0800UL 1621 #define AUDC_DIS_CNTR_PKT_CNT_LOAD 0x1000UL 1622 #define AUDD_DIS_CNTR_PKT_CNT_LOAD 0x2000UL 1623 1624 REG16 PktCntClr; // 0x7c 1625 #define LOCK_PKT_CNT_0_CLR 0x0001UL 1626 #define LOCK_PKT_CNT_1_CLR 0x0002UL 1627 #define LOCK_PKT_CNT_2_CLR 0x0004UL 1628 #define LOCK_PKT_CNT_FI_CLR 0x0010UL 1629 #define V_PKT_CNT_CLR 0x0100UL 1630 #define V3D_PKT_CNT_CLR 0x0200UL 1631 #define AUD_PKT_CNT_CLR 0x0400UL 1632 #define AUDB_PKT_CNT_CLR 0x0800UL 1633 #define AUDC_PKT_CNT_CLR 0x1000UL 1634 #define AUDD_PKT_CNT_CLR 0x2000UL 1635 1636 REG16 PktCntClr1; // 0x7d 1637 #define V_DROP_PKT_CNT_CLR 0x0001UL 1638 #define V3D_DROP_PKT_CNT_CLR 0x0002UL 1639 #define AUD_DROP_PKT_CNT_CLR 0x0004UL 1640 #define AUDB_DROP_PKT_CNT_CLR 0x0008UL 1641 #define AUDC_DROP_PKT_CNT_CLR 0x0010UL 1642 #define AUDD_DROP_PKT_CNT_CLR 0x0020UL 1643 #define V_DIS_CNTR_PKT_CNT_CLR 0x0100UL 1644 #define V3D_DIS_CNTR_PKT_CNT_CLR 0x0200UL 1645 #define AUD_DIS_CNTR_PKT_CNT_CLR 0x0400UL 1646 #define AUDB_DIS_CNTR_PKT_CNT_CLR 0x0800UL 1647 #define AUDC_DIS_CNTR_PKT_CNT_CLR 0x1000UL 1648 #define AUDD_DIS_CNTR_PKT_CNT_CLR 0x2000UL 1649 1650 REG16 PktCntSrc; // 0x7e 1651 #define VID_SRC_MASK 0x0007UL 1652 #define VID_SRC_SHIFT 0UL 1653 #define V3D_SRC_MASK 0x0031UL 1654 #define V3D_SRC_SHIFT 3UL 1655 #define AUD_SRC_MASK 0x01C0UL 1656 #define AUD_SRC_SHIFT 6UL 1657 #define AUDB_SRC_MASK 0x0E00UL 1658 #define AUDB_SRC_SHIFT 9UL 1659 1660 REG16 DebugSrcSel; // 0x7f 1661 #define SRC_SEL_MASK 0x0001UL 1662 #define DROP_PKT_MODE_MASK 0x0002UL 1663 #define PIDFLT_SRC_SEL_MASK 0x001CUL 1664 #define TSIF_SRC_SEL_MASK 0x00E0UL 1665 #define TSIF_SRC_SEL_SHIFT 5UL 1666 #define TSIF_SRC_SEL_TSIF0 0x000UL 1667 #define TSIF_SRC_SEL_TSIF1 0x001UL 1668 #define TSIF_SRC_SEL_TSIF2 0x002UL 1669 #define TSIF_SRC_SEL_TSIF_FI 0x004UL 1670 #define AV_PKT_SRC_SEL 0x0100UL 1671 #define AV_PKT_SRC_SEL_MASK 0x0100UL 1672 #define AV_PKT_SRC_SEL_SHIFT 8UL 1673 #define AV_PKT_SRC_VID 0x0 1674 #define AV_PKT_SRC_AUD 0x1 1675 #define AV_PKT_SRC_V3D 0x0 1676 #define AV_PKT_SRC_AUDB 0x1 1677 #define AV_PKT_SRC_AUDC 0x0 1678 #define AV_PKT_SRC_AUDD 0x1 1679 #define CLR_SRC_MASK 0x0E00UL 1680 #define CLR_SRC_SHIFT 9UL 1681 #define CLR_SRC_TSIF0 0x0200UL 1682 #define CLR_SRC_TSIFFI 0x0400UL 1683 #define CLR_SRC_TSIF1 0x0600UL 1684 #define CLR_SRC_TSIF2 0x0800UL 1685 #define CLR_SRC_MMFI0 0x0C00UL 1686 #define CLR_SRC_MMFI1 0x0E00UL 1687 1688 }REG_Ctrl4; 1689 1690 // TSP part 4 1691 typedef struct _REG_Ctrl5 1692 { 1693 REG16 ATS_Adj_Period; // 0x00 1694 #define TSP_ATS_ADJ_PERIOD_MASK 0x000FUL 1695 1696 REG16 AtsCfg; // 0x01 1697 #define TSP_ATS_MODE_FI_ENABLE 0x0001UL 1698 #define TSP_ATS_OFFSET_FI_ENABLE 0x0002UL 1699 #define TSP_ATS_OFFSET_FI_SHIFT 8UL 1700 #define TSP_ATS_OFFSET_FI_MASK 0x0F00UL 1701 #define TSP_ATS_OFFSET_FI_POSITIVE 0x0000UL 1702 #define TSP_ATS_OFFSET_FI_NEGATIVE 0x1000UL 1703 1704 REG16 Ts_If_Fi_Cfg; // 0x02 1705 #define TSP_FIIF_EN 0x0001UL 1706 #define TSP_FIIF_DATA_SWAP 0x0002UL 1707 #define TSP_FIIF_P_SEL 0x0004UL 1708 #define TSP_FIIF_EXT_SYNC_SEL 0x0008UL 1709 #define TSP_FIIF_MUX_MASK 0x0010UL 1710 #define TSP_FIIF_MUX_FILE_PATH 0x0000UL 1711 #define TSP_FIIF_MUX_LIVE_PATH 0x0010UL 1712 #define TSP_PKT_CHK_SIZE_FI_MASK 0xFF00UL 1713 #define TSP_PKT_CHK_SIZE_FI_SHIFT 8UL 1714 1715 REG16 MatchPidSel; // 0x03 1716 #define TSP_MATCH_PID_SEL_MASK 0x000FUL 1717 #define TSP_MATCH_PID_SEL_SHIFT 0UL 1718 1719 REG16 TsifCfg; // 0x04 1720 #define TSP_TSIFCFG_TSIF0_TSOBLK_EN 0x0100UL 1721 #define TSP_TSIFCFG_TSIF1_TSOBLK_EN 0x0200UL 1722 #define TSP_TSIFCFG_TSIF2_TSOBLK_EN 0x0400UL 1723 #define TSP_TSIFCFG_TSIFFI_TSOBLK_EN 0x0800UL 1724 #define TSP_TSIFCFG_WB_FSM_RESET 0x1000UL 1725 #define TSP_TSIFCFG_WB_FSM_RESET_FINISH 0x2000UL 1726 1727 REG16 TraceMarkCfg; // 0x05 1728 #define TSP_TRACE_MARK_VID_EN 0x0001UL 1729 #define TSP_TRACE_MARK_V3D_EN 0x0002UL 1730 #define TSP_TRACE_MARK_AUD_EN 0x0004UL 1731 #define TSP_TRACE_MARK_AUDB_EN 0x0008UL 1732 #define TSP_TRACE_MARK_AUDC_EN 0x0010UL 1733 #define TSP_TRACE_MARK_AUDD_EN 0x0020UL 1734 1735 REG16 HwCfg0; // 0x06 1736 #define TSP_FIX_192_TIMER_0_EN 0x0001UL 1737 #define TSP_VQ_CLR 0x0002UL 1738 #define TSP_FILTER_NULL_PKT0 0x0004UL 1739 #define TSP_FILTER_NULL_PKT1 0x0008UL 1740 #define TSP_FILTER_NULL_PKT2 0x0010UL 1741 #define TSP_FILTER_NULL_PKT_FILE 0x0020UL 1742 #define TSP_FLUSH_PVR1_DATA 0x0100UL 1743 #define TSP_FLUSH_PVR2_DATA 0x0200UL 1744 1745 REG16 InitTimestamp; // 0x07 1746 #define TSP_INIT_TIMESTAMP_FILEIN 0x0001UL 1747 #define TSP_INIT_TIMESTAMP_MMFI0 0x0002UL 1748 #define TSP_INIT_TIMESTAMP_MMFI1 0x0004UL 1749 #define TSP_MATCH_CNT_FILEIN 0x0008UL // set 1 to enable match cnt function for filein 1750 #define TSP_MATCH_CNT_THRESHOLD_MASK 0x00F0UL // file in will lost lock when match cnt <= threshold 1751 #define TSP_MATCH_CNT_THRESHOLD_SHFT 4UL 1752 #define TSP_INIT_TRUST_SYNC_CNT_MASK 0xFF00UL // reg_init_trust_sync_cnt_value for Filein 1753 #define TSP_INIT_TRUST_SYNC_CNT_SHFT 8UL // 188 : normal 192 mode (+4 is sync byte) 1754 // 189 : nagra dongle 192 mode (+3 is sync byte) 1755 1756 REG16 MiuSelCtrl0; // 0x08 1757 #define TSP_MIU_SEL_FILEIN_MASK 0x0003UL 1758 #define TSP_MIU_SEL_FILEIN_SHIFT 0UL 1759 #define TSP_MIU_SEL_SECTION_MASK 0x000CUL 1760 #define TSP_MIU_SEL_SECTION_SHIFT 2UL 1761 #define TSP_MIU_SEL_MMFI0_MASK 0x0030UL 1762 #define TSP_MIU_SEL_MMFI0_SHIFT 4UL 1763 #define TSP_MIU_SEL_MMFI1_MASK 0x00C0UL 1764 #define TSP_MIU_SEL_MMFI1_SHIFT 6UL 1765 #define TSP_MIU_SEL_VQ_RW_MASK 0x0300UL 1766 #define TSP_MIU_SEL_VQ_RW_SHIFT 8UL 1767 #define TSP_MIU_SEL_OR_RW_MASK 0x0C00UL 1768 #define TSP_MIU_SEL_OR_RW_SHIFT 10UL 1769 #define TSP_MIU_SEL_PVRCB_RW_MASK 0x3000UL 1770 #define TSP_MIU_SEL_PVRCB_RW_SHIFT 12UL 1771 1772 REG16 MiuSelCtrl1; // 0x09 1773 #define TSP_MIU_SEL_PVR1_MASK 0x0003UL 1774 #define TSP_MIU_SEL_PVR1_SHIFT 0UL 1775 #define TSP_MIU_SEL_PVR2_MASK 0x000CUL 1776 #define TSP_MIU_SEL_PVR2_SHIFT 2UL 1777 #define TSP_MIU_SEL_FIQ0_RW_MASK 0x0300UL 1778 #define TSP_MIU_SEL_FIQ0_RW_SHIFT 8UL 1779 #define TSP_MIU_SEL_FIQ1_RW_MASK 0x0C00UL 1780 #define TSP_MIU_SEL_FIQ1_RW_SHIFT 10UL 1781 1782 REG16 MiuRrPri; // 0x0A 1783 #define TSP_MIU_RR_PRI_ABT0 0x0001UL 1784 #define TSP_MIU_RR_PRI_ABT1 0x0002UL 1785 #define TSP_MIU_RR_PRI_ABT2 0x0004UL 1786 #define TSP_MIU_RR_PRI_ABT3 0x0008UL 1787 #define TSP_MIU_RR_PRI_ABT4 0x0010UL 1788 1789 REG16 FIQ_MUX_CFG; // 0xB 1790 #define FIQ_MUX_CFG_MASK 0x0007UL 1791 #define FIQ_MUX_CFG_SHFT 0UL 1792 #define FIQ_MUX_CFG_TS0 0x0000UL 1793 #define FIQ_MUX_CFG_FILE 0x0001UL 1794 #define FIQ_MUX_CFG_TS1 0x0002UL 1795 #define FIQ_MUX_CFG_TS2 0x0003UL 1796 1797 REG16 HWeco2; // 0xC 1798 #define HW_ECO_TIMESTAMP_RING_BACK 0x0001UL // set 1 to fix time stamp ring back from 32'hffff_ffff 1799 #define HW_ECO_LPCR_RING_BACK 0x0002UL // set 1 to fix lpcr ring back from 32'hffff_ffff 1800 #define NMATCH_DISABLE 0x0008UL // set 1 to disable secflt_not_match 1801 #define SCRAMB_BIT_AFTER_CA 0x0010UL // set 1 to see match pid scramble status after ca on TSP1,0c~0d 1802 #define HW_ECO_TS_SYNC_OUT_DELAY 0x0020UL // set 1 to fix MxL FIQ no timestamp issue 1803 #define HW_ECO_TS_SYNC_OUT_REVERSE_BLK 0x0040UL // set 1 to fix MxL FIQ no timestamp issue & reverse block 1804 #define HW_ECO_FIQ_INPUT 0x0080UL // set 1 to fix MxL FIQ sync early issue 1805 #define SECFLT_CTRL_DMA_DISABLE 0x0100UL // set 1 to disable sec_dma update section sram table 1806 #define PKT_CONVERTER_FIRST_SYNC_VLD_MASK 0x0200UL // set 1 to enable first sync valid mask for pkt_converter 1807 1808 REG16 dummy0[0x10-0xD]; // 0xD~0xF 1809 1810 REG16 TS_MUX_CFG0; // 0x10 1811 #define TS_MUX_CFG_TS0_MUX_MASK 0x000FUL 1812 #define TS_MUX_CFG_TS0_MUX_SHIFT 0UL 1813 #define TS_MUX_CFG_TS1_MUX_MASK 0x00F0UL 1814 #define TS_MUX_CFG_TS1_MUX_SHIFT 4UL 1815 #define TS_MUX_CFG_TS2_MUX_MASK 0x0F00UL 1816 #define TS_MUX_CFG_TS2_MUX_SHIFT 8UL 1817 #define TS_MUX_CFG_TSFI_MUX_MASK 0xF000UL 1818 #define TS_MUX_CFG_TSFI_MUX_SHIFT 12UL 1819 #define TS_MUX_CFG_TS_MUX_TS0 0x0000UL 1820 #define TS_MUX_CFG_TS_MUX_TS1 0x0001UL 1821 #define TS_MUX_CFG_TS_MUX_TS2 0x0002UL 1822 #define TS_MUX_CFG_TS_MUX_TSO 0x0006UL 1823 #define TS_MUX_CFG_TS_MUX_DMD 0x0007UL 1824 REG16 TS_MUX_CFG1; // 0x11 1825 1826 REG16 TS_MUX_CFG_S2P; // 0x12 1827 #define TS_MUX_CFG_S2P0_MUX_MASK 0x000FUL 1828 #define TS_MUX_CFG_S2P1_MUX_MASK 0x00F0UL 1829 #define TS_MUX_CFG_S2P0_MUX_SHIFT 0 1830 #define TS_MUX_CFG_S2P1_MUX_SHIFT 4 1831 #define TS_MUX_CFG_S2P_MUX_TS0 0x0000UL 1832 #define TS_MUX_CFG_S2P_MUX_TS1 0x0001UL 1833 #define TS_MUX_CFG_S2P_MUX_TS2 0x0002UL 1834 1835 REG16 TS_MUX_CFG0_TSOIN; // 0x13 1836 #define TS_MUX_CFG_TSOIN0_MUX_MASK 0x000FUL 1837 #define TS_MUX_CFG_TSOIN0_MUX_SHIFT 0UL 1838 #define TS_MUX_CFG_TSOIN1_MUX_MASK 0x00F0UL 1839 #define TS_MUX_CFG_TSOIN1_MUX_SHIFT 4UL 1840 #define TS_MUX_CFG_TSOIN2_MUX_MASK 0x0F00UL 1841 #define TS_MUX_CFG_TSOIN2_MUX_SHIFT 8UL 1842 #define TS_MUX_CFG_TSO_MUX_TS0 0x0000UL 1843 #define TS_MUX_CFG_TSO_MUX_TS1 0x0001UL 1844 #define TS_MUX_CFG_TSO_MUX_TS2 0x0002UL 1845 #define TS_MUX_CFG_TSO_MUX_DMD 0x0007UL 1846 1847 REG16 TSP5_Reserve_14; // 0x14 1848 1849 REG16 TS_MUX_CFG_TSOOUT; // 0x15 1850 #define TS_MUX_CFG_TSOOUT_MASK 0x000FUL 1851 #define TS_MUX_CFG_TSOOUT_FROM_TSO 0x0000UL 1852 #define TS_MUX_CFG_TSOOUT_FROM_S2P 0x0001UL 1853 1854 REG16 TS_MMT_MUX_CFG; // 0x16 1855 #define TS_MMT_MUX_CFG_MASK 0x000FUL 1856 #define TS_MMT_MUX_CFG_TS_MUX_TS0 0x0000UL 1857 #define TS_MMT_MUX_CFG_TS_MUX_TS1 0x0001UL 1858 #define TS_MMT_MUX_CFG_TS_MUX_TS2 0x0002UL 1859 #define TS_MMT_MUX_CFG_TS_MUX_TSO 0x0006UL 1860 REG16 dummy1[0x20-0x17]; // 0x17~0x1F 1861 1862 REG32 FileIn_Dmar_LBnd; // 0x20 1863 #define TS_FILEIN_DMAR_LBND_MASK 0x0FFFFFFFUL 1864 1865 REG32 FileIn_Dmar_UBnd; // 0x22 1866 #define TS_FILEIN_DMAR_UBND_MASK 0x0FFFFFFFUL 1867 1868 REG32 MMFileIn0_Dmar_LBnd; // 0x24 1869 #define TS_MMFILEIN0_DMAR_LBND_MASK 0x0FFFFFFFUL 1870 1871 REG32 MMFileIn0_Dmar_UBnd; // 0x26 1872 #define TS_MMFILEIN0_DMAR_UBND_MASK 0x0FFFFFFFUL 1873 1874 REG32 MMFileIn1_Dmar_LBnd; // 0x28 1875 #define TS_MMFILEIN1_DMAR_LBND_MASK 0x0FFFFFFFUL 1876 1877 REG32 MMFileIn1_Dmar_UBnd; // 0x2A 1878 #define TS_MMFILEIN1_DMAR_UBND_MASK 0x0FFFFFFFUL 1879 1880 REG32 Orz_Dmar_LBnd; // 0x2C 1881 #define TS_ORZ_DMAR_LBND_MASK 0x0FFFFFFFUL 1882 1883 REG32 Orz_Dmar_UBnd; // 0x2E 1884 #define TS_ORZ_DMAR_UBND_MASK 0x0FFFFFFFUL 1885 1886 REG32 VQTX0_Dmar_LBnd; // 0x30 1887 #define TS_VQTX0_DMAR_LBND_MASK 0x0FFFFFFFUL 1888 1889 REG32 VQTX0_Dmar_UBnd; // 0x32 1890 #define TS_VQTX0_DMAR_UBND_MASK 0x0FFFFFFFUL 1891 1892 REG32 VQTX1_Dmar_LBnd; // 0x34 1893 #define TS_VQTX1_DMAR_LBND_MASK 0x0FFFFFFFUL 1894 1895 REG32 VQTX1_Dmar_UBnd; // 0x36 1896 #define TS_VQTX1_DMAR_UBND_MASK 0x0FFFFFFFUL 1897 1898 REG32 VQTX2_Dmar_LBnd; // 0x38 1899 #define TS_VQTX2_DMAR_LBND_MASK 0x0FFFFFFFUL 1900 1901 REG16 dummy_3A_3F[6]; // 0x3A~0x3F 1902 1903 REG32 VQTX2_Dmar_UBnd; // 0x40 1904 #define TS_VQTX2_DMAR_UBND_MASK 0x0FFFFFFFUL 1905 1906 REG32 VQTX3_Dmar_LBnd; // 0x42 1907 #define TS_VQTX3_DMAR_LBND_MASK 0x0FFFFFFFUL 1908 1909 REG32 VQTX3_Dmar_UBnd; // 0x44 1910 #define TS_VQTX3_DMAR_UBND_MASK 0x0FFFFFFFUL 1911 1912 REG32 VQRX_Dmar_LBnd; // 0x46 1913 #define TS_VQRX_DMAR_LBND_MASK 0x0FFFFFFFUL 1914 1915 REG32 VQRX_Dmar_UBnd; // 0x48 1916 #define TS_VQRX_DMAR_UBND_MASK 0x0FFFFFFFUL 1917 1918 REG32 Fiq0_Dmar_LBnd; // 0x4A 1919 #define TS_Fiq0_DMAR_LBND_MASK 0x0FFFFFFFUL 1920 1921 REG32 Fiq0_Dmar_UBnd; // 0x4C 1922 #define TS_Fiq0_DMAR_UBND_MASK 0x0FFFFFFFUL 1923 1924 REG32 Fiq1_Dmar_LBnd; // 0x4E 1925 #define TS_Fiq1_DMAR_LBND_MASK 0x0FFFFFFFUL 1926 1927 REG32 Fiq1_Dmar_UBnd; // 0x50 1928 #define TS_Fiq1_DMAR_UBND_MASK 0x0FFFFFFFUL 1929 1930 REG16 dummy2[0x5D-0x52]; // 0x52~0x5C 1931 1932 REG16 SyncByte_Privilege_FILE; // 0x5D 1933 #define FILE_PRIVILEGE_SYNC_BYTE 0x00FFUL 1934 #define FILE_PRIVILEGE_SYNC_BYTE_REPLACE 0xFF00UL 1935 REG16 SyncByte_Privilege_PVR; // 0x5E 1936 #define PVR1_PRIVILEGE_SYNC_BYTE 0x00FFUL 1937 #define PVR2_PRIVILEGE_SYNC_BYTE 0xFF00UL 1938 1939 REG16 CPU_Secure_Cfg; // 0x5F 1940 #define FW_LOAD_ONCE_BY_TEE 0x0001UL 1941 #define FW_SECURE_STATUS 0x0002UL 1942 #define FW_FIX_DMX_RST_ONEWAY 0x0004UL 1943 #define LEAF_DROP_ENABLE 0x0008UL 1944 1945 REG16 Dma_Ns_Cfg; // 0x60 1946 #define TS_DMA_NS_CTRL_FILEIN 0x0001UL 1947 #define TS_DMA_NS_CTRL_MMFI0 0x0002UL 1948 #define TS_DMA_NS_CTRL_MMFI1 0x0004UL 1949 #define TS_DMA_NS_CTRL_PVR1 0x0008UL 1950 #define TS_DMA_NS_CTRL_PVR2 0x0010UL 1951 #define TS_DMA_NS_CTRL_VQ 0x0020UL 1952 #define TS_DMA_NS_CTRL_ORZ 0x0040UL 1953 #define TS_DMA_NS_CTRL_SEC 0x0080UL 1954 #define TS_DMA_NS_CTRL_FIQ0 0x0100UL 1955 #define TS_DMA_NS_CTRL_FIQ1 0x0200UL 1956 1957 REG16 Dma_Be_Cfg; // 0x61 1958 #define TS_DMA_BE_CTRL_FILEIN 0x0001UL 1959 #define TS_DMA_BE_CTRL_MMFI0 0x0002UL 1960 #define TS_DMA_BE_CTRL_MMFI1 0x0004UL 1961 #define TS_DMA_BE_CTRL_PVR1 0x0008UL 1962 #define TS_DMA_BE_CTRL_PVR2 0x0010UL 1963 #define TS_DMA_BE_CTRL_VQ 0x0020UL 1964 #define TS_DMA_BE_CTRL_ORZ 0x0040UL 1965 #define TS_DMA_BE_CTRL_SEC 0x0080UL 1966 #define TS_DMA_BE_CTRL_FIQ0 0x0100UL 1967 #define TS_DMA_BE_CTRL_FIQ1 0x0200UL 1968 1969 REG16 MIU_NsUseTee_Cfg; // 0x62 1970 #define TS_MIU_NS_USE_TEE_WP_RP_FILEIN 0x0001UL 1971 #define TS_MIU_NS_USE_TEE_WP_RP_MMFI0 0x0002UL 1972 #define TS_MIU_NS_USE_TEE_WP_RP_MMFI1 0x0004UL 1973 1974 REG32 INIT_TIMESTAMP_FILE; // 0x63 1975 REG32 INIT_TIMESTAMP_MMFI0; // 0x65 1976 REG32 INIT_TIMESTAMP_MMFI1; // 0x67 1977 REG16 Reserve[0x71-0x69]; // 0x69-0x70 1978 REG32 PVR1_Int_Cfg; // 0x71 1979 REG32 PVR2_Int_Cfg; // 0x73 1980 REG16 PVR_MetSize; // 0x75 1981 1982 REG32 DMAW_LBND5; // 0x76 1983 REG32 DMAW_UBND5; // 0x78 1984 REG32 DMAW_LBND6; // 0x7A 1985 REG32 DMAW_UBND6; // 0x7C 1986 1987 REG16 VQ_Idle_Cnt; // 0x7E 1988 REG16 Miu_MCM_Cfg; // 0x7F 1989 #define MCM_TURN_OFF_ALL 0x0001UL 1990 #define TS_OR_WRITE_FIX 0x8000UL 1991 }REG_Ctrl5; 1992 1993 typedef struct _REG_Ctrl6 1994 { 1995 REG32 PCR64_3_L; // 0x00 1996 REG32 PCR64_3_H; // 0x02 1997 REG32 PCR64_4_L; // 0x04 1998 REG32 PCR64_4_H; // 0x06 1999 }REG_Ctrl6; 2000 2001 // TSP: ts sample part 2002 typedef struct _REG_TS_Sample 2003 { 2004 REG16 TS0_Clk_Sample; // 0x00 2005 #define TS0_PHASE_ADJUST_COUNT_MASK 0x001FUL 2006 #define TS0_PHASE_ADJUST_EN 0x0020UL 2007 #define TS0_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2008 2009 REG16 TS1_Clk_Sample; // 0x01 2010 #define TS1_PHASE_ADJUST_COUNT_MASK 0x001FUL 2011 #define TS1_PHASE_ADJUST_EN 0x0020UL 2012 #define TS1_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2013 2014 REG16 TS2_Clk_Sample; // 0x02 2015 #define TS2_PHASE_ADJUST_COUNT_MASK 0x001FUL 2016 #define TS2_PHASE_ADJUST_EN 0x0020UL 2017 #define TS2_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2018 2019 REG16 TS3_Clk_Sample; // 0x03 2020 #define TS3_PHASE_ADJUST_COUNT_MASK 0x001FUL 2021 #define TS3_PHASE_ADJUST_EN 0x0020UL 2022 #define TS3_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2023 2024 REG16 TS4_Clk_Sample; // 0x04 2025 #define TS4_PHASE_ADJUST_COUNT_MASK 0x001FUL 2026 #define TS4_PHASE_ADJUST_EN 0x0020UL 2027 #define TS4_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2028 2029 REG16 TS5_Clk_Sample; // 0x05 2030 #define TS5_PHASE_ADJUST_COUNT_MASK 0x001FUL 2031 #define TS5_PHASE_ADJUST_EN 0x0020UL 2032 #define TS5_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2033 2034 REG16 TsSample_Reserved0[0x10-0x6]; // 0x06 - 0x0F 2035 2036 REG16 TSO_Clk_Sample; // 0x10 2037 #define TSO_PHASE_ADJUST_COUNT_MASK 0x001FUL 2038 #define TSO_PHASE_ADJUST_EN 0x0020UL 2039 #define TSO_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2040 #define TSO_CLK_INVERT 0x0080UL 2041 2042 REG16 TsSample_Reserved1[0x20-0x11]; // 0x11 - 0x1F 2043 2044 REG16 TS_Out_Clk_Sample; // 0x20 (for old path: TSIF2 out) 2045 #define TS_OUT_PHASE_ADJUST_COUNT_MASK 0x001FUL 2046 #define TS_OUT_PHASE_ADJUST_EN 0x0020UL 2047 #define TS_OUT_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2048 #define TS_OUT_CLK_INVERT 0x0080UL 2049 2050 REG16 S2P_Out_Clk_Sample; // 0x21 2051 #define S2P_PHASE_ADJUST_COUNT_MASK 0x001FUL 2052 #define S2P_PHASE_ADJUST_EN 0x0020UL 2053 #define S2P_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2054 #define S2P_CLK_INVERT 0x0080UL 2055 2056 REG16 S2P1_Out_Clk_Sample; // 0x22 2057 #define S2P1_PHASE_ADJUST_COUNT_MASK 0x001FUL 2058 #define S2P1_PHASE_ADJUST_EN 0x0020UL 2059 #define S2P1_RESAMPLE_VOTE_ADJUST_EN 0x0040UL 2060 #define S2P1_CLK_INVERT 0x0080UL 2061 2062 }REG_TS_Sample; 2063 2064 // Firmware status 2065 #define TSP_FW_STATE_MASK 0xFFFF0000UL 2066 #define TSP_FW_STATE_LOAD 0x00010000UL 2067 #define TSP_FW_STATE_ENG_OVRUN 0x00020000UL 2068 #define TSP_FW_STATE_ENG1_OVRUN 0x00040000UL //[reserved] 2069 #define TSP_FW_STATE_IC_ENABLE 0x01000000UL 2070 #define TSP_FW_STATE_DC_ENABLE 0x02000000UL 2071 #define TSP_FW_STATE_IS_ENABLE 0x04000000UL 2072 #define TSP_FW_STATE_DS_ENABLE 0x08000000UL 2073 2074 2075 // TSP AEON specific IP address 2076 #define OPENRISC_IP_1_ADDR 0x00200000UL 2077 #define OPENRISC_IP_1_SIZE 0x00020000UL 2078 #define OPENRISC_IP_2_ADDR 0x90000000UL 2079 #define OPENRISC_IP_2_SIZE 0x00010000UL 2080 #define OPENRISC_IP_3_ADDR 0x40080000UL 2081 #define OPENRISC_IP_3_SIZE 0x00020000UL 2082 #define OPENRISC_QMEM_ADDR 0x00000000UL 2083 #define OPENRISC_QMEM_SIZE 0x00003000UL 2084 #endif // _TSP_REG_H_ 2085 2086