1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TSO_ENGINE_NUM (1UL) 137 #define TSO_PIDFLT_NUM (128UL) 138 #define TSO_REP_PIDFLT_NUM (16UL) 139 #define TSO_TSIF_NUM (3UL) 140 #define TSO_FILE_IF_NUM (2UL) 141 #define TSO_SVQ_UNIT_SIZE (208UL) 142 143 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 144 145 #define TSO_PID_NULL 0x1FFFUL 146 147 #define TSO_MIU_BUS 4UL 148 #define TSO_PVR_ENG_NUM 1UL 149 //------------------------------------------------------------------------------------------------- 150 // Harware Capability 151 //------------------------------------------------------------------------------------------------- 152 153 #define TSO_IN_MUX_TS0 0x0UL 154 #define TSO_IN_MUX_TS1 0x1UL 155 #define TSO_IN_MUX_TS2 0x2UL 156 #define TSO_IN_MUX_TS3 0x3UL 157 #define TSO_IN_MUX_TS4 0x4UL 158 #define TSO_IN_MUX_TSDEMOD 0x7UL 159 #define TSO_IN_MUX_MEM 0x8UL 160 161 #define TSO_CLKIN_TS0 0x00UL 162 #define TSO_CLKIN_TS1 0x04UL 163 #define TSO_CLKIN_TS2 0x08UL 164 #define TSO_CLKIN_TS3 0x0CUL 165 #define TSO_CLKIN_TS4 0x10UL 166 #define TSO_CLKIN_DMD 0x1CUL 167 168 //--------------- u16ClkOutDivSrcSel ------------- 169 #define TSO_OUT_DIV_DMPLLDIV5 0x0000UL // dmplldiv5 = 844/5 = 172.8MHz 170 #define TSO_OUT_DIV_DMPLLDIV3 0x0001UL // dmplldiv3 = 844/3 = 288MHz 171 172 // Note: 173 // DVB-T dmplldiv5 / 2 (11+1) = 7.2 MHz 174 // DVB-C dmplldiv5 / 2 (11+1) = 7.2 MHz 175 // ATSC dmplldiv5 / 2 (11+1) = 7.2 MHz 176 // ISDB-T dmplldiv_3 / 2 (17+1) = 8 MHz 177 178 //---------------- u16ClkOutSel --------------- 179 #define TSO_OUT_DIV2 0x0000UL // Must also select div src and set div num 180 #define TSO_OUT_62MHz 0x0400UL 181 #define TSO_OUT_54MHz 0x0800UL 182 #define TSO_OUT_PTSO_OUT 0x0C00UL //live-in 183 #define TSO_OUT_PTSO_OUT_DIV8 0x1000UL //live-in 184 #define TSO_OUT_27MHz 0x1400UL 185 #define TSO_OUT_DEMOD_P 0x1C00UL //live-in 186 187 //--------------- u16PreTsoOutSel ------------- 188 #define TSO_PRE_OUT_TS0IN 0x0000UL 189 #define TSO_PRE_OUT_TS1IN 0x0001UL 190 #define TSO_PRE_OUT_TS2IN 0x0002UL 191 #define TSO_PRE_OUT_DEMDOIN 0x0003UL 192 #define TSO_PRE_OUT_TS3IN 0x0004UL 193 #define TSO_PRE_OUT_TS4IN 0x0005UL 194 195 //------------------------------------------------------------------------------------------------- 196 // Type and Structure 197 //------------------------------------------------------------------------------------------------- 198 199 #define REG_PIDFLT_BASE (0x00210000UL << 1UL) // Fit the size of REG32 200 201 #define REG_CTRL_BASE_TSO (0x27400UL) // 0x113A 202 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D 203 #define REG_CTRL_BASE_TSO2 (0xA7200UL) // 0x1539 204 205 206 typedef struct _REG32 207 { 208 volatile MS_U16 L; 209 volatile MS_U16 empty_L; 210 volatile MS_U16 H; 211 volatile MS_U16 empty_H; 212 } REG32; 213 214 typedef struct _REG16 215 { 216 volatile MS_U16 data; 217 volatile MS_U16 _resv; 218 } REG16; 219 220 typedef REG32 REG_PidFlt; 221 222 // PID 223 #define TSO_PIDFLT_PID_MASK 0x00001FFFUL 224 #define TSO_PIDFLT_PID_SHFT 0UL 225 226 // Channel source 227 #define TSO_PIDFLT_IN_SHIFT 13UL 228 #define TSO_PIDFLT_IN_MASK 0x0000E000UL 229 #define TSO_PIDFLT_IN_CH0 0x00002000UL 230 #define TSO_PIDFLT_IN_CH5 0x0000A000UL 231 #define TSO_PIDFLT_IN_CH6 0x0000C000UL 232 233 typedef struct _REG_Pid 234 { // Index(word) CPU(byte) Default 235 REG_PidFlt Flt[TSO_PIDFLT_NUM]; 236 } REG_Pid; 237 238 239 typedef struct _REG_Ctrl_TSO 240 { 241 //---------------------------------------------- 242 // 0xBF802A00 MIPS direct access 243 //---------------------------------------------- 244 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 245 246 REG16 SW_RSTZ; // 0xbf827400 0x00 247 #define TSO_SW_RSTZ_DISABLE 0x0001UL 248 #define TSO_SW_RSTZ_CLK_STAMP 0x0002UL 249 #define TSO_SW_RSTZ_CMDQ1 0x0100UL 250 #define TSO_SW_RSTZ_WB1 0x0200UL 251 #define TSO_SW_RSTZ_WB_DMA1 0x0400UL 252 #define TSO_SW_RSTZ_TS_FIN1 0x0800UL 253 #define TSO_SW_RSTZ_CMDQ 0x1000UL 254 #define TSO_SW_RSTZ_WB 0x2000UL 255 #define TSO_SW_RSTZ_WB_DMA 0x4000UL 256 #define TSO_SW_RSTZ_TS_FIN 0x8000UL 257 #define TSO_SW_RSTZ_ALL 0x00FEUL 258 259 REG16 SW_RSTZ1; // 0xbf827404 0x01 260 #define TSO_SW_RSTZ1_CH_IF1 0x0001UL 261 #define TSO_SW_RSTZ1_CH_IF5 0x0010UL 262 #define TSO_SW_RSTZ1_CH_IF6 0x0020UL 263 #define TSO_SW_RSTZ1_ALL 0x0031UL 264 265 REG32 _xbf827408_740c; // 0xbf827408~0xbf82740c 0x02~03 266 267 REG16 TSO_CH0_IF1_CFG0; // 0xbf827410 0x04 268 #define TSO_PKT_SIZE_CHK_LIVE_MASK 0x00FFUL 269 #define TSO_PIDFLT_PKT_SIZE_MASK 0xFF00UL 270 #define TSO_PIDFLT_PKT_SIZE_SHIFT 8UL 271 272 REG16 TSO_CH0_IF1_CFG1; // 0xbf827414 0x05 //sunc byte 273 REG16 TSO_CH0_IF1_CFG2; // 0xbf827418 0x06 274 #define TSO_CHCFG_P_SEL 0x0001UL 275 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002UL 276 #define TSO_CHCFG_TS_SIN_C0 0x0004UL 277 #define TSO_CHCFG_TS_SIN_C1 0x0008UL 278 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010UL // bypass all packets 279 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020UL // bypass NULL packets 280 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040UL 281 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080UL 282 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100UL 283 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200UL 284 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400UL 285 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800UL 286 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000UL 287 #define TSO_CHCFG_TRC_CLK_CLR 0x2000UL 288 REG16 TSO_CH0_IF1_CFG3; // 0xbf82741c 0x07 289 290 REG16 _xbf827470_747c[12]; // 0xbf827420~0xbf82744c 0x08~13 291 292 REG16 TSO_CH0_IF5_CFG0; // 0xbf827450 0x14 293 REG16 TSO_CH0_IF5_CFG1; // 0xbf827454 0x15 294 REG16 TSO_CH0_IF5_CFG2; // 0xbf827458 0x16 295 REG16 TSO_CH0_IF5_CFG3; // 0xbf82745c 0x17 296 297 REG16 TSO_CH0_IF6_CFG0; // 0xbf827460 0x18 298 REG16 TSO_CH0_IF6_CFG1; // 0xbf827464 0x19 299 REG16 TSO_CH0_IF6_CFG2; // 0xbf827468 0x1a 300 REG16 TSO_CH0_IF6_CFG3; // 0xbf82746c 0x1b 301 302 REG16 TSO_CFG0; // 0xbf827470 0x1c 303 #define TSO_CFG0_S2P0_SHIFT 0UL 304 #define TSO_CFG0_S2P1_SHIFT 1UL 305 #define TSO_CFG0_S2P_CFG_MASK 0x001FUL 306 #define TSO_CFG0_S2P_EN 0x0001UL 307 #define TSO_CFG0_S2P_TS_SIN_C0 0x0002UL 308 #define TSO_CFG0_S2P_TS_SIN_C1 0x0004UL 309 #define TSO_CFG0_S2P_TS_3WIRE_MOD 0x0008UL 310 #define TSO_CFG0_S2P_BYPASS 0x0010UL 311 312 REG16 TSO_CFG1; // 0xbf827474 0x1d 313 #define TSO_CFG1_TSO_OUT_EN 0x0001UL 314 #define TSO_CFG1_TSO_TSIF1_EN 0x0002UL 315 #define TSO_CFG1_TSO_TSIF5_EN 0x0020UL 316 #define TSO_CFG1_TSO_TSIF6_EN 0x0040UL 317 #define TSO_CFG1_CLK_TRC_SEL_MASK 0x0E00UL 318 #define TSO_CFG1_PKT_LOCK_CLR 0x2000UL 319 #define TSO_CFG1_NULL_EN 0x4000UL 320 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL 321 322 REG16 TSO_CFG2; // 0xbf827478 0x1e 323 #define TSO_CFG2_VALID_BYTECNT_MASK 0x00FFUL 324 #define TSO_CFG2_INVALID_BYTECNT_MASK 0xFF00UL 325 #define TSO_CFG2_VALID_BYTECNT_SHIFT 0UL 326 #define TSO_CFG2_INVALID_BYTECNT_SHIFT 8UL 327 328 REG16 TSO_CFG3; // 0xbf82747c 0x1f //opif_pkt_size 329 330 REG32 REP_PidFlt[16]; // 0xbf827480~0xbf8274F8 0x20~0x3e 331 #define REP_PIDFLT_ORG_PID_MASK 0x00001FFFUL 332 #define REP_PIDFLT_SRC_MASK 0x0000E000UL 333 #define REP_PIDFLT_SRC_SHIFT 13UL 334 #define REP_PIDFLT_SRC_CH1 0x00002000UL 335 #define REP_PIDFLT_SRC_CH5 0x0000A000UL 336 #define REP_PIDFLT_SRC_CH6 0x0000C000UL 337 #define REP_PIDFLT_NEW_PID_MASK 0x01FFF000UL 338 #define REP_PIDFLT_NEW_PID_SHIFT 16UL 339 #define REP_PIDFLT_REPLACE_EN 0x80000000UL 340 341 REG16 TSO_CLR_BYTE_CNT; // 0xbf827500 0x40 342 #define TSO_CLR_BYTE_CNT_1 0x0000UL 343 #define TSO_CLR_BYTE_CNT_5 0x0004UL 344 #define TSO_CLR_BYTE_CNT_6 0x0005UL 345 346 REG32 TSO_SYSTIMESTAMP; // 0xbf827504~0xbf827508 0x41~42 347 348 REG16 TSO_CFG4; // 0xbf82750c 0x43 349 #define TSO_CFG4_LOCK_RET_SYS_TIMESTAMP 0x0001UL 350 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002UL 351 #define TSO_CFG4_SET_SYS_TIMESTAMP 0x0004UL 352 #define TSO_CFG4_SET_TIMESTAMP_BASE_MASK 0x0008UL 353 #define TSO_CFG4_SET_TIMESTAMP_90K 0x0000UL 354 #define TSO_CFG4_SET_TIMESTAMP_27M 0x0008UL 355 #define TSO_CFG4_PIDTABLE_SRAM_SD_EN 0x0010UL 356 #define TSO_TIMESTAMP_RING_BACK 0x0020UL 357 #define TSO_LPCR_RING_BACK 0x0040UL 358 #define TSO_INIT_STAMP_RSTART 0x0100UL 359 #define TSO_CFG4_NULL_PKT_ID_MASK 0xF000UL 360 361 REG16 TSO_CFG5; // 0xbf82750c 0x44 362 #define TSO_CFG5_WIRE_MODE_EN_1 0x0001UL 363 #define TSO_CFG5_WIRE_MODE_EN_5 0x0010UL 364 #define TSO_CFG5_WIRE_MODE_EN_6 0x0020UL 365 #define TSO_CFG5_DIS_MIU_RQ 0x0400UL 366 367 REG32 TSO_INDR_ADDR; // 0xbf82750c~0xbf827510 0x45~0x46 368 REG32 TSO_INDR_WDATA; // 0xbf827514~0xbf827518 0x47~0x48 369 REG16 TSO_INDR_RDATA; // 0xbf82751c 0x49 370 REG16 TSO_INDR_CTRL ; // 0xbf827520 0x4a 371 #define TSO_INDIR_W_ENABLE 0x0001UL 372 #define TSO_INDIR_R_ENABLE 0x0002UL 373 374 REG16 TSO_STATUS; // 0xbf827524 0x4b 375 376 REG16 TSO_FI_TIMER[2]; // 0xbf827528~0xbf82752c 0x4c~0x4d 377 378 REG16 TSO_STATUS1; // 0xbf827530 0x4e 379 #define TSO_PIDFLT_OVF_EVER_TSIF0 0x0001UL 380 #define TSO_PIDFLT_OVF_EVER_TSIF5 0x0010UL 381 #define TSO_PIDFLT_OVF_EVER_TSIF6 0x0020UL 382 383 REG16 _xbf827534_7568[12]; // 0xbf827534~0xbf827568 0x4f~0x5a 384 385 REG16 TSO_TRACE_HIGH; // 0xbf82756c 0x5b 386 REG16 TSO_TRACE_LOW; // 0xbf827570 0x5c 387 REG16 TSO_TRACE_1t; // 0xbf827574 0x5d 388 389 REG16 TSO_BLOCK_SIZE_DB; // 0xbf827578 0x5e 390 REG16 TSO_BLOCK_OPT_DB; // 0xbf82757c 0x5f 391 392 REG32 TSO_Filein_raddr; // 0xbf827580~0xbf827584 0x60-0x61 393 REG32 TSO_Filein_rNum; // 0xbf827588~0xbf82758c 0x62-0x63 394 REG16 TSO_Filein_Ctrl; // 0xbf827590 0x64 395 #define TSO_FILEIN_CTRL_MASK 0x0003UL 396 #define TSO_FILEIN_RSTART 0x0001UL 397 #define TSO_FILEIN_ABORT 0x0002UL 398 #define TSO_FILEIN_MOBF_IDX_MASK 0x1F00UL 399 #define TSO_FILEIN_MOBF_IDX_SHIFT 8UL 400 #define TSO_FILEIN_RIU_TSO_NS 0x2000UL 401 402 REG32 TSO_Filein_raddr1; // 0xbf827594~0xbf827598 0x65-0x66 403 REG32 TSO_Filein_rNum1; // 0xbf82759c~0xbf8275a0 0x67-0x68 404 REG16 TSO_Filein_Ctrl1; // 0xbf8275a4 0x69 405 406 REG16 TSO_PKT_CNT_SEL; // 0xbf8275a8 0x6a 407 #define TSO_PKT_CNT_SEL_MASK 0x000FUL 408 #define TSO_PKT_CNT_LOCKED_CNT_MASK 0x00F0UL 409 #define TSO_PKT_CNT_DBG_MASK 0xFF00UL 410 411 REG16 TSO_PKT_CHKSIZE_FI; // 0xbf8275ac 0x6b 412 #define TSO_PKT_CHKSIZE_FI_MASK 0x00FFUL 413 #define TSO_PKT_CHKSIZE_FI1_MASK 0xFF00UL 414 415 REG32 TSO_LPCR2[2]; // 0xbf8275b0~ 0xbf8275bc 0x6c~0x6f 416 REG32 TSO_TIMESTAMP[2]; // 0xbf8275c0~ 0xbf8275cc 0x70~0x73 417 REG32 TSO_TSO2MI_RADDR[2]; // 0xbf8275d0~ 0xbf8275dc 0x74~0x77 418 419 REG16 TSO_CMDQ_STATUS; // 0xbf8275e0 0x78 420 #define TSO_CMDQ_SIZE 8UL 421 #define TSO_CMDQ_STS_WCNT_MASK 0x000FUL 422 #define TSO_CMDQ_STS_WLEVEL_MASK 0x0030UL 423 #define TSO_CMDQ_STS_FIFO_FULL 0x0040UL 424 #define TSO_CMDQ_STS_FIFO_EMPTY 0x0080UL 425 #define TSO_CMDQ_STS1_SHIFT 8UL 426 427 REG16 TSO_FILE_CFG[2]; // 0xbf8275e4~0xbf8275e8 0x79~0x7a 428 #define TSO_FICFG_TSO2MI_RPRI 0x0001UL 429 #define TSO_FICFG_MEM_TSDATA_ENDIAN 0x0002UL 430 #define TSO_FICFG_MEM_TS_W_ORDER 0x0004UL 431 #define TSO_FICFG_LPCR2_WLD 0x0008UL 432 #define TSO_FICFG_LPCR2_LD 0x0010UL 433 #define TSO_FICFG_DIS_MIU_RQ 0x0020UL 434 #define TSO_FICFG_RADDR_READ 0x0040UL 435 #define TSO_FICFG_TS_DATAPORT_SEL 0x0080UL 436 #define TSO_FICFG_TSO_FILEIN 0x0100UL 437 #define TSO_FICFG_TIMER_ENABLE 0x0200UL 438 #define TSO_FICFG_PKT192_BLK_DISABLE 0x0400UL 439 #define TSO_FICFG_PKT192_ENABLE 0x0800UL 440 #define TSO_FICFG_FILE_SEGMENT 0x1000UL 441 #define TSO_FICFG_CLK_TIMESTAMP_SEL_MASK 0x2000UL 442 #define TSO_FICFG_CLK_TIMESTAMP_27M 0x2000UL 443 #define TSO_FICFG_CLK_TIMESTAMP_90K 0x0000UL 444 #define TSO_FICFG_INIT_TIMESTAMP 0x4000UL 445 446 REG16 TSO_Interrupt; // 0xbf8275ec 0x7b 447 #define TSO_INT_ENABLE_MASK 0x00FFUL 448 #define TSO_INT_STATUS_MASK 0xFF00UL 449 #define TSO_INT_DMA_DONE 0x0001UL 450 #define TSO_INT_DMA_DONE1 0x0002UL 451 #define TSO_INT_TRCCLK_UPDATE 0x0004UL 452 453 REG16 TSO_Interrupt1; // 0xbf8275f0 0x7c 454 #define TSO_INT1_ENABLE_MASK 0x00FFUL 455 #define TSO_INT1_STATUS_MASK 0xFF00UL 456 #define TSO_INT1_PIDFLT1_OVF 0x0001UL 457 #define TSO_INT1_PIDFLT5_OVF 0x0010UL 458 #define TSO_INT1_PIDFLT6_OVF 0x0020UL 459 460 REG32 TSO_DBG; // 0xbf8275f4~0xbf8275f8 0x7d~0x7e 461 REG16 TSO_DBG_SEL; // 0xbf8275fc 0x7f 462 463 } REG_Ctrl_TSO; 464 465 typedef struct _REG_Ctrl_TSO1 466 { 467 //---------------------------------------------- 468 // 0xBF802A00 MIPS direct access 469 //---------------------------------------------- 470 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 471 472 REG16 TSO_PRE_HEADER1_CFG0; // 0xbf847A00 0x00 473 #define TSO_PRE_HD1_CFG0_LOCAL_STRID_MASK 0x00FFUL 474 475 REG16 TSO_PRE_HEADER1_CFG1; // 0xbf847A04 0x01 476 REG16 TSO_PRE_HEADER1_CFG2; // 0xbf847A08 0x02 477 REG16 TSO_PRE_HEADER1_CFG3; // 0xbf847A0c 0x03 478 479 REG16 _xbf827a10_7a3c[12]; // 0xbf847A10~0xbf847A3c 0x04~0x0f 480 481 REG16 TSO_PRE_HEADER5_CFG0; // 0xbf847A40 0x10 482 REG16 TSO_PRE_HEADER5_CFG1; // 0xbf847A44 0x11 483 REG16 TSO_PRE_HEADER5_CFG2; // 0xbf847A48 0x12 484 REG16 TSO_PRE_HEADER5_CFG3; // 0xbf847A4c 0x13 485 486 REG16 TSO_PRE_HEADER6_CFG0; // 0xbf847A40 0x14 487 REG16 TSO_PRE_HEADER6_CFG1; // 0xbf847A44 0x15 488 REG16 TSO_PRE_HEADER6_CFG2; // 0xbf847A48 0x16 489 REG16 TSO_PRE_HEADER6_CFG3; // 0xbf847A4c 0x17 490 491 REG32 TSO_SVQ1_BASE; // 0xbf847A50~0xbf847A54 0x18~0x19 492 REG16 TSO_SVQ1_SIZE; // 0xbf847A58 0x1a //unit:200byte/pkt 493 REG16 TSO_SVQ1_TX_CFG; // 0xbf847A5c 0x1b 494 #define TSO_SVQ_TX_CFG_WR_THRESHOLD_MASK 0x000FUL 495 #define TSO_SVQ_TX_CFG_PRI_THRESHOLD_MASK 0x00F0UL 496 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK 0x0F00UL 497 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT 8UL 498 #define TSO_SVQ_TX_CFG_TX_RESET 0x1000UL 499 #define TSO_SVQ_TX_CFG_OVF_INT_EN 0x2000UL 500 #define TSO_SVQ_TX_CFG_OVF_CLR 0x4000UL 501 #define TSO_SVQ_TX_CFG_SVQ_EN 0x8000UL 502 503 REG16 _xbf827a60_7a9c[12]; // 0xbf847A60~0xbf847A9c 0x1c~0x27 504 505 REG32 TSO_SVQ5_BASE; // 0xbf847Aa0~0xbf847Aa4 0x28~0x29 506 REG16 TSO_SVQ5_SIZE; // 0xbf847Aa8 0x2a //unit:200byte/pkt 507 REG16 TSO_SVQ5_TX_CFG; // 0xbf847Aac 0x2b 508 509 REG32 TSO_SVQ6_BASE; // 0xbf847Ab0~0xbf847Ab4 0x2c~0x2d 510 REG16 TSO_SVQ6_SIZE; // 0xbf847Ab8 0x2e //unit:200byte/pkt 511 REG16 TSO_SVQ6_TX_CFG; // 0xbf847Abc 0x2f 512 513 REG16 TSO_SVQ_RX_CFG; // 0xbf847Ac0 0x30 514 #define TSO_SVQ_RX_CFG_MODE_MASK 0x0003UL 515 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000UL 516 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001UL 517 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002UL 518 #define TSO_SVQ_RX_CFG_MODE_DONGLE 0x0003UL //dongle mode 519 #define TSO_SVQ_RX_CFG_RD_THRESHOLD_MASK 0x001CUL 520 #define TSO_SVQ_RX_CFG_ARBMODE_MASK 0x0060UL 521 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000UL 522 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0020UL 523 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0040UL 524 #define TSO_SVQ_RX_CFG_DRAM_SD_ENABLE 0x0080UL 525 #define TSO_SVQ_RX_CFG_SVQ_FORCE_RESET 0x0100UL 526 #define TSO_SVQ_RX_CFG_SVQ_MIU_NS 0x0200UL 527 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK 0x7C00UL 528 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT 10UL 529 #define TSO_SVQ_RX_CFG_SVQ_DYN_PRI 0x8000UL 530 531 REG16 TSO_SVQ_RX_PRI[3]; // 0xbf847Ac4~0xbf847Acc 0x31~0x33 532 #define TSO_SVQ_RX_NUM 6UL 533 #define TSO_SVQ_RX_PRI_MASK 0xFFUL 534 #define TSO_SVQ_RX_PRI_SHIFT 8UL 535 536 REG32 TSO_SVQ_STATUS; // 0xbf847Ad0~0xbf847Ad4 0x34~0x35 537 #define TSO_SVQ_STS_MASK 0x000FUL 538 #define TSO_SVQ1_STS_SHIFT 0UL 539 #define TSO_SVQ5_STS_SHIFT 16UL 540 #define TSO_SVQ6_STS_SHIFT 20UL 541 #define TSO_SVQ_STS_EVER_FULL 0x0001UL 542 #define TSO_SVQ_STS_EVER_OVF 0x0002UL 543 #define TSO_SVQ_STS_EMPTY 0x0004UL 544 #define TSO_SVQ_STS_BUSY 0x0008UL 545 546 REG32 TSO_SVQ_STATUS2; // 0xbf847Ad8~0xbf847Adc 0x36~0x37 547 #define TSO_SVQ_STS2_MASK 0x000FUL 548 #define TSO_SVQ1_STS2_SHIFT 0UL 549 #define TSO_SVQ5_STS2_SHIFT 16UL 550 #define TSO_SVQ6_STS2_SHIFT 20UL 551 #define TSO_SVQ_STS2_TXFIFO_WLEVEL_MASK 0x000CUL 552 #define TSO_SVQ_STS2_TXFIFO_FULL 0x0002UL 553 #define TSO_SVQ_STS2_TXFIFO_EMPTY 0x0001UL 554 555 REG32 TSO_DELTA; // 0xbf847Ae0~0xbf847Ae4 0x38~0x39 556 557 REG16 TSO_DELTA_CFG; // 0xbf847Ae8 0x3a 558 #define TSO_DELTA_CFG_SEL_CH_MASK 0x0007UL 559 #define TSO_DELTA_CFG_DELTA_CLR 0x0008UL 560 #define TSO_DELTA_CFG_MAX_ID_MASK 0x0700UL 561 #define TSO_DELTA_CFG_MAX_ID_SHIFT 8UL 562 563 REG32 TSO_DONGLE_TSIF1; 564 REG32 TSO_DONGLE_TSIF2; 565 REG32 TSO_DONGLE_TSIF3; 566 REG32 TSO_DONGLE_TSIF4; 567 REG32 TSO_DONGLE_TSIF5; 568 REG32 TSO_DONGLE_TSIF6; 569 #define TSO_DONGLE_PROTOCAL_ID_MASK 0x000000FF 570 #define TSO_DONGLE_PROTOCAL_ID_SHIFT 0 571 #define TSO_DONGLE_RFU0_MASK 0x0000FF00 572 #define TSO_DONGLE_RFU1_MASK 0x00FF0000 573 #define TSO_DONGLE_STREAM_ID_MASK 0xFF000000 574 #define TSO_DONGLE_STREAM_ID_SHIFT 24 575 576 577 REG16 TSO_MIU_SEL; 578 #define TSO_SVQ_TX1 0x00000001 579 #define TSO_SVQ_TX2 0x00000002 580 #define TSO_PVR 0x00000004 581 #define TSO_SVQ_TX4 0x00000008 582 #define TSO_SVQ_TX5 0x00000010 583 #define TSO_SVQ_TX6 0x00000020 584 #define TSO_SVQ_RX 0x00000040 585 #define TSO_FI_CH5 0x00000080 586 #define TSO_FI_CH6 0x00000100 587 } REG_Ctrl_TSO1; 588 589 typedef struct _REG_Ctrl_TSO2 590 { 591 REG16 TSO_CFG_00; // 0x00 592 #define TSO_PVR_PINGPONG 0x0001UL 593 #define TSO_PVR_ENABLE 0x0002UL 594 #define TSO_PVR_RST_WADR 0x0004UL 595 #define TSO_PVR_PAUSE 0x0008UL 596 #define TSO_RECORD192_EN 0x0010UL 597 598 #define TSO_BURST_LEN_MASK 0x0060UL // 00,01: burst length = 4; 10,11: burst length = 1 599 #define TSO_BURST_LEN_4 0x0020UL 600 601 #define TSO_PVR_LPCR1_WLD 0x0080UL // Set 1 to load LPCR1 value 602 #define TSP_PVR_ALIGN_EN 0x0100UL 603 #define TSO_PVR_ENDIAN_BIG 0x0200UL // 1: record TS to MIU with big endian, 0: record TS to MIU with little endian 604 #define TSO_PVRBUF_BYTEORDER_BIG 0x0400UL // Byte order of 8-byte recoding buffer to MIU. 605 #define TSO_PVR_INVERT 0x0800UL // Set 1 to enable data payload invert for PVR record 606 #define TSO_PVR_BLOCK_DIS 0x1000UL 607 #define TSO_PVR_PID_BYPASS 0x2000UL // Set 1 to bypass PID in record 608 #define TSO_PVR_REC_ALL_EN 0x4000UL 609 #define TSO_PVR_LPCR1_RLD 0x8000UL // Set 1 to read LPCR1 value (Default: 1) 610 611 REG32 TSO_PVR_Head1; // 0x01 612 REG32 TSO_PVR_Mid1; // 0x03, PVR1 mid address 613 REG32 TSO_PVR_Tail; // 0x05 614 615 REG32 TSO_PVR_Head2; // 0x07 616 REG32 TSO_PVR_Mid2; // 0x09, PVR1 mid address 617 REG32 TSO_PVR_Tail2; // 0x0B 618 619 REG16 TSO_CFG_0D; // 0x0D 620 #define TSP_FLUSH_EN 0x0002UL //PVR1 dma flush 621 #define TSO_CH_BW_WP_LD 0x0004UL 622 #define TSO_CLR_PVR_OVERFLOW 0x0008UL 623 #define TSO_PVR_DMA_FLUSH_EN 0x0010UL 624 #define TSO_PVR_FORCE_SYNC 0x0020UL 625 #define TSO_PVR_DIS_REC_AT_SYNC 0x0040UL 626 #define TSO_MIU_HIGH_PRIO 0x0080UL 627 #define TSO_RECORD_ALL_OLD 0x0100UL 628 #define TSO_PVR_WPTR_NEXT 0x0200UL 629 #define TSO_PVR_DAMW_PROTECT_EN 0x0400UL 630 #define TSO_CLR_NO_HIT_INT 0x0800UL // set 1 clear all dma write function not hit interrupt 631 632 REG32 DMAW_LBND0; // 0x0E 633 REG32 DMAW_UBND0; // 0x10 634 635 REG32 PVR1_LPcr1; // 0x12 636 REG16 TSO_CFG_14; // 0x14 637 #define TSO_PVR_SRC_MASK 0x0003UL 638 #define TSO_PVR_SRC_SVQ 0x0001UL 639 #define TSO_PVR_SRC_MMT 0x0002UL 640 #define TSO_PVR_CLK_STAMP_27_EN 0x0004UL 641 642 REG16 TSO_RESERVE_15_1F[11]; 643 REG16 TSO_CFG_20; // 0x20 644 #define TSO_MMT_TS_SIN_C0 0x0001UL // Reset bit count when data valid signal of TS interface is low. 645 #define TSO_MMT_TS_SIN_C1 0x0002UL // Reset bit count on the rising sync signal of TS interface. 646 #define TSO_FORCE_SYNCBYTE 0x0004UL 647 #define TSO_MMT_PARL 0x0008UL 648 #define TSO_MMT_EXTSYNC 0x0010UL 649 #define TSO_ISYNC_PATCH_EN 0x0020UL 650 #define TSO_SERIAL_EXT_SYNC_LT 0x0040UL // Set 1 to detect serial-in sync without 8-cycle mode 651 #define TSO_TSIF_OVF_CLR 0x0080UL 652 #define TSO_PACKET_CHK_SIZE_MASK 0xFF00UL 653 #define TSO_PACKET_CHK_SIZE_SHFT 8UL 654 655 REG16 TSO_CFG_21; // 0x21 656 #define TSO_MMT_EN 0x0001UL 657 #define TSO_3WIRE_EN 0x0002UL 658 #define TSO_MMT_SW_RST 0x0004UL 659 #define TSO_LOCK_PKT_CNT_LOAD 0x0008UL 660 #define TSO_LOCK_PKT_CNT_CLR 0x0010UL 661 REG32 TSO_PVR_DMAW_WADDR_ERR; // 0x22 662 REG16 TSO_PVR_MOBF; // 0x24 663 664 REG32 TSO_PVR_WPTR; // 0x25 665 REG16 TSO_CFG_27; // 0x27 666 #define TSO_TSIF_OVF 0x0001UL 667 #define TSO_PVR_FLUSH_STATUS 0x0002UL 668 #define TSO_PVR_FIFO_STATUS 0x0004UL 669 670 } REG_Ctrl_TSO2; 671 672 #endif // _TSO_REG_H_ 673 674