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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //////////////////////////////////////////////////////////////////////////////////////////////////// 78 // file halFQ.h 79 // @brief FQ HAL 80 // @author MStar Semiconductor,Inc. 81 //////////////////////////////////////////////////////////////////////////////////////////////////// 82 #ifndef __HAL_FQ_H__ 83 #define __HAL_FQ_H__ 84 85 //-------------------------------------------------------------------------------------------------- 86 // Driver Compiler Option 87 //-------------------------------------------------------------------------------------------------- 88 89 //-------------------------------------------------------------------------------------------------- 90 // FQ Hardware Abstraction Layer 91 //-------------------------------------------------------------------------------------------------- 92 93 // FQ define 94 #define FQ_NUM 1UL 95 96 // HW characteristic 97 #define MIU_FQ(_addr_) ((_addr_)>>4UL) 98 99 //-------------------------------------------------------------------------------------------------- 100 // Macro of bit operations 101 //-------------------------------------------------------------------------------------------------- 102 #define _AND_(flag, bit) ((flag) & (bit) ) 103 #define _SET_(flag, bit) ((flag) | (bit) ) 104 #define _CLR_(flag, bit) ((flag) & (~(bit))) 105 106 //Skip rush path define 107 #define HAL_FQ_SKIP_RUSH_DATA_PATH_NON 0x00000000UL 108 #define HAL_FQ_SKIP_APES_RUSH_DATA 0x00000008UL 109 #define HAL_FQ_SKIP_APES_B_RUSH_DATA 0x00000010UL 110 #define HAL_FQ_SKIP_VPES_RUSH_DATA 0x00000020UL 111 #define HAL_FQ_SKIP_SEC_RUSH_DATA 0x00000040UL 112 #define HAL_FQ_SKIP_ADP_RUSH_DATA 0x00000080UL 113 #define HAL_FQ_SKIP_PCR_RUSH_DATA 0x00000100UL 114 #define HAL_FQ_SKIP_RASP_RUSH_DATA 0x00000200UL 115 #define HAL_FQ_SKIP_PVR1_RUSH_DATA HAL_FQ_SKIP_RASP_RUSH_DATA 116 #define HAL_FQ_SKIP_PCR1_RUSH_DATA 0x00001000UL 117 #define HAL_FQ_SKIP_PVR3_RUSH_DATA HAL_FQ_SKIP_PCR1_RUSH_DATA 118 #define HAL_FQ_SKIP_CFG1_MASK 0x80000000UL 119 #define HAL_FQ_SKIP_APES_C_RUSH_DATA 0x80000008UL 120 #define HAL_FQ_SKIP_APES_D_RUSH_DATA 0x80000010UL 121 #define HAL_FQ_SKIP_V3DPES_RUSH_DATA 0x80000020UL 122 #define HAL_FQ_SKIP_PVR2_RUSH_DATA 0x80000200UL 123 124 //////////////////////////////////////////////// 125 // HAL API 126 //////////////////////////////////////////////// 127 MS_BOOL HAL_FQ_SetBank(MS_VIRT virtBankAddr); 128 void HAL_FQ_PVR_SetBuf(MS_U32 u32FQEng, MS_PHY phyStartAddr, MS_U32 u32BufSize); 129 void HAL_FQ_PVR_SetRushAddr(MS_U32 u32FQEng, MS_PHY phyRushAddr); 130 void HAL_FQ_PVR_Start(MS_U32 u32FQEng); 131 void HAL_FQ_PVR_Stop(MS_U32 u32FQEng); 132 void HAL_FQ_Rush_Enable(MS_U32 u32FQEng); 133 void HAL_FQ_Bypass(MS_U32 u32FQEng, MS_U8 u8Bypass); 134 void HAL_FQ_SWReset(MS_U32 u32FQEng, MS_U8 u8Reset); 135 void HAL_FQ_AddrMode(MS_U32 u32FQEng, MS_U8 u8AddrMode); 136 void HAL_FQ_SkipRushData(MS_U32 u32FQEng, MS_U32 u32SkipPath); 137 MS_U32 HAL_FQ_GetPVRTimeStamp(MS_U32 u32FQEng); 138 void HAL_FQ_SetPVRTimeStamp(MS_U32 u32FQEng , MS_U32 u32Stamp); 139 MS_U32 HAL_FQ_GetRead(MS_U32 u32FQEng); 140 MS_U32 HAL_FQ_GetWrite(MS_U32 u32FQEng); 141 142 #ifdef MSOS_TYPE_LINUX_KERNEL 143 MS_BOOL HAL_FQ_SaveRegs(void); 144 MS_BOOL HAL_FQ_RestoreRegs(void); 145 #endif 146 147 148 #endif // #ifndef __HAL_FQ_H__ 149