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76 //******************************************************************************
77 ////////////////////////////////////////////////////////////////////////////////////////////////////
78 // file halFQ.c
79 // @brief FQ HAL
80 // @author MStar Semiconductor,Inc.
81 ////////////////////////////////////////////////////////////////////////////////////////////////////
82 #include "MsCommon.h"
83 #include "regFQ.h"
84 #include "halFQ.h"
85 #include "halCHIP.h"
86
87 //--------------------------------------------------------------------------------------------------
88 // Driver Compiler Option
89 //--------------------------------------------------------------------------------------------------
90
91 //--------------------------------------------------------------------------------------------------
92 // TSP Hardware Abstraction Layer
93 //--------------------------------------------------------------------------------------------------
94 static MS_VIRT _virtRegBase = 0;
95 static MS_U32 _dramRASPBase = 0;
96 #define _RASP_DRAM_BASE_128MB_256MB (0x08000000)
97 #define _RASP_DRAM_BASE_0MB_128MB (0x0)
98 #define _RASP_BASE_SET(addr) ((addr)|(_dramRASPBase))
99 #define _RASP_BASE_CLR(addr) ((addr)&(~_dramRASPBase))
100
101 REG_FIQ* _REGFIQ = NULL;
102
103 static MS_PHY _phyFQMiuOffset[FQ_NUM] = {[0 ... (FQ_NUM-1)] = 0UL};
104
105 #ifdef MSOS_TYPE_LINUX_KERNEL
106 static MS_U16 _u16FQRegArray[1][0x11];
107 #endif
108
109 // Some register has write order, for example, writing PCR_L will disable PCR counter
110 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
111 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \
112 (reg)->H = ((value) >> 16);}
113 #define FQ16_W(reg, value); {(reg)->data = ((value) & 0x0000FFFF);}
114 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<<2UL))))
115
116
117 //--------------------------------------------------------------------------------------------------
118 // Forward declaration
119 //--------------------------------------------------------------------------------------------------
120
121 //--------------------------------------------------------------------------------------------------
122 // Implementation
123 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32_FQ * reg)124 static MS_U32 _HAL_REG32_R(REG32_FQ *reg)
125 {
126 MS_U32 value = 0;
127 value = (reg)->H << 16;
128 value |= (reg)->L;
129 return value;
130 }
131
_HAL_REG16_R(REG16_FQ * reg)132 static MS_U16 _HAL_REG16_R(REG16_FQ *reg)
133 {
134 MS_U16 value;
135 value = (reg)->data;
136 return value;
137 }
138
_HAL_FQ_MIU_OFFSET(MS_PHY Phyaddr)139 static MS_PHY _HAL_FQ_MIU_OFFSET(MS_PHY Phyaddr)
140 {
141 #ifdef HAL_MIU2_BASE
142 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
143 return ((MS_PHY)HAL_MIU2_BASE & 0xFFFFFFFFUL);
144 else
145 #endif //HAL_MIU2_BASE
146 #ifdef HAL_MIU1_BASE
147 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
148 return ((MS_PHY)HAL_MIU1_BASE & 0xFFFFFFFFUL);
149 else
150 #endif //HAL_MIU1_BUS_BASE
151 return ((MS_PHY)HAL_MIU0_BASE & 0xFFFFFFFFUL);
152 }
153
154 #define MIU_BUS 4
155
156 //--------------------------------------------------------------------------------------------------
157 // For MISC part
158 //--------------------------------------------------------------------------------------------------
HAL_FQ_SetBank(MS_VIRT virtBankAddr)159 MS_BOOL HAL_FQ_SetBank(MS_VIRT virtBankAddr)
160 {
161 _virtRegBase = virtBankAddr;
162 _REGFIQ = (REG_FIQ*)(_virtRegBase + FQ_REG_CTRL_BASE);
163
164 return TRUE;
165 }
166
167 //for K1 ECO U04 switch RASP dram base from 0-128MB to 128-256MB
168 //This function will be called by HAL_TSP_HWPatch() in halTSP.c of K1
HAL_FQ_SetDramBase(MS_U32 dramBase)169 MS_BOOL HAL_FQ_SetDramBase(MS_U32 dramBase)
170 {
171 if(dramBase == _RASP_DRAM_BASE_0MB_128MB)
172 {
173 _dramRASPBase = dramBase;
174 return TRUE;
175 }
176 if(dramBase == _RASP_DRAM_BASE_128MB_256MB)
177 {
178 _dramRASPBase = dramBase;
179 return TRUE;
180 }
181 else
182 {
183 _dramRASPBase = 0;
184 return FALSE;
185 }
186 }
187
HAL_FQ_PVR_SetBuf(MS_U32 u32FQEng,MS_PHY phyStartAddr,MS_U32 u32BufSize)188 void HAL_FQ_PVR_SetBuf(MS_U32 u32FQEng, MS_PHY phyStartAddr, MS_U32 u32BufSize)
189 {
190 MS_PHY phyEndAddr = phyStartAddr + u32BufSize;
191
192 _phyFQMiuOffset[u32FQEng] = _HAL_FQ_MIU_OFFSET(phyStartAddr);
193
194 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK);
195 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK);
196 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK);
197 }
198
HAL_FQ_PVR_SetRushAddr(MS_U32 u32FQEng,MS_PHY phyRushAddr)199 void HAL_FQ_PVR_SetRushAddr(MS_U32 u32FQEng, MS_PHY phyRushAddr)
200 {
201 _phyFQMiuOffset[u32FQEng] = _HAL_FQ_MIU_OFFSET(phyRushAddr);
202 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & FIQ_STR2MI2_ADDR_MASK);
203 }
204
_HAL_FQ_PVR_Reset(MS_U32 u32FQEng,MS_BOOL bReset)205 void _HAL_FQ_PVR_Reset(MS_U32 u32FQEng, MS_BOOL bReset)
206 {
207 if(bReset)
208 {
209 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_RESET_WR_PTR));
210 }
211 else
212 {
213 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_RESET_WR_PTR));
214 }
215 }
216
HAL_FQ_PVR_Start(MS_U32 u32FQEng)217 void HAL_FQ_PVR_Start(MS_U32 u32FQEng)
218 {
219 //reset write address
220 _HAL_FQ_PVR_Reset(u32FQEng, TRUE);
221 _HAL_FQ_PVR_Reset(u32FQEng, FALSE);
222
223 //enable string to miu
224 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_PVR_ENABLE));
225 }
226
HAL_FQ_PVR_Stop(MS_U32 u32FQEng)227 void HAL_FQ_PVR_Stop(MS_U32 u32FQEng)
228 {
229 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_PVR_ENABLE));
230 }
231
HAL_FQ_Rush_Enable(MS_U32 u32FQEng)232 void HAL_FQ_Rush_Enable(MS_U32 u32FQEng)
233 {
234 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_RUSH_ENABLE));
235 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_RUSH_ENABLE));
236 }
237
HAL_FQ_Bypass(MS_U32 u32FQEng,MS_U8 u8Bypass)238 void HAL_FQ_Bypass(MS_U32 u32FQEng, MS_U8 u8Bypass)
239 {
240 if(u8Bypass)
241 {
242 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config11), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config11)), FIQ_CFG11_FIQ_BYPASS));
243 }
244 else
245 {
246 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config11), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config11)), FIQ_CFG11_FIQ_BYPASS));
247 }
248 }
249
HAL_FQ_SWReset(MS_U32 u32FQEng,MS_U8 u8Reset)250 void HAL_FQ_SWReset(MS_U32 u32FQEng, MS_U8 u8Reset)
251 {
252 if(u8Reset)
253 {
254 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_SW_RSTZ));
255 }
256 else
257 {
258 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_SW_RSTZ));
259 }
260 }
261
HAL_FQ_AddrMode(MS_U32 u32FQEng,MS_U8 u8AddrMode)262 void HAL_FQ_AddrMode(MS_U32 u32FQEng, MS_U8 u8AddrMode)
263 {
264 if(u8AddrMode)
265 {
266 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE));
267 }
268 else
269 {
270 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_ADDR_MODE));
271 }
272 }
273
HAL_FQ_GetRead(MS_U32 u32FQEng)274 MS_U32 HAL_FQ_GetRead(MS_U32 u32FQEng)
275 {
276 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_LOAD_WR_PTR));
277 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_LOAD_WR_PTR));
278 return _HAL_REG32_R(&(_REGFIQ[u32FQEng].Fiq2mi2_radr_r)) << MIU_BUS;
279 }
280
HAL_FQ_GetWrite(MS_U32 u32FQEng)281 MS_U32 HAL_FQ_GetWrite(MS_U32 u32FQEng)
282 {
283 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_LOAD_WR_PTR));
284 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config0)), FIQ_CFG0_LOAD_WR_PTR));
285 return _HAL_REG32_R(&(_REGFIQ[u32FQEng].str2mi2_wadr_r)) << MIU_BUS;
286 }
287
288 /*
289 MS_U32 HAL_FQ_GetPktAddrOffset(MS_U32 u32FQEng)
290 {
291 return REG32_R(&(_REGFIQ[u32FQEng].pkt_addr_offset)) << MIU_BUS;
292 }
293 */
294
HAL_FQ_SkipRushData(MS_U32 u32FQEng,MS_U32 u32SkipPath)295 void HAL_FQ_SkipRushData(MS_U32 u32FQEng, MS_U32 u32SkipPath)
296 {
297 MS_U16 data = 0;
298
299 if(u32SkipPath & HAL_FQ_SKIP_CFG1_MASK)
300 {
301 data = (MS_U16)(u32SkipPath & ~HAL_FQ_SKIP_CFG1_MASK);
302 FQ16_W(&(_REGFIQ[1].Reg_fiq_config11),
303 (_HAL_REG16_R(&(_REGFIQ[1].Reg_fiq_config11)) & ~FIQ_CFG11_SKIP_RUSH_DATA_PATH1_MASK) | (data & FIQ_CFG11_SKIP_RUSH_DATA_PATH1_MASK));
304 }
305 else
306 {
307 data = (MS_U16)(u32SkipPath);
308 FQ16_W(&(_REGFIQ[0].Reg_fiq_config11),
309 (_HAL_REG16_R(&(_REGFIQ[0].Reg_fiq_config11)) & ~FIQ_CFG11_SKIP_RUSH_DATA_PATH_MASK) | (data & FIQ_CFG11_SKIP_RUSH_DATA_PATH_MASK));
310 }
311
312 }
313
314 #if 0
315 void HAL_FQ_INT_Enable(MS_U32 u32FQEng, MS_U16 u16Mask)
316 {
317 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config16), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
318 }
319
320 void HAL_FQ_INT_Disable(MS_U32 u32FQEng, MS_U16 u16Mask)
321 {
322 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config16), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
323 }
324
325 MS_U16 HAL_FQ_INT_GetHW(MS_U32 u32FQEng)
326 {
327 return _HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)) & FIQ_CFG16_INT_STATUS_MASK;
328 }
329
330 void HAL_FQ_INT_ClrHW(MS_U32 u32FQEng, MS_U16 u16Mask)
331 {
332 FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config16), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_STATUS_MASK));
333 }
334 #endif
335
HAL_FQ_GetPVRTimeStamp(MS_U32 u32FQEng)336 MS_U32 HAL_FQ_GetPVRTimeStamp(MS_U32 u32FQEng)
337 {
338 //not inplemented
339 return 0;
340 }
341
HAL_FQ_SetPVRTimeStamp(MS_U32 u32FQEng,MS_U32 u32Stamp)342 void HAL_FQ_SetPVRTimeStamp(MS_U32 u32FQEng , MS_U32 u32Stamp)
343 {
344 //not inplemented
345 }
346
347 #ifdef MSOS_TYPE_LINUX_KERNEL
348
HAL_FQ_SaveRegs(void)349 MS_BOOL HAL_FQ_SaveRegs(void)
350 {
351 MS_U32 u32ii = 0;
352
353 for(u32ii = 0; u32ii <= 0x10; u32ii++)
354 {
355 _u16FQRegArray[0][u32ii] = FIQ_REG(u32ii);
356 }
357
358 //stop rush data
359 if((_HAL_REG16_R(&(_REGFIQ[0].Reg_fiq_config0)) & FIQ_CFG0_RUSH_ENABLE) == 0)
360 {
361 FQ16_W(&(_REGFIQ[0].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[0].Reg_fiq_config0)), FIQ_CFG0_RUSH_ENABLE));
362 }
363 //stop pvr
364 if(_HAL_REG16_R(&(_REGFIQ[0].Reg_fiq_config0)) & FIQ_CFG0_PVR_ENABLE)
365 {
366 FQ16_W(&(_REGFIQ[0].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[0].Reg_fiq_config0)), FIQ_CFG0_PVR_ENABLE));
367 }
368
369 HAL_FQ_SWReset(0, TRUE);
370
371 return TRUE;
372 }
373
HAL_FQ_RestoreRegs(void)374 MS_BOOL HAL_FQ_RestoreRegs(void)
375 {
376 MS_U32 u32ii = 0;
377
378 HAL_FQ_SWReset(0, FALSE);
379
380 FIQ_REG(0)= (_u16FQRegArray[0][0] | FIQ_CFG0_RUSH_ENABLE) & ~FIQ_CFG0_PVR_ENABLE;
381 for(u32ii = 1; u32ii <= 0x10; u32ii++)
382 {
383 FIQ_REG(u32ii)= _u16FQRegArray[0][u32ii];
384 }
385
386 // clear dirty data
387 _HAL_FQ_PVR_Reset(0, TRUE);
388 _HAL_FQ_PVR_Reset(0, FALSE);
389
390 if(_u16FQRegArray[0][0] & FIQ_CFG0_PVR_ENABLE)
391 {
392 FQ16_W(&(_REGFIQ[0].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[0].Reg_fiq_config0)), FIQ_CFG0_PVR_ENABLE));
393 }
394
395 return TRUE;
396 }
397
398 #endif //MSOS_TYPE_LINUX_KERNEL
399
400