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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 /////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file drvTSP2.h 98 /// @brief Transport Stream Processer (TSP) Driver Interface 99 /// @author MStar Semiconductor,Inc. 100 /// @attention 101 /// All TSP DDI are not allowed to use in any interrupt context other than TSP ISR and Callback 102 /////////////////////////////////////////////////////////////////////////////////////////////////// 103 104 #ifndef __DRV_TSP2_H__ 105 #define __DRV_TSP2_H__ 106 107 108 109 #ifdef __cplusplus 110 extern "C" 111 { 112 #endif 113 114 115 //------------------------------------------------------------------------------------------------- 116 // Driver Capability 117 //------------------------------------------------------------------------------------------------- 118 //------------------------------------------------------------------------------------------------- 119 // Macro and Define 120 //------------------------------------------------------------------------------------------------- 121 122 #define TSP_VER_1_0 0x0100 123 #define TSP_VER_2_0 0x0200 124 #define TSP_VER_3_0 0x0300 125 #define TSP_VER_4_0 0x0400 126 127 128 #define TSP_VERSION TSP_VER_4_0 129 130 /// Transport stream null PID 131 #define MSIF_TSP_LIB_CODE {'T','S','P','4'} // Lib code 132 #define MSIF_TSP_LIBVER {'0','1'} // LIB version 133 #define MSIF_TSP_BUILDNUM {'0','0'} // Build Number 134 #define MSIF_TSP_CHANGELIST {'0','0','5','8','5','9','0','3'} // P4 ChangeList Number 135 136 #define TSP_DRV_VERSION /* Character String for DRV/API version */ \ 137 MSIF_TAG, /* 'MSIF' */ \ 138 MSIF_CLASS, /* '00' */ \ 139 MSIF_CUS, /* 0x0000 */ \ 140 MSIF_MOD, /* 0x0000 */ \ 141 MSIF_CHIP, \ 142 MSIF_CPU, \ 143 MSIF_TSP_LIB_CODE, /* IP__ */ \ 144 MSIF_TSP_LIBVER, /* 0.0 ~ Z.Z */ \ 145 MSIF_TSP_BUILDNUM, /* 00 ~ 99 */ \ 146 MSIF_TSP_CHANGELIST, /* CL# */ \ 147 MSIF_OS 148 149 #define __LEGACY__ 1 // only for development 150 151 #define TSP_PID_NULL 0x1FFF 152 153 #define TSP_FILTER_DEPTH 16 // TSP_FILTER_DEPTH 154 155 /// TSP byte address alignment unit 156 #define TSP_ALIGN_UNIT 16 157 158 /// TSP byte address alignment macro 159 #define TSP_ALIGN(_x) ALIGN_16((MS_U32)_x) 160 161 // TSP event define 162 #define TSP_EVENT_SECTION 0x00000001 163 #define TSP_EVENT_DISABLEFLT 0x00000080 164 #define TSP_EVENT_FREEFLT 0x00000040 165 #define TSP_EVENT_TASKEND 0x80000000 166 167 #define TSP_EVENT_SECTION_POLL 0x00000002 168 169 #define TSP_TASK_EVENTS ( TSP_EVENT_SECTION | TSP_EVENT_FREEFLT|TSP_EVENT_DISABLEFLT | TSP_EVENT_TASKEND) 170 #define TSP_POLL_EVENTS ( TSP_EVENT_SECTION_POLL ) 171 172 #if __LEGACY__ 173 174 #undef TSP_TASK_EVENTS 175 #define TSP_TASK_EVENTS ( TSP_EVENT_SECTION | TSP_EVENT_FREEFLT |TSP_EVENT_DISABLEFLT | \ 176 TSP_EVENT_PVR0_RDY | TSP_EVENT_PVR1_RDY | TSP_EVENT_TASKEND ) 177 178 #define TSP_EVENT_PVR0_RDY 0x00000004 179 #define TSP_EVENT_PVR1_RDY 0x00000008 180 // @FIXME: remove 181 #define TSP_EVENT_PVR0_RDY_POLL 0x00000010 182 #define TSP_EVENT_PVR1_RDY_POLL 0x00000020 183 184 // @FIXME: remove 185 #undef TSP_POLL_EVENTS 186 #define TSP_POLL_EVENTS ( TSP_EVENT_SECTION_POLL | \ 187 TSP_EVENT_PVR0_RDY_POLL | \ 188 TSP_EVENT_PVR1_RDY_POLL ) 189 190 #endif // __LEGACY__ 191 192 193 //------------------------------------------------------------------------------------------------- 194 // Type and Structure 195 //------------------------------------------------------------------------------------------------- 196 197 //For Tee 198 //---------------- 199 #ifdef SECURE_PVR_ENABLE 200 typedef enum 201 { 202 E_DRVTSP_REE_TO_TEE_CMD_NULL, 203 E_DRVTSP_REE_TO_TEE_CMD_FW_LoadCode, //None parameters 204 E_DRVTSP_REE_TO_TEE_CMD_SET_VqBuf, //None parameters 205 E_DRVTSP_REE_TO_TEE_CMD_SET_PvrBuf, //Param1: Engine id, Param2: Option 1 is reset buffer to 0 206 E_DRVTSP_REE_TO_TEE_CMD_SET_FileinBuf, //Param1: Engine id, Param2: Buf address, Param3: Buf size 207 E_DRVTSP_REE_TO_TEE_CMD_GET_PvrWPtr, //Param1: Engine id, Param2: Return Buf address 208 E_DRVTSP_REE_TO_TEE_CMD_SET_MMFIBuf //Param1: Engine id, Param2: Return Buf address 209 } TSP_REE_TO_TEE_CMD_TYPE; 210 211 typedef struct __attribute__((__packed__)) 212 { 213 MS_U32 u32BufId; 214 MS_U32 u32BufOpt; 215 MS_U32 u32BufSize; 216 MS_PHY phyBufAddr; 217 }DrvTSP_SecureBuf; 218 219 #endif //SECURE_PVR_ENABLE 220 221 typedef enum _TSP_Id 222 { 223 E_TSP_ID_0 = 0, 224 E_TSP_ID_1, 225 E_TSP_ID_2, 226 E_TSP_ID_NULL = 0xFF, 227 } EN_TSP_Id; 228 229 230 /// TSP DDI return value 231 /// @name TSP_Result 232 /// @ref TSP_Result 233 /// return value 234 /// @{ 235 typedef enum 236 { 237 E_TSP_FAIL = 0, 238 E_TSP_OK, 239 E_TSP_FAIL_PARAMETER, 240 E_TSP_FAIL_FUNCTION, 241 E_TSP_FAIL_NOT_SUPPORTED, 242 E_TSP_FAIL_INVALID, 243 E_TSP_FAIL_NODATA, 244 245 } TSP_Result; 246 /// @} 247 248 /// TSP Init Parameter 249 /// @name TSP_InitParam 250 /// @{ 251 typedef struct DLL_PACKED _TSP_InitParam 252 { 253 MS_PHYADDR phyFWAddr; /// Firmware source physical address 254 #if !defined (__aarch64__) 255 MS_U32 u32AlignDummy0; //align size for MI init share mem size check fail 256 #endif 257 MS_U32 u32FWSize; 258 259 MS_PHYADDR phyVQAddr; /// Internal buffer physical address 260 #if !defined (__aarch64__) 261 MS_U32 u32AlignDummy1; //align size for MI init share mem size check fail 262 #endif 263 MS_U32 u32VQSize; 264 265 } TSP_InitParam; 266 /// @} 267 268 269 // @NOTE should be Exclusive usage 270 typedef MS_U32 TSP_TSIFCfg; 271 #define E_TSP_TSIF_EN 0x0001 // 1: enable ts interface 0 and vice versa 272 #define E_TSP_TSIF_DIS 0x0000 273 #define E_TSP_TSIF_SERL 0x0000 274 #define E_TSP_TSIF_PARL 0x0002 275 #define E_TSP_TSIF_EXTSYNC 0x0004 276 #define E_TSP_TSIF_BITSWAP 0x0008 277 #define E_TSP_TSIF_3WIRE 0x0010 278 279 280 /// TSP TS Input Source 281 typedef enum _TSP_TSPad 282 { 283 E_TSP_TS_PAD0, 284 E_TSP_TS_PAD1, 285 E_TSP_TS_PAD2, 286 E_TSP_TS_PAD3, 287 E_TSP_TS_PAD4, 288 E_TSP_TS_PAD5, 289 E_TSP_TS_PAD6, 290 E_TSP_TS_PAD7, 291 292 E_TSP_TS_DEMOD0, 293 E_TSP_TS_DEMOD1, 294 295 E_TSP_TS_PAD_TSO0, 296 E_TSP_TS_PAD_TSO1, 297 298 E_TSP_TS_PAD0_3WIRE, 299 E_TSP_TS_PAD1_3WIRE, 300 E_TSP_TS_PAD2_3WIRE, 301 E_TSP_TS_PAD3_3WIRE, 302 E_TSP_TS_PAD4_3WIRE, 303 E_TSP_TS_PAD5_3WIRE, 304 E_TSP_TS_PAD6_3WIRE, 305 E_TSP_TS_PAD7_3WIRE, 306 307 E_TSP_TS_PAD_TSIO0, 308 309 E_TSP_TS_INVALID, 310 } TSP_TSPad; 311 312 typedef enum _TSP_TSId // for k3 TSP Path //@FIXME modify _TSP_TSId -> _TSP_TSPATH 313 { 314 E_TSP_TSID_TSIF0 = 0 , 315 E_TSP_TSID_TSIF1 = 1 , 316 E_TSP_TSID_TSIF2 = 2 , 317 E_TSP_TSID_TSIF3 = 3 , 318 E_TSP_TSID_MMFI0 = 4 , 319 E_TSP_TSID_MMFI1 = 5 , 320 321 E_TSP_TSID_INVALID, 322 323 } TSP_TSId; //@FIXME modify TSP_TSId -> TSP_TSPath 324 325 typedef enum _TSP_TSIF // for HW TSIF 326 { 327 E_TSP_TSIF_0 = 0 , 328 E_TSP_TSIF_1 = 1 , 329 E_TSP_TSIF_2 = 2 , 330 E_TSP_TSIF_3 = 3 , 331 E_TSP_TSIF_4 = 4 , 332 E_TSP_TSIF_5 = 5 , 333 E_TSP_TSIF_6 = 6 , 334 E_TSP_TSIF_TSP_MAX = 6 , 335 E_TSP_TSIF_CB = 7 , 336 E_TSP_TSIF_TSO0 = 8 , 337 E_TSP_TSIF_TSO1 = 9 , 338 E_TSP_TSIF_EMMFLT = 10 , 339 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 340 E_TSP_TSIF_PVR0 = 11 , 341 E_TSP_TSIF_PVR1 = 12 , 342 E_TSP_TSIF_PVR2 = 13 , 343 E_TSP_TSIF_PVR3 = 14 , 344 E_TSP_TSIF_INVALID, 345 346 } TSP_TSIF; 347 348 typedef enum _TSP_FLOW // for Dst type 349 { 350 E_DRV_TSP_FLOW_PLAYBACK0, 351 E_DRV_TSP_FLOW_PLAYBACK1, 352 E_DRV_TSP_FLOW_PLAYBACK2, 353 E_DRV_TSP_FLOW_PLAYBACK3, 354 E_DRV_TSP_FLOW_PLAYBACK4, 355 E_DRV_TSP_FLOW_PLAYBACK5, 356 E_DRV_TSP_FLOW_PLAYBACK6, 357 E_DRV_TSP_FLOW_PVR0, 358 E_DRV_TSP_FLOW_PVR1, 359 E_DRV_TSP_FLOW_PVR2, 360 E_DRV_TSP_FLOW_PVR3, 361 E_DRV_TSP_FLOW_TSO0, 362 E_DRV_TSP_FLOW_TSO1, 363 E_DRV_TSP_FLOW_INVALID, 364 } DRV_TSP_FLOW; 365 366 typedef enum // merge this with drvtsp2.h->TSP_TSIF 367 { 368 E_DRVTSP_IF_TSIF0 = 0x0, 369 E_DRVTSP_IF_TSIF1 = 0x1, 370 E_DRVTSP_IF_TSIF2 = 0x2, 371 E_DRVTSP_IF_TSIF3 = 0x3, 372 E_DRVTSP_IF_TSIF4 = 0x4, 373 E_DRVTSP_IF_TSIF5 = 0x5, 374 E_DRVTSP_IF_TSIF6 = 0x6, 375 376 E_DRVTSP_IF_NUM, 377 } DrvTSP_If; 378 379 typedef enum 380 { 381 E_DRV_TSP_PATH_LIVE, 382 E_DRV_TSP_PATH_FILE, 383 384 E_DRV_TSP_PATH_INVALID 385 } DRV_TSP_PATH_TYPE; 386 387 //---------------------------------- 388 /// DMX debug table information structure 389 //---------------------------------- 390 typedef enum 391 { 392 E_DRVTSP_DEBUG_CMD_NONE, 393 E_DRVTSP_DEBUG_CMD_CLEAR, 394 E_DRVTSP_DEBUG_CMD_ENABLE, 395 E_DRVTSP_DEBUG_CMD_DISABLE, 396 397 } DrvTSP_Debug_Cmd; 398 399 typedef enum 400 { 401 E_DRVTSP_FLOW_LIVE0, 402 E_DRVTSP_FLOW_LIVE1, 403 E_DRVTSP_FLOW_LIVE2, 404 E_DRVTSP_FLOW_LIVE3, 405 E_DRVTSP_FLOW_LIVE4, 406 E_DRVTSP_FLOW_LIVE5, 407 E_DRVTSP_FLOW_LIVE6, 408 409 E_DRVTSP_FLOW_FILE0, 410 E_DRVTSP_FLOW_FILE1, 411 E_DRVTSP_FLOW_FILE2, 412 E_DRVTSP_FLOW_FILE3, 413 E_DRVTSP_FLOW_FILE4, 414 E_DRVTSP_FLOW_FILE5, 415 E_DRVTSP_FLOW_FILE6, 416 417 E_DRVTSP_FLOW_MMFI0, 418 E_DRVTSP_FLOW_MMFI1, 419 420 E_DRVTSP_FLOW_INVALID, 421 422 } DrvTSP_Flow; 423 424 typedef enum 425 { 426 E_DRVTSP_AVFIFO_VIDEO, 427 E_DRVTSP_AVFIFO_VIDEO3D, 428 E_DRVTSP_AVFIFO_VIDEO3, 429 E_DRVTSP_AVFIFO_VIDEO4, 430 E_DRVTSP_AVFIFO_VIDEO5, 431 E_DRVTSP_AVFIFO_VIDEO6, 432 E_DRVTSP_AVFIFO_VIDEO7, 433 E_DRVTSP_AVFIFO_VIDEO8, 434 435 E_DRVTSP_AVFIFO_AUDIO, 436 E_DRVTSP_AVFIFO_AUDIOB, 437 E_DRVTSP_AVFIFO_AUDIOC, 438 E_DRVTSP_AVFIFO_AUDIOD, 439 E_DRVTSP_AVFIFO_AUDIOE, 440 E_DRVTSP_AVFIFO_AUDIOF, 441 442 E_DRVTSP_AVFIFO_INVALID, 443 444 } DrvTSP_AVFIFO; 445 446 // @TODO : add flag number define in each chip hal 447 #ifndef TSP_MAX_PVRSIGFLAG_NUM 448 #define TSP_MAX_PVRSIGFLAG_NUM 10 449 #endif 450 #ifndef TSP_MAX_SIGFLAG_NUM 451 #define TSP_MAX_SIGFLAG_NUM 16 452 #endif 453 454 typedef struct DLL_PACKED 455 { 456 MS_U32 u32Eng; 457 MS_U32 u32EvtWaitOpt; 458 MS_U32 u32DmxEvt; 459 MS_U32 u32TspEvt; 460 461 MS_U32 u32PvrBufFullFlag[TSP_MAX_PVRSIGFLAG_NUM]; 462 463 MS_U32 u32SecRdyFlag[TSP_MAX_SIGFLAG_NUM]; 464 MS_U32 u32SecOvfFlag[TSP_MAX_SIGFLAG_NUM]; 465 MS_U32 u32SecCrcErrFlag[TSP_MAX_SIGFLAG_NUM]; 466 467 MS_S32 s32KerModeTspEvtId; //For kernel mode, every user callback process must has itself eventid in multiple process support 468 MS_U32 u32TblIndex; 469 }DrvTSP_IoSignal; 470 471 472 // @TODO: ? 473 #define TSP_FltType MS_U32 474 /// TS stream fifo type 475 #define E_TSP_FLT_FIFO_MASK 0x000000FF 476 #define E_TSP_FLT_FIFO_INVALID 0x00000000 477 #define E_TSP_FLT_FIFO_REC 0x00000001 478 #define E_TSP_FLT_FIFO_PVR0 0x00000002 479 #define E_TSP_FLT_FIFO_PVR E_TSP_FLT_FIFO_PVR0 480 #define E_TSP_FLT_FIFO_PVR1 0x00000003 481 #define E_TSP_FLT_FIFO_PVR2 0x00000004 482 #define E_TSP_FLT_FIFO_PVR3 0x00000005 483 #define E_TSP_FLT_FIFO_PVR4 0x00000006 484 #define E_TSP_FLT_FIFO_PVR5 0x00000007 485 #define E_TSP_FLT_FIFO_PVR6 0x00000008 486 #define E_TSP_FLT_FIFO_PVR7 0x00000009 487 #define E_TSP_FLT_FIFO_PVR8 0x0000000A 488 #define E_TSP_FLT_FIFO_PVR9 0x0000000B 489 #define E_TSP_FLT_FIFO_AUDIO 0x0000000C 490 #define E_TSP_FLT_FIFO_AUDIO2 0x0000000D 491 #define E_TSP_FLT_FIFO_AUDIO3 0x0000000E 492 #define E_TSP_FLT_FIFO_AUDIO4 0x0000000F 493 #define E_TSP_FLT_FIFO_AUDIO5 0x00000010 494 #define E_TSP_FLT_FIFO_AUDIO6 0x00000011 495 #define E_TSP_FLT_FIFO_VIDEO 0x00000012 496 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000013 497 #define E_TSP_FLT_FIFO_VIDEO3 0x00000014 498 #define E_TSP_FLT_FIFO_VIDEO4 0x00000015 499 #define E_TSP_FLT_FIFO_VIDEO5 0x00000016 500 #define E_TSP_FLT_FIFO_VIDEO6 0x00000017 501 #define E_TSP_FLT_FIFO_VIDEO7 0x00000018 502 #define E_TSP_FLT_FIFO_VIDEO8 0x00000019 503 504 /// Section user filter type (Exclusive Usage) 505 #define E_TSP_FLT_USER_MASK 0x00000F00 ///<\n 506 #define E_TSP_FLT_USER_SHFT 8 ///<\n 507 #define E_TSP_FLT_USER_NULL 0x00000000 508 #define E_TSP_FLT_USER_SEC 0x00000100 ///<\n 509 #define E_TSP_FLT_USER_PES 0x00000200 ///<\n 510 #define E_TSP_FLT_USER_PKT 0x00000300 //[Reserved] 511 #define E_TSP_FLT_USER_PCR 0x00000400 ///<\n 512 #define E_TSP_FLT_USER_TTX 0x00000500 513 #define E_TSP_FLT_USER_EMM 0x00000600 //NDS 514 #define E_TSP_FLT_USER_ECM 0x00000700 //NDS 515 #define E_TSP_FLT_USER_OAD 0x00000800 //[Reserved] 516 517 518 #define E_TSP_FLT_FLAG_MASK 0x0000F000 519 #define E_TSP_FLT_FLAG_CA 0x00001000 520 521 /// TSIF Source (Exclusive Usage) 522 #define E_TSP_FLT_SRC_MASK 0xF00F0000 523 #define E_TSP_FLT_SRC_LIVE0 0x00000000 524 #define E_TSP_FLT_SRC_LIVE1 0x00010000 525 #define E_TSP_FLT_SRC_LIVE2 0x00020000 526 #define E_TSP_FLT_SRC_LIVE3 0x00030000 527 #define E_TSP_FLT_SRC_LIVE4 0x00040000 528 #define E_TSP_FLT_SRC_LIVE5 0x00050000 529 #define E_TSP_FLT_SRC_LIVE6 0x00060000 530 #define E_TSP_FLT_SRC_FILE0 0x00070000 531 #define E_TSP_FLT_SRC_FILE1 0x00080000 532 #define E_TSP_FLT_SRC_FILE2 0x00090000 533 #define E_TSP_FLT_SRC_FILE3 0x000A0000 534 #define E_TSP_FLT_SRC_FILE4 0x000B0000 535 #define E_TSP_FLT_SRC_FILE5 0x000C0000 536 #define E_TSP_FLT_SRC_FILE6 0x000D0000 537 538 539 /// Source ID define. For merge stream 540 #define E_TSP_FLT_SRCID_MASK 0x01F00000 541 #define E_TSP_FLT_SRCID_SHIFT 20 542 #define E_TSP_FLT_SRCID_0 0x00000000 543 #define E_TSP_FLT_SRCID_1 0x00100000 544 #define E_TSP_FLT_SRCID_2 0x00200000 545 #define E_TSP_FLT_SRCID_3 0x00300000 546 #define E_TSP_FLT_SRCID_4 0x00400000 547 #define E_TSP_FLT_SRCID_5 0x00500000 548 #define E_TSP_FLT_SRCID_6 0x00600000 549 #define E_TSP_FLT_SRCID_7 0x00700000 550 #define E_TSP_FLT_SRCID_8 0x00800000 551 #define E_TSP_FLT_SRCID_9 0x00900000 552 #define E_TSP_FLT_SRCID_10 0x00a00000 553 #define E_TSP_FLT_SRCID_11 0x00b00000 554 #define E_TSP_FLT_SRCID_12 0x00c00000 555 #define E_TSP_FLT_SRCID_13 0x00d00000 556 #define E_TSP_FLT_SRCID_14 0x00e00000 557 #define E_TSP_FLT_SRCID_15 0x00f00000 558 #define E_TSP_FLT_SRCID_16 0x01000000 559 #define E_TSP_FLT_SRCID_17 0x01100000 560 #define E_TSP_FLT_SRCID_18 0x01200000 561 #define E_TSP_FLT_SRCID_19 0x01300000 562 #define E_TSP_FLT_SRCID_20 0x01400000 563 #define E_TSP_FLT_SRCID_21 0x01500000 564 #define E_TSP_FLT_SRCID_22 0x01600000 565 #define E_TSP_FLT_SRCID_23 0x01700000 566 #define E_TSP_FLT_SRCID_24 0x01800000 567 #define E_TSP_FLT_SRCID_25 0x01900000 568 #define E_TSP_FLT_SRCID_26 0x01a00000 569 #define E_TSP_FLT_SRCID_27 0x01b00000 570 #define E_TSP_FLT_SRCID_28 0x01c00000 571 #define E_TSP_FLT_SRCID_29 0x01d00000 572 #define E_TSP_FLT_SRCID_30 0x01e00000 573 #define E_TSP_FLT_SRCID_31 0x01f00000 574 575 576 /// I frame LUT define. 577 #define E_TSP_DST_IFRAME_LUT 0x08000000 578 579 #define TSP_FltMode MS_U32 580 #define E_TSP_FLT_MODE_CONTI 0x00000000 581 #define E_TSP_FLT_MODE_ONESHOT 0x00000001 582 583 // optional 584 #define E_TSP_FLT_MODE_CRCCHK 0x00000002 585 //#define E_TSP_FLT_MODE_AUTO_ADDR 0x00000004 // auto move read point mode 586 #define E_TSP_FLT_MODE_AUTO_CRCCHK 0x00000008 //not really for setting, mapped to TSP_SECFLT_MODE_AUTO_CRCCHK 587 588 /// TSP channel state bit flags 589 typedef enum //_DrvTSP_FltState // @FIXME we current use this enum with == not &. doesn't have to be exclusive use 590 { 591 E_TSP_FLT_STATE_FREE = 0x00000000, ///<\n 592 E_TSP_FLT_STATE_ALLOC = 0x00000001, ///<\n 593 E_TSP_FLT_STATE_ENABLE = 0x00000002, ///<\n 594 E_TSP_FLT_STATE_SCRAMBLED = 0x00000004, //[TODO] 595 E_TSP_FLT_STATE_STREAM_AVAIL = 0x00000008, //[TODO] 596 E_TSP_FLT_STATE_SCRAMBLED_ORG = 0x00000010, 597 E_TSP_FLT_STATE_ISR_FREE = 0x00000020, ///<\n 598 E_TSP_FLT_STATE_OVERFLOW = 0x00010000, //[Reserved] 599 E_TSP_FLT_STATE_NA = 0xFFFFFFFF, 600 } TSP_FltState; 601 602 603 /// TSP record mode 604 typedef enum //_DrvTSP_RecMode 605 { 606 //[TODO] rename REC_MODE to PVR_MODE 607 608 /// Record ENG0 by @ref E_DRVTSP_FLT_TYPE_PVR 609 E_TSP_REC_MODE_ENG0_FLTTYPE = 0x00000000, // TSP_PVR_CTRL_ENG(0) 610 /// Record ENG1 by @ref E_DRVTSP_FLT_TYPE_PVR 611 E_TSP_REC_MODE_ENG1_FLTTYPE = 0x00000001, // TSP_PVR_CTRL_ENG(1) 612 /// Record ENG0 bypass PID fliter 613 E_TSP_REC_MODE_ENG0_BYPASS = 0x00000002, // TSP_PVR_CTRL_ENG(0) + TSP_PVR_CTRL_BYPASS 614 /// Record ENG1 bypass PID fliter 615 E_TSP_REC_MODE_ENG1_BYPASS = 0x00000003, // TSP_PVR_CTRL_ENG(1) + TSP_PVR_CTRL_BYPASS 616 617 } TSP_RecMode; 618 619 620 /// TSP Control Mode 621 typedef enum //_DrvTSP_CtrlMode 622 { 623 /// Input From Stream Source 0 624 E_TSP_CTRL_MODE_TS0, 625 /// Input From Stream Source 1 626 E_TSP_CTRL_MODE_TS1, 627 /// Input From Memory 628 E_TSP_CTRL_MODE_MEM, 629 } TSP_CtrlMode; 630 631 632 typedef enum 633 { 634 /// Streaming to TSP 635 E_TSP_FILE_2_TSP = 0x00000000, //TSP_TSDMA_CTRL_ENG0 636 /// Streaming to AUDIO FIFO 637 E_TSP_FILE_2_AUDIO = 0x00000001, //TSP_TSDMA_CTRL_APES0 638 /// Streaming to AUDIO2 FIFO 639 E_TSP_FILE_2_AUDIO2 = 0x00000002, //TSP_TSDMA_CTRL_A2PES0 640 /// Streaming to AUDIO3 FIFO 641 E_TSP_FILE_2_AUDIO3 = 0x00000003, //TSP_TSDMA_CTRL_A3PES0 642 /// Streaming to AUDIO4 FIFO 643 E_TSP_FILE_2_AUDIO4 = 0x00000004, //TSP_TSDMA_CTRL_A4PES0 644 /// Streaming to AUDIO5 FIFO 645 E_TSP_FILE_2_AUDIO5 = 0x00000005, //TSP_TSDMA_CTRL_A5PES0 646 /// Streaming to AUDIO6 FIFO 647 E_TSP_FILE_2_AUDIO6 = 0x00000006, //TSP_TSDMA_CTRL_A6PES0 648 /// Streaming to VIDEO FIFO 649 E_TSP_FILE_2_VIDEO = 0x00000007, //TSP_TSDMA_CTRL_VPES0 650 /// Streaming to VIDEO3D FIFO 651 E_TSP_FILE_2_VIDEO3D = 0x00000008, //TSP_TSDMA_CTRL_V3DPES0 652 /// Streaming to VIDEO3 FIFO 653 E_TSP_FILE_2_VIDEO3 = 0x00000009, //TSP_TSDMA_CTRL_V3PES0 654 /// Streaming to VIDEO4 FIFO 655 E_TSP_FILE_2_VIDEO4 = 0x0000000A, //TSP_TSDMA_CTRL_V4PES0 656 /// Streaming to VIDEO5 FIFO 657 E_TSP_FILE_2_VIDEO5 = 0x0000000B, //TSP_TSDMA_CTRL_V5PES0 658 /// Streaming to VIDEO6 FIFO 659 E_TSP_FILE_2_VIDEO6 = 0x0000000C, //TSP_TSDMA_CTRL_V6PES0 660 /// Streaming to VIDEO7 FIFO 661 E_TSP_FILE_2_VIDEO7 = 0x0000000D, //TSP_TSDMA_CTRL_V7PES0 662 /// Streaming to VIDEO8 FIFO 663 E_TSP_FILE_2_VIDEO8 = 0x0000000E, //TSP_TSDMA_CTRL_V8PES0 664 665 } TSP_FileMode; 666 667 668 typedef enum _TSP_FileinState 669 { 670 /// Command Queue is Idle 671 E_TSP_FILE_STATE_IDLE = 0000000000, 672 /// Command Queue is Busy 673 E_TSP_FILE_STATE_BUSY = 0x00000001, 674 /// Command Queue is Paused. 675 E_TSP_FILE_STATE_PAUSE = 0x00000002, 676 } TSP_FileState; 677 678 679 #define TSP_Event MS_U32 680 #define E_TSP_EVENT_DATA_IDLE 0x00000000 681 /// Section Data Ready 682 #define E_TSP_EVENT_DATA_READY 0x00000001 683 /// Section data CRC Error 684 #define E_TSP_EVENT_SEC_CRCERROR 0x00000004 685 /// Section Buffer Overflow 686 #define E_TSP_EVENT_BUF_OVERFLOW 0x00000002 687 /// PVR Buffer is Full 688 #define E_TSP_EVENT_PVRBUF_FULL 0x00000010 689 /// PVR Double Buffer Overflow 690 #define E_TSP_EVENT_PVRBUF_OVERFLOW 0x00000020 691 692 /// TSP self task callback // optional --> default is CB by poll 693 #define E_TSP_EVENT_CB_MASK 0x80000000 694 #define E_TSP_EVENT_CB_POLL 0x00000000 695 #define E_TSP_EVENT_CB_AUTO 0x80000000 696 697 /// TSP file in Engine 698 typedef enum 699 { 700 E_TSP_FILE_ENG_TSIF0 = 0, 701 E_TSP_FILE_ENG_TSIF1 = 1, 702 E_TSP_FILE_ENG_TSIF2 = 2, 703 E_TSP_FILE_ENG_TSIF3 = 3, 704 E_TSP_FILE_ENG_TSIF4 = 4, 705 E_TSP_FILE_ENG_TSIF5 = 5, 706 E_TSP_FILE_ENG_TSIF6 = 6, 707 E_TSP_FILE_ENG_INVALID, 708 } TSP_FILE_ENG; 709 710 /// TSP file in Packet mode 711 typedef enum 712 { 713 E_TSP_PKTMODE_188 = 0x00000000, 714 E_TSP_PKTMODE_192 = 0x00000001, 715 E_TSP_PKTMODE_204 = 0x00000002, 716 E_TSP_PKTMODE_130 = 0x00000003, // RVU 717 E_TSP_PKTMODE_134 = 0x00000004, // RVU with timestamp 718 E_TSP_PKTMODE_FILEIN_MIN = E_TSP_PKTMODE_188, 719 E_TSP_PKTMODE_FILEIN_MAX = E_TSP_PKTMODE_134, 720 721 E_TSP_PKTMODE_CIPLUS = 0x00000005, // CI+ (188 bytes) 722 E_TSP_PKTMODE_ATS = 0x00000006, // ATS (192 bytes) 723 E_TSP_PKTMODE_OPENCABLE = 0x00000007, // OpenCable (200 bytes) 724 725 E_TSP_PKTMODE_MXL192 = 0x00000008, // MxL (192 bytes) 726 E_TSP_PKTMODE_MXL196 = 0x00000009, // MxL (196 bytes) 727 E_TSP_PKTMODE_MXL200 = 0x0000000A, // MxL (200 bytes) 728 E_TSP_PKTMODE_LIVEIN_MIN = E_TSP_PKTMODE_CIPLUS, 729 E_TSP_PKTMODE_LIVEIN_MAX = E_TSP_PKTMODE_MXL200 730 731 } TSP_PktMode; 732 733 /// TSP notification event message 734 typedef struct _TSP_EventMsg 735 { 736 /// Union data type of message 737 union 738 { 739 /// FltInfo message 740 /// - Byte[0] : Section filter id 741 /// - Byte[1] : TSP id 742 MS_U32 FltInfo; 743 /// PvrBufId 744 /// - Byte[0] : PVR buffer id 745 MS_U32 PvrBufId; 746 }; 747 748 } TSP_EventMsg; 749 750 typedef enum 751 { 752 E_TSP_DBG_NONE, // display no message 753 E_TSP_DBG_MUST, // display must print message 754 E_TSP_DBG_ERROR, // display error message 755 E_TSP_DBG_WARNING, // display warning message 756 E_TSP_DBG_FAIL, // display more info and while(1) 757 E_TSP_DBG_INFO, // display info, callee, while(1) 758 E_TSP_DBG_TRACK, 759 E_TSP_DBG_ALL, 760 761 762 } TSP_DbgLevel; 763 764 /// @name TSP_EventMsg 765 /// Macro definitions for manipulating TSP_EventMsg 766 /// @{ 767 #define TSP_MSG_FLTID_MASK 0x000000FF 768 #define TSP_MSG_FLTID_SHFT 0 769 #define TSP_MSG_GETFLTID(msg) ((msg) & TSP_MSG_FLTID_MASK) 770 #define TSP_MSG_SETFLTID(msg, fltid) (((msg) & ~TSP_MSG_FLTID_MASK)) | ((fltid) << TSP_MSG_FLTID_SHFT)) 771 #define TSP_MSG_ENGID_MASK 0x0000FF00 772 #define TSP_MSG_ENGID_SHFT 8 773 #define TSP_MSG_PVRID_MASK 0x000000FF 774 #define TSP_MSG_PVRID_SHFT 0 775 #define TSP_MSG_PVRID_NULL 0xFF 776 /// @} 777 778 typedef enum 779 { 780 E_TSP_CAP_PIDFLT_NUM = 0, 781 E_TSP_CAP_SECFLT_NUM = 1, 782 E_TSP_CAP_SECBUF_NUM = 2, 783 784 E_TSP_CAP_RECENG_NUM = 3, 785 E_TSP_CAP_RECFLT_NUM = 4, 786 E_TSP_CAP_RECFLT1_NUM = 5, 787 788 E_TSP_CAP_MMFI_AUDIO_FILTER_NUM = 6, 789 E_TSP_CAP_MMFI_V3D_FILTER_NUM = 7, 790 791 E_TSP_CAP_TSIF_NUM = 8, 792 E_TSP_CAP_DEMOD_NUM = 9, 793 E_TSP_CAP_TSPAD_NUM = 10, 794 E_TSP_CAP_VQ_NUM = 11, 795 796 E_TSP_CAP_CAFLT_NUM = 12, 797 E_TSP_CAP_CAKEY_NUM = 13, 798 799 E_TSP_CAP_FW_ALIGN = 14, 800 E_TSP_CAP_VQ_ALIGN = 15, 801 E_TSP_CAP_VQ_PITCH = 16, 802 E_TSP_CAP_SECBUF_ALIGN = 17, 803 E_TSP_CAP_PVR_ALIGN = 18, 804 805 E_TSP_CAP_PVRCA_PATH_NUM = 19, 806 E_TSP_CAP_SHAREKEY_FLT_RANGE = 20, 807 E_TSP_CAP_PVRCA0_FLT_RANGE = 21, 808 E_TSP_CAP_PVRCA1_FLT_RANGE = 22, 809 E_TSP_CAP_PVRCA2_FLT_RANGE = 23, 810 E_TSP_CAP_SHAREKEY_FLT1_RANGE = 24, 811 E_TSP_CAP_SHAREKEY_FLT2_RANGE = 25, 812 813 E_TSP_CAP_HW_TYPE = 26, 814 815 E_TSP_CAP_RESOURCE_SIZE = 27, // Get the data structure size of private resource (share resource) 816 817 E_TSP_CAP_VFIFO_NUM = 28, 818 E_TSP_CAP_AFIFO_NUM = 29, 819 820 E_TSP_CAP_HWPCR_SUPPORT = 30, 821 E_TSP_CAP_PCRFLT_START_IDX = 31, 822 823 E_TSP_CAP_HWWP_SET_NUM = 32, // Get TSP write protect set numbers 824 825 E_TSP_CAP_CAP_DSCMB_ENG_NUM = 33, // Get DSCMB engine numbers 826 827 E_TSP_CAP_MAX_MERGESTR_NUM = 34, // Get Maxumum merge stream number 828 E_TSP_CAP_MAX_SEC_FLT_DEPTH = 35, 829 E_TSP_CAP_FW_BUF_SIZE = 36, 830 E_TSP_CAP_FW_BUF_RANGE = 37, 831 E_TSP_CAP_VQ_BUF_RANGE = 38, 832 E_TSP_CAP_SEC_BUF_RANGE = 39, 833 E_TSP_CAP_FIQ_NUM = 40, 834 E_TSP_CAP_RECFLT_IDX = 41, // [NOTE] internal usage 835 E_TSP_CAP_NULL, 836 } TSP_Caps; 837 838 839 840 typedef enum 841 { 842 E_TSP_HW_STATUS = 0, 843 E_TSP_HW_INIT, 844 E_TSP_HW_ALIVE, 845 E_TSP_HW_DEALIVE, 846 } TSP_HW_Status; 847 848 typedef enum 849 { 850 E_TSP_SW_INIT = 0, 851 E_TSP_SW_INIT_FAIL, 852 E_TSP_SW_SUSPEND, 853 E_TSP_SW_RESUME, 854 E_TSP_SW_POWEROFF, 855 E_TSP_SW_CLOSE, 856 E_TSP_SW_EXIT, 857 } TSP_SW_Status; 858 859 860 typedef enum 861 { 862 E_TSP_DRV_PVR_RecMode_PID, 863 E_TSP_DRV_PVR_RecMode_ALL, 864 } TSP_DRV_PVR_RecMode; 865 866 867 typedef struct 868 { 869 TSP_TSPad ePad; 870 MS_BOOL bClkInv; 871 MS_BOOL bExtSync; 872 MS_BOOL bParallel; 873 } DrvTSP_TsIf_Set; 874 875 typedef enum 876 { 877 E_TSP_PIDFLT_FIFO_FULL_LV_100 = 0x00000000, 878 E_TSP_PIDFLT_FIFO_FULL_LV_50 = 0x60000000 879 } TSP_FltFIFOFullLV; 880 881 /// Cmd for DSCMB to do DSCMB functionality accessing registers which are shared with TSP 882 typedef enum//DSCMB owner plz add enum if needed 883 { 884 E_TSP_DSCMB_CMD_NUM 885 } TSP_DSCMB_FuncCMD; 886 887 888 /// TSP TEI Remove Error Packet Infomation 889 typedef enum 890 { 891 E_TSP_DRV_TEI_REMOVE_AUDIO_PKT, ///< DMX TEI Remoce Audio Packet 892 E_TSP_DRV_TEI_REMOVE_VIDEO_PKT, ///< DMX TEI Remoce Video Packet 893 894 E_TSP_DRV_TEI_REMOVE_PKT0_LIVE, 895 E_TSP_DRV_TEI_REMOVE_PKT0_FILE, 896 E_TSP_DRV_TEI_REMOVE_PKT1, 897 E_TSP_DRV_TEI_REMOVE_PKT2, 898 899 }TSP_DRV_TEI_RmPktType; 900 901 /// FQ interface 902 typedef enum 903 { 904 E_DRVFQ_SRC_TSIF0 = 0x00, 905 E_DRVFQ_SRC_TSIF1 = 0x01, 906 E_DRVFQ_SRC_TSIF2 = 0x02, 907 E_DRVFQ_SRC_TSIF3 = 0x03, 908 E_DRVFQ_SRC_TSIF4 = 0x04, 909 E_DRVFQ_SRC_TSIF5 = 0x05, 910 E_DRVFQ_SRC_TSIF6 = 0x06, 911 912 E_DRVFQ_SRC_TSIFFI = 0x07, 913 E_DRVFQ_SRC_DEFAULT = 0xFF, 914 } DrvFQ_SrcIf; 915 916 /// TSP TimeStamp Clk Select 917 typedef enum 918 { 919 E_TSP_TIMESTAMP_CLK_90K = 0, 920 E_TSP_TIMESTAMP_CLK_27M = 1, 921 E_TSP_TIMESTAMP_CLK_INVALID = 2 922 923 } TSP_TimeStamp_Clk; 924 925 926 927 /// TSP notification function 928 typedef void (*P_TSP_Callback)(TSP_Event eEvent, TSP_EventMsg *pMsg); 929 930 //------------------------------------------------------------------------------------------------- 931 // Function Prototype 932 //------------------------------------------------------------------------------------------------- 933 934 // TSP Setting DDIs 935 TSP_Result MDrv_TSP_InitLibResource(void *pu32ResMemAddr); 936 TSP_Result MDrv_TSP_Init(TSP_InitParam *pParam); 937 TSP_Result MDrv_TSP_PowerOff(void); 938 TSP_Result MDrv_TSP_Exit(void); 939 940 TSP_TSIF MDrv_TSP_TsifMapping(TSP_TSIF eTSIF); 941 TSP_Result MDrv_TSP_SetFlowSource(DRV_TSP_FLOW eDst, TSP_TSId eTid); 942 TSP_Result MDrv_TSP_PVR_SetFlowSource(MS_U32 u32PvrEng, MS_U32 u32PvrSrc); 943 TSP_Result MDrv_TSP_SelPad(TSP_TSIF eTSIF, TSP_TSPad eTSPad); 944 TSP_Result MDrv_TSP_SelPad_ClkInv(TSP_TSIF eTSIF ,MS_BOOL bClkInv); 945 TSP_Result MDrv_TSP_SelPad_ClkDis(TSP_TSIF eTSIF ,MS_BOOL bClkDis); 946 TSP_Result MDrv_TSP_TSO_ConfigPad(MS_U32 u32TSOEng, TSP_TSPad eTSPad); 947 TSP_Result MDrv_TSP_SetTSIF(TSP_TSIF eTSIF, TSP_TSIFCfg u16Cfg, MS_BOOL bFileIn); 948 TSP_Result MDrv_TSP_FIFO_Reset(TSP_FltType eFltType, MS_BOOL bFlush); 949 TSP_Result MDrv_TSP_FIFO_BlockEnable(TSP_FltType eFltType, MS_BOOL bDisable); 950 TSP_Result MDrv_TSP_FIFO_GetStatus(TSP_FltType eFltType, MS_U32 *u32FifoLevel); 951 TSP_Result MDrv_TSP_FIFO_SourceSelect(TSP_TSId eTspTSid, TSP_FileMode eFifoType); 952 TSP_Result MDrv_TSP_FIFO_Overflow_Status(TSP_FltType eFltType, MS_BOOL *pbOverflow); 953 //TSP_Result MDrv_TSP_Scmb_Status(MS_U32 u32EngId, TSP_Scmb_Level* pScmbLevel); 954 TSP_Result MDrv_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable); 955 TSP_Result MDrv_TSP_GetTSIFStatus(TSP_TSIF eTSIF, TSP_TSPad* ePad, MS_BOOL* pbClkInv, MS_BOOL* pbExtSyc, MS_BOOL* pbParl); 956 TSP_Result MDrv_TSP_PARL_BitOrderSwap(MS_U16 u16TSIF, MS_BOOL bInvert); 957 958 959 TSP_Result MDrv_TSP_GetLastErr(void); 960 TSP_Result MDrv_TSP_FILE_CmdSTC(MS_U32 u32TSPId, MS_U32 u32STC_H, MS_U32 u32STC); 961 TSP_Result MDrv_TSP_GetPCR(MS_U32 u32TSPId, MS_U32 *pu32PCR_32, MS_U32 *pu32PCR); 962 TSP_Result MDrv_TSP_FLT_GetState(MS_U32 u32FltId, TSP_FltState *pState); 963 964 TSP_Result MDrv_TSP_Proc(MS_U32 u32TSPId, MS_U32 u32FltId, TSP_Event* pEvt); 965 966 // TSP FLT DDis 967 TSP_Result MDrv_TSP_FLT_Alloc(MS_U32 u32TSPId, TSP_FltType eFltType, MS_U32 *pu32FltId); 968 TSP_Result MDrv_TSP_FLT_Alloc_Ex(MS_U32 u32TSPId, TSP_FltType eFltType, MS_U32 *pu32FltId); 969 TSP_Result MDrv_TSP_FLT_Alloc_Common(MS_U32 u32TSPId, TSP_FltType eFltType, MS_U32 *pu32FltId); 970 TSP_Result MDrv_TSP_FLT_Free(MS_U32 u32FltId); 971 TSP_Result MDrv_TSP_FLT_SetPID(MS_U32 u32FltId, MS_U32 u32PID); 972 TSP_Result MDrv_TSP_FLT_GetPID(MS_U32 u32FltId, MS_U32 *pu32PID); ///RESERVED 973 TSP_Result MDrv_TSP_FLT_SelSEC(MS_U32 u32FltId, MS_U32 u32BufId); 974 TSP_Result MDrv_TSP_FLT_GetSEC(MS_U32 u32FltId, MS_U32 *pu32BufId); ///RESERVED 975 TSP_Result MDrv_TSP_FLT_SetCallback(MS_U32 u32FltId, TSP_Event eEvents, P_TSP_Callback pfCallback); 976 TSP_Result MDrv_TSP_FLT_SetMode(MS_U32 u32FltId, TSP_FltMode eFltMode); 977 TSP_Result MDrv_TSP_FLT_SetMatch(MS_U32 u32FltId, MS_U8 *pu8Match, MS_U8 *pu8Mask, MS_U8 *pu8NMask); 978 TSP_Result MDrv_TSP_FLT_Enable(MS_U32 u32FltId, MS_BOOL bEnable); 979 TSP_Result MDrv_TSP_FLT_SetPCRSrc(MS_U32 u32FltId,MS_U32 u32PCRSrc); 980 TSP_Result MDrv_TSP_FLT_SetFltRushPass(MS_U32 u32FltId, MS_U8 u8Enable); 981 TSP_Result MDrv_TSP_Flt_GetScmbSts(TSP_FltType eFltType, MS_U32 u32FltGroupId, MS_U32 PidFltId, MS_U32 *pu32ScmbSts); 982 TSP_Result MDrv_TSP_DropScmbPkt(TSP_FltType eFilterType, MS_BOOL bEnable); 983 TSP_Result MDrv_TSP_FLT_RemapFltId(MS_BOOL bNewApi); 984 985 // TSP SEC DDIs 986 TSP_Result MDrv_TSP_SEC_Alloc(MS_U32 u32TSPId, MS_U32 *pu32BufId); 987 TSP_Result MDrv_TSP_SEC_Free(MS_U32 u32BufId); 988 TSP_Result MDrv_TSP_SEC_SetBuffer(MS_U32 u32BufId, MS_PHYADDR u32Start, MS_U32 u32Size); 989 TSP_Result MDrv_TSP_SEC_GetSize(MS_U32 u32BufId, MS_U32 *pu32Size); 990 TSP_Result MDrv_TSP_SEC_GetStart(MS_U32 u32BufId, MS_PHY *pStart); 991 TSP_Result MDrv_TSP_SEC_SetRead(MS_U32 u32BufId, MS_PHY u32Read); 992 TSP_Result MDrv_TSP_SEC_GetRead(MS_U32 u32BufId, MS_PHY *pu32Read); 993 TSP_Result MDrv_TSP_SEC_GetWrite(MS_U32 u32BufId, MS_PHY *pu32Write); 994 TSP_Result MDrv_TSP_SEC_Reset(MS_U32 u32BufId); 995 TSP_Result MDrv_TSP_SECFLT_BurstLen(MS_U32 u32BurstMode); 996 #ifdef MSOS_TYPE_LINUX_KERNEL 997 TSP_Result MDrv_TSP_SEC_ClrEvent(MS_U32 u32BufId); 998 TSP_Result MDrv_TSP_SEC_GetEvent(MS_U32 u32BufId, MS_U32 *pu32Event); 999 TSP_Result MDrv_TSP_SEC_SetEvent(MS_U32 u32BufId, MS_U32 u32Event); 1000 #endif 1001 1002 // TSP FILE DDIs 1003 TSP_Result MDrv_TSP_FILE_SetPktMode(TSP_PktMode mode); 1004 TSP_Result MDrv_TSP_FILE_SetRate(MS_U32 u32Div2); 1005 TSP_Result MDrv_TSP_FILE_CmdAddr(MS_U32 u32Addr); 1006 TSP_Result MDrv_TSP_FILE_CmdSize(MS_U32 u32Size); 1007 TSP_Result MDrv_TSP_FILE_CmdSTC(MS_U32 u32EngId, MS_U32 u32STC_H, MS_U32 u32STC); 1008 TSP_Result MDrv_TSP_FILE_CmdStart(TSP_FileMode mode); 1009 TSP_Result MDrv_TSP_FILE_GetCmdSlot(MS_U32 *pu32EmptySlot); 1010 TSP_Result MDrv_TSP_FILE_Pause(void); 1011 TSP_Result MDrv_TSP_FILE_Resume(void); 1012 TSP_Result MDrv_TSP_FILE_Stop(void); 1013 TSP_Result MDrv_TSP_FILE_GetState(TSP_FileState *pState); 1014 TSP_Result MDrv_TSP_FILE_Reset(void); 1015 TSP_Result MDrv_TSP_File_192BlockScheme_En(MS_BOOL bEnable); 1016 TSP_Result MDrv_TSP_FILE_PS_Path_Enable(TSP_FileMode mode); 1017 1018 // TSP FILE Eng 1019 TSP_Result MDrv_TSP_FILE_Eng_SetPktMode(TSP_FILE_ENG Eng, TSP_PktMode mode); 1020 TSP_Result MDrv_TSP_FILE_Eng_SetRate(TSP_FILE_ENG Eng, MS_U32 u32Div2); 1021 TSP_Result MDrv_TSP_FILE_Eng_CmdAddr(TSP_FILE_ENG Eng, MS_U32 u32Addr); 1022 TSP_Result MDrv_TSP_FILE_Eng_CmdSize(TSP_FILE_ENG Eng, MS_U32 u32Size); 1023 TSP_Result MDrv_TSP_FILE_Eng_CmdSTC(TSP_FILE_ENG Eng, MS_U32 u32EngId, MS_U32 u32STC_H, MS_U32 u32STC); 1024 TSP_Result MDrv_TSP_FILE_Eng_CmdStart(TSP_FILE_ENG Eng, TSP_FileMode mode); 1025 TSP_Result MDrv_TSP_FILE_Eng_GetCmdSlot(TSP_FILE_ENG Eng, MS_U32 *pu32EmptySlot); 1026 TSP_Result MDrv_TSP_FILE_Eng_Pause(TSP_FILE_ENG Eng); 1027 TSP_Result MDrv_TSP_FILE_Eng_Resume(TSP_FILE_ENG Eng); 1028 TSP_Result MDrv_TSP_FILE_Eng_Stop(TSP_FILE_ENG Eng); 1029 TSP_Result MDrv_TSP_FILE_Eng_GetState(TSP_FILE_ENG Eng, TSP_FileState *pState); 1030 TSP_Result MDrv_TSP_FILE_Eng_Reset(TSP_FILE_ENG Eng); 1031 TSP_Result MDrv_TSP_FILE_Eng_192BlockScheme_En(TSP_FILE_ENG Eng, MS_BOOL bEnable); 1032 TSP_Result MDrv_TSP_FILE_Eng_PS_Path_Enable(TSP_FILE_ENG Eng, TSP_FileMode mode); 1033 TSP_Result MDrv_TSP_FILE_Eng_CmdQFifo_Status(TSP_FILE_ENG Eng, MS_U8 *pu8FifoLevel); 1034 TSP_Result MDrv_TSP_FILE_Eng_GetFileInTimeStamp(TSP_FILE_ENG Eng, MS_U32* u32TSLen); 1035 TSP_Result MDrv_TSP_FILE_Eng_TimeStampEnablePlaybackStamp(TSP_FILE_ENG Eng,MS_BOOL bEnable); 1036 TSP_Result MDrv_TSP_FILE_Eng_TimeStampSetPlaybackStamp(TSP_FILE_ENG Eng, MS_U32 u32Stamp); 1037 TSP_Result MDrv_TSP_FILE_Eng_TimeStampSetPlaybackStampClk(TSP_FILE_ENG Eng, TSP_TimeStamp_Clk eClk); 1038 TSP_Result MDrv_TSP_FILE_Eng_TimeStampGetPlaybackStamp(TSP_FILE_ENG Eng, MS_U32* u32Stamp); 1039 TSP_Result MDrv_TSP_FILE_Eng_GetFileInCurReadAddr(TSP_FILE_ENG Eng, MS_PHY* pu32Addr); 1040 TSP_Result MDrv_TSP_FILE_Eng_MOBF_Enable(TSP_FILE_ENG eEng, MS_BOOL bEnable, MS_U32 u32Key); 1041 1042 // Merge stream 1043 TSP_Result MDrv_TSP_MStr_SyncByte(DrvTSP_If eTsIf, MS_U8 u8StrId, MS_U8 *pu8SyncByte, MS_BOOL bSet); 1044 TSP_Result MDrv_TSP_SetPacketMode(TSP_TSIF u32TSIf, TSP_PktMode eDrvPktMode); 1045 1046 // FQ 1047 TSP_Result MDrv_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, DrvFQ_SrcIf eTsSrc); 1048 TSP_Result MDrv_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng, DrvFQ_SrcIf* peTsSrc); 1049 TSP_Result MDrv_TSP_FQ_FltNullPkt(MS_U32 u32FQEng, MS_BOOL bFltNull); 1050 1051 // Debug table 1052 TSP_Result MDrv_TSP_Get_DisContiCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_AVFIFO eAvType, DrvTSP_Flow eFlow, MS_U32* pu32Cnt); 1053 TSP_Result MDrv_TSP_Get_DropPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_AVFIFO eAvType, DrvTSP_Flow eFlow, MS_U32* pu32Cnt); 1054 TSP_Result MDrv_TSP_Get_LockPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_Flow eFlow, MS_U32* pu32Cnt); 1055 TSP_Result MDrv_TSP_Get_AVPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_AVFIFO eAvType, DrvTSP_Flow eFlow, MS_U32* pu32Cnt); 1056 // @TODO ErrPktCnt Implement 1057 //TSP_Result MDrv_TSP_Get_ErrPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_Flow eFlow, MS_U32* pu32Cnt); 1058 1059 // Protection range 1060 TSP_Result MDrv_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY *pphyStartAddr, MS_PHY *pphyEndAddr); 1061 TSP_Result MDrv_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr); 1062 1063 // Utopia 2K relative functions 1064 //------- For 2K kernel mode, user mode callback thread using events 1065 TSP_Result MDrv_TSP_Create_IoSignal(DrvTSP_IoSignal *pstIoSignal); 1066 TSP_Result MDrv_TSP_Close_IoSignal(DrvTSP_IoSignal *pstIoSignal); 1067 TSP_Result MDrv_TSP_Wait_IoSignal(DrvTSP_IoSignal *pstIoSignal); 1068 TSP_Result MDrv_TSP_Proc_IoSignal(DrvTSP_IoSignal *pstIoSignal); 1069 1070 // @TODO 1071 TSP_Result MDrv_TSP_PVR_TimeStampSetPlaybackStamp(MS_U32 u32Stamp); 1072 TSP_Result MDrv_TSP_PVR_TimeStampGetPlaybackStamp(MS_U32* u32Stamp); 1073 TSP_Result MDrv_TSP_PVR_TimeStamp(MS_BOOL bEnable); 1074 1075 TSP_Result MDrv_TSP_PVR_Eng_FltAlloc(MS_U32 u32Eng, MS_U32* pu32FltId); 1076 TSP_Result MDrv_TSP_PVR_Eng_FltFree(MS_U32 u32Eng, MS_U32 u32FltId); 1077 TSP_Result MDrv_TSP_PVR_Eng_FltSetPID(MS_U32 u32Eng, MS_U32 u32FltId, MS_U32 u32PID); 1078 TSP_Result MDrv_TSP_PVR_Eng_SetBuffer(MS_U32 u32Eng, MS_PHYADDR u32Start0, MS_PHYADDR u32Start1, MS_U32 u32Size0, MS_U32 u32Size1); 1079 TSP_Result MDrv_TSP_PVR_Eng_Start(MS_U32 u32Eng, MS_BOOL bPvrAll, MS_BOOL bStart); 1080 TSP_Result MDrv_TSP_PVR_Eng_Pause(MS_U32 u32Eng, MS_BOOL bPause); 1081 TSP_Result MDrv_TSP_PVR_Eng_GetWriteAddr(MS_U32 u32Eng, MS_PHY *pu32WriteAddr); 1082 TSP_Result MDrv_TSP_PVR_Eng_Notify(MS_U32 u32Eng, TSP_Event eEvents, P_TSP_Callback pfCallback); 1083 TSP_Result MDrv_TSP_PVR_Eng_SetPacketMode(MS_U32 u32Eng, MS_BOOL bSet); 1084 TSP_Result MDrv_TSP_PVR_Eng_TimeStampSetRecordStamp(MS_U32 u32Eng, MS_U32 u32Stamp); 1085 TSP_Result MDrv_TSP_PVR_Eng_TimeStampGetRecordStamp(MS_U32 u32Eng, MS_U32* u32Stamp); 1086 TSP_Result MDrv_TSP_PVR_Eng_FltEnable(MS_U32 u32Eng, MS_U32 u32FltId, MS_BOOL bEnable); 1087 TSP_Result MDrv_TSP_PVR_Eng_FltGetPID(MS_U32 u32Eng, MS_U32 u32FltId, MS_U32* u32PID); 1088 TSP_Result MDrv_TSP_PVR_Eng_SetCaMode(MS_U32 u32EngId, MS_U16 u16CaMode, MS_BOOL bSpsEnable); 1089 TSP_Result MDrv_TSP_PVR_Eng_MOBF_Enable(MS_U32 u32Eng, MS_BOOL bEnable, MS_U32 u32Key); 1090 1091 TSP_Result MDrv_TSP_GetFileInTimeStamp(MS_U32* u32TSLen); 1092 1093 //TSP_Result MDrv_TSP_File_SetPacketMode(TSP_PktMode PKT_Mode); 1094 1095 TSP_Result MDrv_TSP_DBG_GetDBGStatus(MS_U32 u32Sel, MS_U32* u32Status); 1096 1097 // TSP Info DDIs 1098 TSP_Result MDrv_TSP_GetCaps(TSP_Caps eCap, MS_U32 *pu32CapInfo); 1099 TSP_Result MDrv_TSP_GetStatus(TSP_HW_Status *HW_Status, TSP_SW_Status *SW_Status); 1100 TSP_Result MDrv_TSP_GetLibVer(const MSIF_Version **ppVersion); 1101 TSP_Result MDrv_TSP_SetDbgLevel(TSP_DbgLevel DbgLevel); 1102 TSP_Result MDrv_TSP_GetFWVER(MS_U32 *u32FWVer); 1103 TSP_Result MDrv_TSP_CmdQFifo_Status(MS_U8 *pu8FifoLevel); 1104 1105 1106 1107 // ----- Shold be OBSOLETED when U03 return ---- 1108 TSP_Result MDrv_TSP_FLT_DropEnable(MS_BOOL bSet); 1109 //------------------------------------------- 1110 1111 TSP_Result MDrv_TSP_RemoveDupAVPkt(MS_BOOL bEnable); 1112 TSP_Result MDrv_TSP_TEI_RemoveErrorPkt(TSP_DRV_TEI_RmPktType eDrvPktType, MS_BOOL bEnable); 1113 1114 TSP_Result MDrv_TSP_FLT_ChangeSource(MS_U32 u32FltId, TSP_FltType eTSPFltTypeSrc); 1115 TSP_Result MDrv_TSP_FLT_LiveSrcSwitch(TSP_FltType TgtFlow); 1116 1117 // ------ Common API for TSP mode setting ------ 1118 TSP_Result MDrv_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, void *pData); 1119 #define DRV_DMX_CMD_STC_ADJUST_UNIT 0x00000020UL //[u32Config]: data 1120 1121 TSP_Result MDrv_TSP_DSCMB_Functionality(TSP_DSCMB_FuncCMD eCmd, MS_U32 u32Config0, MS_U32 u32Config1 ,void *pData); 1122 1123 1124 //------------------------------------------------------------------------------------------------- 1125 // OBSOLETED 1126 //------------------------------------------------------------------------------------------------- 1127 TSP_Result MDrv_TSP_FLT_SetOwner(MS_U32 u32EngId, MS_U32 u32FltIdStart, MS_U32 u32FltIdEnd, MS_BOOL bOwner) __attribute__ ((deprecated)); // Set/Get the ranges of filters used, which is for AEON/MHEG5 share TSP filters resource. 1128 TSP_Result MDrv_TSP_FLT_ChkOwner(MS_U32 u32EngId, MS_U32 u32PidFltId) __attribute__ ((deprecated)); 1129 TSP_Result MDrv_TSP_SetHK(MS_BOOL bIsHK) __attribute__ ((deprecated)) __attribute__ ((deprecated)); 1130 TSP_Result MDrv_TSP_IsAccess(MS_U32 u32Try) __attribute__ ((deprecated)); 1131 TSP_Result MDrv_TSP_UnlockAccess(void) __attribute__ ((deprecated)); 1132 1133 TSP_Result MDrv_TSP_TTX_SecFlt_GetWriteAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHYADDR *pu32WriteAddr) __attribute__ ((deprecated)); // special case for TTX 1134 TSP_Result MDrv_TSP_GetDbgPortInfo(MS_U32 u32DbgSel,MS_U32* u32DbgInfo) __attribute__ ((deprecated)); 1135 1136 TSP_Result MDrv_TSP_BurstLen(MS_U32 u32Len) __attribute__ ((deprecated)); 1137 1138 #ifdef STC64_SUPPORT 1139 TSP_Result MDrv_TSP_STC64_Mode_Enable(MS_BOOL bEnable); 1140 TSP_Result MDrv_TSP_SetSTC64(MS_U32 u32EngId, MS_U32 u32STC_32, MS_U32 u32STC); 1141 TSP_Result MDrv_TSP_GetSTC64(MS_U32 u32EngId, MS_U32 *pu32STC_32, MS_U32 *pu32STC); 1142 #endif 1143 1144 TSP_Result MDrv_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Mode); 1145 TSP_Result MDrv_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd); 1146 1147 TSP_Result MDrv_TSP_STC_Alloc(MS_U32 *pu32EngId); 1148 TSP_Result MDrv_TSP_STC_Free(MS_U32 u32EngId); 1149 1150 TSP_Result MDrv_TSP_STCClk_Adjust(MS_U32 u32EngId, MS_BOOL bUpClk, MS_U32 u32Percentage); 1151 TSP_Result MDrv_TSP_PcrId_To_StcId(MS_U32 u32PcrFltId,MS_U32 *pu32EngId); 1152 1153 TSP_Result MDrv_TSP_Path_Alloc(DRV_TSP_PATH_TYPE eResType, MS_U32 *pu32PathId); 1154 TSP_Result MDrv_TSP_Path_Free(DRV_TSP_PATH_TYPE eResType, TSP_TSIF ePath); 1155 1156 #ifdef SECURE_PVR_ENABLE 1157 TSP_Result MDrv_TSP_Ree_TeeCmdSystem_Init(void); 1158 TSP_Result MDrv_TSP_Ree_TeeCmdSystem_Exit(void); 1159 TSP_Result MDrv_TSP_Ree_SendTeeCmd(TSP_REE_TO_TEE_CMD_TYPE cmd_type, void* param, size_t datasize); 1160 #endif //SECURE_PVR_ENABLE 1161 1162 #ifdef __cplusplus 1163 } // closing brace for extern "C" 1164 #endif 1165 1166 1167 #endif // __DRV_TSP2_H__ 1168 1169