1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 /////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 /////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file drvTSP.h 98 /// @brief Transport Stream Processer (TSP) Driver Interface 99 /// @author MStar Semiconductor,Inc. 100 /// @attention 101 /// All TSP DDI are not allowed to use in any interrupt context other than TSP ISR and Callback 102 /////////////////////////////////////////////////////////////////////////////////////////////////// 103 104 #ifndef _DRV_TSP_H_ 105 #define _DRV_TSP_H_ 106 107 #include "MsTypes.h" 108 109 #ifdef __cplusplus 110 extern "C" 111 { 112 #endif 113 114 115 //------------------------------------------------------------------------------------------------- 116 // Driver Capability 117 //------------------------------------------------------------------------------------------------- 118 119 #define DRVTSP_FILTER_DEPTH 16 // TSP_FILTER_DEPTH 120 121 /// TSP byte address alignment unit 122 #define DRVTSP_ALIGN_UNIT 8 123 124 /// TSP byte address alignment macro 125 #define DRVTSP_ALIGN(_x) ALIGN_8((MS_U32)_x) 126 127 //------------------------------------------------------------------------------------------------- 128 // Macro and Define 129 //------------------------------------------------------------------------------------------------- 130 /// Transport stream null PID 131 #define DRVTSP_PID_NULL 0x1FFF 132 #define MSIF_TSP_LIB_CODE {'T','S','P','_'} // Lib code 133 #define MSIF_TSP_LIBVER {'1','3'} // LIB version 134 #define MSIF_TSP_BUILDNUM {'0','1'} // Build Number 135 #define MSIF_TSP_CHANGELIST {'0','0','6','1','7','4','7','0'} // P4 ChangeList Number 136 137 #define TSP_DRV_VERSION /* Character String for DRV/API version */ \ 138 MSIF_TAG, /* 'MSIF' */ \ 139 MSIF_CLASS, /* '00' */ \ 140 MSIF_CUS, /* 0x0000 */ \ 141 MSIF_MOD, /* 0x0000 */ \ 142 MSIF_CHIP, \ 143 MSIF_CPU, \ 144 MSIF_TSP_LIB_CODE, /* IP__ */ \ 145 MSIF_TSP_LIBVER, /* 0.0 ~ Z.Z */ \ 146 MSIF_TSP_BUILDNUM, /* 00 ~ 99 */ \ 147 MSIF_TSP_CHANGELIST, /* CL# */ \ 148 MSIF_OS 149 150 151 //------------------------------------------------------------------------------------------------- 152 // Type and Structure 153 //------------------------------------------------------------------------------------------------- 154 /// TSP DDI return value 155 156 /// @name TSP_Result 157 /// @ref TSP_Result 158 /// return value 159 /// @{ 160 typedef enum 161 { 162 DRVTSP_FAIL = 0, 163 DRVTSP_OK, 164 DRVTSP_INVALID_PARAM, 165 DRVTSP_FUNC_ERROR, 166 DRVTSP_INVALID_SECFLT, 167 DRVTSP_NOT_SUPPORTED, 168 } TSP_Result; 169 170 /// @} 171 172 #define DOUBLE_BUFFER_ENABLE TRUE 173 #define DOUBLE_BUFFER_SWITCH FALSE 174 175 #if 0 176 /// TSP channel Type 177 typedef enum //_DrvTSP_FltType 178 { 179 // get TS from Live stream 180 E_DRVTSP_FLT_TYPE_VIDEO = 0x00000000, ///<\n 181 E_DRVTSP_FLT_TYPE_AUDIO , ///<\n 182 E_DRVTSP_FLT_TYPE_AUDIO2 , ///<\n 183 E_DRVTSP_FLT_TYPE_PVR , ///<\n 184 185 // Section Filter Group 186 E_DRVTSP_FLT_TYPE_SECTION_MASK = 0x20000000, ///<\n 187 E_DRVTSP_FLT_TYPE_SECTION , ///<\n 188 E_DRVTSP_FLT_TYPE_PCR , ///<\n 189 E_DRVTSP_FLT_TYPE_PES , ///<\n 190 E_DRVTSP_FLT_TYPE_PACKET , //[Reserved] 191 E_DRVTSP_FLT_TYPE_TELETEXT , 192 E_DRVTSP_FLT_TYPE_EMM , //[Reserved] 193 E_DRVTSP_FLT_TYPE_ECM , //[Reserved] 194 195 196 E_DRVTSP_FLT_SOURCE_TYPE_MASK = 0xC0000000, 197 E_DRVTSP_FLT_SOURCE_TYPE_LIVE = 0x80000000, 198 E_DRVTSP_FLT_SOURCE_TYPE_FILE = 0x40000000, 199 200 E_DRVTSP_FLT_TYPE_LAST_ENUM 201 202 } DrvTSP_FltType; 203 #endif 204 205 206 //TSP IF Source Enum 207 #define TSP_SRC_FROM_TSIF0_LIVE 0x00000001 208 #define TSP_SRC_FROM_TSIF0_FILE 0x00000002 209 #define TSP_SRC_FROM_TSIF1 0x00000003 210 #define TSP_SRC_FROM_TSIF2 0x00000004 211 #define TSP_SRC_FROM_MMFI0 0x00000006 212 #define TSP_SRC_FROM_MMFI1 0x00000007 213 214 215 #define DrvTSP_FltType MS_U32 216 // get TS from Live stream 217 #define E_DRVTSP_FLT_TYPE_VIDEO 0x00000000 ///<\n 218 #define E_DRVTSP_FLT_TYPE_AUDIO 0x00000001 ///<\n 219 #define E_DRVTSP_FLT_TYPE_AUDIO2 0x00000002 ///<\n 220 #define E_DRVTSP_FLT_TYPE_PVR 0x00000003 ///<\n 221 #define E_DRVTSP_FLT_TYPE_VIDEO3D 0x00000008 222 #define E_DRVTSP_FLT_TYPE_CB 0x00000009 223 224 // Section Filter Group 225 #define E_DRVTSP_FLT_TYPE_SECTION_MASK 0x01000000 ///<\n 226 #define E_DRVTSP_FLT_TYPE_SECTION 0x01000001 ///<\n 227 #define E_DRVTSP_FLT_TYPE_PCR 0x01000002 ///<\n 228 #define E_DRVTSP_FLT_TYPE_PES 0x01000003 ///<\n 229 #define E_DRVTSP_FLT_TYPE_PACKET 0x01000004 //[Reserved] 230 #define E_DRVTSP_FLT_TYPE_TELETEXT 0x01000005 231 #define E_DRVTSP_FLT_TYPE_EMM 0x01000006 //[Reserved] 232 #define E_DRVTSP_FLT_TYPE_ECM 0x01000007 //[Reserved] 233 #define E_DRVTSP_FLT_TYPE_SECTION_VER 0x01000008 234 #define E_DRVTSP_FLT_TYPE_SECTION_NO_PUSI 0x01000009 235 236 #define E_DRVTSP_FLT_TYPE_LAST_ENUM 0x0100000A 237 238 #define E_DRVTSP_FLT_MASK 0xF0800000 239 #define E_DRVTSP_FLT_SOURCE_TYPE_MASK 0xC0800000 240 #define E_DRVTSP_FLT_SOURCE_TYPE_LIVE 0x80000000 241 #define E_DRVTSP_FLT_SOURCE_TYPE_FILE 0x40000000 242 #define E_DRVTSP_FLT_SOURCE_TYPE_LIVEB E_DRVTSP_FLT_SOURCE_TYPE_FILE // Input from TS1 to File PID filter 243 #define E_DRVTSP_FLT_SOURCE_TYPE_TS1 0xC0000000 244 #define E_DRVTSP_FLT_SOURCE_TYPE_TS2 0x00800000 245 246 #define E_DRVTSP_FLT_SCMB_MASK 0x20000000 247 #define E_DRVTSP_FLT_TYPE_SCMB 0x20000000 248 #define E_DRVTSP_FLT_TYPE_SCMB_SHAREKEY 0x10000000 249 250 #define DrvTSP_FltMode MS_U32 251 #define E_DRVTSP_FLT_MODE_CONTI 0x00000000 252 #define E_DRVTSP_FLT_MODE_ONESHOT 0x00000001 253 #define E_DRVTSP_FLT_MODE_PESSCMCHK 0x00000003 //Only for PES type checking SCMB status 254 255 // optional 256 #define E_DRVTSP_FLT_MODE_CRCCHK 0x00000002 257 #define E_DRVTSP_FLT_MODE_AUTO_ADDR 0x00000004 // auto move read point mode 258 259 //-------------------------------------------------- 260 // Debug table 261 typedef enum 262 { 263 E_DRVTSP_DEBUG_CMD_NONE, 264 E_DRVTSP_DEBUG_CMD_CLEAR, 265 E_DRVTSP_DEBUG_CMD_ENABLE, 266 E_DRVTSP_DEBUG_CMD_DISABLE, 267 } DrvTSP_Debug_Cmd; 268 269 typedef enum 270 { 271 E_DRVTSP_DEBUG_SRC_TS0, 272 E_DRVTSP_DEBUG_SRC_TS1, 273 E_DRVTSP_DEBUG_SRC_TS2, 274 E_DRVTSP_DEBUG_SRC_FILE, 275 } DrvTSP_Debug_Src; 276 277 typedef enum 278 { 279 E_DRVTSP_DEBUG_TSIF_TS0, 280 E_DRVTSP_DEBUG_TSIF_TS1, 281 E_DRVTSP_DEBUG_TSIF_TSCB, 282 } DrvTSP_Debug_Tsif; 283 284 typedef enum 285 { 286 E_DRVTSP_DEBUG_FIFO_VIDEO, 287 E_DRVTSP_DEBUG_FIFO_AUDIO, 288 E_DRVTSP_DEBUG_FIFO_VIDEO3D, 289 E_DRVTSP_DEBUG_FIFO_AUDIOB, 290 } DrvTSP_Debug_Fifo; 291 292 typedef enum 293 { 294 E_DRVTSP_DEBUG_PKT_DEMUX_0, 295 E_DRVTSP_DEBUG_PKT_DEMUX_0_FILE, 296 E_DRVTSP_DEBUG_PKT_DEMUX_1, 297 E_DRVTSP_DEBUG_PKT_DEMUX_2, 298 E_DRVTSP_DEBUG_MMFI0, 299 E_DRVTSP_DEBUG_MMFI1, 300 } DrvTSP_Debug_Fifo_Src; 301 302 /// TSP channel state bit flags 303 typedef enum //_DrvTSP_FltState 304 { 305 E_DRVTSP_FLT_STATE_FREE = 0x00000000, ///<\n 306 E_DRVTSP_FLT_STATE_ALLOC = 0x00000001, ///<\n 307 E_DRVTSP_FLT_STATE_ENABLE = 0x00000002, ///<\n 308 E_DRVTSP_FLT_STATE_SCRAMBLED = 0x00000004, //[TODO] 309 E_DRVTSP_FLT_STATE_STREAM_AVAIL = 0x00000008, //[TODO] 310 E_DRVTSP_FLT_STATE_SCRAMBLED_ORG = 0x00000010, 311 E_DRVTSP_FLT_STATE_OVERFLOW = 0x00010000, //[Reserved] 312 E_DRVTSP_FLT_STATE_CBRUN = 0x40000000, // Callback processing 313 E_DRVTSP_FLT_STATE_FREEING = 0x80000000, // Free filter is running 314 E_DRVTSP_FLT_STATE_NA = 0xFFFFFFFF, 315 } DrvTSP_FltState; 316 317 318 /// TSP record mode 319 typedef enum //_DrvTSP_RecMode 320 { 321 //[TODO] rename REC_MODE to PVR_MODE 322 323 /// Record ENG0 by @ref E_DRVTSP_FLT_TYPE_PVR 324 E_DRVTSP_REC_MODE_ENG0_FLTTYPE = 0x00000000, // TSP_PVR_CTRL_ENG(0) 325 /// Record ENG1 by @ref E_DRVTSP_FLT_TYPE_PVR 326 E_DRVTSP_REC_MODE_ENG1_FLTTYPE = 0x00000001, // TSP_PVR_CTRL_ENG(1) 327 /// Record ENG0 bypass PID fliter 328 E_DRVTSP_REC_MODE_ENG0_BYPASS = 0x00000002, // TSP_PVR_CTRL_ENG(0) + TSP_PVR_CTRL_BYPASS 329 /// Record ENG1 bypass PID fliter 330 E_DRVTSP_REC_MODE_ENG1_BYPASS = 0x00000003, // TSP_PVR_CTRL_ENG(1) + TSP_PVR_CTRL_BYPASS 331 332 E_DRVTSP_REC_MODE_ENG0_FLT1CA = 0x00000004, 333 334 E_DRVTSP_REC_MODE_ENG0_FI_FLTTYPE = 0x00000008, //File-in record pid 335 336 E_DRVTSP_REC_MODE_ENG0_FI_BYPASS = 0x00000010, //File-in record all 337 338 } DrvTSP_RecMode; 339 340 /// TSP Control Mode 341 typedef enum //_DrvTSP_CtrlMode 342 { 343 /// Input From Stream Source 0 344 E_DRVTSP_CTRL_MODE_TS0, 345 /// Input From Stream Source 1 346 E_DRVTSP_CTRL_MODE_TS1, 347 /// Input From Memory 348 E_DRVTSP_CTRL_MODE_MEM, 349 /// Input From Memory 350 E_DRVTSP_CTRL_MODE_MEM_PVR, 351 /// Input From Stream Source 0, enable output to MAD 352 E_DRVTSP_CTRL_MODE_TS0_AUD, 353 /// Input From Stream Source 1, enable output to MAD 354 E_DRVTSP_CTRL_MODE_TS1_AUD, 355 /// Input From Memory, enable output to MAD 356 E_DRVTSP_CTRL_MODE_MEM_AUD, 357 /// Enable bounding option for PVR descrambled stream 358 E_DRVTSP_CTRL_MODE_PVR_TS0, 359 /// Enable Video PS enable for h264 play file 360 E_DRVTSP_CTRL_MODE_VID, 361 /// Enable bounding option for PVR descrambled stream, from TS1 362 E_DRVTSP_CTRL_MODE_PVR_CA, 363 /// Input From Stream Source 2 364 E_DRVTSP_CTRL_MODE_TS2, 365 /// Input From Stream Source 2, enable output to MAD 366 E_DRVTSP_CTRL_MODE_TS2_AUD, 367 /// Input From Stream Source 1, and output to File PID filter 368 E_DRVTSP_CTRL_MODE_TS1_FILEFLT, 369 /// Enable bounding option for PVR descrambled stream 370 E_DRVTSP_CTRL_MODE_PVR_TS0_CA, 371 /// Input From Memory, but not pass through CA 372 E_DRVTSP_CTRL_MODE_MEM_NOCA, 373 /// Enable bounding option for PVR1 descrambled stream 374 E_DRVTSP_CTRL_MODE_PVR1_CA, 375 /// Enable bounding option for PVR descrambled stream, from TS1, output to TS2 376 E_DRVTSP_CTRL_MODE_PVR_TS2_CA, 377 /// Input From Stream Source 0, but not pass through CA 378 E_DRVTSP_CTRL_MODE_TS0_NOCA, 379 /// Input From Stream Source 1, CA output to Live0 380 E_DRVTSP_CTRL_MODE_TS1_OUT_LIVE0, 381 382 } DrvTSP_CtrlMode; 383 384 /// TSP input pad selection 385 typedef enum 386 { 387 E_DRVTSP_PAD_DEMOD = 0x0, 388 E_DRVTSP_PAD_EXT_INPUT0 = 0x1, 389 E_DRVTSP_PAD_EXT_INPUT1 = 0x2, 390 E_DRVTSP_PAD_EXT_INPUT2 = 0x4, 391 E_DRVTSP_PAD_TSO = 0x8, 392 } DrvTSP_PadIn; 393 394 /// TSP interface 395 typedef enum 396 { 397 E_DRVTSP_IF_PLAYBACK = 0x0, // TS interface 0 398 E_DRVTSP_IF_PVR0 = 0x1, 399 E_DRVTSP_IF_PVR1 = 0x2, 400 E_DRVTSP_IF_NUM, 401 402 } DrvTSP_If; 403 404 typedef struct 405 { 406 DrvTSP_PadIn ePad; 407 MS_BOOL bClkInv; 408 MS_BOOL bExtSync; 409 MS_BOOL bParallel; 410 } DrvTSP_If_Set; 411 412 //---------------------------------- 413 /// DMX debug table information structure 414 //---------------------------------- 415 typedef struct 416 { 417 DrvTSP_Debug_Cmd TspCmd; 418 DrvTSP_Debug_Src TspSrc; 419 DrvTSP_Debug_Fifo TspFifo; 420 } DrvTSP_DisContiCnt_info, DrvTSP_DropPktCnt_info; 421 422 typedef struct 423 { 424 DrvTSP_Debug_Cmd TspCmd; 425 DrvTSP_Debug_Tsif TspTsif; 426 } DrvTSP_LockPktCnt_info; 427 428 typedef struct 429 { 430 DrvTSP_Debug_Cmd TspCmd; 431 DrvTSP_Debug_Fifo TspFifo; 432 DrvTSP_Debug_Fifo_Src TspFifoSrc; 433 } DrvTSP_AVPktCnt_info; 434 435 typedef enum 436 { 437 /// TSP Engine 0 Transport Stream 438 E_DRVTSP_FILEIN_MODE_ENG0_TS = 0x00000000, //TSP_TSDMA_CTRL_ENG0 439 /// TSP Engine 0 Video PES Only 440 E_DRVTSP_FILEIN_MODE_ENG0_VPES = 0x00000004, //TSP_TSDMA_CTRL_VPES0 441 /// TSP Engine 0 Audio PES Only 442 E_DRVTSP_FILEIN_MODE_ENG0_APES = 0x00000008, //TSP_TSDMA_CTRL_APES0 443 /// TSP Engine 0 Audio2 PES Only 444 E_DRVTSP_FILEIN_MODE_ENG0_A2PES = 0x00000010, //TSP_TSDMA_CTRL_A2PES0 445 /// TSP Engine 0 Video3D PES Only 446 E_DRVTSP_FILEIN_MODE_ENG0_V3DPES = 0x00000020, //TSP_TSDMA_CTRL_V3DPES0 447 } DrvTSP_FileinMode; 448 449 450 typedef enum 451 { 452 /// Command Queue is Idle 453 E_DRVTSP_FILEIN_STATE_IDLE = 0000000000, 454 /// Command Queue is Busy 455 E_DRVTSP_FILEIN_STATE_BUSY = 0x00000001, 456 /// Command Queue is Paused. 457 E_DRVTSP_FILEIN_STATE_PAUSE = 0x00000002, 458 } DrvTSP_FileinState; 459 460 #if 0 461 /// TSP notification event 462 typedef enum //_DrvTSP_Event 463 { 464 E_DRVTSP_EVENT_DATA_INIT = 0x00000000, 465 /// Section Data Ready 466 E_DRVTSP_EVENT_DATA_READY = 0x00000001, 467 /// Section Buffer Overflow 468 E_DRVTSP_EVENT_BUF_OVERFLOW = 0x00000002, 469 /// PVR Buffer is Full 470 E_DRVTSP_EVENT_PVRBUF_FULL = 0x00000010, 471 /// PVR Double Buffer Overflow 472 E_DRVTSP_EVENT_PVRBUF_OVERFLOW = 0x00000020, 473 474 475 /// TSP self task callback // optional --> default is CB by poll 476 E_DRVTSP_EVENT_CB_MASK = 0x80000000, 477 E_DRVTSP_EVENT_CB_POLL = 0x00000000, 478 E_DRVTSP_EVENT_CB_SELF = 0x80000000, 479 } DrvTSP_Event; 480 #endif 481 482 #define DrvTSP_Event MS_U32 483 #define E_DRVTSP_EVENT_DATA_INIT 0x00000000 484 /// Section Data Ready 485 #define E_DRVTSP_EVENT_DATA_READY 0x00000001 486 /// Section Buffer Overflow 487 #define E_DRVTSP_EVENT_BUF_OVERFLOW 0x00000002 488 /// Section Buffer CRC error 489 #define E_DRVTSP_EVENT_SEC_CRCERR 0x00000004 490 /// PVR Buffer is Full 491 #define E_DRVTSP_EVENT_PVRBUF_FULL 0x00000010 492 /// PVR Double Buffer Overflow 493 #define E_DRVTSP_EVENT_PVRBUF_OVERFLOW 0x00000020 494 /// Channel Browser Buffer is Full 495 #define E_DRVTSP_EVENT_CBBUF_FULL 0x00000040 496 #define E_DRVTSP_EVENT_CBBUF_OVERFLOW 0x00000080 497 498 499 /// TSP self task callback // optional --> default is CB by poll 500 #define E_DRVTSP_EVENT_CB_MASK 0x80000000 501 #define E_DRVTSP_EVENT_CB_POLL 0x00000000 502 #define E_DRVTSP_EVENT_CB_SELF 0x80000000 503 504 #define DrvTSP_PKTDMXSrcType MS_U32 505 #define E_DRVTSP_PKTSRC_DEMUX0 0x00000001 506 #define E_DRVTSP_PKTSRC_DEMUXFILE 0x00000002 507 #define E_DRVTSP_PKTSRC_DEMUX1 0x00000003 508 #define E_DRVTSP_PKTSRC_DEMUX2 0x00000004 509 #define E_DRVTSP_PKTSRC_DEMUXMMFI0 0x00000006 510 #define E_DRVTSP_PKTSRC_DEMUXMMFI1 0x00000007 511 512 //Ca control path 513 #define DrvTSP_DscmbCtrl MS_U32 514 #define E_DRVTSP_CA_INPUT_LIVE0 0x00000001 515 #define E_DRVTSP_CA_INPUT_FILE0 0x00000002 516 #define E_DRVTSP_CA_INPUT_TSIF1 0x00000004 517 #define E_DRVTSP_CA_INPUT_TSIF2 0x00000800 518 #define E_DRVTSP_CA_OUTPUT_LIVE0 0x00000010 519 #define E_DRVTSP_CA_OUTPUT_FILE0 0x00000020 520 #define E_DRVTSP_CA_OUTPUT_REC0 0x00000040 521 #define E_DRVTSP_CA_OUTPUT_TSIF2 0x00000400 522 523 /// TSP file in Packet mode 524 typedef enum //_DrvTSP_PacketMode 525 { 526 E_DRVTSP_PKTMODE_188 = 0x00000000, 527 E_DRVTSP_PKTMODE_192 = 0x00000001, 528 E_DRVTSP_PKTMODE_204 = 0x00000002, 529 E_DRVTSP_PKTMODE_130 = 0x00000003, // RVU 530 E_DRVTSP_PKTMODE_134 = 0x00000004, // RVU with timestamp 531 E_DRVTSP_PKTMODE_200 = 0x00000005, // packet size with 200 (Open cable Single stream) 532 533 E_DRVTSP_PKTMODE_MERG188 = 0x00000006, // packet size with 188 (Merge stream) 534 E_DRVTSP_PKTMODE_MERG192 = 0x00000007, // packet size with 192 (Merge stream) 535 E_DRVTSP_PKTMODE_MERG200 = 0x00000008, //packet size with 200 (Open cable Merge stream) 536 537 } DrvTSP_PacketMode; 538 539 /// TSP notification event message 540 typedef struct //_DrvTSP_Msg 541 { 542 /// Union data type of message 543 union 544 { 545 /// FltInfo message 546 /// - Byte[0] : Section filter id 547 /// - Byte[1] : TSP id 548 MS_U32 FltInfo; 549 /// PvrBufId 550 /// - Byte[0] : PVR buffer id 551 MS_U32 PvrBufId; 552 553 /// Pvr1BufId; 554 /// - Byte[0] : CB buffer id 555 MS_U32 Pvr1BufId; 556 557 }; 558 559 } DrvTSP_Msg; 560 561 typedef enum //_DrvTSP_DbgLevel 562 { 563 E_DRVTSP_DBG_Release = 0, 564 E_DRVTSP_DBG_L1, // display error msg 565 E_DRVTSP_DBG_L2, // display error msg and enter while(1) 566 } DrvTSP_DbgLevel; 567 568 // legacy 569 typedef enum{ 570 E_DRVTSP_SCMB_NONE = 0x00000000, 571 E_DRVTSP_SCMB_TS = 0x00000001, 572 E_DRVTSP_SCMB_PES = 0x00000002, 573 E_DRVTSP_SCMB_TS_PES = (E_DRVTSP_SCMB_TS| E_DRVTSP_SCMB_PES), 574 } DrvTSP_Scmb_Level; 575 576 /// @name DrvTSP_Msg 577 /// Macro definitions for manipulating DrvTSP_Msg 578 /// @{ 579 #define MSG_FLTINFO_SEC_ID_MASK 0x000000FF 580 #define MSG_FLTINFO_SEC_ID_SHFT 0 581 #define MSG_FLTINFO_ENG_ID_MASK 0x0000FF00 582 #define MSG_FLTINFO_ENG_ID_SHFT 8 583 #define MSG_PVRBUF_ID_MASK 0x000000FF 584 #define MSG_PVRBUF_ID_SHFT 0 585 #define MSG_PVRBUF_ID_NULL 0xFF 586 #define MSG_CBBUF_ID_MASK 0x000000FF 587 #define MSG_CBBUF_ID_SHFT 0 588 #define MSG_CBBUF_ID_NULL 0xFF 589 590 /// @} 591 592 #define TSP_MAX_SIGFLAG_NUM 10 593 #define TSP_MAX_PVRSIGFLAG_NUM 6 594 typedef struct 595 { 596 MS_U32 u32Eng; 597 MS_U32 u32EvtWaitOpt; 598 MS_U32 u32DmxEvt; 599 MS_U32 u32TspEvt; 600 601 MS_U32 u32PvrBufFullFlag[TSP_MAX_PVRSIGFLAG_NUM]; 602 603 MS_U32 u32SecRdyFlag[TSP_MAX_SIGFLAG_NUM]; 604 MS_U32 u32SecOvfFlag[TSP_MAX_SIGFLAG_NUM]; 605 }DrvTSP_IoSignal; 606 607 typedef enum 608 { 609 E_DRVTSP_CAP_PID_FILTER_NUM = 0, // Get filter number 610 E_DRVTSP_CAP_SEC_FILTER_NUM = 1, 611 E_DRVTSP_CAP_SEC_BUF_NUM = 2, 612 613 E_DRVTSP_CAP_PVR_ENG_NUM = 3, 614 E_DRVTSP_CAP_PVR_FILTER_NUM = 4, // Get pvr filter number 615 E_DRVTSP_CAP_PVR1_FILTER_NUM = 5, // Get pvr1 filter number 616 617 E_DRVTSP_CAP_MMFI_AUDIO_FILTER_NUM = 6, // Get MM file in audio path filter number 618 E_DRVTSP_CAP_MMFI_V3D_FILTER_NUM = 7, // Get MM file in video 3D path filter number 619 620 E_DRVTSP_CAP_TSIF_NUM = 8, 621 E_DRVTSP_CAP_DEMOD_NUM = 9, 622 E_DRVTSP_CAP_TS_PAD_NUM = 10, 623 E_DRVTSP_CAP_VQ_NUM = 11, 624 625 E_DRVTSP_CAP_CA_FLT_NUM = 12, // Get dscmb filter number 626 E_DRVTSP_CAP_CA_KEY_NUM = 13, 627 628 E_DRVTSP_CAP_FW_ALIGN = 14, 629 E_DRVTSP_CAP_VQ_ALIGN = 15, 630 E_DRVTSP_CAP_VQ_PITCH = 16, 631 E_DRVTSP_CAP_SEC_BUF_ALIGN = 17, 632 633 E_DRVTSP_CAP_PVR_ALIGN = 18, 634 E_DRVTSP_CAP_PVRCA_PATH_NUM = 19, 635 E_DRVTSP_CAP_SHAREKEY_FLT_RANGE = 20, 636 E_DRVTSP_CAP_PVRCA0_FLT_RANGE = 21, 637 E_DRVTSP_CAP_PVRCA1_FLT_RANGE = 22, 638 E_DRVTSP_CAP_PVRCA2_FLT_RANGE = 23, 639 E_DRVTSP_CAP_SHAREKEY_FLT1_RANGE = 24, 640 E_DRVTSP_CAP_SHAREKEY_FLT2_RANGE = 25, 641 642 E_DRVTSP_CAP_HW_TYPE = 26, 643 644 E_DRVTSP_CAP_RESOURCE_SIZE = 27, // Get the data structure size of private resource (share resource) 645 646 E_DRVTSP_CAP_VFIFO_NUM = 28, // Get VFIFO support number 647 E_DRVTSP_CAP_AFIFO_NUM = 29, // Get AFIFO support number 648 649 E_DRVTSP_CAP_HWPCR_SUPPORT = 30, // Get HWPCR support status 650 E_DRVTSP_CAP_PCRFLT_START_IDX = 31, // Get PCR start index 651 652 E_DRVTSP_CAP_HWWP_SET_NUM = 32, // Get TSP write protect set numbers 653 654 E_DRVTSP_CAP_DSCMB_ENG_NUM = 33, // Get DSCMB engine numbers 655 656 E_DRVTSP_CAP_MAX_MERGESTR_NUM = 34, // Get Maxumum merge stream number 657 E_DRVTSP_CAP_MAX_SEC_FLT_DEPTH = 35, 658 E_DRVTSP_CAP_FW_BUF_SIZE = 36, 659 E_DRVTSP_CAP_FW_BUF_RANGE = 37, 660 E_DRVTSP_CAP_VQ_BUF_RANGE = 38, 661 E_DRVTSP_CAP_SEC_BUF_RANGE = 39, 662 E_DRVTSP_CAP_FIQ_NUM = 40, 663 664 E_DRVTSP_CAP_NULL, 665 } DrvTSP_Cap; 666 667 typedef enum 668 { 669 E_DRVTSP_HW_STATUS = 0, 670 E_DRVTSP_HW_INIT, 671 E_DRVTSP_HW_ALIVE, 672 E_DRVTSP_HW_DEALIVE, 673 } DrvTSP_HW_Status; 674 675 typedef enum 676 { 677 E_DRVTSP_SW_INIT = 0, 678 E_DRVTSP_SW_INIT_FAIL, 679 E_DRVTSP_SW_SUSPEND, 680 E_DRVTSP_SW_RESUME, 681 E_DRVTSP_SW_POWEROFF, 682 E_DRVTSP_SW_CLOSE, 683 E_DRVTSP_SW_EXIT, 684 } DrvTSP_SW_Status; 685 686 // TSP event define 687 #define TSP_TASK_EVENT_SECTION_SELF 0x00000001 688 #define TSP_TASK_EVENT_SECTION_POLL 0x00000002 689 #define TSP_TASK_EVENT_PVR0_RDY_SELF 0x00000004 690 #define TSP_TASK_EVENT_PVR1_RDY_SELF 0x00000008 691 #define TSP_TASK_EVENT_PVR0_RDY_POLL 0x00000010 692 #define TSP_TASK_EVENT_PVR1_RDY_POLL 0x00000020 693 #define TSP_TASK_EVENT_FLT_FREE 0x00000040 694 #define TSP_TASK_EVENT_CBPVR0_RDY_SELF 0x00000080 695 #define TSP_TASK_EVENT_CBPVR0_RDY_POLL 0x00000100 696 #define TSP_TASK_EVENT_FWMSG 0x00000200 697 #define TSP_TASK_EVENT_GROUP_SELF ( TSP_TASK_EVENT_SECTION_SELF | \ 698 TSP_TASK_EVENT_PVR0_RDY_SELF | \ 699 TSP_TASK_EVENT_PVR1_RDY_SELF ) 700 701 #define TSP_TASK_EVENT_GROUP_POLL ( TSP_TASK_EVENT_SECTION_POLL | \ 702 TSP_TASK_EVENT_PVR0_RDY_POLL | \ 703 TSP_TASK_EVENT_PVR1_RDY_POLL ) 704 705 /// TSP notification function 706 typedef void (*P_DrvTSP_EvtCallback)(DrvTSP_Event eEvent, DrvTSP_Msg *pMsg); 707 708 //------------------------------------------------------------------------------------------------- 709 // Function and Variable 710 //------------------------------------------------------------------------------------------------- 711 712 // General API 713 TSP_Result MDrv_TSP_InitLibResource(void *pu32ResMemAddr); 714 TSP_Result MDrv_TSP_Init(MS_PHY u32FWAddr, MS_U32 u32FWSize); // Set FW address and size 715 TSP_Result MDrv_TSP_Reinit(MS_BOOL bHK); //for utopia 2.0 716 TSP_Result MDrv_TSP_PowerOff(void); 717 TSP_Result MDrv_TSP_Exit(void); 718 TSP_Result MDrv_TSP_Suspend(void); 719 TSP_Result MDrv_TSP_Resume(MS_PHY u32FWAddr, MS_U32 u32FWSize); 720 TSP_Result MDrv_TSP_Alive(MS_U32 u32EngId); 721 TSP_Result MDrv_TSP_Reset(void); 722 TSP_Result MDrv_TSP_HW_Lock_Release(void); 723 TSP_Result MDrv_TSP_RemoveDupAVPkt(MS_BOOL bEnable); 724 TSP_Result MDrv_TSP_RemoveDupAVFifoPkt(DrvTSP_FltType flttype, MS_BOOL bEnable); 725 TSP_Result MDrv_TSP_FLT_LiveSrcSwitch(DrvTSP_FltType eFltSrcType); 726 TSP_Result MDrv_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable); 727 728 // Misc API 729 TSP_Result MDrv_TSP_SetFwDBGParam(MS_PHY phyAddr, MS_U32 u32Size, MS_U32 u32DbgWord); // for TSP f/w debug 730 TSP_Result MDrv_TSP_SetOperateMode(MS_U32 u32EngId, DrvTSP_CtrlMode eCtrlMode); // Set TSP internal operate 731 TSP_Result MDrv_TSP_SelPad(MS_U32 u32EngId, DrvTSP_If eIf, DrvTSP_If_Set* pIfSet); // Set TSP input pad and ts0/ts1 732 TSP_Result MDrv_TSP_AVFifo_Reset(DrvTSP_FltType eFilterType, MS_BOOL bFlush); 733 TSP_Result MDrv_TSP_AVFifo_Status(DrvTSP_FltType eFilterType, MS_U32 *u32FifoLevel); 734 TSP_Result MDrv_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, DrvTSP_If eIf, MS_BOOL bInvert); 735 TSP_Result MDrv_TSP_Get_FW_VER(MS_U32* u32FWVer); 736 TSP_Result MDrv_TSP_Get_Intr_Count(MS_U32* pu32Count); 737 TSP_Result MDrv_TSP_Scmb_Status(MS_U32 u32EngId, DrvTSP_Scmb_Level* pScmbLevel); 738 TSP_Result MDrv_TSP_Dscmb_Path(MS_U32 u32EngId, DrvTSP_DscmbCtrl *pScmbPath, MS_BOOL bSet); 739 740 TSP_Result MDrv_TSP_GetLastErr(void); 741 TSP_Result MDrv_TSP_Proc(MS_U32 u32EngId, MS_U32 u32FltId, TSP_Result* pRet, DrvTSP_Event* pEvt); // for non-OS TSP scheduling 742 TSP_Result MDrv_TSP_GetSTC(MS_U32 u32EngId, MS_U32 *pu32STC_32, MS_U32 *pu32STC); 743 TSP_Result MDrv_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC_32, MS_U32 u32STC); 744 TSP_Result MDrv_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd); 745 TSP_Result MDrv_TSP_GetPCR(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr); 746 TSP_Result MDrv_TSP_Flt_GetState(MS_U32 u32EngId, MS_U32 u32FltId, DrvTSP_FltState *peState); // Get PIDFlt and SecFlt state 747 TSP_Result MDrv_TSP_SetPacketMode(MS_U32 u32TSIf, DrvTSP_PacketMode eDrvPktMode); 748 TSP_Result MDrv_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID, MS_U8 u8SyncByte); 749 750 #ifdef STC64_SUPPORT 751 TSP_Result MDrv_TSP_STC64_Mode_Enable(MS_BOOL bEnable); 752 #endif 753 TSP_Result MDrv_TSP_STCClk_Adjust(MS_U32 u32EngId, MS_BOOL bUpClk, MS_U32 u32Percentage); 754 755 756 // NDS --> ECM 757 TSP_Result MDrv_TSP_SecFlt_SetEcmIdx(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32EcmIdx); 758 759 // PIDFlt API 760 TSP_Result MDrv_TSP_PidFlt_Alloc(MS_U32 u32EngId, DrvTSP_FltType eFilterType, MS_U32 *pu32PidFltId); 761 TSP_Result MDrv_TSP_PidFlt_Free(MS_U32 u32EngId, MS_U32 u32PidFltId); 762 TSP_Result MDrv_TSP_PidFlt_SetPid(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32PID); 763 TSP_Result MDrv_TSP_PidFlt_GetPid(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32* pu32PID); 764 TSP_Result MDrv_TSP_PidFlt_SelSecFlt(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32SecFltId); 765 TSP_Result MDrv_TSP_PidFlt_Enable(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_BOOL bEnable); 766 TSP_Result MDrv_TSP_PidFlt_GetState(MS_U32 u32EngId, MS_U32 u32PidFltId, DrvTSP_FltState *peState); 767 TSP_Result MDrv_TSP_PidFlt_PVREnable(MS_U32 u32EngId, MS_U32 u32PidFltId); //only for debug 768 TSP_Result MDrv_TSP_PidFlt_ChangeSource(MS_U32 u32EngId, MS_U32 u32PidFltId, DrvTSP_FltType eFilterType); 769 TSP_Result MDrv_TSP_PidFlt_GetScmbSts(DrvTSP_FltType FltSrc, MS_U32 u32FltGroupId, MS_U32 PidFltId, MS_U32 *pu32ScmbSts); 770 771 772 // SecFlt API 773 TSP_Result MDrv_TSP_SecFlt_Alloc(MS_U32 u32EngId, MS_U32 *pu32SecFltId); 774 TSP_Result MDrv_TSP_SecFlt_Free(MS_U32 u32EngId, MS_U32 u32SecFltId); 775 TSP_Result MDrv_TSP_SecFlt_SetMode(MS_U32 u32EngId, MS_U32 u32SecFltId, DrvTSP_FltMode eSecFltMode); 776 TSP_Result MDrv_TSP_SecFlt_SetPattern(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Match, MS_U8 *pu8Mask, MS_U8 *pu8NotMask); 777 TSP_Result MDrv_TSP_SecFlt_ResetBuffer(MS_U32 u32EngId, MS_U32 u32SecFltId); 778 TSP_Result MDrv_TSP_SecFlt_SetBuffer(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY u32StartAddr, MS_U32 u32BufSize); 779 TSP_Result MDrv_TSP_SecFlt_SetReqCount(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32ReqCount); 780 TSP_Result MDrv_TSP_SecFlt_GetBufStart(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pu32BufStart); 781 TSP_Result MDrv_TSP_SecFlt_GetBufSize(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 *pu32BufSize); 782 TSP_Result MDrv_TSP_SecFlt_GetReadAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pu32ReadAddr); 783 TSP_Result MDrv_TSP_SecFlt_GetWriteAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pu32WriteAddr); 784 785 TSP_Result MDrv_TSP_SecFlt_SetReadAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY u32ReadAddr); 786 TSP_Result MDrv_TSP_SecFlt_Notify(MS_U32 u32EngId, MS_U32 u32SecFltId, DrvTSP_Event eEvents, P_DrvTSP_EvtCallback pfCallback); 787 TSP_Result MDrv_TSP_SecFlt_GetState(MS_U32 u32EngId, MS_U32 u32SecFltId, DrvTSP_FltState *peState); 788 789 // PVR API 790 TSP_Result MDrv_TSP_PVR_SetBuffer(MS_PHY u32BufStart0, MS_PHY u32BufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1); 791 TSP_Result MDrv_TSP_PVR_Start(DrvTSP_RecMode eRecMode, MS_BOOL bStart); 792 TSP_Result MDrv_TSP_PVR_GetWriteAddr(MS_PHY *pu32WriteAddr); 793 TSP_Result MDrv_TSP_PVR_Notify(DrvTSP_Event eEvents, P_DrvTSP_EvtCallback pfCallback); 794 TSP_Result MDrv_TSP_PVR_SetPacketMode(MS_BOOL bSet); 795 TSP_Result MDrv_TSP_PVR_TimeStampSetRecordStamp(MS_U32 u32Stamp); 796 TSP_Result MDrv_TSP_PVR_TimeStampGetRecordStamp(MS_U32* u32Stamp); 797 TSP_Result MDrv_TSP_PVR_TimeStampSetPlaybackStamp(MS_U32 u32Stamp); 798 TSP_Result MDrv_TSP_PVR_TimeStampGetPlaybackStamp(MS_U32* u32Stamp); 799 TSP_Result MDrv_TSP_PVR_TimeStamp(MS_BOOL bEnable); 800 TSP_Result MDrv_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD, MS_BOOL bEnable); //only for debug 801 802 //PVRCA API 803 TSP_Result MDrv_TSP_PVR_PidFlt_Reserved(MS_U32 Pid, MS_U8* pu8DmxId, MS_BOOL bReserved); 804 TSP_Result MDrv_TSP_PVR_FLT1_StartRec(MS_BOOL bEnable); 805 TSP_Result MDrv_TSP_PVRCA_Close(MS_U8 u8PVRId); 806 807 808 // PVR engine API 809 TSP_Result MDrv_TSP_PVR_Eng_SetBuffer(MS_U8 u8PVRId, MS_PHY u32BufStart0, MS_PHY u32BufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1); 810 TSP_Result MDrv_TSP_PVR_Eng_Start(MS_U8 u8PVRId, DrvTSP_RecMode eRecMode, MS_BOOL bStart); 811 TSP_Result MDrv_TSP_PVR_Eng_GetWriteAddr(MS_U8 u8PVRId, MS_PHY *pu32WriteAddr); 812 TSP_Result MDrv_TSP_PVR_Eng_Notify(MS_U8 u8PVRId, DrvTSP_Event eEvents, P_DrvTSP_EvtCallback pfCallback); 813 TSP_Result MDrv_TSP_PVR_Eng_SetPacketMode(MS_U8 u8PVRId, MS_BOOL bSet); 814 TSP_Result MDrv_TSP_PVR_Eng_TimeStampSetRecordStamp(MS_U8 u8PVRId, MS_U32 u32Stamp); 815 TSP_Result MDrv_TSP_PVR_Eng_TimeStampGetRecordStamp(MS_U8 u8PVRId,MS_U32* u32Stamp); 816 TSP_Result MDrv_TSP_PVR_Eng_SetPlaybackStampClk(MS_U32 u32EngId, MS_U32 u32Clk); 817 TSP_Result MDrv_TSP_PVR_Eng_SetRecordStampClk(MS_U32 u32PvrId, MS_U32 u32Clk); 818 TSP_Result MDrv_TSP_PVR_Eng_IsStart(MS_U32 u32PvrId, MS_BOOL *pbIsStart); 819 820 // File API 821 TSP_Result MDrv_TSP_File_SetAddr(MS_PHY u32StreamAddr); 822 TSP_Result MDrv_TSP_File_SetSize(MS_U32 u32StreamSize); 823 TSP_Result MDrv_TSP_File_Start(DrvTSP_FileinMode eFileinMode); 824 TSP_Result MDrv_TSP_File_Stop(void); 825 TSP_Result MDrv_TSP_File_Pause(void); 826 TSP_Result MDrv_TSP_File_Resume(void); 827 TSP_Result MDrv_TSP_File_GetState(DrvTSP_FileinState *peFileinState); 828 TSP_Result MDrv_TSP_File_SetRate(MS_U32 u32Div2); 829 TSP_Result MDrv_TSP_File_SetPacketMode(DrvTSP_PacketMode PKT_Mode); 830 TSP_Result MDrv_TSP_File_CMDQ_GetSlot(MS_U32 *pu32EmptySlot); 831 TSP_Result MDrv_TSP_File_CMDQ_Reset(void); 832 TSP_Result MDrv_TSP_CmdQFifo_Status(MS_U8 *pu8FifoLevel); 833 TSP_Result MDrv_TSP_File_192BlockScheme_En(MS_BOOL bEnable); 834 TSP_Result MDrv_TSP_File_PS_Path_Enable(DrvTSP_FileinMode eFileinMode); 835 TSP_Result MDrv_TSP_File_GetReadAddr(MS_PHY *pu32ReadAddr); 836 837 // Capacity query 838 TSP_Result MDrv_TSP_GetCap(DrvTSP_Cap eCap, void* pOutput); 839 TSP_Result MDrv_TSP_GetStatus(DrvTSP_HW_Status *HW_Status, DrvTSP_SW_Status *SW_Status); 840 TSP_Result MDrv_TSP_GetLibVer(const MSIF_Version **ppVersion); 841 TSP_Result MDrv_TSP_SetDbgLevel(DrvTSP_DbgLevel DbgLevel); 842 TSP_Result MDrv_TSP_GetTSIFStatus(DrvTSP_If eIf, DrvTSP_If_Set* pIfSet, MS_U16 u16Clock); 843 TSP_Result MDrv_TSP_GetPesScmbSts(MS_U8 u8FltId, MS_U8 *pu8status); 844 TSP_Result MDrv_TSP_GetTsScmbSts(MS_U8 u8FltId, MS_U8 *pu8status); 845 846 847 //------------------------------------------------------------------------------------------------- 848 // OBSOLETE 849 //------------------------------------------------------------------------------------------------- 850 TSP_Result MDrv_TSP_Flt_SetOwner(MS_U32 u32EngId, MS_U32 u32FltIdStart, MS_U32 u32FltIdEnd, MS_BOOL bOwner); // Set/Get the ranges of filters used, which is for AEON/MHEG5 share TSP filters resource. 851 TSP_Result MDrv_TSP_PidFlt_ChkOwner(MS_U32 u32EngId, MS_U32 u32PidFltId); 852 TSP_Result MDrv_TSP_SetHK(MS_BOOL bIsHK); 853 TSP_Result MDrv_TSP_IsAccess(MS_U32 u32Try); 854 TSP_Result MDrv_TSP_UnlockAccess(void); 855 856 TSP_Result MDrv_TSP_TTX_SecFlt_GetWriteAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pu32WriteAddr); // special case for TTX 857 TSP_Result MDrv_TSP_GetDbgPortInfo(MS_U32 u32DbgSel,MS_U32* u32DbgInfo); 858 859 TSP_Result MDrv_TSP_BurstLen(MS_U32 u32Len); 860 TSP_Result MDrv_TSP_GetFileInTimeStamp(MS_U32* u32TSLen); 861 TSP_Result MDrv_TSP_SetAVPause(MS_BOOL bSet); 862 #if 0 863 TSP_Result MDrv_TSP_ResetFileinTimestamp(void); 864 #endif 865 866 //--VQ , MOBF -------------- 867 TSP_Result MDrv_TSP_SetVQueBuf(MS_PHY u32VQBaseAddr, MS_U32 u32VQBufLen); 868 TSP_Result MDrv_TSP_VQueEnable(MS_BOOL bEnable); 869 TSP_Result MDrv_TSP_VQueReset(void); 870 TSP_Result MDrv_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable); 871 TSP_Result MDrv_TSP_Set_VQ_Threshold(MS_U8 u8req_len); 872 TSP_Result MDrv_TSP_Get_VQStatus(MS_U32* pu32Status); 873 874 TSP_Result MDrv_TSP_Set_MOBF_PVRKey(MS_U32 u32Key0, MS_U32 u32Key1); 875 TSP_Result MDrv_TSP_Set_MOBF_PVR1Key(MS_U32 u32Key0, MS_U32 u32Key1); 876 TSP_Result MDrv_TSP_Set_MOBF_FileinKey(MS_U32 u32Key); 877 TSP_Result MDrv_TSP_MOBF_PVR_Enable(MS_BOOL benable); 878 TSP_Result MDrv_TSP_MOBF_FileIn_Enable(MS_BOOL benable); 879 880 void MDrv_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pu32StartAddr, MS_PHY* pu32EndAddr); 881 void MDrv_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY u32StartAddr, MS_PHY u32EndAddr); 882 TSP_Result MDrv_TSP_TSIF_Enable(DrvTSP_If tsif, MS_BOOL bEnable); 883 TSP_Result MDrv_TSP_ReadDropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt); 884 885 //--- Common Interface for TSP config and Api commands ------------// 886 TSP_Result MDrv_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1 ,void *pData); 887 888 TSP_Result MDrv_TSP_SetFwDataAddr(MS_PHY u32DataAddr, MS_U32 u32Size); 889 890 TSP_Result MDrv_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt); 891 892 // --Debug table -------------- 893 TSP_Result MDrv_TSP_Get_DisContiCnt(DrvTSP_DisContiCnt_info* tspInfo, MS_U32* pu32Cnt); 894 TSP_Result MDrv_TSP_Get_DropPktCnt(DrvTSP_DropPktCnt_info* tspInfo, MS_U32* pu32Cnt); 895 TSP_Result MDrv_TSP_Get_LockPktCnt(DrvTSP_LockPktCnt_info* tspInfo, MS_U32* pu32Cnt); 896 TSP_Result MDrv_TSP_Get_AVPktCnt(DrvTSP_AVPktCnt_info* tspInfo, MS_U32* pu32Cnt); 897 898 TSP_Result MDrv_TSP_Get_SecTEI_PktCount(DrvTSP_FltType FltSrc, MS_U32* pu32PktCnt); 899 TSP_Result MDrv_TSP_Reset_SecTEI_PktCount(DrvTSP_FltType FltSrc); 900 TSP_Result MDrv_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltID, MS_U32* pu32PktCnt); 901 TSP_Result MDrv_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltID); 902 903 //for 2K 904 TSP_Result MDrv_TSP_Wait_IoSignal(DrvTSP_IoSignal *pstIoSignal); 905 TSP_Result MDrv_TSP_Proc_IoSignal(DrvTSP_IoSignal *pstIoSignal); 906 TSP_Result MDrv_TSP_Get_SecEvents(MS_U32 u32Group, DrvTSP_IoSignal *pstIoSignal); 907 908 909 #ifdef __cplusplus 910 } // closing brace for extern "C" 911 #endif 912 913 914 #endif // _DRV_TSP_H_ 915