1 //<MStar Software>
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77 //<MStar Software>
78 ///////////////////////////////////////////////////////////////////////////////
79 //
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92 //
93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvTSO.c
98 /// @brief TS I/O Driver Interface
99 /// @author MStar Semiconductor,Inc.
100 /// @attention
101 /// All TSO DDI are not allowed to use in any interrupt context other than TSO ISR and Callback
102 ///////////////////////////////////////////////////////////////////////////////////////////////////
103
104 //-------------------------------------------------------------------------------------------------
105 // Include Files
106 //-------------------------------------------------------------------------------------------------
107
108 // Common Definition
109 #include "MsCommon.h"
110 #include "MsVersion.h"
111 #include "drvMMIO.h"
112
113 // Internal Definition
114 #include "asmCPU.h"
115 #include "regTSIO.h"
116 #include "drvTSIO.h"
117 #include "halTSIO.h"
118
119
120 //-------------------------------------------------------------------------------------------------
121 // Driver Compiler Options
122 //-------------------------------------------------------------------------------------------------
123 #define DYNAMIC_VOLTAGE 0
124
125 //-------------------------------------------------------------------------------------------------
126 // Local Defines
127 //-------------------------------------------------------------------------------------------------
128
129 #define TSIO_MUTEX_WAIT_TIME 0xFFFFFFFFUL
130 #define TSIO_LOCDEC_SETKEY_TIMEOUT 0x00000014UL //20 ms
131 #define TSIO_STACK_SIZE 0x1000
132
133 #define TSIO_DBGERR(fmt,args...) {if(_tsiodbglevel >= E_DRVTSIO_DBG_ERR) \
134 printf("[ERROR][%s][%d]" fmt "\n" ,__FUNCTION__,__LINE__,##args);}
135 #define TSIO_DBGINFO(fmt,args...) {if(_tsiodbglevel >= E_DRVTSIO_DBG_INFO) \
136 printf("[%s][%d]" fmt "\n" ,__FUNCTION__,__LINE__,##args);}
137 #define TSIO_DBGTRACE(fmt,args...) {if(_tsiodbglevel >= E_DRVTSIO_DBG_TRACE) \
138 printf("[%s][%d]" fmt "\n" ,__FUNCTION__,__LINE__,##args);}
139
140 #define _TSIO_ENTRY() if (!MsOS_ObtainMutex(_ptsio_res->_s32TSIOMutexId, TSIO_MUTEX_WAIT_TIME)) \
141 { \
142 return DRVTSIO_FAIL; \
143 }
144
145 #define _TSIO_RETURN(_ret) do{ \
146 MsOS_ReleaseMutex(_ptsio_res->_s32TSIOMutexId); \
147 return _ret; \
148 }while(0);
149
150 #define TSIO_CB(Type, Value, ext1, ext2) do{ \
151 if (_TSIO_CbFn != NULL) \
152 { \
153 _TSIO_CbFn(Type, Value, ext1, ext2); \
154 } \
155 }while(0);
156
157
158 #define TSIO_TASK_EVENTS 0xFFFFFFFF
159 #define TSIO_EVENT(type) (0x1 << type)
160 #define TSIO_EVENT_GET(event,type) (event & (0x1 << type))
161 #define TSIO_SGDMAIN_INT_SET(sid) _u64SgdmainInt |= ((MS_U64)0x1 << sid);
162 #define TSIO_SGDMAIN_INT_GET(sid) ((_u64SgdmainInt >> sid) & 0x1)
163 #define TSIO_SGDMAIN_INT_CLR(sid) (_u64SgdmainInt &=~((MS_U64)0x1 << sid))
164 #define TSIO_SGDMAOUT_INT_SET(sid, type) _u64SgdmaoutInt[type-1] |= ((MS_U64)0x1 << sid);
165 #define TSIO_SGDMAOUT_INT_GET(sid, type) ((_u64SgdmaoutInt[type-1] >> sid) & 0x1)
166 #define TSIO_SGDMAOUT_INT_CLR(sid, type) (_u64SgdmaoutInt[type-1] &=~((MS_U64)0x1 << sid))
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Structures
170 //-------------------------------------------------------------------------------------------------
171
172 typedef enum
173 {
174 E_TSIO_SERVICESTATE_FREE = 0x00000000UL,
175 E_TSIO_SERVICESTATE_ALLOC = 0x00000001UL,
176 E_TSIO_SERVICESTATE_ENABLE = 0x00000002UL,
177 E_TSIO_SERVICESTATE_NA = 0xFFFFFFFFUL,
178 }TSIO_SERVICESTATE;
179
180 typedef struct
181 {
182 TSIO_SERVICESTATE eState;
183 MS_U8 u8Sid;
184 MS_BOOL btoTSP; //1: TSP, 0: SGDMA_out
185 MS_BOOL bDecrypt;
186 MS_BOOL bkeyEvenSet;
187 MS_U8 u8keyEven[TSIO_LOCKEY_LEN];
188 MS_BOOL bkeyOddSet;
189 MS_U8 u8keyOdd[TSIO_LOCKEY_LEN];
190 }TSIO_SERVICE;
191
192 typedef struct
193 {
194 TSIO_SERVICESTATE eState;
195 MS_U16 u16FltPid;
196 MS_U8 u8Sid;
197 }TSIO_SGDMAIN_PIDFLT;
198
199 typedef struct _TSIO_RESOURCE_PRIVATE
200 {
201 MS_S32 _s32TSIOMutexId;
202 MS_S32 _s32EventId;
203 MS_S32 _s32TSIOISRTaskId;
204 MS_BOOL _bTSIOISRTaskEn;
205 MS_S32 _s32TSIOMonitorTaskId;
206 MS_BOOL _bTSIOMonitorTaskEn;
207 MS_BOOL _bAnalogphaseEn; // for analog phase issue
208 MS_U8 _u8Analogphase; // for analog phase issue
209 MS_BOOL _bBittrainingEn; //for bittraining
210 MS_U8 _u8offset; //for bittraining
211 HAL_TSIO_CLK _eClk;
212 MS_PHY _phyLastpktBufAddr; // 192 bytes (pkt size) x 64 (service num)
213 MS_U32 _u32LastpktBufSize;
214 MS_PHY _phyDMAVQBufAddr;
215 MS_U32 _u32DMAVQBufSize;
216 MS_PHY _phyDMAinNodeAddr; // 1 node need 16 bytes.
217 MS_U32 _u32DMAinNodeSize;
218 MS_PHY _phyDMAoutNodeAddr; // 1 node need 16 bytes.
219 MS_U32 _u32DMAoutNodeSize;
220 TSIO_SERVICE _Servic[TSIO_SERVICE_NUM];
221 TSIO_SGDMAIN_PIDFLT _PidFlt[TSIO_SGDMAIN_PIDFLT_NUM];
222 MS_BOOL _bDMAoutLSB[TSIO_SERVICE_NUM];
223 MS_BOOL _bSWInit;
224 }TSIO_RESOURCE_PRIVATE;
225
226
227 //-------------------------------------------------------------------------------------------------
228 // Global Variables
229 //-------------------------------------------------------------------------------------------------
230
231 static TSIO_RESOURCE_PRIVATE* _ptsio_res = NULL;
232 static DRVTSIO_SGDMA_NODE* SGDMAIN_NODE = NULL;
233 static DRVTSIO_SGDMA_NODE* SGDMAOUT_NODE = NULL;
234
235 //-------------------------------------------------------------------------------------------------
236 // Local Variables
237 //-------------------------------------------------------------------------------------------------
238 static DRVTSIO_DBGLEVEL _tsiodbglevel = E_DRVTSIO_DBG_ERR;
239 static MS_BOOL _bBankInit = FALSE;
240 #ifndef MSOS_TYPE_LINUX_KERNEL
241 static MS_U32 _TSIO_ISR_Stack[TSIO_STACK_SIZE/sizeof(MS_U32)];
242 #endif
243 static MS_U32 _TSIO_Monitor_Stack[TSIO_STACK_SIZE/sizeof(MS_U32)];
244 static MS_BOOL _CC_RX_INT = FALSE;
245 static MS_BOOL _CC_TX_INT = FALSE;
246 static MS_U16 _CC_RX_ERROR_STATUS = 0;
247 static TSIOIntCB _TSIO_CbFn = NULL;
248 static MS_BOOL _bInvSelect = 0;
249 static MS_U64 _u64SgdmainInt = 0;
250 static MS_U64 _u64SgdmaoutInt[4] = {0};
251
252 //-------------------------------------------------------------------------------------------------
253 // Local Functions
254 //-------------------------------------------------------------------------------------------------
_TSIO_InitResource(TSIO_RESOURCE_PRIVATE * preSource)255 static MS_BOOL _TSIO_InitResource(TSIO_RESOURCE_PRIVATE* preSource)
256 {
257 MS_U16 u16ii;
258
259 if(preSource == NULL)
260 {
261 return FALSE;
262 }
263
264 for (u16ii = 0; u16ii < TSIO_SERVICE_NUM; u16ii++)
265 {
266 preSource->_Servic[u16ii].eState = E_TSIO_SERVICESTATE_FREE;
267 preSource->_Servic[u16ii].bDecrypt = FALSE;
268 preSource->_Servic[u16ii].bkeyEvenSet = FALSE;
269 preSource->_Servic[u16ii].bkeyOddSet = FALSE;
270 preSource->_Servic[u16ii].u8Sid = 0xFF;
271 }
272
273 for (u16ii = 0; u16ii < TSIO_SGDMAIN_PIDFLT_NUM; u16ii++)
274 {
275 preSource->_PidFlt[u16ii].eState = E_TSIO_SERVICESTATE_FREE;
276 preSource->_PidFlt[u16ii].u16FltPid = TSIO_PID_NULL;
277 preSource->_PidFlt[u16ii].u8Sid = 0xFF;
278 HAL_TSIO_SGDMAIN_Flt_SetPid(u16ii, TSIO_PID_NULL);
279 }
280
281 preSource->_s32TSIOMutexId = -1;
282 preSource->_s32TSIOISRTaskId = -1;
283 preSource->_s32TSIOMonitorTaskId = -1;
284 preSource->_s32EventId = -1;
285 preSource->_bTSIOISRTaskEn = FALSE;
286 preSource->_bTSIOMonitorTaskEn = FALSE;
287 preSource->_bSWInit = FALSE;
288 preSource->_bAnalogphaseEn = FALSE; // for analog phase issue
289 preSource->_u8Analogphase = 0; // for analog phase issue
290 preSource->_bBittrainingEn = FALSE;
291 preSource->_u8offset = 0;
292 preSource->_eClk = HAL_TSIO_CLK_200M;
293
294 return TRUE;
295 }
296
MDrv_TSIO_Wait_IoSignal(DRVTSIO_IOSIGNAL * stIosig)297 TSIO_Result MDrv_TSIO_Wait_IoSignal(DRVTSIO_IOSIGNAL * stIosig)
298 {
299 #ifdef MSOS_TYPE_LINUX_KERNEL
300 MS_U32 u32Event = 0;
301 MS_S32 s32Ret = 0;
302 MS_U32 index = 0;
303
304 if (stIosig == NULL)
305 return DRVTSIO_INVALID_PARAM;
306
307 memset(stIosig, '\0', sizeof(DRVTSIO_IOSIGNAL));
308
309 if((s32Ret = MsOS_WaitEvent_Interrupt(_ptsio_res->_s32EventId, TSIO_TASK_EVENTS, &u32Event, E_OR_CLEAR, MSOS_WAIT_FOREVER)) <= 0)
310 {
311 if(s32Ret < 0) // -ERESTARTSYS
312 {
313 return DRVTSIO_FUNC_ERROR;
314 }
315 else
316 {
317 return DRVTSIO_FAIL;
318 }
319 }
320
321 stIosig->u32Event = u32Event;
322
323 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_LASTNODE))
324 {
325 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
326 {
327 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_LASTNODE))
328 {
329 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_LASTNODE);
330 stIosig->u64DmaoutInt[0] |= ((MS_U64)0x1 << index);
331 }
332 }
333 }
334
335 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_NODEINT))
336 {
337 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
338 {
339 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_NODEINT))
340 {
341 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_NODEINT);
342 stIosig->u64DmaoutInt[1] |= ((MS_U64)0x1 << index);
343 }
344 }
345 }
346
347 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_DROP))
348 {
349 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
350 {
351 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_DROP))
352 {
353 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_DROP);
354 stIosig->u64DmaoutInt[2] |= ((MS_U64)0x1 << index);
355 }
356 }
357 }
358
359 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_DMAEND))
360 {
361 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
362 {
363 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_DMAEND))
364 {
365 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_DMAEND);
366 stIosig->u64DmaoutInt[3] |= ((MS_U64)0x1 << index);
367 }
368 }
369 }
370
371 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAIN_DONE))
372 {
373 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
374 {
375 if (TSIO_SGDMAIN_INT_GET(index))
376 {
377 TSIO_SGDMAIN_INT_CLR(index);
378 stIosig->u64DmainInt |= ((MS_U64)0x1 << index);
379 }
380 }
381 }
382
383 TSIO_DBGINFO("stIosig->u32Event = 0x%08X \n", stIosig->u32Event);
384 TSIO_DBGINFO("stIosig->u64DmainInt_0-31 = 0x%08X \n", (MS_U32)(stIosig->u64DmainInt & 0xFFFFFFFF));
385 TSIO_DBGINFO("stIosig->u64DmainInt_31-63 = 0x%08X \n", (MS_U32)((stIosig->u64DmainInt & 0xFFFFFFFF00000000) >> 32));
386 #endif
387 return DRVTSIO_OK;
388 }
389
390 #ifndef MSOS_TYPE_LINUX_KERNEL
_TSIO_ISR_Task(void)391 static void _TSIO_ISR_Task(void)
392 {
393 MS_U32 u32Event;
394 MS_U32 index = 0;
395 _ptsio_res->_bTSIOISRTaskEn = TRUE;
396 while (_ptsio_res->_bTSIOISRTaskEn)
397 {
398 MsOS_WaitEvent(_ptsio_res->_s32EventId, TSIO_TASK_EVENTS, &u32Event, E_OR_CLEAR, MSOS_WAIT_FOREVER);
399 TSIO_DBGINFO("u32Event = 0x%08X \n", u32Event);
400
401 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_LASTNODE))
402 {
403 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
404 {
405 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_LASTNODE))
406 {
407 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_LASTNODE);
408 TSIO_CB(E_TSIO_SGDMAOUT_LASTNODE, index, 0, NULL);
409 }
410 }
411 }
412
413 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_NODEINT))
414 {
415 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
416 {
417 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_NODEINT))
418 {
419 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_NODEINT);
420 TSIO_CB(E_TSIO_SGDMAOUT_NODEINT, index, NULL, NULL);
421 }
422 }
423 }
424
425 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_DROP))
426 {
427 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
428 {
429 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_DROP))
430 {
431 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_DROP);
432 TSIO_CB(E_TSIO_SGDMAOUT_DROP, index, NULL, NULL);
433 }
434 }
435 }
436
437 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAOUT_DMAEND))
438 {
439 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
440 {
441 if (TSIO_SGDMAOUT_INT_GET(index, E_TSIO_SGDMAOUT_DMAEND))
442 {
443 TSIO_SGDMAOUT_INT_CLR(index, E_TSIO_SGDMAOUT_DMAEND);
444 TSIO_CB(E_TSIO_SGDMAOUT_DMAEND, index, 0, NULL);
445 }
446 }
447 }
448
449 if (TSIO_EVENT_GET(u32Event, E_TSIO_SGDMAIN_DONE))
450 {
451 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
452 {
453 if (TSIO_SGDMAIN_INT_GET(index))
454 {
455 TSIO_SGDMAIN_INT_CLR(index);
456 TSIO_CB(E_TSIO_SGDMAIN_DONE, index, NULL, NULL);
457 }
458 }
459 }
460
461 if (TSIO_EVENT_GET(u32Event, E_TSIO_CC_TX_DONE))
462 {
463 TSIO_CB(E_TSIO_CC_TX_DONE, 0, NULL, NULL);
464 }
465
466 if (TSIO_EVENT_GET(u32Event, E_TSIO_CC_RX_DONE))
467 {
468 TSIO_CB(E_TSIO_CC_RX_DONE, 0, NULL, NULL);
469 }
470
471 if (TSIO_EVENT_GET(u32Event, E_TSIO_LIVE_TSO_OVERFLOW))
472 {
473 TSIO_CB(E_TSIO_LIVE_TSO_OVERFLOW, 0, NULL, NULL);
474 }
475
476 if (TSIO_EVENT_GET(u32Event, E_TSIO_OPERATION_START))
477 {
478 TSIO_CB(E_TSIO_OPERATION_START, 0, NULL, NULL);
479 }
480 }
481 }
482 #endif
483
_TSIO_Monitor(void)484 static void _TSIO_Monitor(void)
485 {
486 MS_U32 u32Data = 0;
487 MS_U8 u8Gap = 0;//ANALOG_PHASE_GAP;
488 MS_BOOL bEarly = 0, bLate = 0;
489 #if (DYNAMIC_VOLTAGE == 1)
490 static MS_U8 u8Voltage = 1; //1.8v
491 static MS_BOOL bAdd = TRUE;
492 static MS_U16 u16Count = 0;
493 #endif
494 //for analog phase issue...
495 _ptsio_res->_bTSIOMonitorTaskEn = TRUE;
496 while (_ptsio_res->_bTSIOMonitorTaskEn)
497 {
498 if (_ptsio_res->_bAnalogphaseEn) //dynamic adjust analog phase
499 {
500 if (HAL_TSIO_Analogphase_Read(1))
501 {
502 bEarly = 1;
503 }
504 else
505 {
506 bEarly = 0;
507 }
508 if (HAL_TSIO_Analogphase_Read(0))
509 {
510 bLate = 1;
511 }
512 else
513 {
514 bLate = 0;
515 }
516
517 TSIO_DBGTRACE("Phase = %d, Early = 0x%X, late = 0x%X", _ptsio_res->_u8Analogphase, bEarly, bLate);
518 #if 0
519 if (bEarly || bLate)
520 {
521 TSIO_DBGINFO("Phase = %d, Early = 0x%X, late = 0x%X", _ptsio_res->_u8Analogphase, bEarly, bLate);
522 TSIO_DBGINFO("PHASE CHANGE!!!!!!!!!!");
523 HAL_TSIO_Bittraining_Setvalue(bEarly, bLate);
524 }
525 #else
526 if (bEarly)
527 {
528 TSIO_DBGTRACE("[Early] now Phase = %d", _ptsio_res->_u8Analogphase);
529 _ptsio_res->_u8Analogphase++;
530 if (_ptsio_res->_u8Analogphase > ANALOG_PHASE_MAX)
531 {
532 _ptsio_res->_u8Analogphase = ANALOG_PHASE_MIN;
533 }
534 HAL_TSIO_Analogphase_Set(_bInvSelect, _ptsio_res->_u8Analogphase, ANALOG_PHASE_GAP);
535 _bInvSelect = !_bInvSelect;
536 }
537 else if (bLate)
538 {
539 TSIO_DBGTRACE("[Late] now Phase = %d", _ptsio_res->_u8Analogphase);
540 if (_ptsio_res->_u8Analogphase == ANALOG_PHASE_MIN)
541 {
542 _ptsio_res->_u8Analogphase = ANALOG_PHASE_MAX;
543 }
544 else
545 {
546 _ptsio_res->_u8Analogphase--;
547 }
548 HAL_TSIO_Analogphase_Set(_bInvSelect, _ptsio_res->_u8Analogphase, ANALOG_PHASE_GAP);
549 _bInvSelect = !_bInvSelect;
550 }
551 #endif
552 }
553 else if (_ptsio_res->_bBittrainingEn)
554 {
555 if(HAL_TSIO_Bittraining_Getremapstate())
556 {
557
558 u32Data = HAL_TSIO_DBG_Read(0x0D55);
559 TSIO_DBGTRACE("remap state");
560 TSIO_DBGTRACE("0x0D55 = 0x%X",u32Data);
561 u32Data = HAL_TSIO_DBG_Read(0x0D45);
562 TSIO_DBGTRACE("0x0D45 = 0x%X",u32Data);
563
564 if (u32Data & D45_PH_INCR)
565 {
566 if (_ptsio_res->_u8Analogphase == ANALOG_PHASE_MAX)
567 _ptsio_res->_u8Analogphase = ANALOG_PHASE_MIN;
568 else
569 _ptsio_res->_u8Analogphase++;
570 HAL_TSIO_Analogphase_Set(_bInvSelect, _ptsio_res->_u8Analogphase, u8Gap);
571 _bInvSelect = !_bInvSelect;
572 }
573 else if (u32Data & D45_PH_DECR)
574 {
575 if (_ptsio_res->_u8Analogphase == ANALOG_PHASE_MIN)
576 _ptsio_res->_u8Analogphase = ANALOG_PHASE_MAX;
577 else
578 _ptsio_res->_u8Analogphase--;
579
580 HAL_TSIO_Analogphase_Set(_bInvSelect, _ptsio_res->_u8Analogphase, u8Gap);
581 _bInvSelect = !_bInvSelect;
582 }
583 else if (u32Data & D45_GUARD_PH_SMALL)
584 {
585 HAL_TSIO_Analogphase_Set(_bInvSelect, _ptsio_res->_u8Analogphase, --u8Gap);
586 _bInvSelect = !_bInvSelect;
587 }
588 else if (u32Data & D45_GUARD_PH_LARGE)
589 {
590 HAL_TSIO_Analogphase_Set(_bInvSelect, _ptsio_res->_u8Analogphase, ++u8Gap);
591 _bInvSelect = !_bInvSelect;
592 }
593 TSIO_DBGTRACE("Select = %d, phase = 0x%X, Gap = %d",_bInvSelect, _ptsio_res->_u8Analogphase, u8Gap);
594
595 if (HAL_TSIO_Analogphase_Read(1))
596 {
597 bEarly = 1;
598 }
599 else
600 {
601 bEarly = 0;
602 }
603 if (HAL_TSIO_Analogphase_Read(0))
604 {
605 bLate = 1;
606 }
607 else
608 {
609 bLate = 0;
610 }
611 #if (DYNAMIC_VOLTAGE == 1)
612 if (HAL_TSIO_Analogphase_GetPuhstatus() == 7)
613 {
614 if (u16Count++ >= 10)
615 {
616 if (bAdd)
617 {
618 u8Voltage++;
619 if (u8Voltage == 3)
620 {
621 bAdd = FALSE;
622 }
623 }
624 else
625 {
626 u8Voltage--;
627 if (u8Voltage == 0)
628 {
629 bAdd = TRUE;
630 }
631 }
632 HAL_TSIO_STRLD_SET(u8Voltage);
633 TSIO_DBGTRACE("==================");
634 TSIO_DBGTRACE("Change Voltage");
635 TSIO_DBGTRACE("==================\n\n");
636 u16Count = 0;
637 }
638 TSIO_DBGTRACE("==================");
639 TSIO_DBGTRACE("Voltage = %.02f v",(float)(u8Voltage*0.05 + 1.75));
640 TSIO_DBGTRACE("==================\n\n");
641 }
642 #endif
643 HAL_TSIO_Bittraining_Setvalue(bEarly, bLate);
644
645 TSIO_DBGTRACE("==================");
646 TSIO_DBGTRACE("power state = 0x%04X", HAL_TSIO_Analogphase_GetPuhstatus());
647 TSIO_DBGTRACE("dbg(D45) = 0x%08X", HAL_TSIO_DBG_Read(0xD45));
648 TSIO_DBGTRACE("phase = %d", HAL_TSIO_Bittraining_GetPhase(0));
649 TSIO_DBGTRACE("early = %d", HAL_TSIO_Bittraining_GetPhase(1));
650 TSIO_DBGTRACE("late = %d", HAL_TSIO_Bittraining_GetPhase(2));
651 TSIO_DBGTRACE("==== early's el info=====");
652 HAL_TSIO_Bittraining_GetElinfo(1);
653 TSIO_DBGTRACE("==== late's el info=====");
654 HAL_TSIO_Bittraining_GetElinfo(0);
655 TSIO_DBGTRACE("==== HW phase info=====");
656 HAL_TSIO_Bittraining_GetPhaseinfo();
657 TSIO_DBGTRACE("Prbs Errcnt = 0x%04X",HAL_TSIO_Bittraining_CheckPrbsErrcnt());
658 TSIO_DBGTRACE("==================\n\n");
659 }
660 }
661 //printf("0x%08X\n",HAL_TSIO_DBG_Read(0x0D21));
662 MsOS_DelayTask(20);
663 }
664 }
665
_TSIO_Sgdmaoutinterrupt(MS_U8 u8Chid,E_TSIO_INT_TYPE * Type)666 static MS_BOOL _TSIO_Sgdmaoutinterrupt(MS_U8 u8Chid, E_TSIO_INT_TYPE *Type)
667 {
668 MS_U16 u16Status = 0;
669
670 if (Type == NULL)
671 {
672 return FALSE;
673 }
674
675 HAL_TSIO_SGDMAOUT_IntRead(u8Chid, &u16Status);
676
677 if (u16Status == 0)
678 {
679 *Type = E_TSIO_INT_NONE;
680 return FALSE;
681 }
682 else if (u16Status & TSIO2_SGDMA_OUT_VC_STATUS_DMAEND)
683 {
684 *Type = E_TSIO_SGDMAOUT_DMAEND;
685 return TRUE;
686 }
687 else if (u16Status & TSIO2_SGDMA_OUT_VC_STATUS_DROP)
688 {
689 *Type = E_TSIO_SGDMAOUT_DROP;
690 return TRUE;
691 }
692 else if (u16Status & TSIO2_SGDMA_OUT_VC_STATUS_NODEINT)
693 {
694 *Type = E_TSIO_SGDMAOUT_NODEINT;
695 return TRUE;
696 }
697 else if (u16Status & TSIO2_SGDMA_OUT_VC_STATUS_LASTNODE)
698 {
699 *Type = E_TSIO_SGDMAOUT_LASTNODE;
700 return TRUE;
701 }
702
703 TSIO_DBGINFO("SGDMA out interrupt status error, Chid = %d Status = 0x%X \n", u8Chid, u16Status);
704 return TRUE;
705 }
706
_TSIO_Interrupt_CB_TSIO(InterruptNum eIntNum)707 static void _TSIO_Interrupt_CB_TSIO(InterruptNum eIntNum)
708 {
709 MS_U8 index = 0;
710 E_TSIO_INT_TYPE Type;
711
712 TSIO_DBGTRACE("E_INT_IRQ_TSIO_INT");
713 if (HAL_TSIO_SGDMAOUT_IntAll())
714 {
715 TSIO_DBGTRACE("TSIO_SGDMAOUT_INT_EVENT");
716 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
717 {
718 if (_TSIO_Sgdmaoutinterrupt(index, &Type))
719 {
720 TSIO_DBGINFO("idx = %d Type = %d",index, Type);
721 HAL_TSIO_SGDMAOUT_IntClr(index);
722 break;
723 }
724 }
725 if (index < TSIO_SERVICE_NUM)
726 {
727 //TSIO_CB(Type, index, NULL, NULL); //for nos test, should be move to ISR_TASK
728 TSIO_SGDMAOUT_INT_SET(index, Type);
729 if (Type == E_TSIO_SGDMAOUT_NODEINT)
730 {
731 _ptsio_res->_bDMAoutLSB[index] = !_ptsio_res->_bDMAoutLSB[index];
732 }
733 MsOS_SetEvent(_ptsio_res->_s32EventId, TSIO_EVENT(Type));
734 }
735 }
736 else if(HAL_TSIO_CC_TxInt())
737 {
738 TSIO_DBGTRACE("TSIO_CC_TX_INT_EVENT");
739 //TSIO_CB(E_TSIO_CC_TX_DONE, 0, NULL, NULL); //for nos test, should be move to ISR_TASK
740 MsOS_SetEvent(_ptsio_res->_s32EventId, TSIO_EVENT(E_TSIO_CC_TX_DONE));
741 _CC_TX_INT = TRUE;
742 HAL_TSIO_CC_TxIntClr();
743 }
744 else if (HAL_TSIO_CC_RxInt())
745 {
746 TSIO_DBGTRACE("TSIO_CC_RX_INT_EVENT");
747 _CC_RX_INT = TRUE;
748 _CC_RX_ERROR_STATUS = HAL_TSIO_CC_RxErrStatus();
749 if (_CC_RX_ERROR_STATUS)
750 {
751 HAL_TSIO_CC_RxClr();
752 HAL_TSIO_CC_RxEnable(FALSE);
753 }
754 //TSIO_CB(E_TSIO_CC_RX_DONE, _CC_RX_ERROR_STATUS, NULL, NULL); //for nos test, should be move to ISR_TASK
755 MsOS_SetEvent(_ptsio_res->_s32EventId, TSIO_EVENT(E_TSIO_CC_RX_DONE));
756 HAL_TSIO_CC_RxIntClr();
757 }
758 else if (HAL_TSIO_Int_Bittraining_Read())
759 {
760 //TBD.
761 HAL_TSIO_Int_Bittraining_Clear();
762 }
763 else if (HAL_TSIO_Int_Operation_Read())
764 {
765 HAL_TSIO_Int_Operation_Clear();
766 //TSIO_CB(E_TSIO_OPERATION_START, 0, NULL, NULL); //for nos test, should be move to ISR_TASK
767 MsOS_SetEvent(_ptsio_res->_s32EventId, TSIO_EVENT(E_TSIO_OPERATION_START));
768 }
769 MsOS_EnableInterrupt(E_INT_IRQ_TSIO_INT);
770 }
771
_TSIO_Interrupt_CB_TSO(InterruptNum eIntNum)772 static void _TSIO_Interrupt_CB_TSO(InterruptNum eIntNum)
773 {
774 MS_U8 index = 0;
775 MS_U16 u16Status = 0;
776
777 TSIO_DBGTRACE("E_INT_IRQ_TSP_TSO0");
778 if (HAL_TSIO_SGDMAIN_IntAll())
779 {
780 for (index = 0; index < TSIO_SERVICE_NUM; index ++)
781 {
782 HAL_TSIO_SGDMAIN_IntRead(index, &u16Status);
783 if (u16Status)
784 {
785 TSIO_DBGINFO("idx = %d u16Status = %d",index, u16Status);
786 HAL_TSIO_SGDMAIN_IntClr(index);
787 break;
788 }
789 }
790 if (index < TSIO_SERVICE_NUM)
791 {
792 //TSIO_CB(E_TSIO_SGDMAIN_DONE, index, NULL, NULL); //for nos test, should be move to ISR_TASK
793 TSIO_SGDMAIN_INT_SET(index);
794 MsOS_SetEvent(_ptsio_res->_s32EventId, TSIO_EVENT(E_TSIO_SGDMAIN_DONE));
795 }
796 }
797 else
798 {
799 /*
800 extern MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng);
801 extern void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int);
802 extern void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL benable, MS_U16 u16init);
803 extern MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable);
804 MS_U16 u16TsoIntStatus = 0;
805 for(index = 0; index < 2; index++)
806 index = 0;
807 {
808 u16TsoIntStatus = HAL_TSO_HWInt_Status(index);
809 if(u16TsoIntStatus)
810 {
811 HAL_TSO_ChIf_Cfg(index, 1, 0x8000, TRUE);
812 HAL_TSO_ChIf_Cfg(index, 1, 0x8000, FALSE);
813 HAL_TSO_ChIf_Cfg(index, 2, 0x8000, TRUE);
814 HAL_TSO_ChIf_Cfg(index, 2, 0x8000, FALSE);
815 HAL_TSO_ChIf_Cfg(index, 3, 0x8000, TRUE);
816 HAL_TSO_ChIf_Cfg(index, 3, 0x8000, FALSE);
817 HAL_TSO_ChIf_Cfg(index, 4, 0x8000, TRUE);
818 HAL_TSO_ChIf_Cfg(index, 4, 0x8000, FALSE);
819 HAL_TSO_HWInt_Clear(index, u16TsoIntStatus);
820 TSIO_CB(E_TSIO_LIVE_TSO_OVERFLOW, (u16TsoIntStatus >> 8), NULL, NULL); //for nos test, should be move to ISR_TASK
821 HAL_TSO_HWInt_Enable(index, TRUE, 0xFF);
822 }
823 }
824 */
825 }
826
827 MsOS_EnableInterrupt(E_INT_IRQ_TSP_TSO0);
828 }
829
_TSIO_Interrupt_Init(void)830 static MS_BOOL _TSIO_Interrupt_Init(void)
831 {
832 MsOS_AttachInterrupt(E_INT_IRQ_TSIO_INT, _TSIO_Interrupt_CB_TSIO);
833 MsOS_EnableInterrupt(E_INT_IRQ_TSIO_INT);
834 MsOS_AttachInterrupt(E_INT_IRQ_TSP_TSO0, _TSIO_Interrupt_CB_TSO);
835 MsOS_EnableInterrupt(E_INT_IRQ_TSP_TSO0);
836 return TRUE;
837 }
838
_TSIO_Interrupt_DeInit(void)839 static MS_BOOL _TSIO_Interrupt_DeInit(void)
840 {
841 MsOS_DisableInterrupt(E_INT_IRQ_TSIO_INT);
842 MsOS_DetachInterrupt(E_INT_IRQ_TSIO_INT);
843 MsOS_DisableInterrupt(E_INT_IRQ_TSP_TSO0);
844 MsOS_DetachInterrupt(E_INT_IRQ_TSP_TSO0);
845 return TRUE;
846 }
847
848 //-------------------------------------------------------------------------------------------------
849 /// Initialize lib resource API
850 /// @param pResMemAddr \b IN: Pointer to store resource memory address
851 /// @return TSIO_Result
852 /// @note
853 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_InitLibResource(void * pResMemAddr)854 TSIO_Result MDrv_TSIO_InitLibResource(void* pResMemAddr)
855 {
856 MS_VIRT virtBank;
857 MS_PHY u32BankSize;
858
859 TSIO_DBGTRACE();
860
861 if(pResMemAddr == NULL)
862 return DRVTSIO_FAIL;
863
864 _ptsio_res = (TSIO_RESOURCE_PRIVATE*)pResMemAddr;
865
866 // For multi-process use case. (different process should set the value of bank again)
867 if(_bBankInit == FALSE)
868 {
869 if (FALSE == MDrv_MMIO_GetBASE(&virtBank, &u32BankSize, MS_MODULE_TSO)) //MODULE_TSIO = ??
870 {
871 TSIO_DBGERR("MDrv_TSIO_Init failed");
872 return DRVTSIO_FAIL;
873 }
874 TSIO_DBGINFO("TSIO Base Bank 0x%08X", (unsigned int)virtBank);
875 HAL_TSIO_SetBank(virtBank);
876 _bBankInit = TRUE;
877 }
878
879 if(_ptsio_res->_bSWInit != TRUE)
880 {
881 if(_TSIO_InitResource(_ptsio_res) == FALSE)
882 return DRVTSIO_FAIL;
883 }
884
885 return DRVTSIO_OK;
886 }
887
888 //-------------------------------------------------------------------------------------------------
889 /// Get TSIO Hardware capability
890 /// @param eCap \b IN: Capability item to get
891 /// @param pOutput \b IN: Pointer to store getting result
892 /// @return TSIO_Result
893 /// @note
894 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_GetCap(DRVTSIO_CAP eCap,void * pOutput)895 TSIO_Result MDrv_TSIO_GetCap(DRVTSIO_CAP eCap, void* pOutput)
896 {
897 *((MS_U32*)pOutput) = 0;
898
899 switch (eCap)
900 {
901 case DRVTSIO_CAP_RESOURCE_SIZE:
902 *((MS_U32*)pOutput) = (MS_U32)sizeof(TSIO_RESOURCE_PRIVATE);
903 break;
904
905 default:
906 return DRVTSIO_INVALID_PARAM;
907 }
908
909 return DRVTSIO_OK;
910 }
911
912 //-------------------------------------------------------------------------------------------------
913 /// Initialize TSIO driver
914 /// @return TSIO_Result
915 /// @note
916 /// It should be called before calling any other TSIO functions.
917 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Init(void)918 TSIO_Result MDrv_TSIO_Init(void)
919 {
920 MS_VIRT virtBank;
921 MS_PHY u32BankSize;
922
923 TSIO_DBGTRACE();
924
925 if (_ptsio_res->_bSWInit)
926 {
927 TSIO_DBGINFO("MDrv_TSIO_Init already initialize");
928 return DRVTSIO_OK;
929 }
930 if (FALSE == MDrv_MMIO_GetBASE(&virtBank, &u32BankSize, MS_MODULE_TSO)) //MODULE_TSIO = ??
931 {
932 TSIO_DBGERR("MDrv_TSIO_Init failed");
933 return DRVTSIO_FAIL;
934 }
935 TSIO_DBGINFO("TSIO Base Bank 0x%08X", (unsigned int)virtBank);
936 HAL_TSIO_SetBank(virtBank);
937
938 _ptsio_res->_s32TSIOMutexId = MsOS_CreateMutex(E_MSOS_FIFO, "Mutex TSIO", MSOS_PROCESS_SHARED);
939 if(_ptsio_res->_s32TSIOMutexId == -1)
940 {
941 TSIO_DBGERR("MsOS_CreateMutex failed");
942 return DRVTSIO_FAIL;
943 }
944
945 _ptsio_res->_s32EventId = MsOS_CreateEventGroup("TSIO_EVENT");
946 if (_ptsio_res->_s32EventId == -1)
947 {
948 TSIO_DBGERR("MsOS_CreateEventGroup failed");
949 }
950
951 #ifndef MSOS_TYPE_LINUX_KERNEL
952 _ptsio_res->_s32TSIOISRTaskId = MsOS_CreateTask((TaskEntry)_TSIO_ISR_Task,
953 (MS_U32)NULL,
954 E_TASK_PRI_SYS,
955 TRUE,
956 _TSIO_ISR_Stack,
957 TSIO_STACK_SIZE,
958 (char *)"TSIO_ISR_TASK");
959 if (_ptsio_res->_s32TSIOISRTaskId == -1)
960 {
961 TSIO_DBGERR("MsOS_CreateTask failed");
962 }
963 #endif
964 _ptsio_res->_s32TSIOMonitorTaskId = MsOS_CreateTask((TaskEntry)_TSIO_Monitor,
965 (MS_U32)NULL,
966 E_TASK_PRI_MEDIUM,
967 TRUE,
968 _TSIO_Monitor_Stack,
969 TSIO_STACK_SIZE,
970 (char *)"TSIO_Monitor");
971 if (_ptsio_res->_s32TSIOMonitorTaskId == -1)
972 {
973 TSIO_DBGERR("MsOS_CreateTask failed");
974 }
975
976 _TSIO_ENTRY();
977
978 HAL_TSIO_ClkOpen(1);
979 HAL_TSIO_Reset();
980 _ptsio_res->_bSWInit = TRUE;
981 _TSIO_Interrupt_Init();
982
983 _TSIO_RETURN(DRVTSIO_OK);
984 }
985
986 //-------------------------------------------------------------------------------------------------
987 /// Open TSIO
988 /// @param eClk \b IN: clk speed
989 /// @return TSIO_Result
990 /// @note
991 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Open(DRVTSIO_CLK eClk)992 TSIO_Result MDrv_TSIO_Open(DRVTSIO_CLK eClk)
993 {
994 TSIO_DBGTRACE();
995 _TSIO_ENTRY();
996
997 _ptsio_res->_eClk = (HAL_TSIO_CLK)eClk;
998 HAL_TSIO_Analogphase_Init(_ptsio_res->_eClk,0);
999 #if (BITTRAINING_SW_MODE_ENABLE == 1)
1000 //bit training SW patch initial
1001 HAL_TSIO_Bittraining_init();
1002 #endif
1003 HAL_TSIO_PowerInit();
1004 MsOS_DelayTask(3); // for bittraining init
1005 HAL_TSIO_SGDMAIN_Reset();
1006 HAL_TSIO_SGDMAOUT_Init();
1007
1008 HAL_TSIO_STRLD_SET(3); //for tornado borad, reset voltage have to 1.9v
1009
1010 //reset vqbuffer & lastnode buffer
1011 HAL_TSIO_SGDMAIN_LastPktBuf_Set(_ptsio_res->_phyLastpktBufAddr, _ptsio_res->_phyLastpktBufAddr+_ptsio_res->_u32LastpktBufSize);
1012 HAL_TSIO_SGDMAIN_SGVQBuf_Set(_ptsio_res->_phyDMAVQBufAddr, _ptsio_res->_u32DMAVQBufSize);
1013
1014 _TSIO_RETURN(DRVTSIO_OK);
1015 }
1016
1017 //-------------------------------------------------------------------------------------------------
1018 /// Exit TSIO driver
1019 /// @return TSIO_Result
1020 /// @note
1021 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Exit(void)1022 TSIO_Result MDrv_TSIO_Exit(void)
1023 {
1024 TSIO_DBGTRACE();
1025 _TSIO_ENTRY();
1026
1027 _TSIO_Interrupt_DeInit();
1028 HAL_TSIO_ClkOpen(0);
1029
1030 MsOS_ReleaseMutex(_ptsio_res->_s32TSIOMutexId);
1031 MsOS_DeleteMutex(_ptsio_res->_s32TSIOMutexId);
1032
1033
1034 if (_ptsio_res->_s32EventId != -1)
1035 MsOS_DeleteEventGroup(_ptsio_res->_s32EventId);
1036
1037 _ptsio_res->_bTSIOISRTaskEn = FALSE;
1038 _ptsio_res->_bTSIOMonitorTaskEn = FALSE;
1039 _ptsio_res->_s32TSIOMutexId = -1;
1040 _ptsio_res->_s32EventId = -1;
1041 if (_ptsio_res->_s32TSIOISRTaskId != -1)
1042 MsOS_DeleteTask(_ptsio_res->_s32TSIOISRTaskId);
1043 if (_ptsio_res->_s32TSIOMonitorTaskId != -1)
1044 MsOS_DeleteTask(_ptsio_res->_s32TSIOMonitorTaskId);
1045 _ptsio_res->_s32TSIOISRTaskId = -1;
1046 _ptsio_res->_s32TSIOMonitorTaskId = -1;
1047 _ptsio_res->_bSWInit = FALSE;
1048 _ptsio_res->_bAnalogphaseEn = FALSE;
1049 _ptsio_res->_bBittrainingEn = FALSE;
1050 _ptsio_res->_u8offset = 0;
1051 _ptsio_res->_u8Analogphase = 0;
1052 _ptsio_res->_eClk = HAL_TSIO_CLK_200M;
1053 return DRVTSIO_OK;
1054 }
1055
1056 //-------------------------------------------------------------------------------------------------
1057 /// Close TSIO
1058 /// @return TSIO_Result
1059 /// @note
1060 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Close(void)1061 TSIO_Result MDrv_TSIO_Close(void)
1062 {
1063 TSIO_DBGTRACE();
1064 _TSIO_ENTRY();
1065
1066 HAL_TSIO_Analogphase_Exit();
1067
1068 _TSIO_RETURN(DRVTSIO_OK);
1069 }
1070
1071 //-------------------------------------------------------------------------------------------------
1072 /// Search and setting Analog phase
1073 /// @param u8offset \b IN: shift phase
1074 /// @return TSIO_Result
1075 /// @note
1076 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Analogphase_adj_bittraining(MS_U8 u8offset)1077 TSIO_Result MDrv_TSIO_Analogphase_adj_bittraining(MS_U8 u8offset)
1078 {
1079 TSIO_DBGTRACE();
1080 _TSIO_ENTRY();
1081 #if (BITTRAINING_SW_MODE_ENABLE == 1)
1082 _ptsio_res->_bBittrainingEn = TRUE;//!_ptsio_res->_bBittrainingEn;
1083 _ptsio_res->_u8offset = u8offset;
1084 #endif
1085 _TSIO_RETURN(DRVTSIO_OK);
1086 }
1087
1088 //-------------------------------------------------------------------------------------------------
1089 /// Search and setting Analog phase
1090 /// @return TSIO_Result
1091 /// @note
1092 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Analogphase_adj(void)1093 TSIO_Result MDrv_TSIO_Analogphase_adj(void)
1094 {
1095 MS_BOOL bGoodPhase[ANALOG_PHASE_NUM] = {0};
1096 MS_U8 u8index = 0;
1097 MS_U16 status = 0;
1098 MS_U32 u32Timeout = 0;
1099 MS_U8 gp_start = 0xFF, gp_max_start = 0;
1100 MS_U8 gp_end = 0, gp_max_end = 0;
1101 MS_U8 gp_count = 0, gp_max_count = 0;
1102 MS_U8 selectphase = 0;
1103 MS_U16 u16early = 0, u16late = 0;
1104 MS_BOOL bFixSel = FALSE;
1105
1106 TSIO_DBGTRACE();
1107 _TSIO_ENTRY();
1108
1109 //wait training state
1110 do
1111 {
1112 status = HAL_TSIO_Analogphase_GetPuhstatus();
1113 if (status == 5)
1114 {
1115 break;
1116 }
1117 MsOS_DelayTask(10);
1118 if (u32Timeout++ > 1000)
1119 {
1120 TSIO_DBGERR("wait training status timeout!!!!!");
1121 _TSIO_RETURN(DRVTSIO_FAIL);
1122 }
1123 }while(1);
1124
1125 do
1126 {
1127 for (u8index = ANALOG_PHASE_MIN; u8index <= ANALOG_PHASE_MAX; u8index++)
1128 {
1129 HAL_TSIO_Analogphase_Set(_bInvSelect, u8index, ANALOG_PHASE_GAP);
1130 MsOS_DelayTask(10);
1131 u16early = HAL_TSIO_Analogphase_Read(1);
1132 u16late = HAL_TSIO_Analogphase_Read(0);
1133 TSIO_DBGINFO("Early = 0x%X, late = 0x%X", u16early, u16late);
1134 if (u16early || u16late)
1135 {
1136 bGoodPhase[u8index] = FALSE;
1137 }
1138 else
1139 {
1140 bGoodPhase[u8index] = TRUE;
1141 }
1142 TSIO_DBGINFO("bGoodPhase = %d ", bGoodPhase[u8index]);
1143 if (!bFixSel)
1144 {
1145 _bInvSelect = !_bInvSelect;
1146 }
1147 }
1148
1149 gp_start = 0xFF;
1150 gp_max_start = 0;
1151 gp_end = 0;
1152 gp_max_end = 0;
1153 gp_count = 0;
1154 gp_max_count = 0;
1155 selectphase = 0;
1156
1157 for (u8index = ANALOG_PHASE_MIN; u8index <= ANALOG_PHASE_MAX; u8index++)
1158 {
1159 if (bGoodPhase[u8index] )
1160 {
1161 if (gp_start == 0xFF)
1162 {
1163 gp_end = 0xFF;
1164 gp_start = u8index;
1165 }
1166 gp_count++;
1167
1168 if (u8index == ANALOG_PHASE_MAX) //last phase
1169 {
1170 gp_end = u8index;
1171 if (gp_count > gp_max_count)
1172 {
1173 gp_max_start = gp_start;
1174 gp_max_end = gp_end;
1175 gp_max_count = gp_count;
1176 }
1177 TSIO_DBGINFO("normal: %d %d %d", gp_start, gp_end, gp_count);
1178 gp_start = 0xFF;
1179 gp_count = 0;
1180 }
1181 }
1182 else if (!bGoodPhase[u8index] && (gp_end == 0xFF))
1183 {
1184 gp_end = u8index;
1185 if (gp_count > gp_max_count)
1186 {
1187 gp_max_start = gp_start;
1188 gp_max_end = gp_end;
1189 gp_max_count = gp_count;
1190 }
1191 TSIO_DBGINFO("normal: %d %d %d", gp_start, gp_end, gp_count);
1192 gp_start = 0xFF;
1193 gp_count = 0;
1194 }
1195 }
1196 TSIO_DBGINFO("max: %d %d %d", gp_max_start, gp_max_end, gp_max_count);
1197
1198 selectphase = (gp_max_start + gp_max_end)/2;
1199 TSIO_DBGINFO("selectphase: %d", selectphase);
1200 if (gp_max_count <=1)
1201 {
1202 HAL_TSIO_Analogphase_Pllreset();
1203 bFixSel = TRUE;
1204 _bInvSelect = !_bInvSelect;
1205 }
1206 }while(0);//(gp_max_count <=1);
1207
1208 HAL_TSIO_Analogphase_Set(_bInvSelect, selectphase, ANALOG_PHASE_GAP);
1209 _bInvSelect = !_bInvSelect;
1210 HAL_TSIO_Analogphase_Start();
1211 _ptsio_res->_u8Analogphase = selectphase;
1212 _ptsio_res->_bAnalogphaseEn = TRUE;
1213
1214 _TSIO_RETURN(DRVTSIO_OK);
1215 }
1216
1217
1218 //-------------------------------------------------------------------------------------------------
1219 /// Set debug level of TSIO
1220 /// @param DbgLevel \b IN: Debug Level Value
1221 /// @return TSIO_Result
1222 /// @note
1223 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SetDbgLevel(DRVTSIO_DBGLEVEL DbgLevel)1224 TSIO_Result MDrv_TSIO_SetDbgLevel(DRVTSIO_DBGLEVEL DbgLevel)
1225 {
1226 EN_HAL_TSIO_DBGMSG_LEVEL halLevel = E_HAL_TSIO_DBG_LEVEL_NONE;
1227
1228 TSIO_DBGTRACE();
1229
1230 _tsiodbglevel = DbgLevel;
1231 TSIO_DBGINFO("Debug level : %d", _tsiodbglevel);
1232
1233 switch (DbgLevel)
1234 {
1235 case E_DRVTSIO_DBG_Release:
1236 halLevel = E_HAL_TSIO_DBG_LEVEL_NONE;
1237 break;
1238
1239 case E_DRVTSIO_DBG_ERR:
1240 halLevel = E_HAL_TSIO_DBG_LEVEL_ERR;
1241 break;
1242
1243 case E_DRVTSIO_DBG_INFO:
1244 halLevel = E_HAL_TSIO_DBG_LEVEL_INFO;
1245 break;
1246
1247 default:
1248 case E_DRVTSIO_DBG_TRACE:
1249 halLevel = E_HAL_TSIO_DBG_LEVEL_TRACE;
1250 break;
1251 }
1252
1253 HAL_TSIO_DbgLevel(halLevel);
1254 return DRVTSIO_OK;
1255 }
1256
1257 //-------------------------------------------------------------------------------------------------
1258 /// Reset TSIO driver
1259 /// @return TSIO_Result
1260 /// @note
1261 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Reset(void)1262 TSIO_Result MDrv_TSIO_Reset(void)
1263 {
1264 TSIO_DBGTRACE();
1265 _TSIO_ENTRY();
1266
1267 HAL_TSIO_Reset();
1268 MsOS_DelayTask(500); //delay for analog phase issue
1269 _TSIO_RETURN(DRVTSIO_OK);
1270 }
1271
1272 //-------------------------------------------------------------------------------------------------
1273 /// Enable bypass SMC setting on TSIO module
1274 /// @param u8Mode \b IN: 0: disable, 1: direct8, 2: direct 16, 3: loopback , bypass SMC setting
1275 /// @return TSIO_Result
1276 /// @note
1277 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_BypassSMC_Set(MS_U8 u8Mode)1278 TSIO_Result MDrv_TSIO_BypassSMC_Set(MS_U8 u8Mode)
1279 {
1280 TSIO_DBGTRACE();
1281 _TSIO_ENTRY();
1282
1283 switch (u8Mode)
1284 {
1285 case 0:
1286 default:
1287 HAL_TSIO_Tx2Rx_InsertCTS(FALSE);
1288 HAL_TSIO_Tx2Rx_Direct8(FALSE);
1289 HAL_TSIO_Tx2Rx_Direct16(FALSE);
1290 HAL_TSIO_Tx2Rx_Loopback(FALSE);
1291 break;
1292
1293 case 1:
1294 HAL_TSIO_Tx2Rx_InsertCTS(TRUE);
1295 HAL_TSIO_Tx2Rx_Direct8(TRUE);
1296 HAL_TSIO_Tx2Rx_Direct16(FALSE);
1297 HAL_TSIO_Tx2Rx_Loopback(FALSE);
1298 break;
1299
1300 case 2:
1301 HAL_TSIO_Tx2Rx_InsertCTS(TRUE);
1302 HAL_TSIO_Tx2Rx_Direct8(FALSE);
1303 HAL_TSIO_Tx2Rx_Direct16(TRUE);
1304 HAL_TSIO_Tx2Rx_Loopback(FALSE);
1305 break;
1306
1307 case 3:
1308 HAL_TSIO_Tx2Rx_InsertCTS(TRUE);
1309 HAL_TSIO_Tx2Rx_Direct8(FALSE);
1310 HAL_TSIO_Tx2Rx_Direct16(FALSE);
1311 HAL_TSIO_Tx2Rx_Loopback(TRUE);
1312 break;
1313 }
1314 _TSIO_RETURN(DRVTSIO_OK);
1315 }
1316
1317 //-------------------------------------------------------------------------------------------------
1318 /// Set Stuffing ServiceID to TSIO module
1319 /// @param u32StuffingSID \b IN: stuffing service ID
1320 /// @return TSIO_Result
1321 /// @note
1322 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_StuffingSID_Set(MS_U32 u32StuffingSID)1323 TSIO_Result MDrv_TSIO_StuffingSID_Set(MS_U32 u32StuffingSID)
1324 {
1325 TSIO_DBGTRACE();
1326 _TSIO_ENTRY();
1327
1328 if (u32StuffingSID >= TSIO_SERVICE_NUM)
1329 {
1330 TSIO_DBGERR("Invalid stuffing id, it should be less than %d",TSIO_SERVICE_NUM);
1331 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1332 }
1333
1334 HAL_TSIO_StuffingSID_Set(u32StuffingSID);
1335 _TSIO_RETURN(DRVTSIO_OK);
1336 }
1337
1338 //-------------------------------------------------------------------------------------------------
1339 /// Enable Loc decrypt engine on TSIO module
1340 /// @param bEnable \b IN: enable/disable loc decrypt engine
1341 /// @return TSIO_Result
1342 /// @note
1343 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_LocDecrypt_Set(MS_BOOL bEnable)1344 TSIO_Result MDrv_TSIO_LocDecrypt_Set(MS_BOOL bEnable)
1345 {
1346 TSIO_DBGTRACE();
1347 _TSIO_ENTRY();
1348
1349 HAL_TSIO_Decrypt_Set(bEnable);
1350 _TSIO_RETURN(DRVTSIO_OK);
1351 }
1352
1353 //-------------------------------------------------------------------------------------------------
1354 /// Set Sync threshold value to TSIO module
1355 /// @param u8Value \b IN: threshold value
1356 /// @return TSIO_Result
1357 /// @note
1358 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Syncthreshold_Set(MS_U8 u8Value)1359 TSIO_Result MDrv_TSIO_Syncthreshold_Set(MS_U8 u8Value)
1360 {
1361 TSIO_DBGTRACE();
1362 _TSIO_ENTRY();
1363
1364 if (u8Value > TSIO_MAX_SYNCTHRESHOLD || u8Value < TSIO_MIN_SYNCTHRESHOLD)
1365 {
1366 TSIO_DBGERR("Invalid sync threshold value, it should be %d to %d",TSIO_MIN_SYNCTHRESHOLD, TSIO_MAX_SYNCTHRESHOLD);
1367 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1368 }
1369
1370 HAL_TSIO_Threshold_Set(u8Value);
1371 _TSIO_RETURN(DRVTSIO_OK);
1372 }
1373
1374 //-------------------------------------------------------------------------------------------------
1375 /// Enable Bypass packet merge on TSIO module
1376 /// @param bEnable \b IN: enable/disable bypass packet merge
1377 /// @return TSIO_Result
1378 /// @note
1379 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_BypassMerge_Set(MS_BOOL bEnable)1380 TSIO_Result MDrv_TSIO_BypassMerge_Set(MS_BOOL bEnable)
1381 {
1382 TSIO_DBGTRACE();
1383 _TSIO_ENTRY();
1384
1385 HAL_TSIO_BypassMerge_Set(bEnable);
1386 _TSIO_RETURN(DRVTSIO_OK);
1387 }
1388
1389 //-------------------------------------------------------------------------------------------------
1390 /// Reset SGDMAIN
1391 /// @return TSIO_Result
1392 /// @note
1393 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_Reset(void)1394 TSIO_Result MDrv_TSIO_SGDMAIN_Reset(void)
1395 {
1396 TSIO_DBGTRACE();
1397 _TSIO_ENTRY();
1398
1399 HAL_TSIO_SGDMAIN_Reset();
1400 _TSIO_RETURN(DRVTSIO_OK);
1401 }
1402
1403 //-------------------------------------------------------------------------------------------------
1404 /// Set SGDMAIN Last packet buffer
1405 /// @param u32LastpktBufAddr \b IN: Last packet buffer physic address
1406 /// @param u32LastpktBufSize \b IN: Last packet buffer size
1407 /// @return TSIO_Result
1408 /// @note
1409 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_LastPktBuf_Set(MS_U32 u32LastpktBufAddr,MS_U32 u32LastpktBufSize)1410 TSIO_Result MDrv_TSIO_SGDMAIN_LastPktBuf_Set(MS_U32 u32LastpktBufAddr, MS_U32 u32LastpktBufSize)
1411 {
1412 TSIO_DBGTRACE();
1413 _TSIO_ENTRY();
1414 _ptsio_res->_phyLastpktBufAddr = u32LastpktBufAddr;
1415 _ptsio_res->_u32LastpktBufSize = u32LastpktBufSize;
1416 HAL_TSIO_SGDMAIN_LastPktBuf_Set(u32LastpktBufAddr, u32LastpktBufAddr+u32LastpktBufSize);
1417 _TSIO_RETURN(DRVTSIO_OK);
1418 }
1419
1420 //-------------------------------------------------------------------------------------------------
1421 /// Set SGDMAIN VQ buffer
1422 /// @param u32VQBufAddr \b IN: SGDMAIN VQ buffer physic address
1423 /// @param u32VQBufSize \b IN: SGDMAIN VQ buffer size
1424 /// @return TSIO_Result
1425 /// @note
1426 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_SGVQBuf_Set(MS_U32 u32VQBufAddr,MS_U32 u32VQBufSize)1427 TSIO_Result MDrv_TSIO_SGDMAIN_SGVQBuf_Set(MS_U32 u32VQBufAddr, MS_U32 u32VQBufSize)
1428 {
1429 TSIO_DBGTRACE();
1430 _TSIO_ENTRY();
1431 _ptsio_res->_phyDMAVQBufAddr = u32VQBufAddr;
1432 _ptsio_res->_u32DMAVQBufSize = u32VQBufSize;
1433 HAL_TSIO_SGDMAIN_SGVQBuf_Set(u32VQBufAddr, u32VQBufSize);
1434 _TSIO_RETURN(DRVTSIO_OK);
1435 }
1436
1437 //-------------------------------------------------------------------------------------------------
1438 /// Set SGDMAIN Node buffer
1439 /// @param u32NodeAddr \b IN: SGDMAIN Node buffer physic address
1440 /// @param u32NodeSize \b IN: SGDMAIN Node buffer size
1441 /// @return TSIO_Result
1442 /// @note
1443 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_NodeBuf_Set(MS_U32 u32NodeAddr,MS_U32 u32NodeSize)1444 TSIO_Result MDrv_TSIO_SGDMAIN_NodeBuf_Set(MS_U32 u32NodeAddr, MS_U32 u32NodeSize)
1445 {
1446 TSIO_DBGTRACE();
1447 _TSIO_ENTRY();
1448 _ptsio_res->_phyDMAinNodeAddr = u32NodeAddr;
1449 _ptsio_res->_u32DMAinNodeSize = u32NodeSize;
1450 SGDMAIN_NODE = (DRVTSIO_SGDMA_NODE *)MsOS_PA2KSEG1(u32NodeAddr);
1451 _TSIO_RETURN(DRVTSIO_OK);
1452 }
1453
1454 //-------------------------------------------------------------------------------------------------
1455 /// Set SGDMAOUT Node buffer
1456 /// @param u32NodeAddr \b IN: SGDMAOUT Node buffer physic address
1457 /// @param u32NodeSize \b IN: SGDMAOUT Node buffer size
1458 /// @return TSIO_Result
1459 /// @note
1460 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAOUT_NodeBuf_Set(MS_U32 u32NodeAddr,MS_U32 u32NodeSize)1461 TSIO_Result MDrv_TSIO_SGDMAOUT_NodeBuf_Set(MS_U32 u32NodeAddr, MS_U32 u32NodeSize)
1462 {
1463 TSIO_DBGTRACE();
1464 _TSIO_ENTRY();
1465 _ptsio_res->_phyDMAoutNodeAddr = u32NodeAddr;
1466 _ptsio_res->_u32DMAoutNodeSize = u32NodeSize;
1467 SGDMAOUT_NODE = (DRVTSIO_SGDMA_NODE *)MsOS_PA2KSEG1(u32NodeAddr);
1468 _TSIO_RETURN(DRVTSIO_OK);
1469 }
1470
1471 //-------------------------------------------------------------------------------------------------
1472 /// Allocate TSIO service
1473 /// @param pu16Servicehandle \b OUT: pointer of service handle for return
1474 /// @return TSIO_Result
1475 /// @note
1476 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_Alloc(MS_U16 * pu16Servicehandle)1477 TSIO_Result MDrv_TSIO_Service_Alloc(MS_U16 *pu16Servicehandle)
1478 {
1479 MS_U16 u16ii;
1480
1481 TSIO_DBGTRACE();
1482 _TSIO_ENTRY();
1483
1484 if (pu16Servicehandle == NULL)
1485 {
1486 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1487 }
1488
1489 *pu16Servicehandle = 0xFFFF;
1490 for (u16ii = 0; u16ii < TSIO_SERVICE_NUM; u16ii++)
1491 {
1492 if (_ptsio_res->_Servic[u16ii].eState == E_TSIO_SERVICESTATE_FREE)
1493 {
1494 TSIO_DBGINFO("Allocate service handle %d", u16ii);
1495 _ptsio_res->_Servic[u16ii].eState = E_TSIO_SERVICESTATE_ALLOC;
1496 *pu16Servicehandle = u16ii;
1497 _TSIO_RETURN(DRVTSIO_OK)
1498 }
1499 }
1500
1501 TSIO_DBGERR("service handle is full, max number is %d",TSIO_SERVICE_NUM);
1502 _TSIO_RETURN(DRVTSIO_FAIL);
1503 }
1504
1505 //-------------------------------------------------------------------------------------------------
1506 /// Free TSIO service
1507 /// @param u16Servicehandle \b IN: Service handle ID
1508 /// @return TSIO_Result
1509 /// @note
1510 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_Free(MS_U16 u16Servicehandle)1511 TSIO_Result MDrv_TSIO_Service_Free(MS_U16 u16Servicehandle)
1512 {
1513 TSIO_DBGTRACE();
1514 _TSIO_ENTRY();
1515
1516 if(_ptsio_res->_Servic[u16Servicehandle].eState == E_TSIO_SERVICESTATE_FREE)
1517 {
1518 _TSIO_RETURN(DRVTSIO_OK);
1519 }
1520
1521 HAL_TSIO_SGDMAIN_VC_Close((MS_U8)u16Servicehandle);
1522 HAL_TSIO_SVIDTBL_Set((MS_U8)u16Servicehandle, TSIO_SERVICE_NUM-1, 0, 0);
1523 HAL_TSIO_SGDMAOUT_VC_Close((MS_U8)u16Servicehandle);
1524 HAL_TSIO_SGDMAIN_IntClr((MS_U8)u16Servicehandle);
1525 HAL_TSIO_SGDMAOUT_IntClr((MS_U8)u16Servicehandle);
1526 HAL_TSIO_SGDMAIN_PidFltEnable(_ptsio_res->_Servic[u16Servicehandle].u8Sid, FALSE);
1527
1528 //close loc key
1529 HAL_TSIO_LOCDEC_Xiu_Lock(0);
1530 HAL_TSIO_LOCDEC_KeyEnable(_ptsio_res->_Servic[u16Servicehandle].u8Sid, FALSE);
1531 HAL_TSIO_LOCDEC_PrivilegeSlotEnable(_ptsio_res->_Servic[u16Servicehandle].u8Sid, FALSE);
1532 HAL_TSIO_LOCDEC_Xiu_Unlock();
1533
1534 //reset resource parameters
1535 _ptsio_res->_Servic[u16Servicehandle].eState = E_TSIO_SERVICESTATE_FREE;
1536 _ptsio_res->_Servic[u16Servicehandle].bDecrypt = FALSE;
1537 _ptsio_res->_Servic[u16Servicehandle].bkeyEvenSet = FALSE;
1538 _ptsio_res->_Servic[u16Servicehandle].bkeyOddSet = FALSE;
1539 _ptsio_res->_Servic[u16Servicehandle].u8Sid = 0xFF;
1540 _TSIO_RETURN(DRVTSIO_OK);
1541 }
1542
1543 //-------------------------------------------------------------------------------------------------
1544 /// Set Service ID to TSIO service
1545 /// @param u16Servicehandle \b IN: Service handle ID
1546 /// @param u8Sid \b IN: Service ID
1547 /// @return TSIO_Result
1548 /// @note
1549 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetSid(MS_U16 u16Servicehandle,MS_U8 u8Sid)1550 TSIO_Result MDrv_TSIO_Service_SetSid(MS_U16 u16Servicehandle, MS_U8 u8Sid)
1551 {
1552 TSIO_DBGTRACE();
1553 _TSIO_ENTRY();
1554
1555 if(u8Sid >= TSIO_SERVICE_NUM)
1556 {
1557 TSIO_DBGERR("invalid service ID, the max service ID is %d", TSIO_SERVICE_NUM-1);
1558 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1559 }
1560
1561 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1562 {
1563 TSIO_DBGERR("unknow service handle");
1564 _TSIO_RETURN(DRVTSIO_FAIL);
1565 }
1566
1567 _ptsio_res->_Servic[u16Servicehandle].u8Sid = u8Sid;
1568 _TSIO_RETURN(DRVTSIO_OK);
1569 }
1570
1571 //-------------------------------------------------------------------------------------------------
1572 /// Get Service ID with target Service handle
1573 /// @param u16Servicehandle \b IN: Service handle ID
1574 /// @param u8Sid \b OUT: Service ID
1575 /// @return TSIO_Result
1576 /// @note
1577 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_GetSid(MS_U16 u16Servicehandle,MS_U8 * u8Sid)1578 TSIO_Result MDrv_TSIO_Service_GetSid(MS_U16 u16Servicehandle, MS_U8 *u8Sid)
1579 {
1580 TSIO_DBGTRACE();
1581 _TSIO_ENTRY();
1582
1583 if(u8Sid == NULL)
1584 {
1585 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1586 }
1587
1588 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1589 {
1590 TSIO_DBGERR("unknow service handle");
1591 _TSIO_RETURN(DRVTSIO_FAIL);
1592 }
1593
1594 *u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1595 _TSIO_RETURN(DRVTSIO_OK);
1596 }
1597
1598 //-------------------------------------------------------------------------------------------------
1599 /// Set DMAIN Virture channel to TSIO service
1600 /// @param u16Servicehandle \b IN: Service handle ID
1601 /// @param eSet \b IN: Sgdma in param setting
1602 /// @return TSIO_Result
1603 /// @note
1604 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetDMAinVC(MS_U16 u16Servicehandle,DRVTSIO_DMAIN_SET * peSet)1605 TSIO_Result MDrv_TSIO_Service_SetDMAinVC(MS_U16 u16Servicehandle, DRVTSIO_DMAIN_SET *peSet)
1606 {
1607 MS_U8 u8Sid = 0xFF; ;
1608
1609 TSIO_DBGTRACE();
1610 _TSIO_ENTRY();
1611
1612 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1613 {
1614 TSIO_DBGERR("unknow service handle");
1615 _TSIO_RETURN(DRVTSIO_FAIL);
1616 }
1617
1618 if(_ptsio_res->_Servic[u16Servicehandle].u8Sid == 0xFF)
1619 {
1620 TSIO_DBGERR("invalid service id");
1621 _TSIO_RETURN(DRVTSIO_FAIL);
1622 }
1623 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1624
1625 SGDMAIN_NODE[u16Servicehandle].u32Bufferaddr = peSet->phyBufAddr;
1626 SGDMAIN_NODE[u16Servicehandle].u32Buffersize = peSet->u32BufSize;
1627 SGDMAIN_NODE[u16Servicehandle].u32Endnodeflag = TRUE;
1628 SGDMAIN_NODE[u16Servicehandle].u32Nextnodeaddr = 0;
1629
1630 MsOS_FlushMemory(); // Node flush
1631
1632 HAL_TSIO_SGDMAIN_VC_Open(MsOS_VA2PA((MS_VIRT)&SGDMAIN_NODE[u16Servicehandle]), (MS_U8)u16Servicehandle,
1633 u8Sid, peSet->bTSmode, peSet->bMidPriority, peSet->bLastNodeFlush, peSet->bNewPkt);
1634
1635 _TSIO_RETURN(DRVTSIO_OK);
1636 }
1637
1638 //-------------------------------------------------------------------------------------------------
1639 /// start DMAIN Virture channel
1640 /// @param u16Servicehandle \b IN: Service handle ID
1641 /// @param u32Pacing \b IN: Sgdma in pacing rate
1642 /// @return TSIO_Result
1643 /// @note
1644 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_DMAinVC_Start(MS_U16 u16Servicehandle,MS_U32 u32Pacing)1645 TSIO_Result MDrv_TSIO_Service_DMAinVC_Start(MS_U16 u16Servicehandle, MS_U32 u32Pacing)
1646 {
1647 TSIO_DBGTRACE();
1648 _TSIO_ENTRY();
1649
1650 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1651 {
1652 TSIO_DBGERR("unknow service handle");
1653 _TSIO_RETURN(DRVTSIO_FAIL);
1654 }
1655
1656 if(_ptsio_res->_Servic[u16Servicehandle].u8Sid == 0xFF)
1657 {
1658 TSIO_DBGERR("invalid service id");
1659 _TSIO_RETURN(DRVTSIO_FAIL);
1660 }
1661
1662 if (u32Pacing > 0)
1663 {
1664 HAL_TSIO_SGDMAIN_Global_Pacing();
1665 HAL_TSIO_SGDMAIN_VC_Pacing((MS_U8)u16Servicehandle, TRUE, u32Pacing);
1666 }
1667
1668 HAL_TSIO_SGDMAIN_Start();
1669 _TSIO_RETURN(DRVTSIO_OK);
1670 }
1671
1672 //-------------------------------------------------------------------------------------------------
1673 /// Set DMAOUT VC to TSIO service
1674 /// @param u16Servicehandle \b IN: Service handle ID
1675 /// @param eSet \b IN: Sgdma out param setting
1676 /// @return TSIO_Result
1677 /// @note
1678 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetDMAoutVC(MS_U16 u16Servicehandle,DRVTSIO_DMAOUT_SET * peSet)1679 TSIO_Result MDrv_TSIO_Service_SetDMAoutVC(MS_U16 u16Servicehandle, DRVTSIO_DMAOUT_SET* peSet)
1680 {
1681 TSIO_DBGTRACE();
1682 _TSIO_ENTRY();
1683
1684 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1685 {
1686 TSIO_DBGERR("unknow service handle");
1687 _TSIO_RETURN(DRVTSIO_FAIL);
1688 }
1689
1690 TSIO_DBGINFO("0x%X (0x%X)",(MS_U32)&SGDMAOUT_NODE[u16Servicehandle], (MS_U32)MsOS_VA2PA((MS_VIRT)&SGDMAOUT_NODE[u16Servicehandle]));
1691 TSIO_DBGINFO("eSet.phyBufAddr = 0x%X",(MS_U32)peSet->phyBufAddr);
1692 TSIO_DBGINFO("eSet.u32BufSize = 0x%X",peSet->u32BufSize);
1693
1694 SGDMAOUT_NODE[u16Servicehandle].u32Bufferaddr = (MS_U32)peSet->phyBufAddr;
1695 SGDMAOUT_NODE[u16Servicehandle].u32Buffersize = peSet->u32BufSize;
1696 SGDMAOUT_NODE[u16Servicehandle].u32Endnodeflag = 2; //ring buffer
1697 SGDMAOUT_NODE[u16Servicehandle].u32Nextnodeaddr = MsOS_VA2PA((MS_VIRT)&SGDMAOUT_NODE[u16Servicehandle]); //ring buffer
1698
1699 MsOS_FlushMemory(); // Node flush
1700
1701 HAL_TSIO_SGDMAOUT_VC_Open(MsOS_VA2PA((MS_VIRT)&SGDMAOUT_NODE[u16Servicehandle]), (MS_U8)u16Servicehandle, peSet->bSecurity);
1702 HAL_TSIO_SGDMAOUT_Start();
1703 _ptsio_res->_bDMAoutLSB[u16Servicehandle] = 0;
1704 _TSIO_RETURN(DRVTSIO_OK);
1705 }
1706
1707 //-------------------------------------------------------------------------------------------------
1708 /// Get DMAOUT VC write address
1709 /// @param u16Servicehandle \b IN: Service handle ID
1710 /// @param pphyWrite \b OUT: dma out write address
1711 /// @return TSIO_Result
1712 /// @note
1713 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_DMAout_WriteGet(MS_U16 u16Servicehandle,MS_PHY * pphyWrite)1714 TSIO_Result MDrv_TSIO_Service_DMAout_WriteGet(MS_U16 u16Servicehandle, MS_PHY* pphyWrite)
1715 {
1716 MS_U32 u32Addr = 0;
1717 MS_U32 u32Len = 0;
1718
1719 TSIO_DBGTRACE();
1720 _TSIO_ENTRY();
1721
1722 if (pphyWrite == NULL)
1723 {
1724 TSIO_DBGERR("invalid input");
1725 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1726 }
1727
1728 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1729 {
1730 TSIO_DBGERR("unknow service handle");
1731 _TSIO_RETURN(DRVTSIO_FAIL);
1732 }
1733
1734 u32Addr = HAL_TSIO_SGDMAOUT_ReadSram(u16Servicehandle, HAL_SGDMA_SRAM_BUF_ADDR, _ptsio_res->_bDMAoutLSB[u16Servicehandle]);
1735 u32Len = HAL_TSIO_SGDMAOUT_ReadSram(u16Servicehandle, HAL_SGDMA_SRAM_BUF_USED_SIZE, _ptsio_res->_bDMAoutLSB[u16Servicehandle]);
1736
1737 *pphyWrite = u32Addr + u32Len;
1738
1739 _TSIO_RETURN(DRVTSIO_OK);
1740 }
1741
1742 //-------------------------------------------------------------------------------------------------
1743 /// Set destination to TSIO service
1744 /// @param u16Servicehandle \b IN: Service handle ID
1745 /// @param eSet \b IN: Sgdma out param setting
1746 /// @return TSIO_Result
1747 /// @note
1748 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetDestination(MS_U16 u16Servicehandle,DRVTSIO_SERVICEDEST eDest)1749 TSIO_Result MDrv_TSIO_Service_SetDestination(MS_U16 u16Servicehandle, DRVTSIO_SERVICEDEST eDest)
1750 {
1751 MS_BOOL bLive = FALSE;
1752 MS_U8 u8Sid = 0xFF;
1753 MS_U8 u8SouceID = (MS_U8)u16Servicehandle;
1754
1755 TSIO_DBGTRACE();
1756 _TSIO_ENTRY();
1757
1758 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1759 {
1760 TSIO_DBGERR("unknow service handle");
1761 _TSIO_RETURN(DRVTSIO_FAIL);
1762 }
1763
1764 if(_ptsio_res->_Servic[u16Servicehandle].u8Sid == 0xFF)
1765 {
1766 TSIO_DBGERR("invalid service id");
1767 _TSIO_RETURN(DRVTSIO_FAIL);
1768 }
1769
1770 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1771 if (eDest == E_DRVTSIO_SERVICEDEST_LIVE)
1772 {
1773 u8SouceID = 0x47;
1774 bLive = TRUE;
1775 }
1776
1777 HAL_TSIO_SVIDTBL_Set((MS_U8)u16Servicehandle, u8Sid, u8SouceID, bLive);
1778 _TSIO_RETURN(DRVTSIO_OK);
1779 }
1780
1781 //-------------------------------------------------------------------------------------------------
1782 /// Enable bypass SMC merge setting to TSIO service
1783 /// @param u16Servicehandle \b IN: Service handle ID
1784 /// @param bEnable \b IN: enable/disable bypass SMC setting
1785 /// @return TSIO_Result
1786 /// @note
1787 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_BypassSMCMergeEnable(MS_U16 u16Servicehandle,MS_BOOL bEnable)1788 TSIO_Result MDrv_TSIO_Service_BypassSMCMergeEnable(MS_U16 u16Servicehandle, MS_BOOL bEnable)
1789 {
1790 MS_U8 u8Sid = 0xFF;
1791
1792 TSIO_DBGTRACE();
1793 _TSIO_ENTRY();
1794
1795 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1796 {
1797 TSIO_DBGERR("unknow service handle");
1798 _TSIO_RETURN(DRVTSIO_FAIL);
1799 }
1800
1801 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1802
1803 HAL_TSIO_SIDBypassSMCMergeEnable(u8Sid, bEnable);
1804 _TSIO_RETURN(DRVTSIO_OK);
1805 }
1806
1807 //-------------------------------------------------------------------------------------------------
1808 /// Set Locdecrypt key to TSIO service
1809 /// @param u16Servicehandle \b IN: Service handle ID
1810 /// @param pKey \b IN: Pointer to store loc decrypt key address
1811 /// @param u16KeySize \b IN: Decrypt key size
1812 /// @param bOddKey \b IN: 1: odd key, 0: even key
1813 /// @return TSIO_Result
1814 /// @note
1815 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetLocdecKey(MS_U16 u16Servicehandle,MS_U8 * pKey,MS_U16 u16KeySize,MS_BOOL bOddKey)1816 TSIO_Result MDrv_TSIO_Service_SetLocdecKey(MS_U16 u16Servicehandle, MS_U8 *pKey, MS_U16 u16KeySize, MS_BOOL bOddKey)
1817 {
1818 MS_U32 u32Timeout = 0;
1819 MS_U8 u8Sid = 0xFF;
1820
1821 TSIO_DBGTRACE();
1822 _TSIO_ENTRY();
1823
1824 if (pKey == NULL || u16KeySize != TSIO_LOCDEC_KEY_LEN)
1825 {
1826 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1827 }
1828
1829 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1830 {
1831 TSIO_DBGERR("unknow service handle");
1832 _TSIO_RETURN(DRVTSIO_FAIL);
1833 }
1834
1835 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1836
1837 HAL_TSIO_LOCDEC_Xiu_Lock(0);
1838 HAL_TSIO_LOCDEC_ScbFixRule(TRUE);
1839 HAL_TSIO_LOCDEC_Key_Set(u8Sid, pKey, u16KeySize, bOddKey);
1840
1841 while (!HAL_TSIO_LOCDEC_KeySetDone())
1842 {
1843 MsOS_DelayTask(1);
1844 if (u32Timeout >= TSIO_LOCDEC_SETKEY_TIMEOUT)
1845 {
1846 HAL_TSIO_LOCDEC_Xiu_Unlock();
1847 _TSIO_RETURN(DRVTSIO_FAIL);
1848 }
1849 }
1850 HAL_TSIO_LOCDEC_Xiu_Unlock();
1851 _TSIO_RETURN(DRVTSIO_OK);
1852 }
1853
1854 //-------------------------------------------------------------------------------------------------
1855 /// Enable/disable locdec key
1856 /// @param u16Servicehandle \b IN: Service handle ID
1857 /// @param bEnable \b IN: Enable locdec key
1858 /// @return TSIO_Result
1859 /// @note
1860 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_LocdecKeyEnable(MS_U16 u16Servicehandle,MS_BOOL bEnable)1861 TSIO_Result MDrv_TSIO_Service_LocdecKeyEnable(MS_U16 u16Servicehandle, MS_BOOL bEnable)
1862 {
1863 MS_U8 u8Sid = 0xFF;
1864
1865 TSIO_DBGTRACE();
1866 _TSIO_ENTRY();
1867
1868 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1869 {
1870 TSIO_DBGERR("unknow service handle");
1871 _TSIO_RETURN(DRVTSIO_FAIL);
1872 }
1873
1874 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1875
1876 HAL_TSIO_LOCDEC_Xiu_Lock(0);
1877 HAL_TSIO_LOCDEC_KeyEnable(u8Sid, bEnable);
1878 HAL_TSIO_LOCDEC_Xiu_Unlock();
1879 _TSIO_RETURN(DRVTSIO_OK);
1880 }
1881
1882 //-------------------------------------------------------------------------------------------------
1883 /// Enable secure keyslot on Locdecrypt
1884 /// @param u16Servicehandle \b IN: Service handle ID
1885 /// @param bEnable \b IN: Enable / disable secure keyslot
1886 /// @return TSIO_Result
1887 /// @note
1888 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetLocdecSecureKeyslot(MS_U16 u16Servicehandle,MS_BOOL bEnable)1889 TSIO_Result MDrv_TSIO_Service_SetLocdecSecureKeyslot(MS_U16 u16Servicehandle, MS_BOOL bEnable)
1890 {
1891 MS_U8 u8Sid = 0xFF;
1892
1893 TSIO_DBGTRACE();
1894 _TSIO_ENTRY();
1895
1896 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1897 {
1898 TSIO_DBGERR("unknow service handle");
1899 _TSIO_RETURN(DRVTSIO_FAIL);
1900 }
1901
1902 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1903
1904 HAL_TSIO_LOCDEC_Xiu_Lock(0);
1905 HAL_TSIO_LOCDEC_SecureSlotEnable(u8Sid, bEnable);
1906 HAL_TSIO_LOCDEC_Xiu_Unlock();
1907 _TSIO_RETURN(DRVTSIO_OK);
1908 }
1909
1910 //-------------------------------------------------------------------------------------------------
1911 /// Enable privilege keyslot on Locdecrypt
1912 /// @param u16Servicehandle \b IN: Service handle ID
1913 /// @param bEnable \b IN: Enable / disable secure flag
1914 /// @return TSIO_Result
1915 /// @note
1916 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SetLocdecPrivilegeKeySlot(MS_U16 u16Servicehandle,MS_BOOL bEnable)1917 TSIO_Result MDrv_TSIO_Service_SetLocdecPrivilegeKeySlot(MS_U16 u16Servicehandle, MS_BOOL bEnable)
1918 {
1919 MS_U8 u8Sid = 0xFF;
1920
1921 TSIO_DBGTRACE();
1922 _TSIO_ENTRY();
1923
1924 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1925 {
1926 TSIO_DBGERR("unknow service handle");
1927 _TSIO_RETURN(DRVTSIO_FAIL);
1928 }
1929
1930 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1931
1932 HAL_TSIO_LOCDEC_Xiu_Lock(0);
1933 HAL_TSIO_LOCDEC_PrivilegeSlotEnable(u8Sid, bEnable);
1934 HAL_TSIO_LOCDEC_Xiu_Unlock();
1935 _TSIO_RETURN(DRVTSIO_OK);
1936 }
1937
1938 //-------------------------------------------------------------------------------------------------
1939 /// Enable SGDMAIN PidFlt
1940 /// @param u16Servicehandle \b IN: Service handle ID
1941 /// @param bEnable \b IN: Enable
1942 /// @return TSIO_Result
1943 /// @note
1944 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_Service_SgdmaInPidFltEnable(MS_U16 u16Servicehandle,MS_BOOL bEnable)1945 TSIO_Result MDrv_TSIO_Service_SgdmaInPidFltEnable(MS_U16 u16Servicehandle, MS_BOOL bEnable)
1946 {
1947 MS_U8 u8Sid = 0xFF;
1948
1949 TSIO_DBGTRACE();
1950 _TSIO_ENTRY();
1951
1952 if(_ptsio_res->_Servic[u16Servicehandle].eState != E_TSIO_SERVICESTATE_ALLOC)
1953 {
1954 TSIO_DBGERR("unknow service handle");
1955 _TSIO_RETURN(DRVTSIO_FAIL);
1956 }
1957
1958 u8Sid = _ptsio_res->_Servic[u16Servicehandle].u8Sid;
1959 HAL_TSIO_SGDMAIN_PidFltEnable(u8Sid, bEnable);
1960
1961 _TSIO_RETURN(DRVTSIO_OK);
1962 }
1963
1964 //-------------------------------------------------------------------------------------------------
1965 /// Allocate TSIO SGDMA_in PID filter
1966 /// @param pu16PidFltId \b OUT: pointer of PID filter ID for return
1967 /// @return TSIO_Result
1968 /// @note
1969 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_PidFlt_Alloc(MS_U16 * pu16PidFltId)1970 TSIO_Result MDrv_TSIO_SGDMAIN_PidFlt_Alloc(MS_U16 *pu16PidFltId)
1971 {
1972 MS_U16 u16ii;
1973
1974 TSIO_DBGTRACE();
1975 _TSIO_ENTRY();
1976
1977 if (pu16PidFltId == NULL)
1978 {
1979 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
1980 }
1981
1982 *pu16PidFltId = 0xFFFF;
1983
1984 for(u16ii = 0; u16ii < TSIO_SGDMAIN_PIDFLT_NUM; u16ii++)
1985 {
1986 if(_ptsio_res->_PidFlt[u16ii].eState == E_TSIO_SERVICESTATE_FREE)
1987 {
1988 TSIO_DBGTRACE("Allocate PID Flter %d", u16ii);
1989 _ptsio_res->_PidFlt[u16ii].eState = E_TSIO_SERVICESTATE_ALLOC;
1990 *pu16PidFltId = u16ii;
1991 _TSIO_RETURN(DRVTSIO_OK);
1992 }
1993 }
1994 _TSIO_RETURN(DRVTSIO_FAIL);
1995 }
1996
1997 //-------------------------------------------------------------------------------------------------
1998 /// Free TSIO SGDMA_in PID filter
1999 /// @param u16PidFltId \b IN: PID filter ID
2000 /// @return TSIO_Result
2001 /// @note
2002 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_PidFlt_Free(MS_U16 u16PidFltId)2003 TSIO_Result MDrv_TSIO_SGDMAIN_PidFlt_Free(MS_U16 u16PidFltId)
2004 {
2005 TSIO_DBGTRACE();
2006 _TSIO_ENTRY();
2007
2008 if(_ptsio_res->_PidFlt[u16PidFltId].eState == E_TSIO_SERVICESTATE_FREE)
2009 {
2010 _TSIO_RETURN(DRVTSIO_OK);
2011 }
2012
2013 HAL_TSIO_SGDMAIN_Flt_SetPid(u16PidFltId, TSIO_PID_NULL);
2014 HAL_TSIO_SGDMAIN_Flt_SetSid(u16PidFltId, TSIO_SERVICE_NULL);
2015
2016 //reset resource parameters
2017 _ptsio_res->_PidFlt[u16PidFltId].u16FltPid = TSIO_PID_NULL;
2018 _ptsio_res->_PidFlt[u16PidFltId].u8Sid = TSIO_SERVICE_NULL;
2019 _ptsio_res->_PidFlt[u16PidFltId].eState = E_TSIO_SERVICESTATE_FREE;
2020
2021 _TSIO_RETURN(DRVTSIO_OK);
2022 }
2023
2024 //-------------------------------------------------------------------------------------------------
2025 /// Set PID to SGDMA_in PID filter
2026 /// @param u16PidFltId \b IN: PID filter ID
2027 /// @param u16Pid \b IN: PID
2028 /// @return TSIO_Result
2029 /// @note
2030 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_PidFlt_SetPid(MS_U16 u16PidFltId,MS_U16 u16Pid)2031 TSIO_Result MDrv_TSIO_SGDMAIN_PidFlt_SetPid(MS_U16 u16PidFltId, MS_U16 u16Pid)
2032 {
2033 TSIO_DBGTRACE();
2034 _TSIO_ENTRY();
2035
2036 if(_ptsio_res->_PidFlt[u16PidFltId].eState != E_TSIO_SERVICESTATE_ALLOC)
2037 {
2038 _TSIO_RETURN(DRVTSIO_FAIL);
2039 }
2040
2041 HAL_TSIO_SGDMAIN_Flt_SetPid(u16PidFltId, u16Pid);
2042
2043 _ptsio_res->_PidFlt[u16PidFltId].u16FltPid = u16Pid;
2044 _TSIO_RETURN(DRVTSIO_OK);
2045 }
2046
2047 //-------------------------------------------------------------------------------------------------
2048 /// Set Service ID to PID filter
2049 /// @param u16PidFltId \b IN: PID filter ID
2050 /// @param u8Sid \b IN: Service ID
2051 /// @return TSIO_Result
2052 /// @note
2053 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_SGDMAIN_PidFlt_SetSid(MS_U16 u16PidFltId,MS_U8 u8Sid)2054 TSIO_Result MDrv_TSIO_SGDMAIN_PidFlt_SetSid(MS_U16 u16PidFltId, MS_U8 u8Sid)
2055 {
2056 TSIO_DBGTRACE();
2057 _TSIO_ENTRY();
2058
2059 if(_ptsio_res->_PidFlt[u16PidFltId].eState != E_TSIO_SERVICESTATE_ALLOC)
2060 {
2061 _TSIO_RETURN(DRVTSIO_FAIL);
2062 }
2063
2064 HAL_TSIO_SGDMAIN_Flt_SetSid(u16PidFltId, u8Sid);
2065 _ptsio_res->_PidFlt[u16PidFltId].u8Sid = u8Sid;
2066 _TSIO_RETURN(DRVTSIO_OK);
2067 }
2068
2069 //-------------------------------------------------------------------------------------------------
2070 /// Send C&C cmd
2071 /// @param pu8Cmd \b IN: Pointer to store C&C cmd address
2072 /// @param u16CmdLen \b IN: C&C cmd length
2073 /// @return TSIO_Result
2074 /// @note
2075 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_CC_SendCmd(MS_U8 * pu8Cmd,MS_U16 u16CmdLen)2076 TSIO_Result MDrv_TSIO_CC_SendCmd(MS_U8 *pu8Cmd, MS_U16 u16CmdLen)
2077 {
2078 MS_U16 u16ii = 0;
2079 MS_U32 u32Data = 0;
2080 MS_U8 u8Addr = 0;
2081 MS_U32 u32Timeout = 0;
2082 MS_U8 u8Data[4] = {0xFF, 0xFF, 0xFF, 0xFF};
2083 MS_U16 u16jj = 0;
2084
2085 TSIO_DBGTRACE();
2086 _TSIO_ENTRY();
2087 if (pu8Cmd == NULL || u16CmdLen < TSIO_CC_CMD_MIN_LEN || u16CmdLen > TSIO_CC_CMD_MAX_LEN)
2088 {
2089 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
2090 }
2091
2092 HAL_TSIO_CC_RxEnable(TRUE);
2093 for (u16ii = 0; u16ii < u16CmdLen; u16ii+=4)
2094 {
2095 for (u16jj = 0; u16jj < 4; u16jj++)
2096 {
2097 if ((u16ii + u16jj) >= u16CmdLen)
2098 u8Data[u16jj] = 0xFF;
2099 else
2100 u8Data[u16jj] = pu8Cmd[u16ii+u16jj];
2101 }
2102 u32Data = u8Data[0] + (u8Data[1] << 8)
2103 + (u8Data[2] << 16) + (u8Data[3] << 24);
2104 HAL_TSIO_CC_TxWriteData(u8Addr, u32Data);
2105 u8Addr++;
2106 }
2107 HAL_TSIO_CC_TxWriteSize(u16CmdLen);
2108 HAL_TSIO_CC_TxEnable(TRUE);
2109
2110 while (!_CC_TX_INT)
2111 {
2112 MsOS_DelayTask(1);
2113 if (u32Timeout++ > TSIO_CC_CMD_TIMEOUT)
2114 {
2115 HAL_TSIO_CC_TxEnable(FALSE);
2116 _TSIO_RETURN(DRVTSIO_FAIL);
2117 }
2118 }
2119
2120 _CC_TX_INT = FALSE;
2121 HAL_TSIO_CC_TxEnable(FALSE);
2122 _TSIO_RETURN(DRVTSIO_OK);
2123 }
2124
2125 //-------------------------------------------------------------------------------------------------
2126 /// Send C&C cmd in speed-up mode
2127 /// @param pu8Cmd \b IN: Pointer to store C&C cmd address
2128 /// @param u16CmdLen \b IN: C&C cmd length
2129 /// @return TSIO_Result
2130 /// @note
2131 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_CC_SendCmd_Fast(MS_U8 * pu8Cmd,MS_U16 u16CmdLen)2132 TSIO_Result MDrv_TSIO_CC_SendCmd_Fast(MS_U8 *pu8Cmd, MS_U16 u16CmdLen)
2133 {
2134 MS_U16 u16ii = 0;
2135 MS_U32 u32Data = 0;
2136 MS_U32 u32Timeout = 0;
2137
2138 TSIO_DBGTRACE();
2139 _TSIO_ENTRY();
2140 if (pu8Cmd == NULL || u16CmdLen < TSIO_CC_CMD_MIN_LEN || u16CmdLen > TSIO_CC_CMD_MAX_LEN)
2141 {
2142 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
2143 }
2144
2145 HAL_TSIO_CC_RxEnable(TRUE);
2146
2147 HAL_TSIO_CC_TxWriteData_FastEnable(TRUE);
2148 for (u16ii = 0; u16ii < u16CmdLen; u16ii+=4)
2149 {
2150 u32Data = pu8Cmd[u16ii] + (pu8Cmd[u16ii+1] << 8)
2151 + (pu8Cmd[u16ii+2] << 16) + (pu8Cmd[u16ii+3] << 24);
2152 HAL_TSIO_CC_TxWriteData_Fast(u32Data);
2153 }
2154 HAL_TSIO_CC_TxWriteData_FastEnable(FALSE);
2155
2156 HAL_TSIO_CC_TxWriteSize(u16CmdLen);
2157 HAL_TSIO_CC_TxEnable(TRUE);
2158
2159
2160 while (!_CC_TX_INT)
2161 {
2162 MsOS_DelayTask(1);
2163 if (u32Timeout++ > TSIO_CC_CMD_TIMEOUT)
2164 {
2165 HAL_TSIO_CC_TxEnable(FALSE);
2166 _TSIO_RETURN(DRVTSIO_FAIL);
2167 }
2168 }
2169
2170 _CC_TX_INT = FALSE;
2171 HAL_TSIO_CC_TxEnable(FALSE);
2172 _TSIO_RETURN(DRVTSIO_OK);
2173 }
2174
2175 //-------------------------------------------------------------------------------------------------
2176 /// Receive C&C cmd
2177 /// @param pu8Cmd \b OUT: Pointer to store C&C cmd address
2178 /// @param pu16CmdLen \b OUT: Pointer to store C&C cmd length
2179 /// @return TSIO_Result
2180 /// @note
2181 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_CC_ReceiveCmd(MS_U8 * pu8Cmd,MS_U16 * pu16CmdLen)2182 TSIO_Result MDrv_TSIO_CC_ReceiveCmd(MS_U8 *pu8Cmd, MS_U16 *pu16CmdLen)
2183 {
2184 MS_U16 u16ii = 0;
2185 MS_U32 u32Data = 0;
2186 MS_U8 u8Addr = 0;
2187
2188 TSIO_DBGTRACE();
2189 _TSIO_ENTRY();
2190 if (pu8Cmd == NULL || pu16CmdLen == NULL)
2191 {
2192 HAL_TSIO_CC_RxEnable(FALSE);
2193 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
2194 }
2195
2196 *pu16CmdLen = HAL_TSIO_CC_RxReadSize();
2197 if (*pu16CmdLen < TSIO_CC_CMD_MIN_LEN || *pu16CmdLen > TSIO_CC_CMD_MAX_LEN)
2198 {
2199 HAL_TSIO_CC_RxEnable(FALSE);
2200 _TSIO_RETURN(DRVTSIO_FAIL);
2201 }
2202
2203 for (u16ii = 0; u16ii < *pu16CmdLen; u16ii+=4)
2204 {
2205 u32Data = HAL_TSIO_CC_RxReadData(u8Addr);
2206 pu8Cmd[u16ii] = (u32Data & 0x000000FF);
2207 pu8Cmd[u16ii+1] = (u32Data & 0x0000FF00)>>8;
2208 pu8Cmd[u16ii+2] = (u32Data & 0x00FF0000)>>16;
2209 pu8Cmd[u16ii+3] = (u32Data & 0xFF000000)>>24;
2210 u8Addr++;
2211 }
2212
2213 HAL_TSIO_CC_RxEnable(FALSE);
2214 _TSIO_RETURN(DRVTSIO_OK);
2215 }
2216
2217 //-------------------------------------------------------------------------------------------------
2218 /// Receive C&C cmd in speed-up mode
2219 /// @param pu8Cmd \b OUT: Pointer to store C&C cmd address
2220 /// @param pu16CmdLen \b OUT: Pointer to store C&C cmd length
2221 /// @return TSIO_Result
2222 /// @note
2223 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_CC_ReceiveCmd_Fast(MS_U8 * pu8Cmd,MS_U16 * pu16CmdLen)2224 TSIO_Result MDrv_TSIO_CC_ReceiveCmd_Fast(MS_U8 *pu8Cmd, MS_U16 *pu16CmdLen)
2225 {
2226 MS_U16 u16ii = 0;
2227 MS_U32 u32Data = 0;
2228 MS_U8 u8Addr = 0;
2229
2230 TSIO_DBGTRACE();
2231 _TSIO_ENTRY();
2232 if (pu8Cmd == NULL || pu16CmdLen == NULL)
2233 {
2234 HAL_TSIO_CC_RxEnable(FALSE);
2235 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
2236 }
2237
2238 *pu16CmdLen = HAL_TSIO_CC_RxReadSize();
2239 if (*pu16CmdLen < TSIO_CC_CMD_MIN_LEN || *pu16CmdLen > TSIO_CC_CMD_MAX_LEN)
2240 {
2241 HAL_TSIO_CC_RxEnable(FALSE);
2242 _TSIO_RETURN(DRVTSIO_FAIL);
2243 }
2244
2245 HAL_TSIO_CC_RxReadData_FastEnable(TRUE);
2246 for (u16ii = 0; u16ii < *pu16CmdLen; u16ii+=4)
2247 {
2248 u32Data = HAL_TSIO_CC_RxReadData_Fast(u8Addr);
2249 pu8Cmd[u16ii] = (u32Data & 0x000000FF);
2250 pu8Cmd[u16ii+1] = (u32Data & 0x0000FF00)>>8;
2251 pu8Cmd[u16ii+2] = (u32Data & 0x00FF0000)>>16;
2252 pu8Cmd[u16ii+3] = (u32Data & 0xFF000000)>>24;
2253 u8Addr++;
2254 }
2255 HAL_TSIO_CC_RxReadData_FastEnable(FALSE);
2256
2257 HAL_TSIO_CC_RxEnable(FALSE);
2258 _TSIO_RETURN(DRVTSIO_OK);
2259 }
2260
2261 //-------------------------------------------------------------------------------------------------
2262 /// Receive interupt status
2263 /// @param u32Timeout \b IN: Timeout value
2264 /// @param pu16Status \b OUT: Pointer to store C&C receiver status address
2265 /// @return TSIO_Result
2266 /// @note
2267 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_CC_ReceiveIntStatus(MS_U32 u32Timeout,MS_U16 * pu16Status)2268 TSIO_Result MDrv_TSIO_CC_ReceiveIntStatus(MS_U32 u32Timeout, MS_U16 *pu16Status)
2269 {
2270 MS_U32 u32Timer = 0;
2271
2272 TSIO_DBGTRACE();
2273 _TSIO_ENTRY();
2274 if (pu16Status == NULL)
2275 {
2276 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
2277 }
2278
2279 while (!_CC_RX_INT)
2280 {
2281 MsOS_DelayTask(1);
2282 if (u32Timer++ > u32Timeout)
2283 {
2284 _TSIO_RETURN(DRVTSIO_FAIL);
2285 }
2286 }
2287
2288 *pu16Status = _CC_RX_ERROR_STATUS;
2289 _CC_RX_INT = FALSE;
2290 _CC_RX_ERROR_STATUS = 0;
2291 _TSIO_RETURN(DRVTSIO_OK);
2292 }
2293
2294 //-------------------------------------------------------------------------------------------------
2295 /// Register interrupt callback function
2296 /// @param TSIOIntCB \b IN: Callback function pointer
2297 /// @return TSIO_Result
2298 /// @note
2299 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_RegisterIntCb(TSIOIntCB efn)2300 TSIO_Result MDrv_TSIO_RegisterIntCb(TSIOIntCB efn)
2301 {
2302 _TSIO_CbFn = efn;
2303 return DRVTSIO_OK;
2304 }
2305
2306 //-------------------------------------------------------------------------------------------------
2307 /// Get TSIO informaiton
2308 /// @param eInfo \b IN: Info type
2309 /// @param u32Arg \b IN: detail value
2310 /// @param u32Retinfo \b OUT: Pointer to store Info address
2311 /// @return DMX_FILTER_STATUS
2312 /// @note
2313 //-------------------------------------------------------------------------------------------------
MDrv_TSIO_GetInfo(DRVTSIO_INFO eInfo,MS_U32 u32Arg,MS_U32 * u32Retinfo)2314 TSIO_Result MDrv_TSIO_GetInfo(DRVTSIO_INFO eInfo, MS_U32 u32Arg, MS_U32 *u32Retinfo)
2315 {
2316 MS_U32 u32RetData = 0;
2317
2318 TSIO_DBGTRACE();
2319 _TSIO_ENTRY();
2320 if (u32Retinfo == NULL)
2321 {
2322 _TSIO_RETURN(DRVTSIO_INVALID_PARAM);
2323 }
2324
2325 switch (eInfo)
2326 {
2327 case DRVTSIO_INFO_LOSELOCKCNT:
2328 u32RetData = HAL_TSIO_GetLoselockcnt();
2329 break;
2330
2331 case DRVTSIO_INFO_USEBUFLEN:
2332 u32RetData = HAL_TSIO_SGDMAOUT_ReadSram(u32Arg, HAL_SGDMA_SRAM_BUF_USED_SIZE, _ptsio_res->_bDMAoutLSB[u32Arg]);
2333 break;
2334
2335 default:
2336 u32RetData = 0;
2337 break;
2338 }
2339
2340 *u32Retinfo = u32RetData;
2341 _TSIO_RETURN(DRVTSIO_OK);
2342 }
2343
2344
2345