1 #include <linux/kernel.h>
2 #include <linux/string.h>
3 #include <linux/slab.h>
4
5 #include "utopia.h"
6 #include "utopia_adp.h"
7
8 #include "drvDMD_DTMB_v2.h"
9
10 #ifdef MS_DEBUG
11 #define DMD_DBG(x) (x)
12 #else
13 #define DMD_DBG(x) //(x)
14 #endif
15
16 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_PTR_VAL[5];
17
18 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_DBG_LEVEL_PARAM[5];
19 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_Info[5];
20 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_INFO_PARAM[5];
21 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_ID_PARAM[5];
22 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_InitData[10];
23 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_INIT_PARAM[5];
24 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_SET_CONFIG_PARAM[5];
25 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_SET_QAM_SR_PARAM[5];
26 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_SET_ACTIVE_PARAM[5];
27 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_SET_POWER_STATE_PARAM[5];
28 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_LOCK_PARAM[5];
29 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_MODULATION_MODE_PARAM[5];
30 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_SIGNAL_STRENGTH_PARAM[5];
31 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_READ_FREQ_OFFSET_PARAM[5];
32 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_SIGNAL_QUALITY_PARAM[5];
33 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_BER_PARAM[5];
34 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GET_SNR_PARAM[5];
35 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_SET_SERIAL_CONTROL_PARAM[5];
36 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_IIC_BYPASS_MODE_PARAM[5];
37 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_SWITCH_SSPI_GPIO_PARAM[5];
38 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GPIO_LEVEL_PARAM[5];
39 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_GPIO_OUT_ENABLE_PARAM[5];
40 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_DO_IQSWAP_PARAM[5];
41 UADP_STRUCT_POINTER_TABLE spt_DMD_DTMB_REG_PARAM[5];
42
43 MS_U32 DTMB_adp_Ioctl(void* pInstanceTmp, MS_U32 u32Cmd, void* const pArgs);
44
DTMB_adp_Init(FUtopiaIOctl * pIoctl)45 MS_U32 DTMB_adp_Init(FUtopiaIOctl* pIoctl)
46 {
47 DMD_DBG(printk("DTMB_adp_Init\n"));
48
49 UADP_SPT_BGN(&spt_DMD_DTMB_PTR_VAL[0], 8);
50 UADP_SPT_FIN(&spt_DMD_DTMB_PTR_VAL[1]);
51
52 UADP_SPT_BGN(&spt_DMD_DTMB_DBG_LEVEL_PARAM[0], sizeof(DTMB_DBG_LEVEL_PARAM));
53 UADP_SPT_FIN(&spt_DMD_DTMB_DBG_LEVEL_PARAM[1]);
54
55 UADP_SDT_BGN(&spt_DMD_DTMB_Info[0], sizeof(DMD_DTMB_Info));
56 UADP_SDT_FIN(&spt_DMD_DTMB_Info[1]);
57 UADP_SDT_BGN(&spt_DMD_DTMB_GET_INFO_PARAM[0], sizeof(DTMB_GET_INFO_PARAM));
58 UADP_SDT_KIND(&spt_DMD_DTMB_GET_INFO_PARAM[1], DTMB_GET_INFO_PARAM, UADP_SDT_P2N, pInfo, spt_DMD_DTMB_Info);
59 UADP_SDT_FIN(&spt_DMD_DTMB_GET_INFO_PARAM[2]);
60
61 UADP_SPT_BGN(&spt_DMD_DTMB_ID_PARAM[0], sizeof(DTMB_ID_PARAM));
62 UADP_SPT_FIN(&spt_DMD_DTMB_ID_PARAM[1]);
63
64 UADP_SDT_BGN(&spt_DMD_DTMB_InitData[0], sizeof(DMD_DTMB_InitData));
65 UADP_SDT_KIND(&spt_DMD_DTMB_InitData[1], DMD_DTMB_InitData, UADP_SDT_P2N, u8DMD_DTMB_DSPRegInitExt, spt_DMD_DTMB_PTR_VAL);
66 UADP_SDT_KIND(&spt_DMD_DTMB_InitData[2], DMD_DTMB_InitData, UADP_SDT_P2N, u8DMD_DTMB_InitExt, spt_DMD_DTMB_PTR_VAL);
67 UADP_SDT_KIND(&spt_DMD_DTMB_InitData[3], DMD_DTMB_InitData, UADP_SDT_AT, I2C_WriteBytes, spt_DMD_DTMB_PTR_VAL);
68 UADP_SDT_KIND(&spt_DMD_DTMB_InitData[4], DMD_DTMB_InitData, UADP_SDT_AT, I2C_ReadBytes, spt_DMD_DTMB_PTR_VAL);
69 UADP_SDT_FIN(&spt_DMD_DTMB_InitData[5]);
70 UADP_SDT_BGN(&spt_DMD_DTMB_INIT_PARAM[0], sizeof(DTMB_INIT_PARAM));
71 UADP_SDT_KIND(&spt_DMD_DTMB_INIT_PARAM[1], DTMB_INIT_PARAM, UADP_SDT_P2N, pDMD_DTMB_InitData, spt_DMD_DTMB_InitData);
72 UADP_SDT_FIN(&spt_DMD_DTMB_INIT_PARAM[2]);
73
74 UADP_SPT_BGN(&spt_DMD_DTMB_SET_CONFIG_PARAM[0], sizeof(DTMB_SET_CONFIG_PARAM));
75 UADP_SPT_FIN(&spt_DMD_DTMB_SET_CONFIG_PARAM[1]);
76
77 UADP_SPT_BGN(&spt_DMD_DTMB_SET_QAM_SR_PARAM[0], sizeof(DTMB_SET_QAM_SR_PARAM));
78 UADP_SPT_FIN(&spt_DMD_DTMB_SET_QAM_SR_PARAM[1]);
79
80 UADP_SPT_BGN(&spt_DMD_DTMB_SET_ACTIVE_PARAM[0], sizeof(DTMB_SET_ACTIVE_PARAM));
81 UADP_SPT_FIN(&spt_DMD_DTMB_SET_ACTIVE_PARAM[1]);
82
83 UADP_SPT_BGN(&spt_DMD_DTMB_SET_POWER_STATE_PARAM[0], sizeof(DTMB_SET_POWER_STATE_PARAM));
84 UADP_SPT_FIN(&spt_DMD_DTMB_SET_POWER_STATE_PARAM[1]);
85
86 UADP_SPT_BGN(&spt_DMD_DTMB_GET_LOCK_PARAM[0], sizeof(DTMB_GET_LOCK_PARAM));
87 UADP_SPT_FIN(&spt_DMD_DTMB_GET_LOCK_PARAM[1]);
88
89 UADP_SPT_BGN(&spt_DMD_DTMB_GET_MODULATION_MODE_PARAM[0], sizeof(DTMB_GET_MODULATION_MODE_PARAM));
90 UADP_SPT_FIN(&spt_DMD_DTMB_GET_MODULATION_MODE_PARAM[1]);
91
92 UADP_SPT_BGN(&spt_DMD_DTMB_GET_SIGNAL_STRENGTH_PARAM[0], sizeof(DTMB_GET_SIGNAL_STRENGTH_PARAM));
93 UADP_SPT_FIN(&spt_DMD_DTMB_GET_SIGNAL_STRENGTH_PARAM[1]);
94
95 UADP_SPT_BGN(&spt_DMD_DTMB_READ_FREQ_OFFSET_PARAM[0], sizeof(DTMB_READ_FREQ_OFFSET_PARAM));
96 UADP_SPT_FIN(&spt_DMD_DTMB_READ_FREQ_OFFSET_PARAM[1]);
97
98 UADP_SPT_BGN(&spt_DMD_DTMB_GET_SIGNAL_QUALITY_PARAM[0], sizeof(DTMB_GET_SIGNAL_QUALITY_PARAM));
99 UADP_SPT_FIN(&spt_DMD_DTMB_GET_SIGNAL_QUALITY_PARAM[1]);
100
101 UADP_SPT_BGN(&spt_DMD_DTMB_GET_BER_PARAM[0], sizeof(DTMB_GET_BER_PARAM));
102 UADP_SPT_FIN(&spt_DMD_DTMB_GET_BER_PARAM[1]);
103
104 UADP_SPT_BGN(&spt_DMD_DTMB_GET_SNR_PARAM[0], sizeof(DTMB_GET_SNR_PARAM));
105 UADP_SPT_FIN(&spt_DMD_DTMB_GET_SNR_PARAM[1]);
106
107 UADP_SPT_BGN(&spt_DMD_DTMB_SET_SERIAL_CONTROL_PARAM[0], sizeof(DTMB_SET_SERIAL_CONTROL_PARAM));
108 UADP_SPT_FIN(&spt_DMD_DTMB_SET_SERIAL_CONTROL_PARAM[1]);
109
110 UADP_SPT_BGN(&spt_DMD_DTMB_IIC_BYPASS_MODE_PARAM[0], sizeof(DTMB_IIC_BYPASS_MODE_PARAM));
111 UADP_SPT_FIN(&spt_DMD_DTMB_IIC_BYPASS_MODE_PARAM[1]);
112
113 UADP_SPT_BGN(&spt_DMD_DTMB_SWITCH_SSPI_GPIO_PARAM[0], sizeof(DTMB_SWITCH_SSPI_GPIO_PARAM));
114 UADP_SPT_FIN(&spt_DMD_DTMB_SWITCH_SSPI_GPIO_PARAM[1]);
115
116 UADP_SPT_BGN(&spt_DMD_DTMB_GPIO_LEVEL_PARAM[0], sizeof(DTMB_GPIO_LEVEL_PARAM));
117 UADP_SPT_FIN(&spt_DMD_DTMB_GPIO_LEVEL_PARAM[1]);
118
119 UADP_SPT_BGN(&spt_DMD_DTMB_GPIO_OUT_ENABLE_PARAM[0], sizeof(DTMB_GPIO_OUT_ENABLE_PARAM));
120 UADP_SPT_FIN(&spt_DMD_DTMB_GPIO_OUT_ENABLE_PARAM[1]);
121
122 UADP_SPT_BGN(&spt_DMD_DTMB_DO_IQSWAP_PARAM[0], sizeof(DTMB_DO_IQSWAP_PARAM));
123 UADP_SPT_FIN(&spt_DMD_DTMB_DO_IQSWAP_PARAM[1]);
124
125 UADP_SPT_BGN(&spt_DMD_DTMB_REG_PARAM[0], sizeof(DTMB_REG_PARAM));
126 UADP_SPT_FIN(&spt_DMD_DTMB_REG_PARAM[1]);
127
128 *pIoctl= (FUtopiaIOctl)DTMB_adp_Ioctl;
129
130 return 0;
131 }
132
DTMB_adp_Ioctl(void * pInstanceTmp,MS_U32 u32Cmd,void * const pArgs)133 MS_U32 DTMB_adp_Ioctl(void* pInstanceTmp, MS_U32 u32Cmd, void* const pArgs)
134 {
135 MS_U32 u32Ret = UTOPIA_STATUS_FAIL;
136 char buffer_arg[2048];
137
138 switch(u32Cmd)
139 {
140 case DMD_DTMB_DRV_CMD_SetDbgLevel:
141 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_SetDbgLevel\n"));
142 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_DBG_LEVEL_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
143 break;
144 case DMD_DTMB_DRV_CMD_GetInfo:
145 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_GetInfo\n"));
146 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_INFO_PARAM, spt_DMD_DTMB_GET_INFO_PARAM, buffer_arg, sizeof(buffer_arg));
147 break;
148 case DMD_DTMB_DRV_CMD_GetLibVer:
149 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_GetLibVer\n"));
150 break;
151 case DMD_DTMB_DRV_CMD_Init:
152 case DMD_DTMB_DRV_CMD_MD_Init:
153 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_Init\n"));
154 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_INIT_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
155 break;
156 case DMD_DTMB_DRV_CMD_Exit:
157 case DMD_DTMB_DRV_CMD_MD_Exit:
158 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_Exit\n"));
159 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_ID_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
160 break;
161 case DMD_DTMB_DRV_CMD_GetConfig:
162 case DMD_DTMB_DRV_CMD_MD_GetConfig:
163 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetConfig\n"));
164 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_INIT_PARAM, spt_DMD_DTMB_INIT_PARAM, buffer_arg, sizeof(buffer_arg));
165 break;
166 case DMD_DTMB_DRV_CMD_SetConfig:
167 case DMD_DTMB_DRV_CMD_MD_SetConfig:
168 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_SetConfig\n"));
169 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_SET_CONFIG_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
170 break;
171 case DMD_DTMB_DRV_CMD_SetReset:
172 case DMD_DTMB_DRV_CMD_MD_SetReset:
173 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_SetReset\n"));
174 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_ID_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
175 break;
176 case DMD_DTMB_DRV_CMD_Set_QAM_SR:
177 case DMD_DTMB_DRV_CMD_MD_Set_QAM_SR:
178 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_Set_QAM_SR\n"));
179 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_SET_QAM_SR_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
180 break;
181 case DMD_DTMB_DRV_CMD_SetActive:
182 case DMD_DTMB_DRV_CMD_MD_SetActive:
183 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_SetActive\n"));
184 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_SET_ACTIVE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
185 break;
186 case DMD_DTMB_DRV_CMD_SetPowerState:
187 case DMD_DTMB_DRV_CMD_MD_SetPowerState:
188 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_SetPowerState\n"));
189 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_SET_POWER_STATE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
190 break;
191 case DMD_DTMB_DRV_CMD_GetLock:
192 case DMD_DTMB_DRV_CMD_MD_GetLock:
193 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetLock\n"));
194 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_LOCK_PARAM, spt_DMD_DTMB_GET_LOCK_PARAM, buffer_arg, sizeof(buffer_arg));
195 break;
196 case DMD_DTMB_DRV_CMD_GetModulationMode:
197 case DMD_DTMB_DRV_CMD_MD_GetModulationMode:
198 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetModulationMode\n"));
199 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_MODULATION_MODE_PARAM, spt_DMD_DTMB_GET_MODULATION_MODE_PARAM, buffer_arg, sizeof(buffer_arg));
200 break;
201 case DMD_DTMB_DRV_CMD_GetSignalStrength:
202 case DMD_DTMB_DRV_CMD_MD_GetSignalStrength:
203 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_GetSignalStrength\n"));
204 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_SIGNAL_STRENGTH_PARAM, spt_DMD_DTMB_GET_SIGNAL_STRENGTH_PARAM, buffer_arg, sizeof(buffer_arg));
205 break;
206 case DMD_DTMB_DRV_CMD_ReadFrequencyOffset:
207 case DMD_DTMB_DRV_CMD_MD_ReadFrequencyOffset:
208 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_ReadFrequencyOffset\n"));
209 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_READ_FREQ_OFFSET_PARAM, spt_DMD_DTMB_READ_FREQ_OFFSET_PARAM, buffer_arg, sizeof(buffer_arg));
210 break;
211 case DMD_DTMB_DRV_CMD_GetSignalQuality:
212 case DMD_DTMB_DRV_CMD_MD_GetSignalQuality:
213 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetSignalQuality\n"));
214 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_SIGNAL_QUALITY_PARAM, spt_DMD_DTMB_GET_SIGNAL_QUALITY_PARAM, buffer_arg, sizeof(buffer_arg));
215 break;
216 case DMD_DTMB_DRV_CMD_GetPreLdpcBer:
217 case DMD_DTMB_DRV_CMD_MD_GetPreLdpcBer:
218 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetPreLdpcBer\n"));
219 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_BER_PARAM, spt_DMD_DTMB_GET_BER_PARAM, buffer_arg, sizeof(buffer_arg));
220 break;
221 case DMD_DTMB_DRV_CMD_GetPreViterbiBer:
222 case DMD_DTMB_DRV_CMD_MD_GetPreViterbiBer:
223 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetPreViterbiBer\n"));
224 break;
225 case DMD_DTMB_DRV_CMD_GetPostViterbiBer:
226 case DMD_DTMB_DRV_CMD_MD_GetPostViterbiBer:
227 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetPostViterbiBer\n"));
228 break;
229 case DMD_DTMB_DRV_CMD_GetSNR:
230 case DMD_DTMB_DRV_CMD_MD_GetSNR:
231 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_DM_GetSNR\n"));
232 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GET_SNR_PARAM, spt_DMD_DTMB_GET_SNR_PARAM, buffer_arg, sizeof(buffer_arg));
233 break;
234 case DMD_DTMB_DRV_CMD_SetSerialControl:
235 case DMD_DTMB_DRV_CMD_MD_SetSerialControl:
236 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_SetSerialControl\n"));
237 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_SET_SERIAL_CONTROL_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
238 break;
239 case DMD_DTMB_DRV_CMD_IIC_BYPASS_MODE:
240 case DMD_DTMB_DRV_CMD_MD_IIC_BYPASS_MODE:
241 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_IIC_BYPASS_MODE\n"));
242 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_IIC_BYPASS_MODE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
243 break;
244 case DMD_DTMB_DRV_CMD_SWITCH_SSPI_GPIO:
245 case DMD_DTMB_DRV_CMD_MD_SWITCH_SSPI_GPIO:
246 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_SWITCH_SSPI_GPIO\n"));
247 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_SWITCH_SSPI_GPIO_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
248 break;
249 case DMD_DTMB_DRV_CMD_GPIO_GET_LEVEL:
250 case DMD_DTMB_DRV_CMD_MD_GPIO_GET_LEVEL:
251 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GPIO_GET_LEVEL\n"));
252 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GPIO_LEVEL_PARAM, spt_DMD_DTMB_GPIO_LEVEL_PARAM, buffer_arg, sizeof(buffer_arg));
253 break;
254 case DMD_DTMB_DRV_CMD_GPIO_SET_LEVEL:
255 case DMD_DTMB_DRV_CMD_MD_GPIO_SET_LEVEL:
256 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GPIO_SET_LEVEL\n"));
257 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GPIO_LEVEL_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
258 break;
259 case DMD_DTMB_DRV_CMD_GPIO_OUT_ENABLE:
260 case DMD_DTMB_DRV_CMD_MD_GPIO_OUT_ENABLE:
261 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GPIO_OUT_ENABLE\n"));
262 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_GPIO_OUT_ENABLE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
263 break;
264 case DMD_DTMB_DRV_CMD_DoIQSwap:
265 case DMD_DTMB_DRV_CMD_MD_DoIQSwap:
266 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_DoIQSwap\n"));
267 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_DO_IQSWAP_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
268 break;
269 case DMD_DTMB_DRV_CMD_GetReg:
270 case DMD_DTMB_DRV_CMD_MD_GetReg:
271 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_GetReg\n"));
272 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_REG_PARAM, spt_DMD_DTMB_REG_PARAM, buffer_arg, sizeof(buffer_arg));
273 break;
274 case DMD_DTMB_DRV_CMD_SetReg:
275 case DMD_DTMB_DRV_CMD_MD_SetReg:
276 DMD_DBG(printk("DTMB_adp_Ioctl - MDrv_DMD_DTMB_MD_SetReg\n"));
277 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_DTMB_REG_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
278 break;
279 default:
280 break;
281 }
282
283 return u32Ret;
284 }
285