1 #include <linux/kernel.h>
2 #include <linux/string.h>
3 #include <linux/slab.h>
4
5 #include "utopia.h"
6 #include "utopia_adp.h"
7
8 #include "drvDMD_ATSC_v2.h"
9
10 #ifdef MS_DEBUG
11 #define DMD_DBG(x) (x)
12 #else
13 #define DMD_DBG(x) //(x)
14 #endif
15
16 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_PTR_VAL[5];
17
18 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_DBG_LEVEL_PARAM[5];
19 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_Info[5];
20 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_INFO_PARAM[5];
21 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_ID_PARAM[5];
22 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_InitData[10];
23 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_INIT_PARAM[5];
24 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SET_CONFIG_PARAM[5];
25 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SET_QAM_SR_PARAM[5];
26 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SET_ACTIVE_PARAM[5];
27 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SET_POWER_STATE_PARAM[5];
28 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_LOCK_PARAM[5];
29 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_MODULATION_MODE_PARAM[5];
30 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_SIGNAL_STRENGTH_PARAM[5];
31 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_SIGNAL_QUALITY_PARAM[5];
32 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_SNR_PERCENTAGE_PARAM[5];
33 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SnrData[5];
34 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_SNR_PARAM[5];
35 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_UCPKT_ERR_PARAM[5];
36 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_BerData[5];
37 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GET_BER_PARAM[5];
38 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_CfoData[5];
39 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_READ_FREQ_OFFSET_PARAM[5];
40 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SET_SERIAL_CONTROL_PARAM[5];
41 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_IIC_BYPASS_MODE_PARAM[5];
42 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_SWITCH_SSPI_GPIO_PARAM[5];
43 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GPIO_LEVEL_PARAM[5];
44 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_GPIO_OUT_ENABLE_PARAM[5];
45 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_DO_IQ_SWAP_PARAM[5];
46 UADP_STRUCT_POINTER_TABLE spt_DMD_ATSC_REG_PARAM[5];
47
48 MS_U32 ATSC_adp_Ioctl(void* pInstanceTmp, MS_U32 u32Cmd, void* const pArgs);
49
ATSC_adp_Init(FUtopiaIOctl * pIoctl)50 MS_U32 ATSC_adp_Init(FUtopiaIOctl* pIoctl)
51 {
52 DMD_DBG(printk("ATSC_adp_Init\n"));
53
54 UADP_SPT_BGN(&spt_DMD_ATSC_PTR_VAL[0], 8);
55 UADP_SPT_FIN(&spt_DMD_ATSC_PTR_VAL[1]);
56
57 UADP_SPT_BGN(&spt_DMD_ATSC_DBG_LEVEL_PARAM[0], sizeof(ATSC_DBG_LEVEL_PARAM));
58 UADP_SPT_FIN(&spt_DMD_ATSC_DBG_LEVEL_PARAM[1]);
59
60 UADP_SDT_BGN(&spt_DMD_ATSC_Info[0], sizeof(DMD_ATSC_Info));
61 UADP_SDT_FIN(&spt_DMD_ATSC_Info[1]);
62 UADP_SDT_BGN(&spt_DMD_ATSC_GET_INFO_PARAM[0], sizeof(ATSC_GET_INFO_PARAM));
63 UADP_SDT_KIND(&spt_DMD_ATSC_GET_INFO_PARAM[1], ATSC_GET_INFO_PARAM, UADP_SDT_P2N, pInfo, spt_DMD_ATSC_Info);
64 UADP_SDT_FIN(&spt_DMD_ATSC_GET_INFO_PARAM[2]);
65
66 UADP_SPT_BGN(&spt_DMD_ATSC_ID_PARAM[0], sizeof(ATSC_ID_PARAM));
67 UADP_SPT_FIN(&spt_DMD_ATSC_ID_PARAM[1]);
68
69 UADP_SDT_BGN(&spt_DMD_ATSC_InitData[0], sizeof(DMD_ATSC_InitData));
70 UADP_SDT_KIND(&spt_DMD_ATSC_InitData[1], DMD_ATSC_InitData, UADP_SDT_P2N, u8DMD_ATSC_DSPRegInitExt, spt_DMD_ATSC_PTR_VAL);
71 UADP_SDT_KIND(&spt_DMD_ATSC_InitData[2], DMD_ATSC_InitData, UADP_SDT_P2N, u8DMD_ATSC_InitExt, spt_DMD_ATSC_PTR_VAL);
72 UADP_SDT_KIND(&spt_DMD_ATSC_InitData[3], DMD_ATSC_InitData, UADP_SDT_AT, I2C_WriteBytes, spt_DMD_ATSC_PTR_VAL);
73 UADP_SDT_KIND(&spt_DMD_ATSC_InitData[4], DMD_ATSC_InitData, UADP_SDT_AT, I2C_ReadBytes, spt_DMD_ATSC_PTR_VAL);
74 UADP_SDT_FIN(&spt_DMD_ATSC_InitData[5]);
75
76 UADP_SDT_BGN(&spt_DMD_ATSC_INIT_PARAM[0], sizeof(ATSC_INIT_PARAM));
77 UADP_SDT_KIND(&spt_DMD_ATSC_INIT_PARAM[1], ATSC_INIT_PARAM, UADP_SDT_P2N, pDMD_ATSC_InitData, spt_DMD_ATSC_InitData);
78 UADP_SDT_FIN(&spt_DMD_ATSC_INIT_PARAM[2]);
79
80 UADP_SPT_BGN(&spt_DMD_ATSC_SET_CONFIG_PARAM[0], sizeof(ATSC_SET_CONFIG_PARAM));
81 UADP_SPT_FIN(&spt_DMD_ATSC_SET_CONFIG_PARAM[1]);
82
83 UADP_SPT_BGN(&spt_DMD_ATSC_SET_QAM_SR_PARAM[0], sizeof(ATSC_SET_QAM_SR_PARAM));
84 UADP_SPT_FIN(&spt_DMD_ATSC_SET_QAM_SR_PARAM[1]);
85
86 UADP_SPT_BGN(&spt_DMD_ATSC_SET_ACTIVE_PARAM[0], sizeof(ATSC_SET_ACTIVE_PARAM));
87 UADP_SPT_FIN(&spt_DMD_ATSC_SET_ACTIVE_PARAM[1]);
88
89 UADP_SPT_BGN(&spt_DMD_ATSC_SET_POWER_STATE_PARAM[0], sizeof(ATSC_SET_POWER_STATE_PARAM));
90 UADP_SPT_FIN(&spt_DMD_ATSC_SET_POWER_STATE_PARAM[1]);
91
92 UADP_SPT_BGN(&spt_DMD_ATSC_GET_LOCK_PARAM[0], sizeof(ATSC_GET_LOCK_PARAM));
93 UADP_SPT_FIN(&spt_DMD_ATSC_GET_LOCK_PARAM[1]);
94
95 UADP_SPT_BGN(&spt_DMD_ATSC_GET_MODULATION_MODE_PARAM[0], sizeof(ATSC_GET_MODULATION_MODE_PARAM));
96 UADP_SPT_FIN(&spt_DMD_ATSC_GET_MODULATION_MODE_PARAM[1]);
97
98 UADP_SPT_BGN(&spt_DMD_ATSC_GET_SIGNAL_STRENGTH_PARAM[0], sizeof(ATSC_GET_SIGNAL_STRENGTH_PARAM));
99 UADP_SPT_FIN(&spt_DMD_ATSC_GET_SIGNAL_STRENGTH_PARAM[1]);
100
101 UADP_SPT_BGN(&spt_DMD_ATSC_GET_SIGNAL_QUALITY_PARAM[0], sizeof(ATSC_GET_SIGNAL_QUALITY_PARAM));
102 UADP_SPT_FIN(&spt_DMD_ATSC_GET_SIGNAL_QUALITY_PARAM[1]);
103
104 UADP_SPT_BGN(&spt_DMD_ATSC_GET_SNR_PERCENTAGE_PARAM[0], sizeof(ATSC_GET_SNR_PERCENTAGE_PARAM));
105 UADP_SPT_FIN(&spt_DMD_ATSC_GET_SNR_PERCENTAGE_PARAM[1]);
106
107 UADP_SPT_BGN(&spt_DMD_ATSC_SnrData[0], sizeof(DMD_ATSC_SNR_DATA));
108 UADP_SPT_FIN(&spt_DMD_ATSC_SnrData[1]);
109 UADP_SPT_BGN(&spt_DMD_ATSC_GET_SNR_PARAM[0], sizeof(ATSC_GET_SNR_PARAM));
110 UADP_SPT_NXT(&spt_DMD_ATSC_GET_SNR_PARAM[1], ATSC_GET_SNR_PARAM, snr, spt_DMD_ATSC_SnrData);
111 UADP_SPT_FIN(&spt_DMD_ATSC_GET_SNR_PARAM[2]);
112
113 UADP_SPT_BGN(&spt_DMD_ATSC_GET_UCPKT_ERR_PARAM[0], sizeof(ATSC_GET_UCPKT_ERR_PARAM));
114 UADP_SPT_FIN(&spt_DMD_ATSC_GET_UCPKT_ERR_PARAM[1]);
115
116 UADP_SPT_BGN(&spt_DMD_ATSC_BerData[0], sizeof(DMD_ATSC_BER_DATA));
117 UADP_SPT_FIN(&spt_DMD_ATSC_BerData[1]);
118 UADP_SPT_BGN(&spt_DMD_ATSC_GET_BER_PARAM[0], sizeof(ATSC_GET_BER_PARAM));
119 UADP_SPT_NXT(&spt_DMD_ATSC_GET_BER_PARAM[1], ATSC_GET_BER_PARAM, ber, spt_DMD_ATSC_BerData);
120 UADP_SPT_FIN(&spt_DMD_ATSC_GET_BER_PARAM[2]);
121
122 UADP_SPT_BGN(&spt_DMD_ATSC_CfoData[0], sizeof(DMD_ATSC_CFO_DATA));
123 UADP_SPT_FIN(&spt_DMD_ATSC_CfoData[1]);
124 UADP_SPT_BGN(&spt_DMD_ATSC_READ_FREQ_OFFSET_PARAM[0], sizeof(ATSC_READ_FREQ_OFFSET_PARAM));
125 UADP_SPT_NXT(&spt_DMD_ATSC_READ_FREQ_OFFSET_PARAM[1], ATSC_READ_FREQ_OFFSET_PARAM, cfo, spt_DMD_ATSC_CfoData);
126 UADP_SPT_FIN(&spt_DMD_ATSC_READ_FREQ_OFFSET_PARAM[2]);
127
128 UADP_SPT_BGN(&spt_DMD_ATSC_SET_SERIAL_CONTROL_PARAM[0], sizeof(ATSC_SET_SERIAL_CONTROL_PARAM));
129 UADP_SPT_FIN(&spt_DMD_ATSC_SET_SERIAL_CONTROL_PARAM[1]);
130
131 UADP_SPT_BGN(&spt_DMD_ATSC_IIC_BYPASS_MODE_PARAM[0], sizeof(ATSC_IIC_BYPASS_MODE_PARAM));
132 UADP_SPT_FIN(&spt_DMD_ATSC_IIC_BYPASS_MODE_PARAM[1]);
133
134 UADP_SPT_BGN(&spt_DMD_ATSC_SWITCH_SSPI_GPIO_PARAM[0], sizeof(ATSC_SWITCH_SSPI_GPIO_PARAM));
135 UADP_SPT_FIN(&spt_DMD_ATSC_SWITCH_SSPI_GPIO_PARAM[1]);
136
137 UADP_SPT_BGN(&spt_DMD_ATSC_GPIO_LEVEL_PARAM[0], sizeof(ATSC_GPIO_LEVEL_PARAM));
138 UADP_SPT_FIN(&spt_DMD_ATSC_GPIO_LEVEL_PARAM[1]);
139
140 UADP_SPT_BGN(&spt_DMD_ATSC_GPIO_OUT_ENABLE_PARAM[0], sizeof(ATSC_GPIO_OUT_ENABLE_PARAM));
141 UADP_SPT_FIN(&spt_DMD_ATSC_GPIO_OUT_ENABLE_PARAM[1]);
142
143 UADP_SPT_BGN(&spt_DMD_ATSC_DO_IQ_SWAP_PARAM[0], sizeof(ATSC_DO_IQ_SWAP_PARAM));
144 UADP_SPT_FIN(&spt_DMD_ATSC_DO_IQ_SWAP_PARAM[1]);
145
146 UADP_SPT_BGN(&spt_DMD_ATSC_REG_PARAM[0], sizeof(ATSC_REG_PARAM));
147 UADP_SPT_FIN(&spt_DMD_ATSC_REG_PARAM[1]);
148
149 *pIoctl= (FUtopiaIOctl)ATSC_adp_Ioctl;
150
151 return 0;
152 }
153
ATSC_adp_Ioctl(void * pInstanceTmp,MS_U32 u32Cmd,void * const pArgs)154 MS_U32 ATSC_adp_Ioctl(void* pInstanceTmp, MS_U32 u32Cmd, void* const pArgs)
155 {
156 MS_U32 u32Ret = UTOPIA_STATUS_FAIL;
157 char buffer_arg[2048];
158
159 switch(u32Cmd)
160 {
161 case DMD_ATSC_DRV_CMD_SetDbgLevel:
162 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_SetDbgLevel\n"));
163 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_DBG_LEVEL_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
164 break;
165 case DMD_ATSC_DRV_CMD_GetInfo:
166 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_GetInfo\n"));
167 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_INFO_PARAM, spt_DMD_ATSC_GET_INFO_PARAM, buffer_arg, sizeof(buffer_arg));
168 break;
169 case DMD_ATSC_DRV_CMD_GetLibVer:
170 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_GetLibVer\n"));
171 break;
172 case DMD_ATSC_DRV_CMD_Init:
173 case DMD_ATSC_DRV_CMD_MD_Init:
174 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_Init\n"));
175 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_INIT_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
176 break;
177 case DMD_ATSC_DRV_CMD_Exit:
178 case DMD_ATSC_DRV_CMD_MD_Exit:
179 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_Exit\n"));
180 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_ID_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
181 break;
182 case DMD_ATSC_DRV_CMD_GetConfig:
183 case DMD_ATSC_DRV_CMD_MD_GetConfig:
184 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetConfig\n"));
185 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_INIT_PARAM, spt_DMD_ATSC_INIT_PARAM, buffer_arg, sizeof(buffer_arg));
186 break;
187 case DMD_ATSC_DRV_CMD_SetConfig:
188 case DMD_ATSC_DRV_CMD_MD_SetConfig:
189 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SetConfig\n"));
190 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_SET_CONFIG_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
191 break;
192 case DMD_ATSC_DRV_CMD_SetReset:
193 case DMD_ATSC_DRV_CMD_MD_SetReset:
194 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SetReset\n"));
195 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_ID_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
196 break;
197 case DMD_ATSC_DRV_CMD_Set_QAM_SR:
198 case DMD_ATSC_DRV_CMD_MD_Set_QAM_SR:
199 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_Set_QAM_SR\n"));
200 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_SET_QAM_SR_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
201 break;
202 case DMD_ATSC_DRV_CMD_SetActive:
203 case DMD_ATSC_DRV_CMD_MD_SetActive:
204 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SetActive\n"));
205 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_SET_ACTIVE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
206 break;
207 case DMD_ATSC_DRV_CMD_SetPowerState:
208 case DMD_ATSC_DRV_CMD_MD_SetPowerState:
209 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SetPowerState\n"));
210 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_SET_POWER_STATE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
211 break;
212 case DMD_ATSC_DRV_CMD_GetLock:
213 case DMD_ATSC_DRV_CMD_MD_GetLock:
214 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetLock\n"));
215 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_LOCK_PARAM, spt_DMD_ATSC_GET_LOCK_PARAM, buffer_arg, sizeof(buffer_arg));
216 break;
217 case DMD_ATSC_DRV_CMD_GetModulationMode:
218 case DMD_ATSC_DRV_CMD_MD_GetModulationMode:
219 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetModulationMode\n"));
220 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_MODULATION_MODE_PARAM, spt_DMD_ATSC_GET_MODULATION_MODE_PARAM, buffer_arg, sizeof(buffer_arg));
221 break;
222 case DMD_ATSC_DRV_CMD_GetSignalStrength:
223 case DMD_ATSC_DRV_CMD_MD_GetSignalStrength:
224 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetSignalStrength\n"));
225 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_SIGNAL_STRENGTH_PARAM, spt_DMD_ATSC_GET_SIGNAL_STRENGTH_PARAM, buffer_arg, sizeof(buffer_arg));
226 break;
227 case DMD_ATSC_DRV_CMD_GetSignalQuality:
228 case DMD_ATSC_DRV_CMD_MD_GetSignalQuality:
229 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetSignalQuality\n"));
230 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_SIGNAL_QUALITY_PARAM, spt_DMD_ATSC_GET_SIGNAL_QUALITY_PARAM, buffer_arg, sizeof(buffer_arg));
231 break;
232 case DMD_ATSC_DRV_CMD_GetSNRPercentage:
233 case DMD_ATSC_DRV_CMD_MD_GetSNRPercentage:
234 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetSNRPercentage\n"));
235 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_SNR_PERCENTAGE_PARAM, spt_DMD_ATSC_GET_SNR_PERCENTAGE_PARAM, buffer_arg, sizeof(buffer_arg));
236 break;
237 case DMD_ATSC_DRV_CMD_GET_QAM_SNR:
238 case DMD_ATSC_DRV_CMD_MD_GET_QAM_SNR:
239 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GET_QAM_SNR\n"));
240 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_SNR_PARAM, spt_DMD_ATSC_GET_SNR_PARAM, buffer_arg, sizeof(buffer_arg));
241 break;
242 case DMD_ATSC_DRV_CMD_Read_uCPKT_ERR:
243 case DMD_ATSC_DRV_CMD_MD_Read_uCPKT_ERR:
244 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_Read_uCPKT_ERR\n"));
245 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, NULL, spt_DMD_ATSC_GET_UCPKT_ERR_PARAM, buffer_arg, sizeof(buffer_arg));
246 break;
247 case DMD_ATSC_DRV_CMD_GetPreViterbiBer:
248 case DMD_ATSC_DRV_CMD_MD_GetPreViterbiBer:
249 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetPreViterbiBer\n"));
250 break;
251 case DMD_ATSC_DRV_CMD_GetPostViterbiBer:
252 case DMD_ATSC_DRV_CMD_MD_GetPostViterbiBer:
253 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetPostViterbiBer\n"));
254 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GET_BER_PARAM, spt_DMD_ATSC_GET_BER_PARAM, buffer_arg, sizeof(buffer_arg));
255 break;
256 case DMD_ATSC_DRV_CMD_ReadFrequencyOffset:
257 case DMD_ATSC_DRV_CMD_MD_ReadFrequencyOffset:
258 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_ReadFrequencyOffset\n"));
259 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_READ_FREQ_OFFSET_PARAM, spt_DMD_ATSC_READ_FREQ_OFFSET_PARAM, buffer_arg, sizeof(buffer_arg));
260 break;
261 case DMD_ATSC_DRV_CMD_SetSerialControl:
262 case DMD_ATSC_DRV_CMD_MD_SetSerialControl:
263 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SetSerialControl\n"));
264 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_SET_SERIAL_CONTROL_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
265 break;
266 case DMD_ATSC_DRV_CMD_IIC_BYPASS_MODE:
267 case DMD_ATSC_DRV_CMD_MD_IIC_BYPASS_MODE:
268 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_IIC_BYPASS_MODE\n"));
269 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_IIC_BYPASS_MODE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
270 break;
271 case DMD_ATSC_DRV_CMD_SWITCH_SSPI_GPIO:
272 case DMD_ATSC_DRV_CMD_MD_SWITCH_SSPI_GPIO:
273 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SWITCH_SSPI_GPIO\n"));
274 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_SWITCH_SSPI_GPIO_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
275 break;
276 case DMD_ATSC_DRV_CMD_GPIO_GET_LEVEL:
277 case DMD_ATSC_DRV_CMD_MD_GPIO_GET_LEVEL:
278 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GPIO_GET_LEVEL\n"));
279 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GPIO_LEVEL_PARAM, spt_DMD_ATSC_GPIO_LEVEL_PARAM, buffer_arg, sizeof(buffer_arg));
280 break;
281 case DMD_ATSC_DRV_CMD_GPIO_SET_LEVEL:
282 case DMD_ATSC_DRV_CMD_MD_GPIO_SET_LEVEL:
283 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GPIO_SET_LEVEL\n"));
284 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GPIO_LEVEL_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
285 break;
286 case DMD_ATSC_DRV_CMD_GPIO_OUT_ENABLE:
287 case DMD_ATSC_DRV_CMD_MD_GPIO_OUT_ENABLE:
288 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GPIO_OUT_ENABLE\n"));
289 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_GPIO_OUT_ENABLE_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
290 break;
291 case DMD_ATSC_DRV_CMD_DoIQSwap:
292 case DMD_ATSC_DRV_CMD_MD_DoIQSwap:
293 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_DO_IQ_SWAP\n"));
294 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_DO_IQ_SWAP_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
295 break;
296 case DMD_ATSC_DRV_CMD_GetReg:
297 case DMD_ATSC_DRV_CMD_MD_GetReg:
298 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_GetReg\n"));
299 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_REG_PARAM, spt_DMD_ATSC_REG_PARAM, buffer_arg, sizeof(buffer_arg));
300 break;
301 case DMD_ATSC_DRV_CMD_SetReg:
302 case DMD_ATSC_DRV_CMD_MD_SetReg:
303 DMD_DBG(printk("ATSC_adp_Ioctl - MDrv_DMD_ATSC_MD_SetReg\n"));
304 u32Ret = UADPBypassIoctl(pInstanceTmp, u32Cmd, pArgs, spt_DMD_ATSC_REG_PARAM, NULL, buffer_arg, sizeof(buffer_arg));
305 break;
306 default:
307 break;
308 }
309
310 return u32Ret;
311 }
312