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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT2.c
98 /// @brief INTERN_DVBT2 DVBT2
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT2_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 //#include "BinInfo.h"
114 #include "drvDMD_VD_MBX.h"
115 #include "drvDMD_INTERN_DVBT2.h"
116 #include "halDMD_INTERN_DVBT2.h"
117 #include "halDMD_INTERN_common.h"
118
119 extern void *memcpy(void *destination, const void *source, size_t num);
120
121 #define TEST_EMBEDED_DEMOD 0
122 //U8 load_data_variable=1;
123 //-----------------------------------------------------------------------
124 #define BIN_ID_INTERN_DVBT2_DEMOD BIN_ID_INTERN_DVBT
125
126 #define TDE_REG_BASE 0x2400
127 #define DIV_REG_BASE 0x2500
128 #define TR_REG_BASE 0x2600
129 #define FTN_REG_BASE 0x2700
130 #define FTNEXT_REG_BASE 0x2800
131
132
133 #define INTERNAL_DVBT2_DRAM_OFFSET 0x5000
134 #define INTERNAL_DVBT2_FW_LEN (0x10000 - INTERNAL_DVBT2_DRAM_OFFSET)
135 #define INTERNAL_DVBT2_PS2XDATA_LEN 15
136
137
138 #if 0//ENABLE_SCAN_ONELINE_MSG
139 #define DBG_INTERN_DVBT2_ONELINE(x) x
140 #else
141 #define DBG_INTERN_DVBT2_ONELINE(x) // x
142 #endif
143
144 #ifdef MS_DEBUG
145 #define DBG_INTERN_DVBT2(x) x
146 #define DBG_GET_SIGNAL(x) x
147 #define DBG_INTERN_DVBT2_TIME(x) x
148 #define DBG_INTERN_DVBT2_LOCK(x) x
149 #else
150 #define DBG_INTERN_DVBT2(x) //x
151 #define DBG_GET_SIGNAL(x) //x
152 #define DBG_INTERN_DVBT2_TIME(x) // x
153 #define DBG_INTERN_DVBT2_LOCK(x) //x
154 #endif
155 #define DBG_DUMP_LOAD_DSP_TIME 0
156
157 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0
158 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1
159 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1
160 #define INTERN_DVBT2_INTERNAL_DEBUG 1
161
162 #define SIGNAL_LEVEL_OFFSET 0.00
163 #define TAKEOVERPOINT -59.0
164 #define TAKEOVERRANGE 0.5
165 #define LOG10_OFFSET -0.21
166 #define INTERN_DVBT2_USE_SAR_3_ENABLE 0
167 #define INTERN_DVBT2_GET_TIME msAPI_Timer_GetTime0()
168 #define AUTO_TS_DATA_RATE 1
169
170 #if(AUTO_TS_DATA_RATE)
171 #define TS_DATA_RATE_RATIO 1.01
172 #define DBG_AUTO_TS_DATA_RATE(x)
173 #endif
174
175 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
176 #define TUNER_VPP 2
177 #define IF_AGC_VPP 2
178 #else
179 #define TUNER_VPP 1
180 #define IF_AGC_VPP 2
181 #endif
182
183 #if (TUNER_VPP == 1)
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
185 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
186 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
187 #endif
188
189 /*BEG INTERN_DVBT2_DSPREG_TABLE*/
190 #define DVBT2_FS 24000
191
192 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
193 #define T2_BW_VAL 0x04
194 // FC: FC = FS = 5000 = 0x1388 (5.0MHz IF)
195 #define T2_FC_L_VAL 0x88 // 5.0M
196 #define T2_FC_H_VAL 0x13
197 #define T2_TS_SERIAL_VAL 0x00
198 #define T2_TS_CLK_RATE_VAL 0x06
199 #define T2_TS_OUT_INV_VAL 0x00
200 #define T2_TS_DATA_SWAP_VAL 0x00
201 #define T2_IF_AGC_INV_PWM_EN_VAL 0x00
202 #define T2_LITE_VAL 0x00
203 #define T2_AGC_REF_VAL 0x40
204
205 #define DVBT2_BER_TH_HY 0.1
206
207 /*END INTERN_DVBT2_DSPREG_TABLE*/
208 //-----------------------------------------------------------------------
209 /****************************************************************
210 *Local Variables *
211 ****************************************************************/
212 static MS_BOOL bFECLock=0;
213 static MS_BOOL bP1Lock = 0;
214 static MS_U32 u32ChkScanTimeStart = 0;
215 static MS_U32 u32FecFirstLockTime=0;
216 static MS_U32 u32FecLastLockTime=0;
217 static float fLDPCBerFiltered=-1;
218 static float fBerFilteredDVBT2 = -1.0;
219
220 //Global Variables
221 S_CMDPKTREG gsCmdPacket;
222 //U8 gCalIdacCh0, gCalIdacCh1;
223 extern MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
224 extern MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
225 extern MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
226 extern MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
227 extern MS_U32 u32DMD_DVBT2_FW_START_ADDR;
228
229 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
230 MS_U8 INTERN_DVBT2_table[] = {
231 #include "fwDMD_INTERN_DVBT2.dat"
232 };
233
234 #endif
235 /*
236 static DMD_T2_SSI_DBM_NORDIGP1 dvbt2_ssi_dbm_nordigp1[] =
237 {
238 {_T2_QPSK, _T2_CR1Y2, -95.7},
239 {_T2_QPSK, _T2_CR3Y5, -94.4},
240 {_T2_QPSK, _T2_CR2Y3, -93.6},
241 {_T2_QPSK, _T2_CR3Y4, -92.6},
242 {_T2_QPSK, _T2_CR4Y5, -92.0},
243 {_T2_QPSK, _T2_CR5Y6, -91.5},
244
245 {_T2_16QAM, _T2_CR1Y2, -90.8},
246 {_T2_16QAM, _T2_CR3Y5, -89.1},
247 {_T2_16QAM, _T2_CR2Y3, -87.9},
248 {_T2_16QAM, _T2_CR3Y4, -86.7},
249 {_T2_16QAM, _T2_CR4Y5, -85.8},
250 {_T2_16QAM, _T2_CR5Y6, -85.2},
251
252 {_T2_64QAM, _T2_CR1Y2, -86.9},
253 {_T2_64QAM, _T2_CR3Y5, -84.6},
254 {_T2_64QAM, _T2_CR2Y3, -83.2},
255 {_T2_64QAM, _T2_CR3Y4, -81.4},
256 {_T2_64QAM, _T2_CR4Y5, -80.3},
257 {_T2_64QAM, _T2_CR5Y6, -79.7},
258
259 {_T2_256QAM, _T2_CR1Y2, -83.5},
260 {_T2_256QAM, _T2_CR3Y5, -80.4},
261 {_T2_256QAM, _T2_CR2Y3, -78.6},
262 {_T2_256QAM, _T2_CR3Y4, -76.0},
263 {_T2_256QAM, _T2_CR4Y5, -74.4},
264 {_T2_256QAM, _T2_CR5Y6, -73.3},
265 {_T2_QAM_UNKNOWN, _T2_CR_UNKNOWN, 0.0}
266 };
267 */
268 static float dvbt2_ssi_dbm_nordigp1[][6] =
269 {
270 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
271 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
272 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
273 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
274 };
275
276 // cr, 3/5(1), 2/3(2), 3/4 (3)
277 float fT2_SSI_formula[][12]=
278 {
279 {1.0/5, 97.0, 3.0/2, 82.0, 16.0/5, 50.0, 29.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/5
280 {2.0/3, 95.0, 9.0/5, 77.0, 17.0/5, 43.0, 14.0/5.0, 15.0, 13.0/15, 2.0, 2.0/5, 0.0}, // CR2/3
281 {1.0/2, 93.0, 19.0/10, 74.0, 31.0/10, 43.0, 22.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/4
282 };
283 static void INTERN_DVBT2_SignalQualityReset(void);
284 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void);
285
286 #if (AUTO_TS_DATA_RATE)
287 MS_BOOL INTERN_DVBT2_GetTsDivNum(MS_U8* u8TSDivNum);
288 MS_BOOL INTERN_DVBT2_ConfigAdaptiveTsDivNum(void);
289 #endif
290
INTERN_DVBT2_SignalQualityReset(void)291 static void INTERN_DVBT2_SignalQualityReset(void)
292 {
293 u32FecFirstLockTime=0;
294 fLDPCBerFiltered=-1;
295 }
296
INTERN_DVBT2_DSPReg_Init(const MS_U8 * u8DVBT2_DSPReg,MS_U8 u8Size)297 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT2_DSPReg, MS_U8 u8Size)
298 {
299 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
300 MS_BOOL status = TRUE;
301 MS_U16 u16DspAddr = 0;
302
303 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_DSPReg_Init\n"));
304
305 //for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
306 // status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
307 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_BW, T2_BW_VAL) != TRUE)
308 {
309 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
310 }
311 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_L, T2_FC_L_VAL) != TRUE)
312 {
313 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
314 }
315 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_H, T2_FC_H_VAL) != TRUE)
316 {
317 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
318 }
319 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_SERIAL, T2_TS_SERIAL_VAL) != TRUE)
320 {
321 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
322 }
323 //if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_CLK_RATE, T2_TS_CLK_RATE_VAL) != TRUE)
324 //{
325 // printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
326 //}
327 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_OUT_INV, T2_TS_OUT_INV_VAL) != TRUE)
328 {
329 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
330 }
331 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_SWAP, T2_TS_DATA_SWAP_VAL) != TRUE)
332 {
333 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
334 }
335 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_IF_AGC_INV_PWM_EN, T2_IF_AGC_INV_PWM_EN_VAL) != TRUE)
336 {
337 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
338 }
339 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_LITE, T2_LITE_VAL) != TRUE)
340 {
341 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
342 }
343
344 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_AGC_REF, T2_AGC_REF_VAL) != TRUE) //brown:0x40->agc_ref
345 {
346 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
347 }
348
349 if (u8DVBT2_DSPReg != NULL)
350 {
351 /*temp solution until new dsp table applied.*/
352 // if (INTERN_DVBT2_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
353 if (u8DVBT2_DSPReg[0] >= 1)
354 {
355 u8DVBT2_DSPReg+=2;
356 for (idx = 0; idx<u8Size; idx++)
357 {
358 u16DspAddr = *u8DVBT2_DSPReg;
359 u8DVBT2_DSPReg++;
360 u16DspAddr = (u16DspAddr) + ((*u8DVBT2_DSPReg)<<8);
361 u8DVBT2_DSPReg++;
362 u8Mask = *u8DVBT2_DSPReg;
363 u8DVBT2_DSPReg++;
364 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
365 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT2_DSPReg) & (u8Mask));
366 u8DVBT2_DSPReg++;
367 DBG_INTERN_DVBT2(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
368 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
369 }
370 }
371 else
372 {
373 printf("FATAL: parameter version incorrect\n");
374 }
375 }
376
377 return status;
378 }
379
380 /***********************************************************************************
381 Subject: SoftStop
382 Function: INTERN_DVBT2_SoftStop
383 Parmeter:
384 Return: MS_BOOL
385 Remark:
386 ************************************************************************************/
387
INTERN_DVBT2_SoftStop(void)388 MS_BOOL INTERN_DVBT2_SoftStop ( void )
389 {
390 MS_U16 u8WaitCnt=0;
391 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
392 {
393 printf(">> MB Busy!\n");
394 return FALSE;
395 }
396
397 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
398
399 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
400 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
401
402 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
403 {
404 if (u8WaitCnt++ >= 0xFFF)
405 {
406 printf(">> DVBT2 SoftStop Fail!\n");
407 return FALSE;
408 }
409 }
410
411 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
412 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
413 return TRUE;
414 }
415
INTERN_DVBT2_SoftReset(void)416 MS_BOOL INTERN_DVBT2_SoftReset ( void )
417 {
418 MS_BOOL bRet=TRUE;
419 //MS_U8 u8Data, fdp_fifo_done, djb_fifo_done, tdi_fifo_done;
420 MS_U8 u8Data = 0, fdp_fifo_done = 0, tdi_fifo_done = 0;
421 MS_U8 u8_timeout = 0;
422
423 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_SoftReset\n"));
424
425 //stop FSM_EN
426 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN
427
428 MsOS_DelayTask(5);
429
430 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
431 DBG_INTERN_DVBT2(printf("@@@TOP_RESET:0x%x\n", u8Data));
432 // MIU hold function
433 if((u8Data & 0x20) == 0x00)
434 {
435 // mask miu service with fdp, djb, tdi
436 //fdp 0x17 [12] reg_fdp_fifo_stop=1'b1
437 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
438 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10));
439 // [8] reg_fdp_load, fdp register dynamic change protection, 1->load register
440 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10);
441 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
442 //printf("@@@@@@ DVBT2 [reg_fdp_fifo_stop]=0x%x\n", u8Data);
443 //djb 0x65 [0] reg_stop_mu_request
444 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01));
446 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
447 //printf("@@@@@@ DVBT2 [reg_stop_mu_request]=0x%x\n", u8Data);
448 //snr 0x23 [8] reg_tdi_miu_off
449 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
450 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01));
451 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
452 //printf("@@@@@@ DVBT2 [reg_tdi_miu_off]=0x%x\n", u8Data);
453 // ---------------------------------------------
454 // Wait MIU mask or timeout!
455 // DVBT2_TIMER_INT[ 7:0] : indicator of the selected Timer's max count(15:8) (r)
456 // DVBT2_TIMER_INT[11:8] : timer3~timer0 interrupt (r)
457 // ---------------------------------------------
458 //fdp 0x18 [2] reg_fdp_fifo_req_done
459 //djb 0x65 [8] reg_miu_req_terminate_done
460 //tdi 0x23 [9] reg_tdi_miu_off_done
461 do
462 {
463 // Wait MIU mask done or timeout!
464 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data);
465 fdp_fifo_done = u8Data & 0x04;
466 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2)+1, &u8Data);
467 //djb_fifo_done = u8Data & 0x01;
468 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
469 tdi_fifo_done = u8Data & 0x02;
470
471 u8_timeout++;
472 }
473 //while(((fdp_fifo_done != 0x04)||(djb_fifo_done != 0x01)||(tdi_fifo_done != 0x02))
474 while(((fdp_fifo_done != 0x04)||(tdi_fifo_done != 0x02))
475 && u8_timeout != 0x7f);
476
477 //printf(">> DVBT2 fdp_fifo_done=%d, djb_fifo_done=%d, tdi_fifo_done=%d \n", fdp_fifo_done, djb_fifo_done, tdi_fifo_done);
478 printf(">> DVBT2 [fdp_fifo_done]=%d, [tdi_fifo_done]=%d \n", fdp_fifo_done, tdi_fifo_done);
479
480 MsOS_DelayTask(2);
481
482 if(u8_timeout == 0x7f)
483 {
484 printf(">> DVBT2 MIU hold function Fail!\n");
485 //return FALSE;
486 }
487 else
488 {
489 printf(">> DVBT2 MIU hold function done!!\n");
490 }
491 }
492 else
493 printf(">> No need DVBT2 MIU hold function!!\n");
494
495 // demod_top reset
496 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
497 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data|0x20));
498
499 MsOS_DelayTask(1);
500
501 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data&(~0x20)));
502
503 DBG_INTERN_DVBT2(printf("@INTERN_DVBT2_SoftReset done!!\n"));
504
505 return bRet;
506 }
507
508
509 /***********************************************************************************
510 Subject: Reset
511 Function: INTERN_DVBT2_Reset
512 Parmeter:
513 Return: MS_BOOL
514 Remark:
515 ************************************************************************************/
516 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT2_Reset(void)517 MS_BOOL INTERN_DVBT2_Reset ( void )
518 {
519 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_reset\n"));
520
521 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Reset, t = %ld\n",MsOS_GetSystemTime()));
522
523 //INTERN_DVBT2_SoftStop();
524
525
526 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
527 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset DMD_MCU
528 MsOS_DelayTask(5);
529 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
530
531 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
532 MsOS_DelayTask(5);
533
534 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
535 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
536
537 bFECLock = FALSE;
538 bP1Lock = FALSE;
539 u32ChkScanTimeStart = MsOS_GetSystemTime();
540 return TRUE;
541 }
542
543 /***********************************************************************************
544 Subject: Exit
545 Function: INTERN_DVBT2_Exit
546 Parmeter:
547 Return: MS_BOOL
548 Remark:
549 ************************************************************************************/
INTERN_DVBT2_Exit(void)550 MS_BOOL INTERN_DVBT2_Exit ( void )
551 {
552 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_Exit\n"));
553
554 INTERN_DVBT2_SoftStop();
555
556 // SRAM End Address
557 HAL_DMD_RIU_WriteByte(0x111707,0xff);
558 HAL_DMD_RIU_WriteByte(0x111706,0xff);
559
560 // DRAM Disable
561 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
562
563
564 //diable clk gen
565 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
566 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
567 /*
568 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
569 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
570
571 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
572 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
573
574 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
575 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
576
577 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
578 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
579
580 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
581 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
582
583 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
584 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
585
586 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
587 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
588
589 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
590 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
591
592 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
593 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
594
595 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
596 */
597 return TRUE;
598 }
599 /*
600 MS_BOOL INTERN_DVBT2_Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length)
601 {
602
603 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Load2Sdram, len=0x%x, \n",data_length));
604 MS_U8 addrhi, addrlo;
605 int i, j, k, old_i=0;
606 int sdram_start_addr = 0;//1024 >> 2; //StrToInt(ed_sdram_start->Text)>>2; // 4KB alignment
607
608 //I2C_CH_Exit(); // exit CH4
609 //I2C_CH5_Reset(); // switch to CH5
610 //MDrv_DMD_I2C_Channel_Change(5);
611 //--------------------------------------------------------------------------
612 // Set xData map for DRAM
613 //--------------------------------------------------------------------------
614
615 //banknum = 0x1d; //dmdmcu51_xdmiu
616
617 //set xData map upper and low bound for 64k DRAM window
618 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x2020);
619 if(SLAVE_I2CWrite16(banknum,0x63,0x2020)==false)
620 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
621
622 //set xData map offset for 64k DRAM window
623 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x64, 0x0000);
624 if(SLAVE_I2CWrite16(banknum,0x64,0x0000)==false)
625 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
626
627 //set xData map upper and low bound for 4k DRAM window
628 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x65, 0x2420);
629 if(SLAVE_I2CWrite16(banknum,0x65,0x2420)==false)
630 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
631
632 //set xData map offset for 4k DRAM window
633 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, sdram_start_addr);
634 if(SLAVE_I2CWrite16(banknum,0x66,sdram_start_addr)==false)
635 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
636
637 //I2C_CH_Exit(); // exit CH5
638 //EnterDebugMode(1); // switch to CH1
639
640 //enable xData map for DRAM
641 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x0007);
642 if(SLAVE_I2CWrite16(banknum,0x62,0x0007)==false)
643 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
644
645
646 for ( i = 0, j = SDRAM_BASE, k = sdram_start_addr + 0x01; i < size;)
647 {
648 if (j == SDRAM_BASE + 0x1000)
649 {
650 //I2C_CH_Exit(); // exit CH1
651 //I2C_CH5_Reset(); // switch to CH5
652 //set xData map offset for 4k DRAM window
653 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, k++);
654 if(SLAVE_I2CWrite16(banknum,0x66,k++)==false)
655 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
656 j = SDRAM_BASE;
657
658 //I2C_CH_Exit(); // exit CH5
659 //EnterDebugMode(1); // switch to CH1
660
661 }
662
663 addrhi = (j >> 8) & 0xff;
664 addrlo = j & 0xff;
665
666 if (i+EZUSB_Write_Buffer<size)
667 {
668 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,EZUSB_Write_Buffer)==FALSE)
669 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
670
671 j=j+EZUSB_Write_Buffer;
672 i=i+EZUSB_Write_Buffer;
673 }
674 else
675 {
676 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,size-i)==FALSE)
677 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
678
679 i=size;
680 }
681
682 if ((i-old_i)>=2048)
683 {
684 ShowMCUDL_Progress(0,3*i,size);
685 old_i=i;
686 }
687 }//end for
688
689
690 FWDLRichEdit->Lines->Add(">SDRAM Down Load OK!");
691
692 I2C_CH_Exit(); // exit CH1
693 I2C_CH5_Reset(); // switch to CH5
694
695 //--------------------------------------------------------------------------
696 // Release xData map for SDRAM
697 //--------------------------------------------------------------------------
698
699 if(SLAVE_I2CWrite16(banknum,0x62,0x0000)==false)
700 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
701
702 }
703 */
704 /***********************************************************************************
705 Subject: Load DSP code to chip
706 Function: INTERN_DVBT2_LoadDSPCode
707 Parmeter:
708 Return: MS_BOOL
709 Remark:
710 ************************************************************************************/
INTERN_DVBT2_LoadDSPCode(void)711 static MS_BOOL INTERN_DVBT2_LoadDSPCode(void)
712 {
713 MS_U8 u8data = 0x00;
714 MS_U16 i;
715 MS_U16 fail_cnt=0;
716 //MS_U16 u16AddressOffset;
717 MS_U32 u32VA_DramCodeAddr;
718
719 #if (DBG_DUMP_LOAD_DSP_TIME==1)
720 MS_U32 u32Time;
721 #endif
722
723
724 #ifndef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
725 BININFO BinInfo;
726 MS_BOOL bResult;
727 MS_U32 u32GEAddr;
728 MS_U8 Data;
729 MS_S8 op;
730 MS_U32 srcaddr;
731 MS_U32 len;
732 MS_U32 SizeBy4K;
733 MS_U16 u16Counter=0;
734 MS_U8 *pU8Data;
735 #endif
736
737 #if 0
738 if(HAL_DMD_RIU_ReadByte(0x101E3E))
739 {
740 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
741 return FALSE;
742 }
743 #endif
744
745 // MDrv_Sys_DisableWatchDog();
746
747
748 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
749 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset VD_MCU
750 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
751 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
752 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
753 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
754 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
755
756 //// Load code thru VDMCU_IF ////
757 DBG_INTERN_DVBT2(printf(">Load Code...\n"));
758 //#ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
759 //for ( i = 0; i < sizeof(INTERN_DVBT2_table); i++)
760 //{
761 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
762 //}
763 if (sizeof(INTERN_DVBT2_table) < 0x8000)
764 {
765 printf("----->Bin file Size is not match...\n");
766 }
767 else
768 {
769 // load half code to SRAM
770 for ( i = 0; i < 0x8000; i++)
771 {
772 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
773 }
774 DBG_INTERN_DVBT2(printf(">Load SRAM code done...\n"));
775
776
777 if((u32DMD_DVBT2_FW_START_ADDR & 0x5000) != 0x5000)
778 {
779 for(i=0; i<50; i++)
780 {
781 printf(">DVB-T2 DRAM Start address is not correct!!\n");
782 }
783
784 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR);
785 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR);
786 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR);
787 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR);
788 }
789 else
790 {
791 // load another half code to SDRAM
792 // VA = MsOS_PA2KSEG1(PA); //NonCache
793 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
794 u32VA_DramCodeAddr = MsOS_PA2KSEG1(u32DMD_DVBT2_FW_START_ADDR);
795 memcpy((void*)(MS_VIRT)u32VA_DramCodeAddr, &INTERN_DVBT2_table[0x8000], sizeof(INTERN_DVBT2_table) - 0x8000);
796
797 DBG_INTERN_DVBT2(printf(">Load DRAM code done...\n"));
798 }
799 }
800
801 //#endif
802
803 //// Content verification ////
804 DBG_INTERN_DVBT2(printf(">Verify Code...\n"));
805
806 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
807 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
808
809 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
810 for ( i = 0; i < 0x8000; i++)
811 {
812 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
813 if (u8data != INTERN_DVBT2_table[i])
814 {
815 printf(">fail add = 0x%x\n", i);
816 printf(">code = 0x%x\n", INTERN_DVBT2_table[i]);
817 printf(">data = 0x%x\n", u8data);
818
819 if (fail_cnt++ > 10)
820 {
821 printf(">DVB-T2 DSP SRAM Loadcode fail!\n");
822 return false;
823 }
824 }
825 }
826 #else
827 for (i=0;i<=SizeBy4K;i++)
828 {
829 if(i==SizeBy4K)
830 len=BinInfo.B_Len%0x1000;
831 else
832 len=0x1000;
833
834 srcaddr = u32GEAddr+(0x1000*i);
835 //printf("\t i = %08LX\n", i);
836 //printf("\t len = %08LX\n", len);
837 op = 1;
838 u16Counter = 0 ;
839 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
840 while(len--)
841 {
842 u16Counter ++ ;
843 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
844 //pU8Data = (U8 *)(srcaddr|0x80000000);
845 #if OBA2
846 pU8Data = (U8 *)(srcaddr);
847 #else
848 pU8Data = (U8 *)(srcaddr|0x80000000);
849 #endif
850 Data = *pU8Data;
851
852 #if 0
853 if(u16Counter < 0x100)
854 printf("0x%bx,", Data);
855 #endif
856 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
857 if (u8data != Data)
858 {
859 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
860 printf(">code = 0x%x\n", Data);
861 printf(">data = 0x%x\n", u8data);
862
863 if (fail_cnt++ > 10)
864 {
865 printf(">DVB-T DSP Loadcode fail!");
866 return false;
867 }
868 }
869
870 srcaddr += op;
871 }
872 // printf("\n\n\n");
873 }
874 #endif
875
876 // add T2 DRAM bufer start address into fixed location
877 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
878 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
879
880 // write Start address to VD MCU 51 code sram
881 // //0x30~0x33
882 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR);
883 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 8));
884 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 16));
885 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 24));
886 //0x30~0x33
887 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_EQ_START_ADDR);
888 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 8));
889 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 16));
890 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 24));
891 //0x34~0x37
892 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_TDI_START_ADDR);
893 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 8));
894 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 16));
895 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 24));
896 //0x38~0x3b
897 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_DJB_START_ADDR);
898 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 8));
899 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 16));
900 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 24));
901 //0x3c~0x3f
902 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_FW_START_ADDR);
903 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 8));
904 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 16));
905 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 24));
906
907 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR));
908 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR));
909 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR));
910 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
911
912 #if 0
913 // DEBUG
914 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
915 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
916
917 // for ( i = 0; i < 16; i++)
918 // {
919 // u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
920 // printf(">add = 0x%x\t", i);
921 // printf(">data = 0x%x\n", u8data);
922 // }
923
924 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR);
925 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR);
926 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR);
927 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR);
928 #endif
929
930 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
931 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
932 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
933 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
934
935 DBG_INTERN_DVBT2(printf(">DSP Loadcode done."));
936 //while(load_data_variable);
937
938 return TRUE;
939 }
940
941 /***********************************************************************************
942 Subject: DVB-T CLKGEN initialized function
943 Function: INTERN_DVBT2_Power_On_Initialization
944 Parmeter:
945 Return: MS_BOOL
946 Remark:
947 ************************************************************************************/
INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)948 void INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)
949 {
950 MS_U8 temp_val;
951 MS_U16 u16_temp_val;
952
953 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_InitClkgen\n"));
954
955 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
956 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
957 // ----------------------------------------------
958 // start demod CLKGEN setting
959 // ----------------------------------------------
960 // *** Set register at CLKGEN1
961 // enable DMD MCU clock "bit[0] set 0"
962 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
963 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
964 // CLK_DMDMCU clock setting
965 // [0] disable clock
966 // [1] invert clock
967 // [4:2]
968 // 000:170 MHz(MPLL_DIV_BUf)
969 // 001:160MHz
970 // 010:144MHz
971 // 011:123MHz
972 // 100:108MHz
973 // 101:mem_clcok
974 // 110:mem_clock div 2
975 // 111:select XTAL
976 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
977 // HAL_DMD_RIU_WriteByte(0x10331e,0x1c); // 24MHz
978 HAL_DMD_RIU_WriteByte(0x10331e,0x10); // 108MHz
979
980 // set parallet ts clock
981 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
982 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
983 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0615
984 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
985 temp_val|=0x05;
986 // temp_val|=0x07;
987 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
988
989 HAL_DMD_RIU_WriteByte(0x103300,0x10);
990
991 // enable DVBTC ts clock
992 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
993 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
994 HAL_DMD_RIU_WriteByte(0x103309,0x00);
995 HAL_DMD_RIU_WriteByte(0x103308,0x00);
996
997 // enable dvbc adc clock
998 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
999 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1000 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1001 HAL_DMD_RIU_WriteByte(0x103314,0x00);
1002
1003 // ----------------------------------------------
1004 // start demod_0 CLKGEN setting
1005 // ----------------------------------------------
1006
1007 // enable clk_atsc_adcd_sync
1008 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1009 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1010 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1011 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1012
1013 //reg_ckg_dvbt_inner
1014 HAL_DMD_RIU_WriteByte(0x111f21,0x11);
1015 HAL_DMD_RIU_WriteByte(0x111f20,0x10);
1016
1017 //reg_ckg_dvbt_outer
1018 HAL_DMD_RIU_WriteByte(0x111f23,0x01);
1019 HAL_DMD_RIU_WriteByte(0x111f22,0x11);
1020
1021 //reg_ckg_acifir
1022 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
1023
1024 //reg_ckg_dvbtm_sram_t1o2x_t22x
1025 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
1026 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
1027
1028 //reg_ckg_dvbtm_sram_adc_t22x
1029 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
1030 HAL_DMD_RIU_WriteByte(0x111f2c,0x01);
1031
1032 //reg_ckg_dvbtm_sram_t12x_t24x
1033 HAL_DMD_RIU_WriteByte(0x111f2f,0x00);
1034 HAL_DMD_RIU_WriteByte(0x111f2e,0x00);
1035
1036 //reg_ckg_dvbtm_ts_in
1037 HAL_DMD_RIU_WriteByte(0x111f31,0x04);
1038 HAL_DMD_RIU_WriteByte(0x111f30,0x00);
1039
1040 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
1041 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
1042
1043 HAL_DMD_RIU_WriteByte(0x111f35,0x00);
1044 HAL_DMD_RIU_WriteByte(0x111f34,0x00);
1045
1046 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
1047 HAL_DMD_RIU_WriteByte(0x111f36,0x00);
1048
1049 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
1050 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
1051
1052 HAL_DMD_RIU_WriteByte(0x111f3d,0x00);
1053 HAL_DMD_RIU_WriteByte(0x111f3c,0x00);
1054
1055 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1056 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1057
1058 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1059 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1060
1061 HAL_DMD_RIU_WriteByte(0x111fe1,0x00);
1062 HAL_DMD_RIU_WriteByte(0x111fe0,0x00);
1063
1064 HAL_DMD_RIU_WriteByte(0x111fe3,0x00);
1065 HAL_DMD_RIU_WriteByte(0x111fe2,0x00);
1066
1067 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1068 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1069
1070 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1071 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1072
1073 HAL_DMD_RIU_WriteByte(0x111fe9,0x00);
1074 HAL_DMD_RIU_WriteByte(0x111fe8,0x00);
1075
1076 HAL_DMD_RIU_WriteByte(0x111feb,0xc8);
1077 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1078
1079 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1080 HAL_DMD_RIU_WriteByte(0x111fec,0x0c);
1081
1082 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1083 HAL_DMD_RIU_WriteByte(0x111fee,0x00);
1084
1085 // Maserati special
1086 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1087 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1088
1089 HAL_DMD_RIU_WriteByte(0x111ff0,0x00);
1090
1091 // Mulan special
1092 // TEQ CLK for DVBT2
1093 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1094
1095 // SRAM share
1096 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
1097 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
1098
1099 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1100 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1101
1102 HAL_DMD_RIU_WriteByte(0x111f79,0x00);
1103 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
1104
1105 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
1106 HAL_DMD_RIU_WriteByte(0x111f7a,0x00);
1107
1108 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1109 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1110
1111 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
1112 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
1113
1114 // 32+4K xdata sram
1115 HAL_DMD_RIU_WriteByte(0x1117e0,(0x21+INTERNAL_DVBT2_PS2XDATA_LEN-1));
1116 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1117 HAL_DMD_RIU_WriteByte(0x1117e4,(INTERNAL_DVBT2_PS2XDATA_LEN-2));
1118 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1119
1120 // SRAM allocation
1121 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1122 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1123
1124 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1125 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1126
1127 HAL_DMD_RIU_WriteByte(0x111703,0x00);
1128 HAL_DMD_RIU_WriteByte(0x111702,0x00);
1129
1130 HAL_DMD_RIU_WriteByte(0x111707,(INTERNAL_DVBT2_DRAM_OFFSET-1)>>8);
1131 HAL_DMD_RIU_WriteByte(0x111706,(INTERNAL_DVBT2_DRAM_OFFSET-1)&0xff);
1132
1133 // SDRAM address offset
1134 u16_temp_val = (MS_U16)(u32DMD_DVBT2_FW_START_ADDR>>16);
1135 HAL_DMD_RIU_WriteByte(0x11171b,(MS_U8)(u16_temp_val>>8));
1136 HAL_DMD_RIU_WriteByte(0x11171a,(MS_U8)u16_temp_val);
1137
1138 // DRAM allocation
1139 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1140 HAL_DMD_RIU_WriteByte(0x111708,0x00);
1141
1142 HAL_DMD_RIU_WriteByte(0x11170d,INTERNAL_DVBT2_DRAM_OFFSET>>8);
1143 HAL_DMD_RIU_WriteByte(0x11170c,INTERNAL_DVBT2_DRAM_OFFSET&0xff);
1144
1145 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1146 HAL_DMD_RIU_WriteByte(0x11170a,0x00);
1147
1148 HAL_DMD_RIU_WriteByte(0x11170f,0xff);
1149 HAL_DMD_RIU_WriteByte(0x11170e,0xff);
1150
1151 // DRAM EN
1152 HAL_DMD_RIU_WriteByte(0x111718,0x04);
1153
1154 // [0]switch dram address mode:
1155 // 0: address from dmdmcu51 bank (old mode)
1156 // 1: address from dmdmcu51_top bank (new mode)
1157 HAL_DMD_RIU_WriteByte(0x11171c,0x01);
1158
1159 // ----------------------------------------------
1160 // start demod CLKGEN setting
1161 // ----------------------------------------------
1162 // select DMD MCU
1163 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1164 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1165 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1166
1167 // stream2miu_en, activate rst_wadr
1168 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1169 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1170 // stream2miu_en, turn off rst_wadr
1171 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1172
1173 }
1174
1175 /***********************************************************************************
1176 Subject: Power on initialized function
1177 Function: INTERN_DVBT2_Power_On_Initialization
1178 Parmeter:
1179 Return: MS_BOOL
1180 Remark:
1181 ************************************************************************************/
1182
INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT2_DSPRegInitExt,MS_U8 u8DMD_DVBT2_DSPRegInitSize)1183 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT2_DSPRegInitExt, MS_U8 u8DMD_DVBT2_DSPRegInitSize)
1184 {
1185 MS_U16 status = true;
1186
1187 // MS_U8 temp_val;
1188 //MS_U8 cData = 0;
1189 //U8 cal_done;
1190 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Power_On_Initialization\n"));
1191
1192 #if defined(PWS_ENABLE)
1193 Mapi_PWS_Stop_VDMCU();
1194 #endif
1195 // No definition for Mulan
1196 #if 0
1197 // Global demod reset. To fix DVBS -> DVBT2 or DVBS blind scan -> DVBT2 unlock issue.
1198 temp_val=HAL_DMD_RIU_ReadByte(0x101e3a);
1199 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val|0x02);
1200
1201 MsOS_DelayTask(1);
1202
1203 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val&(~0x02));
1204 #endif
1205
1206 INTERN_DVBT2_InitClkgen(bRFAGCTristateEnable);
1207 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1208 //// Firmware download //////////
1209 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Load DSP...\n"));
1210 //MsOS_DelayTask(100);
1211
1212 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1213 {
1214 if (INTERN_DVBT2_LoadDSPCode() == FALSE)
1215 {
1216 printf("DVB-T2 Load DSP Code Fail\n");
1217 return FALSE;
1218 }
1219 else
1220 {
1221 DBG_INTERN_DVBT2(printf("DVB-T2 Load DSP Code OK\n"));
1222 }
1223 }
1224
1225
1226 //// MCU Reset //////////
1227 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Reset...\n"));
1228 if (INTERN_DVBT2_Reset() == FALSE)
1229 {
1230 DBG_INTERN_DVBT2(printf("Fail\n"));
1231 return FALSE;
1232 }
1233 else
1234 {
1235 DBG_INTERN_DVBT2(printf("OK\n"));
1236 }
1237
1238 // SRAM setting, DVB-T use it.
1239 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1240 //MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1241 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1242
1243 status &= INTERN_DVBT2_DSPReg_Init(u8DMD_DVBT2_DSPRegInitExt, u8DMD_DVBT2_DSPRegInitSize);
1244 return status;
1245 }
1246
1247 /************************************************************************************************
1248 Subject: Driving control
1249 Function: INTERN_DVBT2_Driving_Control
1250 Parmeter: bInversionEnable : TRUE For High
1251 Return: void
1252 Remark:
1253 *************************************************************************************************/
INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)1254 void INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)
1255 {
1256 MS_U8 u8Temp;
1257
1258 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1259
1260 if (bEnable)
1261 {
1262 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1263 }
1264 else
1265 {
1266 u8Temp = u8Temp & (~0x01);
1267 }
1268
1269 DBG_INTERN_DVBT2(printf("---> INTERN_DVBT2_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1270 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1271 }
1272 /************************************************************************************************
1273 Subject: Clk Inversion control
1274 Function: INTERN_DVBT2_Clk_Inversion_Control
1275 Parmeter: bInversionEnable : TRUE For Inversion Action
1276 Return: void
1277 Remark:
1278 *************************************************************************************************/
INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)1279 void INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1280 {
1281 MS_U8 u8Temp;
1282
1283 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1284
1285 if (bInversionEnable)
1286 {
1287 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1288 }
1289 else
1290 {
1291 u8Temp = u8Temp & (~0x02);
1292 }
1293
1294 DBG_INTERN_DVBT2(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1295 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1296 }
1297 /************************************************************************************************
1298 Subject: Transport stream serial/parallel control
1299 Function: INTERN_DVBT2_Serial_Control
1300 Parmeter: bEnable : TRUE For serial
1301 Return: MS_BOOL :
1302 Remark:
1303 *************************************************************************************************/
INTERN_DVBT2_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1304 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1305 {
1306 MS_U8 status = true;
1307 MS_U8 temp_val;
1308 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_ts... u8TSClk=%d\n",u8TSClk));
1309
1310 if (u8TSClk == 0xFF) u8TSClk=0x13;
1311 if (bEnable) //Serial mode for TS pad
1312 {
1313 // serial
1314 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1315 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1316
1317 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1318 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1319 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1320
1321 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1322 temp_val|=0x04;
1323 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1324 #else
1325 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1326 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1327 temp_val|=0x07;
1328 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1329 #endif
1330 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1331 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1332 }
1333 else
1334 {
1335 //parallel
1336 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1337 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1338
1339 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1340 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1341 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1342 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1343 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1344 temp_val|=0x05;
1345 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1346 #else
1347 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1348 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1349 temp_val|=0x07;
1350 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1351 #endif
1352
1353 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1354 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1355 }
1356
1357 //DBG_INTERN_DVBT2(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1358
1359 INTERN_DVBT2_Driving_Control(INTERN_DVBT2_DTV_DRIVING_LEVEL);
1360 return status;
1361 }
1362
1363 /************************************************************************************************
1364 Subject: TS1 output control
1365 Function: INTERN_DVBT2_PAD_TS1_Enable
1366 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1367 Return: void
1368 Remark:
1369 *************************************************************************************************/
INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)1370 void INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)
1371 {
1372 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_TS1_Enable... \n"));
1373
1374 if(flag) // PAD_TS1 Enable TS CLK PAD
1375 {
1376 //printf("=== TS1_Enable ===\n");
1377 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1378 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1379 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1380 }
1381 else // PAD_TS1 Disable TS CLK PAD
1382 {
1383 //printf("=== TS1_Disable ===\n");
1384 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1385 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1386 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1387 }
1388 }
1389
1390 /************************************************************************************************
1391 Subject: channel change config
1392 Function: INTERN_DVBT2_Config
1393 Parmeter: BW: bandwidth
1394 Return: MS_BOOL :
1395 Remark:
1396 *************************************************************************************************/
INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U8 u8PlpID)1397 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID)
1398 {
1399 MS_U8 bandwidth;
1400 MS_U8 status = true;
1401 //MS_U8 temp_val;
1402 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_config %d %d %d %ld %d\n", BW, bSerialTS, u8TSClk, u32IFFreq, u8PlpID));
1403 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Config, t = %ld\n",MsOS_GetSystemTime()));
1404
1405 if (u8TSClk == 0xFF) u8TSClk=0x13;
1406 switch(BW)
1407 {
1408 case E_DMD_T2_RF_BAND_5MHz:
1409 bandwidth = 1;
1410 break;
1411 case E_DMD_T2_RF_BAND_6MHz:
1412 bandwidth = 2;
1413 break;
1414 case E_DMD_T2_RF_BAND_7MHz:
1415 bandwidth = 3;
1416 break;
1417 case E_DMD_T2_RF_BAND_10MHz:
1418 bandwidth = 5;
1419 break;
1420 case E_DMD_T2_RF_BAND_1p7MHz:
1421 bandwidth = 0;
1422 break;
1423 case E_DMD_T2_RF_BAND_8MHz:
1424 default:
1425 bandwidth = 4;
1426 break;
1427 }
1428
1429 status &= INTERN_DVBT2_Reset();
1430
1431 // BW mode
1432 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_BW, BW);
1433 // TS mode
1434 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_T2_TS_SERIAL, bSerialTS? 0x01:0x00);
1435 // FC
1436 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_L, u32IFFreq&0xff);
1437 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_H, (u32IFFreq>>8)&0xff);
1438 // PLP_ID
1439 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
1440
1441 /*
1442 if(bSerialTS)
1443 {
1444 // serial
1445 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1446 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1447
1448 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1449 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1450 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1451 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1452 temp_val|=0x04;
1453 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1454 #else
1455 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1456 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1457 temp_val|=0x07;
1458 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1459 #endif
1460 }
1461 else
1462 {
1463 //parallel
1464 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1465 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1466
1467 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1468 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1469 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1470 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1471 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1472 temp_val|=0x05;
1473 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1474 #else
1475 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1476 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1477 temp_val|=0x07;
1478 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1479 #endif
1480 }
1481 */
1482 return status;
1483 }
1484 /************************************************************************************************
1485 Subject: enable hw to lock channel
1486 Function: INTERN_DVBT2_Active
1487 Parmeter: bEnable
1488 Return: MS_BOOL
1489 Remark:
1490 *************************************************************************************************/
INTERN_DVBT2_Active(MS_BOOL bEnable)1491 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable)
1492 {
1493 MS_U8 status = true;
1494
1495 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_active\n"));
1496
1497 //// INTERN_DVBT2 Finite State Machine on/off //////////
1498 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1499
1500 INTERN_DVBT2_SignalQualityReset();
1501
1502 //printf("++++++++++++++++++Active! While(1)+++++++++++++++++++++\n");
1503 //while(1);
1504
1505 return status;
1506 }
1507 /************************************************************************************************
1508 Subject: Return lock status
1509 Function: INTERN_DVBT2_Lock
1510 Parmeter: eStatus :
1511 Return: MS_BOOL
1512 Remark:
1513 *************************************************************************************************/
INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout,MS_U16 u16DMD_DVBT2_FEC_Timeout)1514 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout)
1515 {
1516 float fBER=0.0f;
1517
1518
1519 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK))
1520 {
1521 // copy from msb1240 >>>>>
1522 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1523 {
1524 if ((fBerFilteredDVBT2 <= 0.0) || ((fBerFilteredDVBT2/fBER) > 30.0 || (fBerFilteredDVBT2/fBER) < 0.03))
1525 fBerFilteredDVBT2 = fBER;
1526 else
1527 fBerFilteredDVBT2 = 0.9f*fBerFilteredDVBT2+0.1f*fBER;
1528 }
1529 // <<<<< copy from msb1240
1530
1531 if (bFECLock == FALSE)
1532 {
1533 u32FecFirstLockTime = MsOS_GetSystemTime();
1534 DBG_INTERN_DVBT2(printf("++++++++[utopia]dvbt2 lock\n"));
1535 }
1536
1537 #if (AUTO_TS_DATA_RATE)
1538 INTERN_DVBT2_ConfigAdaptiveTsDivNum();
1539 #endif
1540
1541 #if 0
1542 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1543 {
1544 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1545 {
1546 if(fLDPCBerFiltered <= 0.0)
1547 fLDPCBerFiltered = fBER;
1548 else
1549 fLDPCBerFiltered = 0.9f*fLDPCBerFiltered+0.1f*fBER;
1550 }
1551 DBG_INTERN_DVBT2(printf("[dvbt2]f_ber=%8.3e, g_ldpc_ber=%8.3e\n",fBER,fLDPCBerFiltered));
1552 }
1553 #endif
1554 u32FecLastLockTime = MsOS_GetSystemTime();
1555 bFECLock = TRUE;
1556 return E_DMD_T2_LOCK;
1557 }
1558 else
1559 {
1560 #if 0
1561 INTERN_DVBT2_SignalQualityReset();
1562 #endif
1563 if (bFECLock == TRUE)
1564 {
1565 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1566 {
1567 return E_DMD_T2_LOCK;
1568 }
1569 }
1570 bFECLock = FALSE;
1571 }
1572 /*
1573 #ifdef CHIP_KRITI
1574 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_NO_CHANNEL))
1575 {
1576 // DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- E_DMD_DVBT2_NO_CHANNEL \n"););
1577 return E_DMD_T2_UNLOCK;
1578 }
1579 #endif
1580 */
1581 if(!bP1Lock)
1582 {
1583 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_EVER_LOCK))
1584 {
1585 DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- P1Lock \n"));
1586 bP1Lock = TRUE;
1587 }
1588 }
1589 if(bP1Lock)
1590 {
1591 DBG_INTERN_DVBT2(printf("P1Lock %ld\n",MsOS_GetSystemTime()));
1592 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_FEC_Timeout)
1593 {
1594 return E_DMD_T2_CHECKING;
1595 }
1596 }
1597 else
1598 {
1599 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_P1_Timeout)
1600 {
1601 return E_DMD_T2_CHECKING;
1602 }
1603 }
1604 return E_DMD_T2_UNLOCK;
1605
1606 }
1607
1608
INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)1609 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)
1610 {
1611 MS_U16 u16Address = 0;
1612 MS_U8 cData = 0;
1613 MS_U8 cBitMask = 0;
1614 MS_U8 use_dsp_reg = 0;
1615
1616 switch( eStatus )
1617 {
1618 case E_DMD_DVBT2_FEC_LOCK:
1619 use_dsp_reg = 1;
1620 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //FEC lock,
1621 cBitMask = BIT(7);
1622 break;
1623
1624 case E_DMD_DVBT2_P1_LOCK:
1625 u16Address = 0x3082; //P1 HW Lock,
1626 cBitMask = BIT(3);
1627 break;
1628
1629 case E_DMD_DVBT2_DCR_LOCK:
1630 use_dsp_reg = 1;
1631 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //DCR Lock,
1632 cBitMask = BIT(2);
1633 break;
1634
1635 case E_DMD_DVBT2_AGC_LOCK:
1636 use_dsp_reg = 1;
1637 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //AGC Lock,
1638 cBitMask = BIT(0);
1639 break;
1640
1641 case E_DMD_DVBT2_MODE_DET:
1642 u16Address = 0x3082; //Mode CP Detect,
1643 cBitMask = BIT(1);
1644 break;
1645
1646 case E_DMD_DVBT2_P1_EVER_LOCK:
1647 use_dsp_reg = 1;
1648 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //P1 Ever Lock,
1649 cBitMask = BIT(5);
1650 break;
1651
1652 case E_DMD_DVBT2_L1_CRC_LOCK:
1653 u16Address = 0x2B41; //P1 Ever Lock,
1654 cBitMask = BIT(5)|BIT(6)|BIT(7);
1655 break;
1656
1657 case E_DMD_DVBT2_NO_CHANNEL:
1658 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1659 cBitMask = BIT(7);
1660 break;
1661
1662
1663 default:
1664 return FALSE;
1665 }
1666
1667 if (use_dsp_reg == 1)
1668 {
1669 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Address, &cData) == FALSE)
1670 {
1671 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1672 return FALSE;
1673 }
1674 }
1675 else
1676 {
1677 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1678 {
1679 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadReg fail \n"));
1680 return FALSE;
1681 }
1682 }
1683
1684 #ifdef MS_DEBUG
1685 MS_U8 u8tmp;
1686 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20c4, &u8tmp);
1687 DBG_INTERN_DVBT2(printf(">>>>>>>>>> DVBT2 State=%d \n", u8tmp));
1688 #endif
1689
1690 if ((cData & cBitMask) == cBitMask)
1691 {
1692 #if (AUTO_TS_DATA_RATE)
1693 if(eStatus == E_DMD_DVBT2_FEC_LOCK)
1694 INTERN_DVBT2_ConfigAdaptiveTsDivNum();
1695 #endif
1696 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is lock \n", eStatus));
1697 return TRUE;
1698 }
1699 else
1700 {
1701 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is unlock \n", eStatus));
1702 return FALSE;
1703 }
1704
1705 }
1706
1707 /****************************************************************************
1708 Subject: To get the Post LDPC BER
1709 Function: INTERN_DVBT2_GetPostLdpcBer
1710 Parmeter: Quility
1711 Return: E_RESULT_SUCCESS
1712 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1713 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1714 We will not read the Period, and have the "/256/8"
1715 *****************************************************************************/
INTERN_DVBT2_GetPostLdpcBer(float * ber)1716 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber)
1717 {
1718 MS_BOOL status = true;
1719 MS_U8 reg=0;
1720 MS_U16 BitErrPeriod;
1721 MS_U32 BitErr;
1722 MS_U16 FecType = 0;
1723
1724 /////////// Post-Viterbi BER /////////////
1725
1726 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1727 {
1728 *ber = (float)-1.0;
1729 return false;
1730 }
1731
1732 /////////// Data BER /////////////
1733 // bank 0x33 0x02 [0] freeze
1734 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1735
1736 // bank 0x33 0x12 Data BER Window[15:0]
1737 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1738 BitErrPeriod = reg;
1739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1740 BitErrPeriod = (BitErrPeriod << 8) | reg;
1741
1742 // bank 0x33 0x34 Data BER count[15:0]
1743 // bank 0x33 0x35 Data BER count[31:16]
1744 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1745 BitErr = reg;
1746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1747 BitErr = (BitErr << 8) | reg;
1748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1749 BitErr = (BitErr << 8) | reg;
1750 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1751 BitErr = (BitErr << 8) | reg;
1752
1753 // bank 0x33 0x02 [0] freeze
1754 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1755
1756 if (BitErrPeriod == 0)
1757 //protect 0
1758 BitErrPeriod = 1;
1759
1760 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1761 FecType = reg;
1762 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1763 FecType = (FecType << 8) | reg;
1764
1765 if (FecType & 0x0180)
1766 {
1767 if (BitErr == 0)
1768 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1769 else
1770 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1771 }
1772 else
1773 {
1774 if (BitErr == 0)
1775 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1776 else
1777 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1778 }
1779
1780 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1781
1782 if (status == FALSE)
1783 {
1784 printf("INTERN_DVBT2_GetPostLdpcBer Fail!\n");
1785 return FALSE;
1786 }
1787
1788 return status;
1789 }
1790
1791 /****************************************************************************
1792 Subject: To get the Pre LDPC BER
1793 Function: INTERN_DVBT2_GetPreLdpcBer
1794 Parmeter: ber
1795 Return: E_RESULT_SUCCESS
1796 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1797 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1798 We will not read the Period, and have the "/256/8"
1799 *****************************************************************************/
INTERN_DVBT2_GetPreLdpcBer(float * ber)1800 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber)
1801 {
1802 MS_U8 status = true;
1803 MS_U8 reg=0;
1804 MS_U16 BitErrPeriod;
1805 MS_U32 BitErr;
1806 MS_U16 FecType = 0;
1807
1808 /////////// Data BER /////////////
1809 // bank 0x33 0x02 [0] freeze
1810 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1811
1812 // bank 0x33 0x12 Data BER Window[15:0]
1813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1814 BitErrPeriod = reg;
1815 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1816 BitErrPeriod = (BitErrPeriod << 8) | reg;
1817
1818 // bank 0x33 0x34 Data BER count[15:0]
1819 // bank 0x33 0x35 Data BER count[31:16]
1820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1821 BitErr = reg;
1822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1823 BitErr = (BitErr << 8) | reg;
1824 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1825 BitErr = (BitErr << 8) | reg;
1826 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1827 BitErr = (BitErr << 8) | reg;
1828
1829 // bank 0x33 0x02 [0] freeze
1830 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1831
1832 if (BitErrPeriod == 0)
1833 //protect 0
1834 BitErrPeriod = 1;
1835
1836 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1837 FecType = reg;
1838 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1839 FecType = (FecType << 8) | reg;
1840
1841 if (FecType & 0x0180)
1842 {
1843 if (BitErr == 0)
1844 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1845 else
1846 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1847 }
1848 else
1849 {
1850 if (BitErr == 0)
1851 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1852 else
1853 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1854 }
1855
1856 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1857
1858 if (status == FALSE)
1859 {
1860 printf("INTERN_DVBT2_GetPreLdpcBer Fail!\n");
1861 return FALSE;
1862 }
1863
1864 return status;
1865 }
1866
1867 /****************************************************************************
1868 Subject: To get the Packet error
1869 Function: INTERN_DVBT2_GetPacketErr
1870 Parmeter: pktErr
1871 Return: E_RESULT_SUCCESS
1872 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1873 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1874 We will not read the Period, and have the "/256/8"
1875 *****************************************************************************/
INTERN_DVBT2_GetPacketErr(MS_U16 * u16PktErr)1876 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr)
1877 {
1878 MS_BOOL status = true;
1879 MS_U8 reg = 0;
1880 MS_U16 PktErr;
1881
1882 //freeze
1883 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01);
1884 //read packet error
1885 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5B, ®);
1886 PktErr = reg;
1887 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5A, ®);
1888 PktErr = (PktErr << 8) | reg;
1889
1890 *u16PktErr = PktErr;
1891 //release
1892 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00);
1893
1894 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PktErr = %d \n ", (int)PktErr));
1895
1896 *u16PktErr = PktErr;
1897
1898 return status;
1899 }
1900
1901 /****************************************************************************
1902 Subject: To get the DVBT2 parameter
1903 Function: INTERN_DVBT2_Get_L1_Info
1904 Parmeter: point to return parameter
1905 Return: TRUE
1906 FALSE
1907 Remark: The TPS parameters will be available after TPS lock
1908 *****************************************************************************/
INTERN_DVBT2_Get_L1_Parameter(MS_U16 * pu16L1_parameter,DMD_DVBT2_SIGNAL_INFO eSignalType)1909 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType)
1910 {
1911 MS_U8 u8Data = 0;
1912 MS_U16 FecType = 0;
1913 MS_U16 u16Data = 0;
1914 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
1915 {
1916 if (eSignalType == T2_MODUL_MODE)
1917 {
1918 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1919 return FALSE;
1920
1921 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(5) | BIT(4) | BIT(3))) >> 3;
1922 }
1923 else if (eSignalType == T2_FFT_VALUE)
1924 {
1925 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1926 {
1927 return FALSE;
1928 }
1929 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1930 }
1931 else if (eSignalType == T2_GUARD_INTERVAL)
1932 {
1933 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1934 {
1935 return FALSE;
1936 }
1937 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(6) | BIT(5) | BIT(4))) >> 4;
1938 }
1939 else if (eSignalType == T2_CODE_RATE)
1940 {
1941 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1942 {
1943 return FALSE;
1944 }
1945 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1946 }
1947 else if (eSignalType == T2_PREAMBLE)
1948 {
1949 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1950 {
1951 return FALSE;
1952 }
1953 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(4))) >> 4;
1954 }
1955 else if (eSignalType == T2_S1_SIGNALLING)
1956 {
1957 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1958 {
1959 return FALSE;
1960 }
1961 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(3) | BIT(2) | BIT(1))) >> 1;
1962 }
1963 else if (eSignalType == T2_PILOT_PATTERN)
1964 {
1965 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE)
1966 {
1967 return FALSE;
1968 }
1969 *pu16L1_parameter = (((MS_U16) u8Data) & 0x0F);
1970 }
1971 else if (eSignalType == T2_BW_EXT)
1972 {
1973 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1974 {
1975 return FALSE;
1976 }
1977 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(0)));
1978 }
1979 else if (eSignalType == T2_PAPR_REDUCTION)
1980 {
1981 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2), &u8Data) == FALSE)
1982 {
1983 return FALSE;
1984 }
1985 *pu16L1_parameter = (((MS_U16) u8Data) & 0xF0) >> 4;
1986 }
1987 else if (eSignalType == T2_OFDM_SYMBOLS_PER_FRAME)
1988 {
1989 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2), &u8Data) == FALSE)
1990 {
1991 return FALSE;
1992 }
1993 *pu16L1_parameter = (MS_U16) u8Data;
1994 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2) + 1, &u8Data) == FALSE)
1995 {
1996 return FALSE;
1997 }
1998 *pu16L1_parameter |= (((MS_U16) u8Data) & 0x0F) << 8;
1999 }
2000 else if (eSignalType == T2_PLP_ROTATION)
2001 {
2002 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
2003 {
2004 return FALSE;
2005 }
2006 *pu16L1_parameter = (((MS_U16) u8Data) & BIT(6)) >> 6;
2007 }
2008 else if (eSignalType == T2_PLP_FEC_TYPE)
2009 {
2010 //FEC Type[8:7]
2011 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8f, &u8Data) == FALSE) return FALSE;
2012 FecType = u8Data;
2013 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8e, &u8Data) == FALSE) return FALSE;
2014 FecType = (FecType << 8) | u8Data;
2015
2016 *pu16L1_parameter = (FecType & 0x0180) >> 7;
2017 }
2018 else if (eSignalType == T2_NUM_PLP)
2019 {
2020 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x42 * 2), &u8Data) == FALSE)
2021 {
2022 return FALSE;
2023 }
2024 *pu16L1_parameter = (MS_U16)u8Data;
2025 }
2026 else if (eSignalType == T2_PLP_TYPE)
2027 {
2028 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x45 * 2) + 1, &u8Data) == FALSE)
2029 {
2030 return FALSE;
2031 }
2032 *pu16L1_parameter = ((MS_U16) u8Data) & 0x07;
2033 }
2034 else if (eSignalType == T2_PLP_TIME_IL_TYPE)
2035 {
2036 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x48 * 2) + 1, &u8Data) == FALSE)
2037 {
2038 return FALSE;
2039 }
2040 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2041 }
2042 else if (eSignalType == T2_PLP_TIME_IL_LENGTH)
2043 {
2044 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x49 * 2) + 1, &u8Data) == FALSE)
2045 {
2046 return FALSE;
2047 }
2048 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2049 }
2050 else if (eSignalType == T2_DAT_ISSY)
2051 {
2052 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2053 {
2054 return FALSE;
2055 }
2056 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2057 }
2058 else if (eSignalType == T2_PLP_MODE)
2059 {
2060 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE)
2061 {
2062 return FALSE;
2063 }
2064 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE)
2065 {
2066 return FALSE;
2067 }
2068 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2069 {
2070 return FALSE;
2071 }
2072 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE)
2073 {
2074 return FALSE;
2075 }
2076 *pu16L1_parameter = ((MS_U16) u8Data) & 0x03;
2077 }
2078 else if (eSignalType == T2_L1_MODULATION)
2079 {
2080 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2) + 1, &u8Data) == FALSE)
2081 {
2082 return FALSE;
2083 }
2084 *pu16L1_parameter = ((MS_U16) u8Data) & 0x0F;
2085 }
2086 else if (eSignalType == T2_NUM_T2_FRAMES)
2087 {
2088 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3b * 2), &u8Data) == FALSE)
2089 {
2090 return FALSE;
2091 }
2092 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2093 }
2094 else if (eSignalType == T2_PLP_NUM_BLOCKS_MAX)
2095 {
2096 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2) + 1, &u8Data) == FALSE) return FALSE;
2097 u16Data = u8Data & 0x03;
2098 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2), &u8Data) == FALSE) return FALSE;
2099 u16Data = (u16Data << 8) | u8Data;
2100
2101 *pu16L1_parameter = u16Data;
2102 }
2103 else if (eSignalType == T2_FEF_ENABLE)
2104 {
2105
2106 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(0x00F1, &u8Data) == FALSE)
2107 {
2108 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2109 return FALSE;
2110 }
2111 *pu16L1_parameter = ((MS_U16) u8Data) & 0x01;
2112 }
2113 else
2114 {
2115 return FALSE;
2116 }
2117
2118 return TRUE;
2119
2120 }
2121
2122 return FALSE;
2123 }
2124
2125
2126 /****************************************************************************
2127 Subject: Read the signal to noise ratio (SNR)
2128 Function: INTERN_DVBT2_GetSNR
2129 Parmeter: None
2130 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2131 Remark:
2132 *****************************************************************************/
INTERN_DVBT2_GetSNR(void)2133 float INTERN_DVBT2_GetSNR (void)
2134 {
2135 MS_U8 status = true;
2136 MS_U8 reg=0, reg_frz=0;
2137 MS_U16 u16_snr100 = 0;
2138 float f_snr;
2139 MS_U8 u8_win = 0;
2140 MS_U8 u8_gi = 0;
2141
2142 // freeze
2143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2144 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2145
2146 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2147 u16_snr100 = reg;
2148 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2149 u16_snr100 = (u16_snr100<<8)|reg;
2150
2151 // unfreeze
2152 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2153
2154 f_snr = (float)u16_snr100/100.0;
2155
2156 // snr cali
2157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2158 u8_win = (reg>>2)&0x01;
2159
2160 if (u8_win == 1)
2161 {
2162 float snr_offset = 0.0;
2163 float snr_cali = 0.0;
2164
2165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2166 u8_gi = (reg>>1)&0x07;
2167
2168 if (u8_gi == 0) snr_offset = 0.157;
2169 else if(u8_gi == 1) snr_offset = 0.317;
2170 else if(u8_gi == 2) snr_offset = 0.645;
2171 else if(u8_gi == 3) snr_offset = 1.335;
2172 else if(u8_gi == 4) snr_offset = 0.039;
2173 else if(u8_gi == 5) snr_offset = 0.771;
2174 else if(u8_gi == 6) snr_offset = 0.378;
2175
2176 snr_cali = f_snr - snr_offset;
2177 if (snr_cali > 0.0) f_snr = snr_cali;
2178 }
2179 //use Polynomial curve fitting to fix snr
2180 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2181 //f_snr = f_snr + snr_poly;
2182
2183 if (status == true)
2184 return f_snr;
2185 else
2186 return -1;
2187
2188 }
2189
INTERN_DVBT2_GetSignalStrength(MS_U16 * strength,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2190 MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength,const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2191 {
2192 MS_U8 status = true;
2193 float ch_power_db = 0.0f;
2194 float ch_power_ref = 11.0f;
2195 float ch_power_rel = 0.0f;
2196 //MS_U8 u8_index = 0;
2197 MS_U16 L1_info_qam, L1_info_cr;
2198 // MS_U8 demodState = 0;
2199
2200 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2201 {
2202 *strength = 0;
2203 return TRUE;
2204 }
2205 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2206
2207 // if (INTERN_DVBT2_Lock(COFDM_TPS_LOCK))
2208 //if (INTERN_DVBT2_Lock(COFDM_AGC_LOCK))
2209 /* Actually, it's more reasonable, that signal level depended on cable input power level
2210 * thougth the signal isn't dvb-t signal.
2211 */
2212
2213 // use pointer of IFAGC table to identify
2214 // case 1: RFAGC from SAR, IFAGC controlled by demod
2215 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2216 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2217 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
2218 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2219 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2220 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
2221 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
2222
2223
2224 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2225 printf("[dvbt2] QAM parameter retrieve failure\n");
2226
2227 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2228 printf("[dvbt2]code rate parameter retrieve failure\n");
2229
2230 /*
2231 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2232 {
2233 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
2234 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
2235 {
2236 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2237 break;
2238 }
2239 else
2240 {
2241 u8_index++;
2242 }
2243 }
2244 */
2245 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
2246
2247 // status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + (0x62*2), &demodState);
2248
2249 if (ch_power_ref > 10.0f)
2250 *strength = 0;
2251 else
2252 {
2253 // For Nordig's SSI test items
2254 if ( (L1_info_qam == 3) //256qam
2255 && (L1_info_cr > 0 && L1_info_cr < 4) // CR 3/5,2/3,3/4
2256 )
2257 {
2258 MS_U8 u8_x = L1_info_cr - 1;
2259 float f_ssi = 0.0;
2260
2261 if(ch_power_db >= -45)f_ssi = 100;
2262 else if (ch_power_db >= -50) f_ssi = fT2_SSI_formula[u8_x][0]*(ch_power_db + 50) + fT2_SSI_formula[u8_x][1];
2263 else if (ch_power_db >= -60) f_ssi = fT2_SSI_formula[u8_x][2]*(ch_power_db + 60) + fT2_SSI_formula[u8_x][3];
2264 else if (ch_power_db >= -70) f_ssi = fT2_SSI_formula[u8_x][4]*(ch_power_db + 70) + fT2_SSI_formula[u8_x][5];
2265 else if (ch_power_db >= -80) f_ssi = fT2_SSI_formula[u8_x][6]*(ch_power_db + 80) + fT2_SSI_formula[u8_x][7];
2266 else if (ch_power_db >= -95) f_ssi = fT2_SSI_formula[u8_x][8]*(ch_power_db + 95) + fT2_SSI_formula[u8_x][9];
2267 else if (ch_power_db >= -100) f_ssi = fT2_SSI_formula[u8_x][10]*(ch_power_db + 100) + fT2_SSI_formula[u8_x][11];
2268
2269 if (f_ssi > 100) *strength = 100;
2270 else if (f_ssi < 0) *strength = 0;
2271 else *strength = (MS_U16)(f_ssi+0.5);
2272
2273 DBG_GET_SIGNAL(printf(">>> SSI... RF_level=%d, f_ssi=%d, ssi=%d, cr=%d, mod=%d\n", (MS_S16)ch_power_db, (MS_S16)f_ssi, (MS_S16)(*strength), L1_info_cr, L1_info_qam));
2274 }
2275 else
2276 {
2277 ch_power_rel = ch_power_db - ch_power_ref;
2278 /*
2279 if (demodState != 0x09)
2280 {
2281 ch_power_rel = ch_power_db - (-50.0f);
2282 }
2283 else
2284 {
2285 ch_power_rel = ch_power_db - ch_power_ref;
2286 }
2287 */
2288 if ( ch_power_rel < -15.0f )
2289 {
2290 *strength = 0;
2291 }
2292 else if ( ch_power_rel < 0.0f )
2293 {
2294 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2295 }
2296 else if ( ch_power_rel < 20 )
2297 {
2298 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2299 }
2300 else if ( ch_power_rel < 35.0f )
2301 {
2302 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2303 }
2304 else
2305 {
2306 *strength = 100;
2307 }
2308 }
2309 }
2310
2311 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2312 {
2313 *strength = 0;
2314 return TRUE;
2315 }
2316
2317 DBG_GET_SIGNAL(printf(">>> ch_power_ref(dB) = %d , ch_power_db(dB) = %d, ch_power_rel(dB) = %d<<<\n", (MS_S16)ch_power_ref, (MS_S16)ch_power_db, (MS_S16)ch_power_rel));
2318 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %d , Score = %d<<<\n", (MS_S16)ch_power_db, *strength));
2319 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2320
2321 return status;
2322 }
2323
2324 /****************************************************************************
2325 Subject: To get the DVT Signal quility
2326 Function: INTERN_DVBT2_GetSignalQuality
2327 Parmeter: Quility
2328 Return: E_RESULT_SUCCESS
2329 E_RESULT_FAILURE
2330 Remark: Here we have 4 level range
2331 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
2332 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
2333 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
2334 <4>.4th Range => Quality <10
2335 *****************************************************************************/
INTERN_DVBT2_GetSignalQuality(MS_U16 * quality,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2336 MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2337 {
2338 // float ber_sqi, SQI;
2339 float fber;
2340 float cn_rec = 0;
2341 float cn_ref = 0;
2342 float cn_rel = 0;
2343 float fBerTH1[] = {1E-4, 1E-4*(1.0-DVBT2_BER_TH_HY), 1E-4*(1.0+DVBT2_BER_TH_HY), 1E-4};
2344 float fBerTH2[] = {3E-7, 3E-7, 3E-7*(1.0-DVBT2_BER_TH_HY), 3E-7*(1.0+DVBT2_BER_TH_HY)};
2345 float BER_SQI = (float)0.0;
2346 float SQI = (float)0.0;
2347 static MS_U8 u8SQIState = 0;
2348
2349 MS_U8 status = true;
2350 MS_U16 L1_info_qam = 0, L1_info_cr = 0, i = 0;
2351
2352 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2353
2354 if (TRUE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_LOCK) )
2355 {
2356 #if 1 // copy from msb1240
2357 if (fBerFilteredDVBT2 < 0.0)
2358 {
2359 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2360 {
2361 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2362 return FALSE;
2363 }
2364 fBerFilteredDVBT2 = fber;
2365 }
2366 else
2367 {
2368 fber = fBerFilteredDVBT2;
2369 }
2370
2371 if (fber > fBerTH1[u8SQIState])
2372 {
2373 BER_SQI = 0.0;
2374 u8SQIState = 1;
2375 }
2376 else if (fber >=fBerTH2[u8SQIState])
2377 {
2378 BER_SQI = 100.0/15;
2379 u8SQIState = 2;
2380 }
2381 else
2382 {
2383 BER_SQI = 100.0/6;
2384 u8SQIState = 3;
2385 }
2386
2387 cn_rec = INTERN_DVBT2_GetSNR();
2388 if (cn_rec < 0.0)
2389 return FALSE;
2390
2391 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2392 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2393 L1_info_qam = 0xff;
2394 L1_info_cr = 0xff;
2395
2396 cn_ref = (float)-1.0;
2397 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2398 printf("[dvbt2] QAM parameter retrieve failure\n");
2399
2400 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2401 printf("[dvbt2]code rate parameter retrieve failure\n");
2402
2403 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2404 {
2405 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2406 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2407 {
2408 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2409 break;
2410 }
2411 }
2412
2413 if (cn_ref < 0.0)
2414 {
2415 SQI = (float)0.0;
2416 printf("SQI is zero, 1\n");
2417 }
2418 else
2419 {
2420 // 0.7, snr offset
2421 cn_rel = cn_rec - cn_ref + 0.7f;
2422 if (cn_rel > 3.0)
2423 SQI = 100;
2424 else if (cn_rel >= -3)
2425 {
2426 SQI = (cn_rel+3)*BER_SQI;
2427 if (SQI > 100.0) SQI = 100.0;
2428 else if (SQI < 0.0) SQI = 0.0;
2429 }
2430 else
2431 {
2432 SQI = (float)0.0;
2433 printf("SQI is zero, 2\n");
2434 }
2435 }
2436
2437 *quality = (MS_U16)SQI;
2438 #else
2439 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2440 {
2441 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2442 }
2443 ///////// Get Pre-BCH (Post-LDPC) BER to determine BER_SQI //////////
2444 if(fLDPCBerFiltered<= 0.0)
2445 {
2446 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2447 {
2448 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2449 return FALSE;
2450 }
2451 fLDPCBerFiltered = fber;
2452 }
2453 else
2454 {
2455 fber = fLDPCBerFiltered;
2456 }
2457 /*
2458 if (fber > 1.0E-3)
2459 ber_sqi = 0.0;
2460 else if (fber > 8.5E-7)
2461 #ifdef MSOS_TYPE_LINUX
2462 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2463 #else
2464 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2465 #endif
2466 else
2467 ber_sqi = 100.0;
2468 */
2469 if (fber > 1E-4)
2470 ber_sqi = 0.0;
2471 else if (fber >= 1E-7)
2472 ber_sqi = 100.0 / 15;
2473 else
2474 ber_sqi = 100.0 / 6;
2475
2476 cn_rec = INTERN_DVBT2_GetSNR();
2477
2478 if (cn_rec == -1) //get SNR return fail
2479 status = false;
2480
2481 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2482 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2483 L1_info_qam = 0xff;
2484 L1_info_cr = 0xff;
2485
2486 cn_ref = (float)-1.0;
2487 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2488 printf("[dvbt2] QAM parameter retrieve failure\n");
2489
2490 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2491 printf("[dvbt2]code rate parameter retrieve failure\n");
2492
2493 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2494 {
2495 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2496 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2497 {
2498 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2499 break;
2500 }
2501 }
2502
2503 if (cn_ref == -1.0)
2504 SQI = (float)0.0;
2505 else
2506 {
2507 cn_rel = cn_rec - cn_ref;
2508 if (cn_rel > 3.0)
2509 SQI = 100;
2510 else if (cn_rel >= -3)
2511 {
2512 SQI = (cn_rel+3)*ber_sqi;
2513 if (SQI > 100.0) SQI = 100.0;
2514 else if (SQI < 0.0) SQI = 0.0;
2515 }
2516 else
2517 SQI = (float)0.0;
2518 }
2519
2520 // SQI patch, 256qam, R3/4 CN=20.8, SQI=0~13
2521 if ((L1_info_qam==_T2_256QAM) && (L1_info_cr==_T2_CR3Y4))
2522 {
2523 if ( (cn_rec > 20.6) && (cn_rec < 20.9))
2524 {
2525 if (SQI > 3) SQI -= 3;
2526 }
2527 else if ( (cn_rec >= 20.9) && (cn_rec < 21.2))
2528 {
2529 if (SQI > 9) SQI -= 9;
2530 }
2531 }
2532
2533 *quality = (MS_U16)SQI;
2534 #endif
2535 }
2536 else
2537 {
2538 *quality = 0;
2539 }
2540
2541 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
2542 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2543 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2544 return status;
2545 }
2546
2547 /****************************************************************************
2548 Subject: To get the DVBT Carrier Freq Offset
2549 Function: INTERN_DVBT2_Get_FreqOffset
2550 Parmeter: Frequency offset (in KHz), bandwidth
2551 Return: E_RESULT_SUCCESS
2552 E_RESULT_FAILURE
2553 Remark:
2554 *****************************************************************************/
INTERN_DVBT2_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2555 MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2556 {
2557 float N, FreqB;
2558 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2559 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2560 MS_U8 reg_frz=0, reg=0;
2561 MS_U8 status;
2562
2563 FreqB = (float)u8BW * 8 / 7;
2564
2565 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2566
2567 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2568
2569 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2570 RegCfoTd = reg;
2571
2572 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2573 RegCfoTd = (RegCfoTd << 8)|reg;
2574
2575 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2576 RegCfoTd = (RegCfoTd << 8)|reg;
2577
2578 FreqCfoTd = (float)RegCfoTd;
2579
2580 if (RegCfoTd & 0x800000)
2581 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2582
2583 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2584
2585 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2586
2587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2588 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2589
2590 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2591
2592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2593 RegCfoFd = reg;
2594
2595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2596 RegCfoFd = (RegCfoFd << 8)|reg;
2597
2598 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2599 RegCfoFd = (RegCfoFd << 8)|reg;
2600
2601 FreqCfoFd = (float)RegCfoFd;
2602
2603 if (RegCfoFd & 0x800000)
2604 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2605
2606 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2607
2608 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2609 RegIcfo = reg & 0x07;
2610
2611 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2612 RegIcfo = (RegIcfo << 8)|reg;
2613
2614 FreqIcfo = (float)RegIcfo;
2615
2616 if (RegIcfo & 0x400)
2617 FreqIcfo = FreqIcfo - (float)0x800;
2618
2619 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2620 reg = reg & 0x30;
2621
2622 switch (reg)
2623 {
2624 case 0x00: N = 2048; break;
2625 case 0x20: N = 4096; break;
2626 case 0x10:
2627 default: N = 8192; break;
2628 }
2629
2630 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2631 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2632 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2633 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2634 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2635 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2636 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2637 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2638 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2639 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2640
2641 if (status == TRUE)
2642 return TRUE;
2643 else
2644 return FALSE;
2645 }
2646
2647
INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)2648 void INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)
2649 {
2650
2651 bPowerOn = bPowerOn;
2652 }
2653
INTERN_DVBT2_Power_Save(void)2654 MS_BOOL INTERN_DVBT2_Power_Save(void)
2655 {
2656
2657 return TRUE;
2658 }
2659
INTERN_DVBT2_Version(MS_U16 * ver)2660 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver)
2661 {
2662
2663 MS_U8 status = true;
2664 MS_U8 tmp = 0;
2665 MS_U16 u16_INTERN_DVBT2_Version;
2666
2667 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2668 u16_INTERN_DVBT2_Version = tmp;
2669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2670 u16_INTERN_DVBT2_Version = u16_INTERN_DVBT2_Version<<8|tmp;
2671 *ver = u16_INTERN_DVBT2_Version;
2672
2673 return status;
2674 }
2675
INTERN_DVBT2_Version_minor(MS_U8 * ver2)2676 MS_BOOL INTERN_DVBT2_Version_minor(MS_U8 *ver2)
2677 {
2678
2679 MS_U8 status = true;
2680
2681 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2682
2683 return status;
2684 }
2685
2686
INTERN_DVBT2_Show_Demod_Version(void)2687 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void)
2688 {
2689
2690 MS_BOOL status = true;
2691 MS_U16 u16_INTERN_DVBT2_Version = 0;
2692 MS_U8 u8_minor_ver = 0;
2693
2694 status &= INTERN_DVBT2_Version(&u16_INTERN_DVBT2_Version);
2695 status &= INTERN_DVBT2_Version_minor(&u8_minor_ver);
2696 printf("[DVBT2]Version = 0x%x,0x%x\n",u16_INTERN_DVBT2_Version,u8_minor_ver);
2697
2698 return status;
2699 }
2700
INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float write_value)2701 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
2702 {
2703 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
2704 return TRUE;
2705 /*
2706 MS_U8 u8_index = 0;
2707 MS_BOOL bRet = false;
2708
2709 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2710 {
2711 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2712 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2713 {
2714 dvbt2_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2715 bRet = true;
2716 break;
2717 }
2718 else
2719 {
2720 u8_index++;
2721 }
2722 }
2723 return bRet;
2724 */
2725 }
2726
INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float * read_value)2727 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
2728 {
2729 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
2730 return TRUE;
2731 /*
2732 MS_U8 u8_index = 0;
2733 MS_BOOL bRet = false;
2734
2735 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2736 {
2737 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2738 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2739 {
2740 *read_value = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2741 bRet = true;
2742 break;
2743 }
2744 else
2745 {
2746 u8_index++;
2747 }
2748 }
2749 return bRet;
2750 */
2751 }
2752
INTERN_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)2753 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
2754 {
2755 MS_BOOL status = TRUE;
2756 MS_U8 u8Data = 0;
2757 MS_U8 indx = 0;
2758
2759 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_GetPlpBitMap\n"));
2760
2761 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2762 if (u8Data != 0x30)
2763 {
2764 DBG_INTERN_DVBT2(printf("\n[INTERN_DVBT2_GetPlpBitMap] Check L1 NOT Ready !! E_DMD_T2_L1_FLAG = 0x%x\n", u8Data));
2765 return FALSE;
2766 }
2767 while (indx < 32)
2768 {
2769 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_PLP_ID_ARR + indx, &u8Data);
2770 u8PlpBitMap[indx] = u8Data;
2771 indx++;
2772 }
2773
2774 if (status)
2775 {
2776 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap data+++++++++++++++\n"));
2777 for (indx = 0; indx < 32; indx++)
2778 DBG_INTERN_DVBT2(printf("[%d] ", u8PlpBitMap[indx]));
2779 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap end+++++++++++++++\n"));
2780 }
2781 return status;
2782 }
2783
INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)2784 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
2785 {
2786 MS_BOOL status = TRUE;
2787 MS_U8 u8Data = 0;
2788 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2789 if (u8Data != 0x30)
2790 {
2791 printf(">>>dvbt2 L1 not ready yet\n");
2792 return FALSE;
2793 }
2794 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_DVBT2_LOCK_HIS, &u8Data);
2795
2796 if ((u8Data & BIT(7)) == 0x00)
2797 {
2798 printf(">>>dvbt2 is un-lock\n");
2799 return FALSE;
2800 }
2801 // assign PLP-ID value
2802 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x78) * 2, u8PlpID);
2803 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x01); // MEM_EN
2804 MsOS_DelayTask(1);
2805 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x79) * 2, u8GroupID);
2806 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x00); // ~MEM_EN
2807
2808 return status;
2809 }
2810
INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID,MS_U8 u8GroupID)2811 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID)
2812 {
2813 MS_BOOL status = TRUE;
2814
2815 // assign Group-ID and PLP-ID value (must be written in order)
2816 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_GROUP_ID, u8GroupID);
2817 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
2818
2819 return status;
2820 }
2821
2822 #if (AUTO_TS_DATA_RATE)
INTERN_DVBT2_GetTsDivNum(MS_U8 * u8TSDivNum)2823 MS_BOOL INTERN_DVBT2_GetTsDivNum(MS_U8* u8TSDivNum)
2824 {
2825 int TS_DATA_RATE =0;
2826 MS_U8 u8_tmp =0;
2827
2828 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_3, &u8_tmp) == FALSE)
2829 {
2830 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2831 return FALSE;
2832 }
2833 //printf("[dvbt2] TS_DATA_RATE_3 = 0x%x \n\n", u8_tmp);
2834 TS_DATA_RATE = u8_tmp;
2835
2836 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_2, &u8_tmp) == FALSE)
2837 {
2838 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2839 return FALSE;
2840 }
2841 //printf("[dvbt2] TS_DATA_RATE_2 = 0x%x \n\n", u8_tmp);
2842 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
2843
2844 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_1, &u8_tmp) == FALSE)
2845 {
2846 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2847 return FALSE;
2848 }
2849 //printf("[dvbt2] TS_DATA_RATE_1 = 0x%x \n\n", u8_tmp);
2850 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
2851
2852 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_0, &u8_tmp) == FALSE)
2853 {
2854 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2855 return FALSE;
2856 }
2857 //printf("[dvbt2] TS_DATA_RATE_0 = 0x%x \n\n", u8_tmp);
2858 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
2859
2860 DBG_AUTO_TS_DATA_RATE(printf("[dvbt2] TS_DATA_RATE_total = 0x%x %d \n\n", TS_DATA_RATE, TS_DATA_RATE));
2861
2862
2863 u8_tmp=HAL_DMD_RIU_ReadByte(0x103301);
2864 u8_tmp &= 0x01;
2865
2866 if(u8_tmp == 0x01)
2867 {
2868 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DIV_288, &u8_tmp) == FALSE)
2869 {
2870 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2871 return FALSE;
2872 }
2873 *u8TSDivNum = u8_tmp;
2874
2875 DBG_AUTO_TS_DATA_RATE(printf(" CLK Source: 288 MHz \n"));
2876 }
2877 else
2878 {
2879 printf("@@@@@@@@@@@@@ DVB-T2 TS clock source error!!!\n");
2880 }
2881
2882
2883 if (*u8TSDivNum > 0x1f)// 36 MHz/8 = 4.5 MHz
2884 *u8TSDivNum = 0x1f;
2885
2886 if (*u8TSDivNum < 0x0f)// 72 MHz/8 = 9 MHz
2887 *u8TSDivNum = 0x0f;
2888
2889 DBG_AUTO_TS_DATA_RATE(printf(">>>INTERN_DVBT2_GetTsDivNum = 0x%x<<<\n", *u8TSDivNum));
2890
2891 return TRUE;
2892 }
2893
INTERN_DVBT2_ConfigAdaptiveTsDivNum(void)2894 MS_BOOL INTERN_DVBT2_ConfigAdaptiveTsDivNum(void)
2895 {
2896 MS_U8 u8TSDivNum =0;
2897 MS_U8 u8_tmp =0;
2898
2899 //check if TS DATA RATE change
2900 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_CHANGE_IND, &u8_tmp) == FALSE)
2901 {
2902 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2903 return FALSE;
2904 }
2905
2906 if (u8_tmp ==1)
2907 {
2908 INTERN_DVBT2_GetTsDivNum(&u8TSDivNum);
2909 DBG_INTERN_DVBT2(printf(">>>INTERN_DVBT2_GetLock TsClkDivNum = 0x%x<<<\n", u8TSDivNum));
2910 DBG_AUTO_TS_DATA_RATE(printf(">>>TS_DATA_RATE_CHANGE Detected: TsClkDivNum = 0x%x<<<\n", u8TSDivNum));
2911 // ** Caution: for TS parallel mode
2912 HAL_DMD_RIU_WriteByte(0x103300, u8TSDivNum);
2913 MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_RATE_CHANGE_IND,0x00);
2914 }
2915
2916 return TRUE;
2917 }
2918 #endif
2919
2920 #if (INTERN_DVBT2_INTERNAL_DEBUG == 1)
INTERN_DVBT2_get_demod_state(MS_U8 * state)2921 void INTERN_DVBT2_get_demod_state(MS_U8* state)
2922 {
2923 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2924 return;
2925 }
2926
INTERN_DVBT2_Show_ChannelLength(void)2927 MS_BOOL INTERN_DVBT2_Show_ChannelLength(void)
2928 {
2929 MS_U8 status = true;
2930 MS_U8 tmp = 0;
2931 MS_U16 len = 0;
2932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2933 len = tmp;
2934 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2935 len = (len<<8)|tmp;
2936 printf("[dvbt]Hw_channel=%d\n",len);
2937 return status;
2938 }
2939
INTERN_DVBT2_Show_SW_ChannelLength(void)2940 MS_BOOL INTERN_DVBT2_Show_SW_ChannelLength(void)
2941 {
2942 MS_U8 status = true;
2943 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2944 MS_U16 sw_len = 0;
2945 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2946 sw_len = tmp;
2947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2948 sw_len = (sw_len<<8)|tmp;
2949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2950 peak_num = tmp;
2951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2952 insideGI = tmp&0x01;
2953 stoptracking = (tmp&0x02)>>1;
2954 flag_short_echo = (tmp&0x0C)>>2;
2955 fsa_mode = (tmp&0x30)>>4;
2956
2957 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2958 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2959
2960 return status;
2961 }
2962
INTERN_DVBT2_Show_ACI_CI(void)2963 MS_BOOL INTERN_DVBT2_Show_ACI_CI(void)
2964 {
2965
2966 #define BIT4 0x10
2967 MS_U8 status = true;
2968 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2969
2970 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2971 digACI = (tmp&BIT4)>>4;
2972
2973 // get flag_CI
2974 // 0: No interference
2975 // 1: CCI
2976 // 2: in-band ACI
2977 // 3: N+1 ACI
2978 // flag_ci = (tmp&0xc0)>>6;
2979 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2980 flag_CI = (tmp&0xC0)>>6;
2981 td_coef = (tmp&0x0C)>>2;
2982
2983 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2984
2985 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2986
2987 return status;
2988 }
2989
INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)2990 MS_BOOL INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)
2991 {
2992 MS_U8 status = true;
2993 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2995 fd = tmp;
2996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2997 ch_len = tmp;
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2999 snr_sel = (tmp>>4)&0x03;
3000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
3001 pertone_num = tmp;
3002
3003 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
3004
3005 return status;
3006 }
3007
INTERN_DVBT2_Get_CFO(void)3008 MS_BOOL INTERN_DVBT2_Get_CFO(void)
3009 {
3010
3011 float N = 0, FreqB = 0;
3012 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
3013 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
3014 MS_U8 reg_frz = 0, reg = 0;
3015 MS_U8 status = 0;
3016 MS_U8 u8BW = 8;
3017
3018 FreqB = (float)u8BW * 8 / 7;
3019
3020 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
3021
3022 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
3023
3024 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
3025 RegCfoTd = reg;
3026
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
3028 RegCfoTd = (RegCfoTd << 8)|reg;
3029
3030 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
3031 RegCfoTd = (RegCfoTd << 8)|reg;
3032
3033 FreqCfoTd = (float)RegCfoTd;
3034
3035 if (RegCfoTd & 0x800000)
3036 FreqCfoTd = FreqCfoTd - (float)0x1000000;
3037
3038 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
3039
3040 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
3041
3042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
3043 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
3044
3045 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3046
3047 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
3048 RegCfoFd = reg;
3049
3050 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
3051 RegCfoFd = (RegCfoFd << 8)|reg;
3052
3053 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
3054 RegCfoFd = (RegCfoFd << 8)|reg;
3055
3056 FreqCfoFd = (float)RegCfoFd;
3057
3058 if (RegCfoFd & 0x800000)
3059 FreqCfoFd = FreqCfoFd - (float)0x1000000;
3060
3061 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
3062
3063 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
3064 RegIcfo = reg & 0x07;
3065
3066 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
3067 RegIcfo = (RegIcfo << 8)|reg;
3068
3069 FreqIcfo = (float)RegIcfo;
3070
3071 if (RegIcfo & 0x400)
3072 FreqIcfo = FreqIcfo - (float)0x800;
3073
3074 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
3075 reg = reg & 0x30;
3076
3077 switch (reg)
3078 {
3079 case 0x00: N = 2048; break;
3080 case 0x20: N = 4096; break;
3081 case 0x10:
3082 default: N = 8192; break;
3083 }
3084
3085 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
3086 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
3087 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
3088 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3089 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
3090
3091 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
3092
3093 return status;
3094
3095 }
INTERN_DVBT2_Get_SFO(void)3096 MS_BOOL INTERN_DVBT2_Get_SFO(void)
3097 {
3098 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
3099 MS_BOOL status = true;
3100 MS_U8 reg = 0;
3101 float FreqB = 9.143, FreqS = 45.473; //20.48
3102 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
3103 float sfo_value = 0;
3104
3105 // get Reg_TDP_SFO,
3106 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
3107 Reg_TDP_SFO = reg;
3108 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
3109 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3110 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
3111 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3112
3113 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3114
3115 // get Reg_FDP_SFO,
3116 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
3117 Reg_FDP_SFO = reg;
3118 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
3119 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3120 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
3121 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3122
3123 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3124
3125 // get Reg_FSA_SFO,
3126 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
3127 Reg_FSA_SFO = reg;
3128 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
3129 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3130 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
3131 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3132
3133 // get Reg_FSA_IN,
3134 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
3135 Reg_FSA_IN = reg;
3136 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
3137 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
3138 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
3139
3140 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
3141 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
3142
3143 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
3144 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
3145 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
3146
3147
3148 return status;
3149 }
3150
INTERN_DVBT2_Get_SYA_status(void)3151 void INTERN_DVBT2_Get_SYA_status(void)
3152 {
3153 MS_U8 status = true;
3154 MS_U8 sya_k = 0,reg = 0;
3155 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
3156
3157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
3158 sya_k = reg;
3159
3160 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
3161 sya_th = reg;
3162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
3163 sya_th = (sya_th<<8)|reg;
3164
3165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
3166 sya_offset = reg;
3167 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
3168 sya_offset = (sya_offset<<8)|reg;
3169
3170 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
3171 len_m = reg;
3172 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
3173 len_m = (len_m<<8)|reg;
3174
3175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
3176 len_b = reg;
3177 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
3178 len_b = (len_b<<8)|reg;
3179
3180
3181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
3182 len_a = reg;
3183 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
3184 len_a = (len_a<<8)|reg;
3185
3186
3187 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
3188 tracking_reg = reg;
3189
3190
3191 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
3192 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
3193
3194 return;
3195 }
3196
INTERN_DVBT2_Get_cci_status(void)3197 void INTERN_DVBT2_Get_cci_status(void)
3198 {
3199 MS_U8 status = true;
3200 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
3201
3202 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
3203 cci_fsweep = reg;
3204
3205 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
3206 cci_kp = reg;
3207
3208 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
3209
3210 return;
3211 }
3212
INTERN_DVBT2_Show_PRESFO_Info(void)3213 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void)
3214 {
3215 MS_U8 tmp = 0;
3216 MS_BOOL status = TRUE;
3217 printf("\n[SFO]");
3218 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
3219 printf("[%x]",tmp);
3220 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
3221 printf("[%x]",tmp);
3222 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
3223 printf("[%x]",tmp);
3224 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
3225 printf("[%x]",tmp);
3226 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
3227 printf("[%x]",tmp);
3228 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
3229 printf("[%x]",tmp);
3230 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
3231 printf("[%x]",tmp);
3232 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
3233 printf("[%x][End]",tmp);
3234
3235 return status;
3236 }
3237
INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 * locktime)3238 MS_BOOL INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 *locktime)
3239 {
3240 MS_BOOL status = true;
3241
3242 *locktime = 0xffff;
3243 printf("[dvbt]INTERN_DVBT2_Get_Lock_Time_Info not implement\n");
3244
3245 status = false;
3246 return status;
3247 }
3248
3249
INTERN_DVBT2_Show_Lock_Time_Info(void)3250 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void)
3251 {
3252 MS_U16 locktime = 0;
3253 MS_BOOL status = TRUE;
3254 status &= INTERN_DVBT2_Get_Lock_Time_Info(&locktime);
3255 printf("[DVBT]lock_time = %d ms\n",locktime);
3256 return status;
3257 }
3258
INTERN_DVBT2_Show_BER_Info(void)3259 MS_BOOL INTERN_DVBT2_Show_BER_Info(void)
3260 {
3261 MS_U8 tmp = 0;
3262 MS_BOOL status = TRUE;
3263 printf("\n[BER]");
3264 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
3265 printf("[%x,",tmp);
3266 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
3267 printf("%x]",tmp);
3268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
3269 printf("[%x,",tmp);
3270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
3271 printf("%x]",tmp);
3272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
3273 printf("[%x,",tmp);
3274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
3275 printf("%x][End]",tmp);
3276
3277 return status;
3278
3279 }
3280
3281
INTERN_DVBT2_Show_AGC_Info(void)3282 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void)
3283 {
3284 MS_U8 tmp = 0;
3285 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3286 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3287 MS_U16 if_agc_err = 0;
3288 MS_BOOL status = TRUE;
3289 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
3290
3291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
3292 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
3293 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
3294 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
3295 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
3296 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3297
3298
3299 // select IF gain to read
3300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3301 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3302
3303 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3304 if_agc_gain = tmp;
3305 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3306 if_agc_gain = (if_agc_gain<<8)|tmp;
3307
3308
3309 // select d1 gain to read.
3310 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3311 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3312
3313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3314 d1_gain = tmp;
3315 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3316 d1_gain = (d1_gain<<8)|tmp;
3317
3318 // select d2 gain to read.
3319 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3320 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3321
3322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3323 d2_gain = tmp;
3324 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3325 d2_gain = (d2_gain<<8)|tmp;
3326
3327 // select IF gain err to read
3328 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3329 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3330
3331 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3332 if_agc_err = tmp;
3333 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3334 if_agc_err = (if_agc_err<<8)|tmp;
3335
3336 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3337 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3338 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3339
3340
3341
3342 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3343 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3344
3345 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3346 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3347
3348 return status;
3349
3350 }
3351
INTERN_DVBT2_Show_WIN_Info(void)3352 MS_BOOL INTERN_DVBT2_Show_WIN_Info(void)
3353 {
3354 MS_U8 tmp = 0;
3355 MS_U8 trigger = 0;
3356 MS_U16 win_len = 0;
3357
3358 MS_BOOL status = TRUE;
3359
3360 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3361 win_len = tmp;
3362 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3363 win_len = (win_len<<8)|tmp;
3364
3365 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3366
3367 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3368
3369 return status;
3370 }
3371
INTERN_DVBT2_Show_td_coeff(void)3372 void INTERN_DVBT2_Show_td_coeff(void)
3373 {
3374 MS_U8 status = true;
3375 MS_U8 w1 = 0,w2 = 0,reg = 0;
3376
3377 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3378 w1 = reg;
3379
3380 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3381 w2 = reg;
3382
3383 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3384
3385 return;
3386 }
3387
3388 /********************************************************
3389 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM
3390 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
3391 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256
3392 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE
3393 *Preamble(b12) : 0~1 => mixed, not_mixed
3394 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved
3395 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8
3396 *BW_Extend(b19) : 0~1 => normal, extension
3397 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved
3398 ********************************/
INTERN_DVBT2_Show_Modulation_info(void)3399 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void)
3400 {
3401 MS_BOOL bRet = TRUE;
3402 MS_U16 u16Data = 0;
3403
3404 char* cConStr[] = {"qpsk", "16qam", "64qam", "256qam"};
3405 char* cCRStr[] = {"1_2", "3_5", "2_3", "3_4", "4_5", "5_6"};
3406 char* cGIStr[] = {"1_32", "1_16", "1_8", "1_4", "1_128", "19_128", "19_256"};
3407 char* cFFTStr[] = {"2k", "8k", "4k", "1k", "16k", "32k", "8k", "32k"};
3408 char* cPreAStr[] = {"mixed", "not_mixed"};
3409 char* cS1SStr[] = {"t2_siso", "t2_miso", "non_t2", "reserved"};
3410 char* cPPSStr[] = {"PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", "PP8", "reserved"};
3411 char* cBWStr[] = {"normal", "extension"};
3412 char* cPAPRStr[] = {"none", "ace", "tr", "tr_and_ace", "reserved"};
3413
3414 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
3415 {
3416
3417 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_MODUL_MODE) == FALSE)
3418 {
3419 printf("T2_MODUL_MODE Error!\n");
3420 bRet = FALSE;
3421 }
3422 u16Data &= 0x07;
3423 //*L1_Info = (MS_U64)(u16Data);
3424 printf("T2 Constellation:%s\n", cConStr[u16Data]);
3425
3426 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_CODE_RATE) == FALSE)
3427 {
3428 printf(("T2_CODE_RATE Error!\n"));
3429 bRet = FALSE;
3430 }
3431 u16Data &= 0x07;
3432 //*L1_Info |= (MS_U64)(u16Data << 3);
3433 printf("T2 Code Rate:%s\n", cCRStr[u16Data]);
3434
3435 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_GUARD_INTERVAL) == FALSE)
3436 {
3437 printf("T2_GUARD_INTERVAL Error!\n");
3438 bRet = FALSE;
3439 }
3440 u16Data &= 0x07;
3441 //*L1_Info |= (MS_U64)(u16Data << 6);
3442 printf("T2 GI:%s\n", cGIStr[u16Data]);
3443
3444 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_FFT_VALUE) == FALSE)
3445 {
3446 printf("T2_FFT_VALUE Error!\n");
3447 bRet = FALSE;
3448 }
3449 u16Data &= 0x07;
3450 //*L1_Info |= (MS_U64)(u16Data << 9);
3451 printf("T2 FFT:%s\n", cFFTStr[u16Data]);
3452
3453 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PREAMBLE) == FALSE)
3454 {
3455 printf("T2_PREAMBLE Error!\n");
3456 bRet = FALSE;
3457 }
3458 u16Data &= 0x01;
3459 //*L1_Info |= (MS_U64)(u16Data << 12);
3460 printf("Preamble:%s\n", cPreAStr[u16Data]);
3461
3462 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_S1_SIGNALLING) == FALSE)
3463 {
3464 printf("T2_S1_SIGNALLING Error!\n");
3465 bRet = FALSE;
3466 }
3467 u16Data &= 0x03;
3468 if (u16Data > 2)
3469 u16Data = 3;
3470 //*L1_Info |= (MS_U64)(u16Data << 13);
3471 printf("S1 Signalling:%s\n", cS1SStr[u16Data]);
3472
3473 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PILOT_PATTERN) == FALSE)
3474 {
3475 printf("T2_PILOT_PATTERN Error!\n");
3476 bRet = FALSE;
3477 }
3478 u16Data &= 0x0F;
3479 if (u16Data > 7)
3480 u16Data = 8;
3481 //*L1_Info |= (MS_U64)(u16Data << 15);
3482 printf("PilotPattern:%s\n", cPPSStr[u16Data]);
3483
3484 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_BW_EXT) == FALSE)
3485 {
3486 printf("T2_BW_EXT Error!\n");
3487 bRet = FALSE;
3488 }
3489 u16Data &= 0x01;
3490 //*L1_Info |= (MS_U64)(u16Data << 19);
3491 printf("BW EXT:%s\n", cBWStr[u16Data]);
3492
3493 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PAPR_REDUCTION) == FALSE)
3494 {
3495 printf("T2_PAPR_REDUCTION Error!\n");
3496 bRet = FALSE;
3497 }
3498 u16Data &= 0x07;
3499 if (u16Data > 3)
3500 u16Data = 4;
3501 //*L1_Info |= (MS_U64)(u16Data << 20);
3502 printf("T2 PAPR:%s\n", cPAPRStr[u16Data]);
3503
3504 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_OFDM_SYMBOLS_PER_FRAME) == FALSE)
3505 {
3506 printf("T2_OFDM_SYMBOLS_PER_FRAME Error!\n");
3507 bRet = FALSE;
3508 }
3509 u16Data &= 0xFFF;
3510 //*L1_Info |= (MS_U64)(u16Data << 23);
3511 printf("T2 OFDM Symbols:%u\n", u16Data);
3512 }
3513 else
3514 {
3515 printf("INVALID\n");
3516 return FALSE;
3517 }
3518
3519 return bRet;
3520
3521 }
3522
3523
INTERN_DVBT2_Show_BER_PacketErr(void)3524 void INTERN_DVBT2_Show_BER_PacketErr(void)
3525 {
3526 float f_ber = 0;
3527 MS_U16 packetErr = 0;
3528 INTERN_DVBT2_GetPostLdpcBer(&f_ber);
3529 INTERN_DVBT2_GetPacketErr(&packetErr);
3530
3531 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3532 return;
3533 }
3534
INTERN_DVBT2_Show_Lock_Info(void)3535 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void)
3536 {
3537
3538 printf("[dvbt]INTERN_DVBT2_Show_Lock_Info not implement!!!\n");
3539 return false;
3540 }
3541
3542
INTERN_DVBT2_Show_Demod_Info(void)3543 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void)
3544 {
3545 MS_U8 demod_state = 0;
3546 MS_BOOL status = true;
3547 static MS_U8 counter = 0;
3548
3549 INTERN_DVBT2_get_demod_state(&demod_state);
3550
3551 printf("==========[dvbt]state=%d\n",demod_state);
3552 if (demod_state < 5)
3553 {
3554 INTERN_DVBT2_Show_Demod_Version();
3555 INTERN_DVBT2_Show_AGC_Info();
3556 INTERN_DVBT2_Show_ACI_CI();
3557 }
3558 else if(demod_state < 8)
3559 {
3560 INTERN_DVBT2_Show_Demod_Version();
3561 INTERN_DVBT2_Show_AGC_Info();
3562 INTERN_DVBT2_Show_ACI_CI();
3563 INTERN_DVBT2_Show_ChannelLength();
3564 INTERN_DVBT2_Get_CFO();
3565 INTERN_DVBT2_Get_SFO();
3566 INTERN_DVBT2_Show_td_coeff();
3567 }
3568 else if(demod_state < 11)
3569 {
3570 INTERN_DVBT2_Show_Demod_Version();
3571 INTERN_DVBT2_Show_AGC_Info();
3572 INTERN_DVBT2_Show_ACI_CI();
3573 INTERN_DVBT2_Show_ChannelLength();
3574 INTERN_DVBT2_Get_CFO();
3575 INTERN_DVBT2_Get_SFO();
3576 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3577 INTERN_DVBT2_Get_SYA_status();
3578 INTERN_DVBT2_Show_td_coeff();
3579 }
3580 else if((demod_state == 11) && ((counter%4) == 0))
3581 {
3582 INTERN_DVBT2_Show_Demod_Version();
3583 INTERN_DVBT2_Show_AGC_Info();
3584 INTERN_DVBT2_Show_ACI_CI();
3585 INTERN_DVBT2_Show_ChannelLength();
3586 INTERN_DVBT2_Get_CFO();
3587 INTERN_DVBT2_Get_SFO();
3588 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3589 INTERN_DVBT2_Get_SYA_status();
3590 INTERN_DVBT2_Show_td_coeff();
3591 INTERN_DVBT2_Show_Modulation_info();
3592 INTERN_DVBT2_Show_BER_PacketErr();
3593 }
3594 else
3595 status = false;
3596
3597 printf("===========================\n");
3598 counter++;
3599
3600 return status;
3601 }
3602 #endif
3603
3604