1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (��MStar Confidential Information��) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #define TEST_EMBEDED_DEMOD 0
129 //U8 load_data_variable=1;
130 //-----------------------------------------------------------------------
131 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
132
133 #define TDE_REG_BASE 0x2400UL
134 #define DIV_REG_BASE 0x2500UL
135 #define TR_REG_BASE 0x2600UL
136 #define FTN_REG_BASE 0x2800UL
137 #define FTNEXT_REG_BASE 0x2900UL
138 #define MBX_REG_BASE 0x2F00UL
139
140
141
142 #if 0//ENABLE_SCAN_ONELINE_MSG
143 #define DBG_INTERN_DVBT_ONELINE(x) x
144 #else
145 #define DBG_INTERN_DVBT_ONELINE(x) // x
146 #endif
147
148 #ifdef MS_DEBUG
149 #define DBG_INTERN_DVBT(x) x
150 #define DBG_GET_SIGNAL(x) x
151 #define DBG_INTERN_DVBT_TIME(x) x
152 #define DBG_INTERN_DVBT_LOCK(x) x
153 #else
154 #define DBG_INTERN_DVBT(x) //x
155 #define DBG_GET_SIGNAL(x) //x
156 #define DBG_INTERN_DVBT_TIME(x) // x
157 #define DBG_INTERN_DVBT_LOCK(x) //x
158 #endif
159 #define DBG_DUMP_LOAD_DSP_TIME 0
160
161 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
162 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
163 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
164 #define INTERN_DVBT_INTERNAL_DEBUG 1
165
166 #define SIGNAL_LEVEL_OFFSET 0.00
167 #define TAKEOVERPOINT -59.0
168 #define TAKEOVERRANGE 0.5
169 #define LOG10_OFFSET -0.21
170 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
171 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
172
173
174 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
175 #define TUNER_VPP 2
176 #define IF_AGC_VPP 2
177 #else
178 #define TUNER_VPP 1
179 #define IF_AGC_VPP 2
180 #endif
181
182 #if (TUNER_VPP == 1)
183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
184 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
186 #endif
187
188 /*BEG INTERN_DVBT_DSPREG_TABLE*/
189 #define D_DMD_DVBT_PARAM_VERSION 0x01
190 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
191 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
192 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
193 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
194 #define D_DMD_DVBT_OP_DCR_EN 0x01
195 #define D_DMD_DVBT_OP_IIS_EN 0x01
196 #define D_DMD_DVBT_OP_IQB_EN 0x00
197 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
198 #define D_DMD_DVBT_OP_ACI_EN 0x01
199 #define D_DMD_DVBT_OP_CCI_EN 0x01
200 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
201 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
202 #define D_DMD_DVBT_CFG_BW 0x03 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
203 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
204 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
205 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
206 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
207 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
208 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
209 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
210 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
211 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
212 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
213 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
214 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
215 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
216 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
217 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
218 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
219 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
220 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
221 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
222
223 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
224 #define D_DMD_DVBT_CFG_FC_H 0x4E
225 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
226 #define D_DMD_DVBT_CFG_FS_H 0x5D
227 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
228
229 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
230 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
231 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
232 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
233 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
234 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
235 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
236 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
237 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
238 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
239 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
240 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
241
242 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
243 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
244 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
245 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
246 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
247 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
248 #else
249 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
250 #endif
251 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
252 //#define DMD_DVBT_CHECKSUM 0x00
253 /*END INTERN_DVBT_DSPREG_TABLE*/
254 #define DVBT_FS 24000 // 24000
255 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
256 #define FC_L 0x20 // 0323 jason
257 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
258 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
259 #define SET_ZIF 0x00
260 #define IQB_EN 0x00
261
262 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
263 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
264 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
265 #define CSTL 0x02 //0:QPSK 1:16 2: 64
266 #define HIER 0x00
267 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
268 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
269 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
270 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
271 #define LP_SEL 0x00 // LP select
272 #define IQ_SWAP 0x00 //0x01
273 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
274 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
275 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
276 #define TS_SER 0
277 #define TS_INV 0
278 #define FIF_H 0x13
279 #define FIF_L 0x88
280 #define IF_INV_PWM 0x00
281 #define T_LOWIF 1
282
283 MS_U8 INTERN_DVBT_DSPREG[] =
284 {
285 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
286 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
287 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
288 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
289 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
290 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
293 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
294 /*
295 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
296 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
297 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
298 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
299 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
300 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
301 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
302 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
303 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
304 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
305 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
306 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
307 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
308 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
309 */
310 };
311 /*END INTERN_DVBT_DSPREG_TABLE*/
312 //-----------------------------------------------------------------------
313 /****************************************************************
314 *Local Variables *
315 ****************************************************************/
316 static MS_BOOL bFECLock=0;
317 static MS_BOOL bTPSLock = 0;
318 static MS_U32 u32ChkScanTimeStart = 0;
319 static MS_U32 u32FecFirstLockTime=0;
320 static MS_U32 u32FecLastLockTime=0;
321 static float fViterbiBerFiltered=-1;
322 //Global Variables
323 S_CMDPKTREG gsCmdPacket;
324 //U8 gCalIdacCh0, gCalIdacCh1;
325
326 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
327 MS_U8 INTERN_DVBT_table[] = {
328 #include "fwDMD_INTERN_DVBT.dat"
329 };
330
331 #endif
332
333 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
334 {
335 { _QPSK , _CR1Y2, -93},
336 { _QPSK , _CR2Y3, -91},
337 { _QPSK , _CR3Y4, -90},
338 { _QPSK , _CR5Y6, -89},
339 { _QPSK , _CR7Y8, -88},
340
341 { _16QAM , _CR1Y2, -87},
342 { _16QAM , _CR2Y3, -85},
343 { _16QAM , _CR3Y4, -84},
344 { _16QAM , _CR5Y6, -83},
345 { _16QAM , _CR7Y8, -82},
346
347 { _64QAM , _CR1Y2, -82},
348 { _64QAM , _CR2Y3, -80},
349 { _64QAM , _CR3Y4, -78},
350 { _64QAM , _CR5Y6, -77},
351 { _64QAM , _CR7Y8, -76},
352 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
353 };
354
355
356
357 static void INTERN_DVBT_SignalQualityReset(void);
358 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
359
INTERN_DVBT_SignalQualityReset(void)360 static void INTERN_DVBT_SignalQualityReset(void)
361 {
362 u32FecFirstLockTime=0;
363 fViterbiBerFiltered=-1;
364 }
365
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)366 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
367 {
368 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
369 MS_BOOL status = TRUE;
370 MS_U16 u16DspAddr = 0;
371
372 DBG_INTERN_DVBT(printf("INTERN_DVBT_DSPReg_Init\n"));
373
374 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
375 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
376
377 if (u8DVBT_DSPReg != NULL)
378 {
379 /*temp solution until new dsp table applied.*/
380 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
381 if (u8DVBT_DSPReg[0] >= 1)
382 {
383 u8DVBT_DSPReg+=2;
384 for (idx = 0; idx<u8Size; idx++)
385 {
386 u16DspAddr = *u8DVBT_DSPReg;
387 u8DVBT_DSPReg++;
388 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
389 u8DVBT_DSPReg++;
390 u8Mask = *u8DVBT_DSPReg;
391 u8DVBT_DSPReg++;
392 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
393 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
394 u8DVBT_DSPReg++;
395 DBG_INTERN_DVBT(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
396 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
397 }
398 }
399 else
400 {
401 printf("FATAL: parameter version incorrect\n");
402 }
403 }
404
405 return status;
406 }
407
408 /***********************************************************************************
409 Subject: Command Packet Interface
410 Function: INTERN_DVBT_Cmd_Packet_Send
411 Parmeter:
412 Return: MS_BOOL
413 Remark:
414 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)415 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
416 {
417
418 return TRUE;
419
420 }
421
422
423 /***********************************************************************************
424 Subject: Command Packet Interface
425 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
426 Parmeter:
427 Return: MS_BOOL
428 Remark:
429 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)430 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
431 {
432 return TRUE;
433 }
434
435 /***********************************************************************************
436 Subject: SoftStop
437 Function: INTERN_DVBT_SoftStop
438 Parmeter:
439 Return: MS_BOOL
440 Remark:
441 ************************************************************************************/
442
INTERN_DVBT_SoftStop(void)443 MS_BOOL INTERN_DVBT_SoftStop ( void )
444 {
445 #if 1
446 MS_U16 u8WaitCnt=0;
447
448 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
449 {
450 printf(">> MB Busy!\n");
451 return FALSE;
452 }
453
454 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
455
456 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
457 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
458
459 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
460 {
461 #if TEST_EMBEDED_DEMOD
462 MsOS_DelayTask(1); // << Ken 20090629
463 #endif
464 if (u8WaitCnt++ >= 0x7FFF)
465 {
466 printf(">> DVBT SoftStop Fail!\n");
467 return FALSE;
468 }
469 }
470
471 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
472 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
473 #endif
474 return TRUE;
475 }
476
477
478 /***********************************************************************************
479 Subject: Reset
480 Function: INTERN_DVBT_Reset
481 Parmeter:
482 Return: MS_BOOL
483 Remark:
484 ************************************************************************************/
485 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)486 MS_BOOL INTERN_DVBT_Reset ( void )
487 {
488 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_reset\n"));
489
490 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime()));
491
492 //INTERN_DVBT_SoftStop();
493
494 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
495 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset DMD_MCU
496 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
497 MsOS_DelayTask(5);
498 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
499 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
500 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
501 MsOS_DelayTask(5);
502
503 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
504 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
505
506 bFECLock = FALSE;
507 bTPSLock = FALSE;
508 u32ChkScanTimeStart = MsOS_GetSystemTime();
509 return TRUE;
510 }
511
512 /***********************************************************************************
513 Subject: Exit
514 Function: INTERN_DVBT_Exit
515 Parmeter:
516 Return: MS_BOOL
517 Remark:
518 ************************************************************************************/
INTERN_DVBT_Exit(void)519 MS_BOOL INTERN_DVBT_Exit ( void )
520 {
521
522 INTERN_DVBT_SoftStop();
523
524
525
526 return TRUE;
527 }
528
529 /***********************************************************************************
530 Subject: Load DSP code to chip
531 Function: INTERN_DVBT_LoadDSPCode
532 Parmeter:
533 Return: MS_BOOL
534 Remark:
535 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)536 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
537 {
538 MS_U8 udata = 0x00;
539 MS_U16 i;
540 MS_U16 fail_cnt=0;
541
542 #if (DBG_DUMP_LOAD_DSP_TIME==1)
543 MS_U32 u32Time;
544 #endif
545
546
547 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
548 BININFO BinInfo;
549 MS_BOOL bResult;
550 MS_U32 u32GEAddr;
551 MS_U8 Data;
552 MS_S8 op;
553 MS_U32 srcaddr;
554 MS_U32 len;
555 MS_U32 SizeBy4K;
556 MS_U16 u16Counter=0;
557 MS_U8 *pU8Data;
558 #endif
559
560
561
562 // MDrv_Sys_DisableWatchDog();
563
564 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset
565 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset VD_MCU
566 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
567 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
568 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
569 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
570 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
571
572 //// Load code thru VDMCU_IF ////
573 DBG_INTERN_DVBT(printf(">Load Code...\n"));
574 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
575 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
576 {
577 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
578 }
579 #else
580 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
581 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
582 if ( bResult != PASS )
583 {
584 return FALSE;
585 }
586 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
587
588 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
589 InfoBlock_Flash_2_Checking_Start(&BinInfo);
590 #endif
591
592 #if OBA2
593 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
594 #else
595 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
596 #endif
597
598 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
599 InfoBlock_Flash_2_Checking_End(&BinInfo);
600 #endif
601
602 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
603 SizeBy4K=BinInfo.B_Len/0x1000;
604 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
605
606 #if (DBG_DUMP_LOAD_DSP_TIME==1)
607 u32Time = msAPI_Timer_GetTime0();
608 #endif
609
610 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
611
612 for (i=0;i<=SizeBy4K;i++)
613 {
614 if(i==SizeBy4K)
615 len=BinInfo.B_Len%0x1000;
616 else
617 len=0x1000;
618
619 srcaddr = u32GEAddr+(0x1000*i);
620 //printf("\t i = %08X\n", i);
621 //printf("\t len = %08X\n", len);
622 op = 1;
623 u16Counter = 0 ;
624 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
625 while(len--)
626 {
627 u16Counter ++ ;
628 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
629 //pU8Data = (U8 *)(srcaddr|0x80000000);
630 #if OBA2
631 pU8Data = (U8 *)(srcaddr);
632 #else
633 pU8Data = (U8 *)(srcaddr|0x80000000);
634 #endif
635 Data = *pU8Data;
636
637 #if 0
638 if(u16Counter < 0x100)
639 printf("0x%bx,", Data);
640 #endif
641 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
642
643 srcaddr += op;
644 }
645 // printf("\n\n\n");
646 }
647
648 #if (DBG_DUMP_LOAD_DSP_TIME==1)
649 printf("------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
650 #endif
651
652 #endif
653
654 //// Content verification ////
655 DBG_INTERN_DVBT(printf(">Verify Code...\n"));
656
657 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
658 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
659
660 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
661 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
662 {
663 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
664 if (udata != INTERN_DVBT_table[i])
665 {
666 printf(">fail add = 0x%x\n", i);
667 printf(">code = 0x%x\n", INTERN_DVBT_table[i]);
668 printf(">data = 0x%x\n", udata);
669
670 if (fail_cnt++ > 10)
671 {
672 printf(">DVB-T DSP Loadcode fail!");
673 return false;
674 }
675 }
676 }
677 #else
678 for (i=0;i<=SizeBy4K;i++)
679 {
680 if(i==SizeBy4K)
681 len=BinInfo.B_Len%0x1000;
682 else
683 len=0x1000;
684
685 srcaddr = u32GEAddr+(0x1000*i);
686 //printf("\t i = %08LX\n", i);
687 //printf("\t len = %08LX\n", len);
688 op = 1;
689 u16Counter = 0 ;
690 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
691 while(len--)
692 {
693 u16Counter ++ ;
694 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
695 //pU8Data = (U8 *)(srcaddr|0x80000000);
696 #if OBA2
697 pU8Data = (U8 *)(srcaddr);
698 #else
699 pU8Data = (U8 *)(srcaddr|0x80000000);
700 #endif
701 Data = *pU8Data;
702
703 #if 0
704 if(u16Counter < 0x100)
705 printf("0x%bx,", Data);
706 #endif
707 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
708 if (udata != Data)
709 {
710 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
711 printf(">code = 0x%x\n", Data);
712 printf(">data = 0x%x\n", udata);
713
714 if (fail_cnt++ > 10)
715 {
716 printf(">DVB-T DSP Loadcode fail!");
717 return false;
718 }
719 }
720
721 srcaddr += op;
722 }
723 // printf("\n\n\n");
724 }
725 #endif
726
727 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
728 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
729 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
730 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
731
732 DBG_INTERN_DVBT(printf(">DSP Loadcode done."));
733 //while(load_data_variable);
734
735
736 return TRUE;
737 }
738
739 /***********************************************************************************
740 Subject: DVB-T CLKGEN initialized function
741 Function: INTERN_DVBT_Power_On_Initialization
742 Parmeter:
743 Return: MS_BOOL
744 Remark:
745 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)746 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
747 {
748 HAL_DMD_RIU_WriteByte(0x103c0e,0x00);
749 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
750 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
751 // ----------------------------------------------
752 // start demod CLKGEN setting
753 // ----------------------------------------------
754 // *** Set register at CLKGEN1
755 // enable DMD MCU clock "bit[0] set 0"
756 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
757 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
758 // CLK_DMDMCU clock setting
759 // [0] disable clock
760 // [1] invert clock
761 // [4:2]
762 // 000:170 MHz(MPLL_DIV_BUf)
763 // 001:160MHz
764 // 010:144MHz
765 // 011:123MHz
766 // 100:108MHz
767 // 101:mem_clcok
768 // 110:mem_clock div 2
769 // 111:select XTAL
770 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
771 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
772
773 // set parallet ts clock
774 HAL_DMD_RIU_WriteByte(0x103301,0x05);
775 HAL_DMD_RIU_WriteByte(0x103300,0x14);
776
777 // enable atsc, DVBTC ts clock
778 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
779 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
780 HAL_DMD_RIU_WriteByte(0x103309,0x00);
781 HAL_DMD_RIU_WriteByte(0x103308,0x00);
782
783 // enable dvbc adc clock
784 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
785 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
786 HAL_DMD_RIU_WriteByte(0x103315,0x00);
787 HAL_DMD_RIU_WriteByte(0x103314,0x00);
788
789 // Reset TS divider
790 HAL_DMD_RIU_WriteByte(0x103302,0x01);
791 HAL_DMD_RIU_WriteByte(0x103302,0x00);
792
793
794 // enable clk_atsc_adcd_sync
795 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
796 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
797 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
798 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
799
800 // enable dvbt inner clock
801 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
802 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
803 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
804 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
805
806
807
808 // enable dvbt inner clock
809 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
810 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
811 HAL_DMD_RIU_WriteByte(0x111f21,0x44);
812 HAL_DMD_RIU_WriteByte(0x111f20,0x40);
813
814 // enable dvbc outer clock
815 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
816 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
817 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
818 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
819
820
821 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
822
823 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
824 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
825
826 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
827 HAL_DMD_RIU_WriteByte(0x111f2c,0x41);
828
829
830 HAL_DMD_RIU_WriteByte(0x111f2f,0x0c);
831 HAL_DMD_RIU_WriteByte(0x111f2e,0x04);
832
833
834 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
835 HAL_DMD_RIU_WriteByte(0x111f30,0x04);
836
837 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
838 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
839
840
841 HAL_DMD_RIU_WriteByte(0x111f35,0x10);
842 HAL_DMD_RIU_WriteByte(0x111f34,0x10);
843
844 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
845 HAL_DMD_RIU_WriteByte(0x111f36,0x11);
846
847 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
848 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
849
850 HAL_DMD_RIU_WriteByte(0x111f3d,0x0c);
851 HAL_DMD_RIU_WriteByte(0x111f3c,0x04);
852
853 HAL_DMD_RIU_WriteByte(0x111f45,0x04);
854 HAL_DMD_RIU_WriteByte(0x111f44,0x44);
855
856 HAL_DMD_RIU_WriteByte(0x111f69,0x00);
857 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
858
859 HAL_DMD_RIU_WriteByte(0x111f6b,0x00);
860 HAL_DMD_RIU_WriteByte(0x111f6a,0x00);
861
862 HAL_DMD_RIU_WriteByte(0x111f6d,0x00);
863 HAL_DMD_RIU_WriteByte(0x111f6c,0x10);
864
865 HAL_DMD_RIU_WriteByte(0x111f6f,0x0c);
866 HAL_DMD_RIU_WriteByte(0x111f6e,0x40);
867
868 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
869 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
870
871 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
872 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
873
874 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
875 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
876
877 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
878 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
879
880 HAL_DMD_RIU_WriteByte(0x111f79,0x40);
881 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
882
883 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
884 HAL_DMD_RIU_WriteByte(0x111f7a,0x04);
885
886 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
887 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
888
889 HAL_DMD_RIU_WriteByte(0x111f7f,0x40);
890 HAL_DMD_RIU_WriteByte(0x111f7e,0x40);
891
892 HAL_DMD_RIU_WriteByte(0x111fe1,0x04);
893 HAL_DMD_RIU_WriteByte(0x111fe0,0x04);
894
895 HAL_DMD_RIU_WriteByte(0x111ff0,0x04);
896
897 HAL_DMD_RIU_WriteByte(0x111fe3,0x04);
898 HAL_DMD_RIU_WriteByte(0x111fe2,0x0c);
899
900 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
901 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
902
903 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
904 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
905
906 HAL_DMD_RIU_WriteByte(0x111fe9,0x04);
907 HAL_DMD_RIU_WriteByte(0x111fe8,0x0c);
908
909 HAL_DMD_RIU_WriteByte(0x111feb,0x88);
910 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
911
912 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
913 HAL_DMD_RIU_WriteByte(0x111fec,0x08);
914
915 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
916 HAL_DMD_RIU_WriteByte(0x111fee,0x88);
917
918 HAL_DMD_RIU_WriteByte(0x15298f,0x00);
919 HAL_DMD_RIU_WriteByte(0x15298e,0x00);
920
921 HAL_DMD_RIU_WriteByte(0x152991,0x00);
922 HAL_DMD_RIU_WriteByte(0x152990,0x00);
923 HAL_DMD_RIU_WriteByte(0x152992,0x00);
924
925 HAL_DMD_RIU_WriteByte(0x1529e5,0x00);
926 HAL_DMD_RIU_WriteByte(0x1529e4,0x00);
927
928
929 HAL_DMD_RIU_WriteByte(0x152971,0x10);
930 HAL_DMD_RIU_WriteByte(0x152970,0x01);
931
932 HAL_DMD_RIU_WriteByte(0x111f43,0x04);
933 HAL_DMD_RIU_WriteByte(0x111f42,0x04);
934
935
936 // 32+4K xdata sram
937 //wriu 0x1117e0 0x23
938 //wriu 0x1117e1 0x21
939
940 //wriu 0x1117e4 0x01
941 //wriu 0x1117e6 0x11
942 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
943 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
944 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
945 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
946
947 // SRAM End Address
948 HAL_DMD_RIU_WriteByte(0x111707,0xff);
949 HAL_DMD_RIU_WriteByte(0x111706,0xff);
950
951 // DRAM Disable
952 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
953
954
955
956 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
957 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
958 }
959
960 /***********************************************************************************
961 Subject: Power on initialized function
962 Function: INTERN_DVBT_Power_On_Initialization
963 Parmeter:
964 Return: MS_BOOL
965 Remark:
966 ************************************************************************************/
967
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)968 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
969 {
970 MS_U16 status = true;
971 MS_U8 cData = 0;
972 //U8 cal_done;
973 DBG_INTERN_DVBT(printf("INTERN_DVBT_Power_On_Initialization\n"));
974
975 #if defined(PWS_ENABLE)
976 Mapi_PWS_Stop_VDMCU();
977 #endif
978
979 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
980 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
981 //// Firmware download //////////
982 DBG_INTERN_DVBT(printf("INTERN_DVBT Load DSP...\n"));
983 //MsOS_DelayTask(100);
984
985
986 {
987 if (INTERN_DVBT_LoadDSPCode() == FALSE)
988 {
989 printf("DVB-T Load DSP Code Fail\n");
990 return FALSE;
991 }
992 else
993 {
994 DBG_INTERN_DVBT(printf("DVB-T Load DSP Code OK\n"));
995 }
996 }
997
998
999 //// MCU Reset //////////
1000 DBG_INTERN_DVBT(printf("INTERN_DVBT Reset...\n"));
1001 if (INTERN_DVBT_Reset() == FALSE)
1002 {
1003 DBG_INTERN_DVBT(printf("Fail\n"));
1004 return FALSE;
1005 }
1006 else
1007 {
1008 DBG_INTERN_DVBT(printf("OK\n"));
1009 }
1010
1011 // reset FDP
1012 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1013 // SRAM setting, DVB-T use it.
1014 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1015 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1016 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1017
1018 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1019 return status;
1020 }
1021
1022 /************************************************************************************************
1023 Subject: Driving control
1024 Function: INTERN_DVBT_Driving_Control
1025 Parmeter: bInversionEnable : TRUE For High
1026 Return: void
1027 Remark:
1028 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1029 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1030 {
1031 MS_U8 u8Temp;
1032
1033 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1034
1035 if (bEnable)
1036 {
1037 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1038 }
1039 else
1040 {
1041 u8Temp = u8Temp & (~0x01);
1042 }
1043
1044 DBG_INTERN_DVBT(printf("---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1045 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1046 }
1047 /************************************************************************************************
1048 Subject: Clk Inversion control
1049 Function: INTERN_DVBT_Clk_Inversion_Control
1050 Parmeter: bInversionEnable : TRUE For Inversion Action
1051 Return: void
1052 Remark:
1053 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1054 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1055 {
1056 MS_U8 u8Temp;
1057
1058 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1059
1060 if (bInversionEnable)
1061 {
1062 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1063 }
1064 else
1065 {
1066 u8Temp = u8Temp & (~0x02);
1067 }
1068
1069 DBG_INTERN_DVBT(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1070 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1071 }
1072 /************************************************************************************************
1073 Subject: Transport stream serial/parallel control
1074 Function: INTERN_DVBT_Serial_Control
1075 Parmeter: bEnable : TRUE For serial
1076 Return: MS_BOOL :
1077 Remark:
1078 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1079 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1080 {
1081 MS_U8 status = true;
1082
1083 return status;
1084
1085 }
1086
1087 /************************************************************************************************
1088 Subject: TS1 output control
1089 Function: INTERN_DVBT_PAD_TS1_Enable
1090 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1091 Return: void
1092 Remark:
1093 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1094 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1095 {
1096 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_TS1_Enable... \n"));
1097
1098 if(flag) // PAD_TS1 Enable TS CLK PAD
1099 {
1100 //printf("=== TS1_Enable ===\n");
1101 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1102 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1103 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1104 }
1105 else // PAD_TS1 Disable TS CLK PAD
1106 {
1107 //printf("=== TS1_Disable ===\n");
1108 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1109 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1110 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1111 }
1112 }
1113
1114 /************************************************************************************************
1115 Subject: channel change config
1116 Function: INTERN_DVBT_Config
1117 Parmeter: BW: bandwidth
1118 Return: MS_BOOL :
1119 Remark:
1120 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1121 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1122 {
1123 MS_U8 bandwidth;
1124 MS_U8 status = true;
1125
1126 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap));
1127 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime()));
1128
1129 if (u8TSClk == 0xFF) u8TSClk=0x13;
1130 switch(BW)
1131 {
1132 case E_DMD_RF_CH_BAND_6MHz:
1133 bandwidth = 1;
1134 break;
1135 case E_DMD_RF_CH_BAND_7MHz:
1136 bandwidth = 2;
1137 break;
1138 case E_DMD_RF_CH_BAND_8MHz:
1139 default:
1140 bandwidth = 3;
1141 break;
1142 }
1143
1144 status &= INTERN_DVBT_Reset();
1145
1146 // BW mode
1147 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1148 // TS mode
1149 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1150 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1151 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1152 // Hierarchy mode
1153 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1154 // FC
1155 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1156 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1157 // FS
1158 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1159 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1160 // IQSwap
1161 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1162
1163 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1164 // Fif
1165 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1166 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1167
1168 return status;
1169 }
1170 /************************************************************************************************
1171 Subject: enable hw to lock channel
1172 Function: INTERN_DVBT_Active
1173 Parmeter: bEnable
1174 Return: MS_BOOL
1175 Remark:
1176 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1177 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1178 {
1179 MS_U8 status = true;
1180
1181 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_active\n"));
1182
1183 //// INTERN_DVBT Finite State Machine on/off //////////
1184 #if 0
1185 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1186
1187 gsCmdPacket.param[0] = (MS_U8)bEnable;
1188 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1189 #else
1190 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1191 #endif
1192 INTERN_DVBT_SignalQualityReset();
1193
1194 return status;
1195 }
1196
1197
1198
1199
1200
1201 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBT_Locked_Task(void)1202 MS_BOOL INTERN_DVBT_Locked_Task(void)
1203 {
1204 INTERN_DVBT_Adaptive_TS_CLK();
1205
1206 //extension task
1207 {
1208 }
1209 return TRUE;
1210 }
1211
1212
1213
1214
INTERN_DVBT_Adaptive_TS_CLK(void)1215 MS_BOOL INTERN_DVBT_Adaptive_TS_CLK(void)
1216 {
1217 MS_U8 u8_ts_clk=0x00;
1218 MS_U8 TS_Clock_Temp;
1219 u8_ts_clk = HAL_DMD_RIU_ReadByte(0x112615);
1220 //printf("*************************************************************\n");
1221 //printf(" The TS clock: %x\n",u8_ts_clk);
1222
1223 //reg_atsc_dvb_div_reset =1
1224 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1225 TS_Clock_Temp=TS_Clock_Temp|0x01;
1226 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1227
1228 //set TS clock source div 5
1229 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1);
1230 TS_Clock_Temp=(TS_Clock_Temp&(~0x01));
1231 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp);
1232
1233 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
1234 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1235 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_ts_clk;
1236 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp);
1237
1238
1239 //reg_atsc_dvb_div_reset =0
1240 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1241 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
1242 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1243
1244 // set ts FIFO
1245 // reg_RS_BACKEND
1246 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
1247 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ;
1248
1249 // enable ts
1250 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ;
1251 TS_Clock_Temp=TS_Clock_Temp|0x01;
1252 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ;
1253
1254 //debug: re-check ts clock
1255 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1256 TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
1257
1258 //printf("-------------------------------------------------------\n");
1259 //printf(" System report: %x\n",TS_Clock_Temp);
1260 //printf("*************************************************************\n");
1261
1262 return TRUE;
1263 }
1264
1265 #endif
1266 /************************************************************************************************
1267 Subject: Return lock status
1268 Function: INTERN_DVBT_Lock
1269 Parmeter: eStatus :
1270 Return: MS_BOOL
1271 Remark:
1272 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1273 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1274 {
1275 float fBER=0.0f;
1276
1277 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1278 {
1279 if (bFECLock == FALSE)
1280 {
1281 u32FecFirstLockTime = MsOS_GetSystemTime();
1282 DBG_INTERN_DVBT(printf("++++++++[utopia]dvbt lock\n"));
1283 }
1284
1285 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1286 {
1287 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1288 {
1289 if(fViterbiBerFiltered <= 0.0)
1290 fViterbiBerFiltered = fBER;
1291 else
1292 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1293 }
1294 DBG_INTERN_DVBT(printf("[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1295 }
1296 u32FecLastLockTime = MsOS_GetSystemTime();
1297 bFECLock = TRUE;
1298 return E_DMD_LOCK;
1299 }
1300 else
1301 {
1302 INTERN_DVBT_SignalQualityReset();
1303 if (bFECLock == TRUE)
1304 {
1305 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1306 {
1307 return E_DMD_LOCK;
1308 }
1309 }
1310 bFECLock = FALSE;
1311 }
1312
1313 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1314 {
1315 printf("==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1316 return E_DMD_UNLOCK;
1317 }
1318
1319 if(!bTPSLock)
1320 {
1321 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1322 {
1323 DBG_INTERN_DVBT(printf("==> INTERN_DVBT_Lock -- TPSLock \n"););
1324 bTPSLock = TRUE;
1325 }
1326 }
1327 if(bTPSLock)
1328 {
1329 DBG_INTERN_DVBT(printf("TPSLock %ld\n",MsOS_GetSystemTime()));
1330 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1331 {
1332 return E_DMD_CHECKING;
1333 }
1334 }
1335 else
1336 {
1337 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1338 {
1339 return E_DMD_CHECKING;
1340 }
1341 }
1342 return E_DMD_UNLOCK;
1343
1344 }
1345
1346
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1347 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1348 {
1349 MS_U16 u16Address = 0;
1350 MS_U8 cData = 0;
1351 MS_U8 cBitMask = 0;
1352 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1353 MS_U8 lock_to_unlock_flag=0;
1354 #endif
1355 switch( eStatus )
1356 {
1357 case E_DMD_COFDM_FEC_LOCK:
1358 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1359 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1360 MDrv_SYS_DMD_VD_MBX_ReadReg(MBX_REG_BASE+0x16, &lock_to_unlock_flag);
1361 if (((cData == 0x0B) && (bFECLock == FALSE)) ||((cData == 0x0B) && ((lock_to_unlock_flag & 0x01)==0x01)) )
1362 {
1363 // printf("Support adaptive TS CLK in polling mode! \n");
1364 INTERN_DVBT_Locked_Task();
1365 if((lock_to_unlock_flag & 0x01)==0x01)
1366 {
1367 MDrv_SYS_DMD_VD_MBX_WriteReg(MBX_REG_BASE+0x16,0x00);
1368 }
1369
1370 }
1371 #endif
1372
1373 if (cData == 0x0B)
1374 {
1375 return TRUE;
1376 }
1377 else
1378 {
1379 return FALSE; // continuously un-lock
1380 }
1381 break;
1382
1383 case E_DMD_COFDM_PSYNC_LOCK:
1384 u16Address = 0x232C; //FEC: P-sync Lock,
1385 cBitMask = BIT(1);
1386 break;
1387
1388 case E_DMD_COFDM_TPS_LOCK:
1389 u16Address = 0x2222; //TPS HW Lock,
1390 cBitMask = BIT(1);
1391 break;
1392
1393 case E_DMD_COFDM_DCR_LOCK:
1394 u16Address = 0x2737; //DCR Lock,
1395 cBitMask = BIT(0);
1396 break;
1397
1398 case E_DMD_COFDM_AGC_LOCK:
1399 u16Address = 0x2829; //AGC Lock,
1400 cBitMask = BIT(0);
1401 break;
1402
1403 case E_DMD_COFDM_MODE_DET:
1404 u16Address = 0x24CF; //Mode CP Detect,
1405 cBitMask = BIT(4);
1406 break;
1407
1408 case E_DMD_COFDM_TPS_EVER_LOCK:
1409 u16Address = 0x20C0; //TPS Ever Lock,
1410 cBitMask = BIT(3);
1411 break;
1412
1413 case E_DMD_COFDM_NO_CHANNEL:
1414 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1415 cBitMask = BIT(7);
1416 break;
1417
1418 default:
1419 return FALSE;
1420 }
1421
1422 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1423 return FALSE;
1424
1425 if ((cData & cBitMask) == cBitMask)
1426 {
1427 return TRUE;
1428 }
1429
1430 return FALSE;
1431
1432 }
1433
1434 /****************************************************************************
1435 Subject: To get the Post viterbi BER
1436 Function: INTERN_DVBT_GetPostViterbiBer
1437 Parmeter: Quility
1438 Return: E_RESULT_SUCCESS
1439 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1440 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1441 We will not read the Period, and have the "/256/8"
1442 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1443 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1444 {
1445 MS_BOOL status = true;
1446 MS_U8 reg=0, reg_frz=0;
1447 MS_U16 BitErrPeriod;
1448 MS_U32 BitErr;
1449 MS_U16 PktErr;
1450
1451 /////////// Post-Viterbi BER /////////////
1452
1453 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1454 {
1455 *ber = (float)-1.0;
1456 return false;
1457 }
1458 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1460 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1461
1462 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1463 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1464 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1465 BitErrPeriod = reg;
1466
1467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1468 BitErrPeriod = (BitErrPeriod << 8)|reg;
1469
1470 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1471 // 0x6b [15:8] reg_bit_err_num_15_8
1472 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1473 // 0x6d [15:8] reg_bit_err_num_31_24
1474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1475 BitErr = reg;
1476
1477 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1478 BitErr = (BitErr << 8)|reg;
1479
1480 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1481 BitErr = (BitErr << 8)|reg;
1482
1483 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1484 BitErr = (BitErr << 8)|reg;
1485
1486 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1487 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1488 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1489 PktErr = reg;
1490
1491 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1492 PktErr = (PktErr << 8)|reg;
1493
1494 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1495 reg_frz=reg_frz&(~0x03);
1496 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1497
1498 if (BitErrPeriod == 0 ) //protect 0
1499 BitErrPeriod = 1;
1500
1501 if (BitErr <=0 )
1502 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1503 else
1504 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1505
1506
1507 DBG_GET_SIGNAL(printf("INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1508 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1509
1510 return status;
1511 }
1512
1513 /****************************************************************************
1514 Subject: To get the Pre viterbi BER
1515 Function: INTERN_DVBT_GetPreViterbiBer
1516 Parmeter: ber
1517 Return: E_RESULT_SUCCESS
1518 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1519 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1520 We will not read the Period, and have the "/256/8"
1521 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1522 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1523 {
1524 MS_U8 status = true;
1525 MS_U8 reg=0, reg_frz=0;
1526 MS_U16 BitErrPeriod;
1527 MS_U32 BitErr;
1528 MS_BOOL BEROver;
1529
1530 // bank 7 0x10 [3] reg_rd_freezeber
1531 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1532 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1533
1534 // bank 7 0x16 [7:0] reg_ber_timerl
1535 // [15:8] reg_ber_timerm
1536 // bank 7 0x18 [5:0] reg_ber_timerh
1537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1538 BitErrPeriod = reg&0x3f;
1539
1540 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1541 BitErrPeriod = (BitErrPeriod << 8)|reg;
1542
1543 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1544 BitErrPeriod = (BitErrPeriod << 8)|reg;
1545
1546 // bank 7 0x1e [7:0] reg_ber_7_0
1547 // [15:8] reg_ber_15_8
1548 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1549 BitErr = reg;
1550
1551 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1552 BitErr = (BitErr << 8)|reg;
1553
1554 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1556 if (reg & 0x10)
1557 BEROver = true;
1558 else
1559 BEROver = false;
1560
1561 if (BitErrPeriod ==0 )//protect 0
1562 BitErrPeriod=1;
1563
1564 if (BEROver)
1565 {
1566 *ber = 1;
1567 printf("BER is over\n");
1568 }
1569 else
1570 {
1571 if (BitErr <=0 )
1572 *ber=0.5 / (float)(BitErrPeriod * 256);
1573 else
1574 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1575 }
1576
1577 // bank 7 0x10 [3] reg_rd_freezeber
1578 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1579
1580 return status;
1581 }
1582
1583 /****************************************************************************
1584 Subject: To get the Packet error
1585 Function: INTERN_DVBT_GetPacketErr
1586 Parmeter: pktErr
1587 Return: E_RESULT_SUCCESS
1588 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1589 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1590 We will not read the Period, and have the "/256/8"
1591 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1592 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1593 {
1594 MS_BOOL status = true;
1595 MS_U8 reg = 0, reg_frz = 0;
1596 MS_U16 PktErr;
1597
1598 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1599 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1601
1602 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1603 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1604 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1605 PktErr = reg;
1606
1607 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1608 PktErr = (PktErr << 8)|reg;
1609
1610 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1611 reg_frz=reg_frz&(~0x03);
1612 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1613
1614 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1615
1616 *u16PktErr = PktErr;
1617
1618 return status;
1619 }
1620
1621 /****************************************************************************
1622 Subject: To get the DVBT parameter
1623 Function: INTERN_DVBT_Get_TPS_Info
1624 Parmeter: point to return parameter
1625 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1626 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1627 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1628 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1629 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1630 FFT ( b14) : 0~1 => 2K, 8K
1631 Priority(bit 15) : 0~1=> HP,LP
1632 Return: TRUE
1633 FALSE
1634 Remark: The TPS parameters will be available after TPS lock
1635 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1636 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1637 {
1638 MS_U8 u8Temp;
1639
1640 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1641 return FALSE;
1642
1643 if ((u8Temp& 0x02) != 0x02)
1644 {
1645 return FALSE; //TPS unlock
1646 }
1647 else
1648 {
1649 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1650 return FALSE;
1651
1652 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1653 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1654
1655 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1656 return FALSE;
1657
1658 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1659 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1660
1661 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1662 return FALSE;
1663
1664 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1665 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1666
1667 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1668 return FALSE;
1669
1670 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
1671
1672 }
1673 return TRUE;
1674 }
1675
1676
1677 /****************************************************************************
1678 Subject: Read the signal to noise ratio (SNR)
1679 Function: INTERN_DVBT_GetSNR
1680 Parmeter: None
1681 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1682 Remark:
1683 *****************************************************************************/
INTERN_DVBT_GetSNR(void)1684 float INTERN_DVBT_GetSNR (void)
1685 {
1686 MS_U8 status = true;
1687 MS_U8 reg=0, reg_frz=0;
1688 MS_U32 noise_power;
1689 float snr;
1690
1691 // bank 6 0xfe [0] reg_fdp_freeze
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
1693 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
1694
1695 // bank 6 0xff [0] reg_fdp_load
1696 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1697
1698 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
1700 noise_power = reg & 0x07;
1701
1702 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
1703 noise_power = (noise_power << 8)|reg;
1704
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
1706 noise_power = (noise_power << 8)|reg;
1707
1708 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
1709 noise_power = (noise_power << 8)|reg;
1710
1711 // bank 6 0x26 [5:4] reg_transmission_mode
1712 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
1713
1714 // bank 6 0xfe [0] reg_fdp_freeze
1715 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
1716
1717 // bank 6 0xff [0] reg_fdp_load
1718 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1719
1720 #if 1 // copy from utopia2\mxlib\hal\miami\demod\halDMD_INTERN_DVBT.c
1721 noise_power = noise_power/2;
1722 noise_power /=1280;
1723 // noisepower = (rand()%256)*256;
1724 if (noise_power==0)//protect value 0
1725 noise_power=1;
1726
1727 #ifdef MSOS_TYPE_LINUX
1728 snr = 10*log10f((float)noise_power);
1729 #else
1730 snr = 10*Log10Approx((float)noise_power);
1731 #endif
1732
1733
1734 #else
1735 noise_power = noise_power/2;
1736
1737 if ((reg&0x30)==0x00) //2K
1738 {
1739 if (noise_power<1512)
1740 snr = 0;
1741 else
1742 #ifdef MSOS_TYPE_LINUX
1743 snr = 10*log10f((float)noise_power/1512);
1744 #else
1745 snr = 10*Log10Approx((float)noise_power/1512);
1746 #endif
1747 }
1748 //else if ((reg&0x30)==0x10)//8K
1749 else
1750 {
1751 if (noise_power<6048)
1752 snr = 0;
1753 else
1754 #ifdef MSOS_TYPE_LINUX
1755 snr = 10*log10f((float)noise_power/6048);
1756 #else
1757 snr = 10*Log10Approx((float)noise_power/6048);
1758 #endif
1759 }
1760 /* ignore 4K
1761 else //4K
1762 {
1763 if (noise_power<3024)
1764 snr = 0;
1765 else
1766 snr = 10*Log10Approx(noise_power/3024);
1767 }
1768 */
1769 #endif
1770
1771 if (status == true)
1772 return snr;
1773 else
1774 return -1;
1775
1776 }
1777
1778 /****************************************************************************
1779 Subject: To check if Hierarchy on
1780 Function: INTERN_DVBT_Is_HierarchyOn
1781 Parmeter:
1782 Return: BOOLEAN
1783 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)1784 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
1785 {
1786 MS_U16 u16_tmp;
1787
1788 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
1789 return FALSE;
1790 //printf("u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
1791 if(u16_tmp&0x38)
1792 {
1793 return TRUE;
1794 }
1795 return FALSE;
1796 }
1797
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1798 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1799 {
1800 MS_U8 status = true;
1801 float ch_power_db = 0.0f;
1802 float ch_power_ref = 11.0f;
1803 float ch_power_rel = 0.0f;
1804 MS_U8 u8_index = 0;
1805 MS_U16 tps_info_qam,tps_info_cr;
1806
1807 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1808 {
1809 *strength = 0;
1810 return TRUE;
1811 }
1812 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
1813
1814 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
1815 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
1816 /* Actually, it's more reasonable, that signal level depended on cable input power level
1817 * thougth the signal isn't dvb-t signal.
1818 */
1819
1820 // use pointer of IFAGC table to identify
1821 // case 1: RFAGC from SAR, IFAGC controlled by demod
1822 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1823 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1824 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
1825 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1826 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1827 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
1828 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
1829
1830
1831 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
1832 printf("[dvbt]TPS qam parameter retrieve failure\n");
1833
1834 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
1835 printf("[dvbt]TPS cr parameter retrieve failure\n");
1836
1837
1838 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
1839 {
1840 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
1841 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
1842 {
1843 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
1844 break;
1845 }
1846 else
1847 {
1848 u8_index++;
1849 }
1850 }
1851
1852 if (ch_power_ref > 10.0f)
1853 *strength = 0;
1854 else
1855 {
1856 ch_power_rel = ch_power_db - ch_power_ref;
1857
1858 if ( ch_power_rel < -15.0f )
1859 {
1860 *strength = 0;
1861 }
1862 else if ( ch_power_rel < 0.0f )
1863 {
1864 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
1865 }
1866 else if ( ch_power_rel < 20 )
1867 {
1868 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
1869 }
1870 else if ( ch_power_rel < 35.0f )
1871 {
1872 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
1873 }
1874 else
1875 {
1876 *strength = 100;
1877 }
1878 }
1879
1880 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1881 {
1882 *strength = 0;
1883 return TRUE;
1884 }
1885
1886 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
1887 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
1888
1889 return status;
1890 }
1891
1892 /****************************************************************************
1893 Subject: To get the DVT Signal quility
1894 Function: INTERN_DVBT_GetSignalQuality
1895 Parmeter: Quility
1896 Return: E_RESULT_SUCCESS
1897 E_RESULT_FAILURE
1898 Remark: Here we have 4 level range
1899 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1900 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1901 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1902 <4>.4th Range => Quality <10
1903 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1904 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1905 {
1906 float ber_sqi;
1907 float fber;
1908 float cn_rec = 0;
1909 float cn_nordig_p1 = 0;
1910 float cn_rel = 0;
1911
1912 MS_U8 status = true;
1913 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
1914 MS_U16 u16_tmp;
1915
1916 DBG_INTERN_DVBT_TIME(printf("INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
1917
1918 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
1919 {
1920
1921 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1922 {
1923 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
1924 }
1925 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
1926 if(fViterbiBerFiltered<= 0.0)
1927 {
1928 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
1929 {
1930 DBG_INTERN_DVBT(printf("GetPostViterbiBer Fail!\n"));
1931 return FALSE;
1932 }
1933 fViterbiBerFiltered = fber;
1934 }
1935 else
1936 {
1937 fber = fViterbiBerFiltered;
1938 }
1939
1940 if (fber > 1.0E-3)
1941 ber_sqi = 0.0;
1942 else if (fber > 8.5E-7)
1943 #ifdef MSOS_TYPE_LINUX
1944 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
1945 #else
1946 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
1947 #endif
1948 else
1949 ber_sqi = 100.0;
1950
1951 cn_rec = INTERN_DVBT_GetSNR();
1952
1953 if (cn_rec == -1) //get SNR return fail
1954 status = false;
1955
1956 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
1957 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
1958 tps_cnstl = 0xff;
1959 tps_cr = 0xff;
1960 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
1961 tps_cnstl = (MS_U8)u16_tmp&0x07;
1962 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
1963 tps_cr = (MS_U8)u16_tmp&0x07;
1964
1965 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
1966 {
1967 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
1968 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
1969 {
1970 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
1971 break;
1972 }
1973 }
1974
1975 // 0,5, snr offset
1976 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
1977
1978 // patch....
1979 // Noridg SQI,
1980 // 64QAM, CR34, GI14, SNR 22dB.
1981 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
1982 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
1983 {
1984 cn_rel += 1.5f;
1985 }
1986
1987 if (cn_rel < -7.0f)
1988 {
1989 *quality = 0;
1990 }
1991 else if (cn_rel < 3.0)
1992 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
1993 else
1994 *quality = (MS_U16)ber_sqi;
1995 }
1996 else
1997 {
1998 *quality = 0;
1999 }
2000
2001 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2002 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2003 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2004 return status;
2005 }
2006
2007 /****************************************************************************
2008 Subject: To get the Cell ID
2009 Function: INTERN_DVBT_Get_CELL_ID
2010 Parmeter: point to return parameter cell_id
2011
2012 Return: TRUE
2013 FALSE
2014 Remark:
2015 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2016 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2017 {
2018 MS_U8 status = true;
2019 MS_U8 value1=0;
2020 MS_U8 value2=0;
2021
2022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2024
2025 *cell_id = ((MS_U16)value1<<8)|value2;
2026 return status;
2027 }
2028 /*
2029 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2030 {
2031 #define SQI_LOOP_NUM 50
2032 U8 inn = 0;
2033 WORD sqi = 0;
2034 WORD ave_sqi = 0;
2035 WORD ave_num = 0;
2036 while(inn++<SQI_LOOP_NUM)
2037 {
2038 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2039 {
2040 printf("[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2041 ave_sqi+=sqi;
2042 ave_num++;
2043 }
2044 MsOS_DelayTask(50);
2045 }
2046
2047 if(ave_num != 0 )
2048 *quality = ave_sqi/ave_num;
2049
2050 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2051 }
2052 */
2053 /****************************************************************************
2054 Subject: To get the DVBT Carrier Freq Offset
2055 Function: INTERN_DVBT_Get_FreqOffset
2056 Parmeter: Frequency offset (in KHz), bandwidth
2057 Return: E_RESULT_SUCCESS
2058 E_RESULT_FAILURE
2059 Remark:
2060 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2061 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2062 {
2063 float N, FreqB;
2064 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2065 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2066 MS_U8 reg_frz=0, reg=0;
2067 MS_U8 status;
2068
2069 FreqB = (float)u8BW * 8 / 7;
2070
2071 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2072
2073 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2074
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2076 RegCfoTd = reg;
2077
2078 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2079 RegCfoTd = (RegCfoTd << 8)|reg;
2080
2081 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2082 RegCfoTd = (RegCfoTd << 8)|reg;
2083
2084 FreqCfoTd = (float)RegCfoTd;
2085
2086 if (RegCfoTd & 0x800000)
2087 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2088
2089 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2090
2091 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2092
2093 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2094 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2095
2096 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2097
2098 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2099 RegCfoFd = reg;
2100
2101 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2102 RegCfoFd = (RegCfoFd << 8)|reg;
2103
2104 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2105 RegCfoFd = (RegCfoFd << 8)|reg;
2106
2107 FreqCfoFd = (float)RegCfoFd;
2108
2109 if (RegCfoFd & 0x800000)
2110 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2111
2112 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2113
2114 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2115 RegIcfo = reg & 0x07;
2116
2117 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2118 RegIcfo = (RegIcfo << 8)|reg;
2119
2120 FreqIcfo = (float)RegIcfo;
2121
2122 if (RegIcfo & 0x400)
2123 FreqIcfo = FreqIcfo - (float)0x800;
2124
2125 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2126 reg = reg & 0x30;
2127
2128 switch (reg)
2129 {
2130 case 0x00: N = 2048; break;
2131 case 0x20: N = 4096; break;
2132 case 0x10:
2133 default: N = 8192; break;
2134 }
2135
2136 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2137 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2138 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2139 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2140 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2141 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2142 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2143 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2144 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2145 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2146
2147 if (status == TRUE)
2148 return TRUE;
2149 else
2150 return FALSE;
2151 }
2152
2153
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2154 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2155 {
2156
2157 bPowerOn = bPowerOn;
2158 }
2159
INTERN_DVBT_Power_Save(void)2160 MS_BOOL INTERN_DVBT_Power_Save(void)
2161 {
2162
2163 return TRUE;
2164 }
2165
2166 /****************************************************************************
2167 Subject: To get the DVBT constellation parameter
2168 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2169 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2170 Return: TRUE
2171 FALSE
2172 Remark: The TPS parameters will be available after TPS lock
2173 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2174 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2175 {
2176 MS_U8 tps_param;
2177
2178 //@@++ Arki 20100125
2179 if (eSignalType == TS_MODUL_MODE)
2180 {
2181 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2182 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2183 }
2184
2185 if (eSignalType == TS_CODE_RATE)
2186 {
2187 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2188 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2189 }
2190
2191 if (eSignalType == TS_GUARD_INTERVAL)
2192 {
2193 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2194 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2195 }
2196
2197 if (eSignalType == TS_FFX_VALUE)
2198 {
2199 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2200 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2201 }
2202 //@@-- Arki 20100125
2203 return TRUE;
2204 }
2205
INTERN_DVBT_Version(MS_U16 * ver)2206 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2207 {
2208
2209 MS_U8 status = true;
2210 MS_U8 tmp = 0;
2211 MS_U16 u16_INTERN_DVBT_Version;
2212
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2214 u16_INTERN_DVBT_Version = tmp;
2215 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2216 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2217 *ver = u16_INTERN_DVBT_Version;
2218
2219 return status;
2220 }
2221
INTERN_DVBT_Version_minor(MS_U8 * ver2)2222 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2223 {
2224
2225 MS_U8 status = true;
2226
2227 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2228
2229 return status;
2230 }
2231
2232
INTERN_DVBT_Show_Demod_Version(void)2233 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2234 {
2235
2236 MS_BOOL status = true;
2237 MS_U16 u16_INTERN_DVBT_Version;
2238 MS_U8 u8_minor_ver = 0;
2239
2240 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2241 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2242 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2243
2244 return status;
2245 }
2246
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2247 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2248 {
2249 MS_U8 u8_index = 0;
2250 MS_BOOL bRet = false;
2251
2252 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2253 {
2254 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2255 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2256 {
2257 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2258 bRet = true;
2259 break;
2260 }
2261 else
2262 {
2263 u8_index++;
2264 }
2265 }
2266 return bRet;
2267 }
2268
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2269 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2270 {
2271 MS_U8 u8_index = 0;
2272 MS_BOOL bRet = false;
2273
2274 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2275 {
2276 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2277 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2278 {
2279 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2280 bRet = true;
2281 break;
2282 }
2283 else
2284 {
2285 u8_index++;
2286 }
2287 }
2288 return bRet;
2289 }
2290
2291
2292 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2293 void INTERN_DVBT_get_demod_state(MS_U8* state)
2294 {
2295 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2296 return;
2297 }
2298
INTERN_DVBT_Show_ChannelLength(void)2299 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2300 {
2301 MS_U8 status = true;
2302 MS_U8 tmp = 0;
2303 MS_U16 len = 0;
2304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2305 len = tmp;
2306 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2307 len = (len<<8)|tmp;
2308 printf("[dvbt]Hw_channel=%d\n",len);
2309 return status;
2310 }
2311
INTERN_DVBT_Show_SW_ChannelLength(void)2312 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2313 {
2314 MS_U8 status = true;
2315 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2316 MS_U16 sw_len = 0;
2317 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2318 sw_len = tmp;
2319 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2320 sw_len = (sw_len<<8)|tmp;
2321 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2322 peak_num = tmp;
2323 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2324 insideGI = tmp&0x01;
2325 stoptracking = (tmp&0x02)>>1;
2326 flag_short_echo = (tmp&0x0C)>>2;
2327 fsa_mode = (tmp&0x30)>>4;
2328
2329 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2330 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2331
2332 return status;
2333 }
2334
INTERN_DVBT_Show_ACI_CI(void)2335 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2336 {
2337
2338 #define BIT4 0x10
2339 MS_U8 status = true;
2340 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2341
2342 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2343 digACI = (tmp&BIT4)>>4;
2344
2345 // get flag_CI
2346 // 0: No interference
2347 // 1: CCI
2348 // 2: in-band ACI
2349 // 3: N+1 ACI
2350 // flag_ci = (tmp&0xc0)>>6;
2351 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2352 flag_CI = (tmp&0xC0)>>6;
2353 td_coef = (tmp&0x0C)>>2;
2354
2355 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2356
2357 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2358
2359 return status;
2360 }
2361
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2362 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2363 {
2364 MS_U8 status = true;
2365 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2366 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2367 fd = tmp;
2368 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2369 ch_len = tmp;
2370 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2371 snr_sel = (tmp>>4)&0x03;
2372 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2373 pertone_num = tmp;
2374
2375 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2376
2377 return status;
2378 }
2379
INTERN_DVBT_Get_CFO(void)2380 MS_BOOL INTERN_DVBT_Get_CFO(void)
2381 {
2382
2383 float N = 0, FreqB = 0;
2384 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2385 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2386 MS_U8 reg_frz = 0, reg = 0;
2387 MS_U8 status = 0;
2388 MS_U8 u8BW = 8;
2389
2390 FreqB = (float)u8BW * 8 / 7;
2391
2392 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2393
2394 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2395
2396 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2397 RegCfoTd = reg;
2398
2399 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2400 RegCfoTd = (RegCfoTd << 8)|reg;
2401
2402 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2403 RegCfoTd = (RegCfoTd << 8)|reg;
2404
2405 FreqCfoTd = (float)RegCfoTd;
2406
2407 if (RegCfoTd & 0x800000)
2408 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2409
2410 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2411
2412 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2413
2414 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2415 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2416
2417 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2418
2419 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2420 RegCfoFd = reg;
2421
2422 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2423 RegCfoFd = (RegCfoFd << 8)|reg;
2424
2425 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2426 RegCfoFd = (RegCfoFd << 8)|reg;
2427
2428 FreqCfoFd = (float)RegCfoFd;
2429
2430 if (RegCfoFd & 0x800000)
2431 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2432
2433 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2434
2435 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2436 RegIcfo = reg & 0x07;
2437
2438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2439 RegIcfo = (RegIcfo << 8)|reg;
2440
2441 FreqIcfo = (float)RegIcfo;
2442
2443 if (RegIcfo & 0x400)
2444 FreqIcfo = FreqIcfo - (float)0x800;
2445
2446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2447 reg = reg & 0x30;
2448
2449 switch (reg)
2450 {
2451 case 0x00: N = 2048; break;
2452 case 0x20: N = 4096; break;
2453 case 0x10:
2454 default: N = 8192; break;
2455 }
2456
2457 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2458 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2459 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2460 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2461 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2462
2463 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2464
2465 return status;
2466
2467 }
INTERN_DVBT_Get_SFO(void)2468 MS_BOOL INTERN_DVBT_Get_SFO(void)
2469 {
2470 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2471 MS_BOOL status = true;
2472 MS_U8 reg = 0;
2473 float FreqB = 9.143, FreqS = 45.473; //20.48
2474 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2475 float sfo_value = 0;
2476
2477 // get Reg_TDP_SFO,
2478 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2479 Reg_TDP_SFO = reg;
2480 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2481 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2482 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2483 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2484
2485 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2486
2487 // get Reg_FDP_SFO,
2488 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2489 Reg_FDP_SFO = reg;
2490 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2491 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2492 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2493 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2494
2495 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2496
2497 // get Reg_FSA_SFO,
2498 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2499 Reg_FSA_SFO = reg;
2500 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2501 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2503 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2504
2505 // get Reg_FSA_IN,
2506 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2507 Reg_FSA_IN = reg;
2508 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2509 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2510 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2511
2512 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2513 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2514
2515 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2516 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2517 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2518
2519
2520 return status;
2521 }
2522
INTERN_DVBT_Get_SYA_status(void)2523 void INTERN_DVBT_Get_SYA_status(void)
2524 {
2525 MS_U8 status = true;
2526 MS_U8 sya_k = 0,reg = 0;
2527 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2528
2529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2530 sya_k = reg;
2531
2532 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2533 sya_th = reg;
2534 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2535 sya_th = (sya_th<<8)|reg;
2536
2537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2538 sya_offset = reg;
2539 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2540 sya_offset = (sya_offset<<8)|reg;
2541
2542 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2543 len_m = reg;
2544 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2545 len_m = (len_m<<8)|reg;
2546
2547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2548 len_b = reg;
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2550 len_b = (len_b<<8)|reg;
2551
2552
2553 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2554 len_a = reg;
2555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2556 len_a = (len_a<<8)|reg;
2557
2558
2559 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2560 tracking_reg = reg;
2561
2562
2563 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2564 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2565
2566 return;
2567 }
2568
INTERN_DVBT_Get_cci_status(void)2569 void INTERN_DVBT_Get_cci_status(void)
2570 {
2571 MS_U8 status = true;
2572 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2573
2574 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2575 cci_fsweep = reg;
2576
2577 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2578 cci_kp = reg;
2579
2580 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2581
2582 return;
2583 }
2584
INTERN_DVBT_Show_PRESFO_Info(void)2585 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2586 {
2587 MS_U8 tmp = 0;
2588 MS_BOOL status = TRUE;
2589 printf("\n[SFO]");
2590 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2591 printf("[%x]",tmp);
2592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2593 printf("[%x]",tmp);
2594 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2595 printf("[%x]",tmp);
2596 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2597 printf("[%x]",tmp);
2598 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2599 printf("[%x]",tmp);
2600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2601 printf("[%x]",tmp);
2602 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2603 printf("[%x]",tmp);
2604 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2605 printf("[%x][End]",tmp);
2606
2607 return status;
2608 }
2609
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2610 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2611 {
2612 MS_BOOL status = true;
2613
2614 *locktime = 0xffff;
2615 printf("[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2616
2617 status = false;
2618 return status;
2619 }
2620
2621
INTERN_DVBT_Show_Lock_Time_Info(void)2622 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2623 {
2624 MS_U16 locktime = 0;
2625 MS_BOOL status = TRUE;
2626 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2627 printf("[DVBT]lock_time = %d ms\n",locktime);
2628 return status;
2629 }
2630
INTERN_DVBT_Show_BER_Info(void)2631 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2632 {
2633 MS_U8 tmp = 0;
2634 MS_BOOL status = TRUE;
2635 printf("\n[BER]");
2636 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2637 printf("[%x,",tmp);
2638 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2639 printf("%x]",tmp);
2640 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2641 printf("[%x,",tmp);
2642 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2643 printf("%x]",tmp);
2644 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2645 printf("[%x,",tmp);
2646 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2647 printf("%x][End]",tmp);
2648
2649 return status;
2650
2651 }
2652
2653
INTERN_DVBT_Show_AGC_Info(void)2654 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2655 {
2656 MS_U8 tmp = 0;
2657 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2658 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2659 MS_U16 if_agc_err = 0;
2660 MS_BOOL status = TRUE;
2661 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2662
2663 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2664 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2666 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2667 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2668 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2669
2670
2671 // select IF gain to read
2672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2673 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2674
2675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2676 if_agc_gain = tmp;
2677 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2678 if_agc_gain = (if_agc_gain<<8)|tmp;
2679
2680
2681 // select d1 gain to read.
2682 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2683 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2684
2685 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2686 d1_gain = tmp;
2687 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2688 d1_gain = (d1_gain<<8)|tmp;
2689
2690 // select d2 gain to read.
2691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2692 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2693
2694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2695 d2_gain = tmp;
2696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
2697 d2_gain = (d2_gain<<8)|tmp;
2698
2699 // select IF gain err to read
2700 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2701 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
2702
2703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2704 if_agc_err = tmp;
2705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2706 if_agc_err = (if_agc_err<<8)|tmp;
2707
2708 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
2709 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
2710 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
2711
2712
2713
2714 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2715 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2716
2717 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2718 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
2719
2720 return status;
2721
2722 }
2723
INTERN_DVBT_Show_WIN_Info(void)2724 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
2725 {
2726 MS_U8 tmp = 0;
2727 MS_U8 trigger = 0;
2728 MS_U16 win_len = 0;
2729
2730 MS_BOOL status = TRUE;
2731
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
2733 win_len = tmp;
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
2735 win_len = (win_len<<8)|tmp;
2736
2737 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
2738
2739 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
2740
2741 return status;
2742 }
2743
INTERN_DVBT_Show_td_coeff(void)2744 void INTERN_DVBT_Show_td_coeff(void)
2745 {
2746 MS_U8 status = true;
2747 MS_U8 w1 = 0,w2 = 0,reg = 0;
2748
2749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
2750 w1 = reg;
2751
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
2753 w2 = reg;
2754
2755 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
2756
2757 return;
2758 }
2759
2760 /********************************************************
2761 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
2762 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
2763 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2764 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2765 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
2766 * FFT ( b14) : 0~1 => 2K, 8K
2767 ********************************/
INTERN_DVBT_Show_Modulation_info(void)2768 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
2769 {
2770 MS_U16 tps_info;
2771
2772 // printf("[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
2773
2774 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
2775 {
2776 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
2777 MS_U8 constel = tps_info&0x0007;
2778 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
2779 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
2780 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
2781 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
2782
2783 printf("tps=0x%x ",tps_info);
2784
2785 switch(fft)
2786 {
2787 case 0:
2788 printf("mode = 2K,");
2789 break;
2790 case 1:
2791 printf("mode = 8K,");
2792 break;
2793 default:
2794 printf("mode = unknow,");
2795 break;
2796 }
2797 switch(constel)
2798 {
2799 case 0:
2800 printf(" QPSK, ");
2801 break;
2802 case 1:
2803 printf("16QAM, ");
2804 break;
2805 case 2:
2806 printf("64QAM, ");
2807 break;
2808 default:
2809 printf("unknow QAM, ");
2810 break;
2811 }
2812 switch(gi)
2813 {
2814 case 0:
2815 printf("GI=1/32, ");
2816 break;
2817 case 1:
2818 printf("GI=1/16, ");
2819 break;
2820 case 2:
2821 printf("GI= 1/8, ");
2822 break;
2823 case 3:
2824 printf("GI= 1/4, ");
2825 break;
2826 default:
2827 printf("unknow GI, ");
2828 break;
2829 }
2830
2831 switch(hp_cr)
2832 {
2833 case 0:
2834 printf("HP_CR=1/2, ");
2835 break;
2836 case 1:
2837 printf("HP_CR=2/3, ");
2838 break;
2839 case 2:
2840 printf("HP_CR=3/4, ");
2841 break;
2842 case 3:
2843 printf("HP_CR=5/6, ");
2844 break;
2845 case 4:
2846 printf("HP_CR=7/8, ");
2847 break;
2848 default:
2849 printf("unknow hp_cr, ");
2850 break;
2851 }
2852
2853 switch(lp_cr)
2854 {
2855 case 0:
2856 printf("LP_CR=1/2, ");
2857 break;
2858 case 1:
2859 printf("LP_CR=2/3, ");
2860 break;
2861 case 2:
2862 printf("LP_CR=3/4, ");
2863 break;
2864 case 3:
2865 printf("LP_CR=5/6, ");
2866 break;
2867 case 4:
2868 printf("LP_CR=7/8, ");
2869 break;
2870 default:
2871 printf("unknow lp_cr, ");
2872 break;
2873 }
2874
2875 printf(" Hiearchy=0x%x\n",hiearchy);
2876
2877 // printf("\n");
2878 return TRUE;
2879 }
2880 else
2881 {
2882 printf("INVALID\n");
2883 return FALSE;
2884 }
2885 }
2886
2887
2888
2889
INTERN_DVBT_Show_BER_PacketErr(void)2890 void INTERN_DVBT_Show_BER_PacketErr(void)
2891 {
2892 float f_ber = 0;
2893 MS_U16 packetErr = 0;
2894 INTERN_DVBT_GetPostViterbiBer(&f_ber);
2895 INTERN_DVBT_GetPacketErr(&packetErr);
2896
2897 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
2898 return;
2899 }
2900
INTERN_DVBT_Show_Lock_Info(void)2901 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
2902 {
2903
2904 printf("[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
2905 return false;
2906 }
2907
2908
INTERN_DVBT_Show_Demod_Info(void)2909 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
2910 {
2911 MS_U8 demod_state = 0;
2912 MS_BOOL status = true;
2913 static MS_U8 counter = 0;
2914
2915 INTERN_DVBT_get_demod_state(&demod_state);
2916
2917 printf("==========[dvbt]state=%d\n",demod_state);
2918 if (demod_state < 5)
2919 {
2920 INTERN_DVBT_Show_Demod_Version();
2921 INTERN_DVBT_Show_AGC_Info();
2922 INTERN_DVBT_Show_ACI_CI();
2923 }
2924 else if(demod_state < 8)
2925 {
2926 INTERN_DVBT_Show_Demod_Version();
2927 INTERN_DVBT_Show_AGC_Info();
2928 INTERN_DVBT_Show_ACI_CI();
2929 INTERN_DVBT_Show_ChannelLength();
2930 INTERN_DVBT_Get_CFO();
2931 INTERN_DVBT_Get_SFO();
2932 INTERN_DVBT_Show_td_coeff();
2933 }
2934 else if(demod_state < 11)
2935 {
2936 INTERN_DVBT_Show_Demod_Version();
2937 INTERN_DVBT_Show_AGC_Info();
2938 INTERN_DVBT_Show_ACI_CI();
2939 INTERN_DVBT_Show_ChannelLength();
2940 INTERN_DVBT_Get_CFO();
2941 INTERN_DVBT_Get_SFO();
2942 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
2943 INTERN_DVBT_Get_SYA_status();
2944 INTERN_DVBT_Show_td_coeff();
2945 }
2946 else if((demod_state == 11) && ((counter%4) == 0))
2947 {
2948 INTERN_DVBT_Show_Demod_Version();
2949 INTERN_DVBT_Show_AGC_Info();
2950 INTERN_DVBT_Show_ACI_CI();
2951 INTERN_DVBT_Show_ChannelLength();
2952 INTERN_DVBT_Get_CFO();
2953 INTERN_DVBT_Get_SFO();
2954 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
2955 INTERN_DVBT_Get_SYA_status();
2956 INTERN_DVBT_Show_td_coeff();
2957 INTERN_DVBT_Show_Modulation_info();
2958 INTERN_DVBT_Show_BER_PacketErr();
2959 }
2960 else
2961 status = false;
2962
2963 printf("===========================\n");
2964 counter++;
2965
2966 return status;
2967 }
2968 #endif
2969
2970