1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ISDBT.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ISDBT_CHIP_EULER 0x00
112 #define DMD_ISDBT_CHIP_NUGGET 0x01
113 #define DMD_ISDBT_CHIP_KAPPA 0x02
114 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
115 #define DMD_ISDBT_CHIP_NAPOLI 0x04
116 #define DMD_ISDBT_CHIP_MONACO 0x05
117 #define DMD_ISDBT_CHIP_MIAMI 0x06
118 #define DMD_ISDBT_CHIP_MUJI 0x07
119 #define DMD_ISDBT_CHIP_MUNICH 0x08
120 #define DMD_ISDBT_CHIP_MANHATTAN 0x09
121 #define DMD_ISDBT_CHIP_MULAN 0x0A
122 #define DMD_ISDBT_CHIP_MESSI 0x0B
123 #define DMD_ISDBT_CHIP_MASERATI 0x0C
124 #define DMD_ISDBT_CHIP_KIWI 0x0D
125 #define DMD_ISDBT_CHIP_MACAN 0x0E
126 #define DMD_ISDBT_CHIP_MUSTANG 0x0F
127 #define DMD_ISDBT_CHIP_MAXIM 0x10
128 #define DMD_ISDBT_CHIP_KENTUCKY 0x11
129 #define DMD_ISDBT_CHIP_MAINZ 0x12
130 #if defined(CHIP_EULER)
131 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
132 #elif defined(CHIP_NUGGET)
133 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
134 #elif defined(CHIP_KAPPA)
135 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
136 #elif defined(CHIP_EINSTEIN)
137 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
138 #elif defined(CHIP_NAPOLI)
139 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
140 #elif defined(CHIP_MIAMI)
141 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
142 #elif defined(CHIP_MUJI)
143 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
144 #elif defined(CHIP_MUNICH)
145 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUNICH
146 #elif defined(CHIP_MANHATTAN)
147 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MANHATTAN
148 #elif defined(CHIP_MULAN)
149 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MULAN
150 #elif defined(CHIP_MESSI)
151 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MESSI
152 #elif defined(CHIP_MASERATI)
153 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MASERATI
154 #elif defined(CHIP_KIWI)
155 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KIWI
156 #elif defined(CHIP_MACAN)
157 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MACAN
158 #elif defined(CHIP_MUSTANG)
159 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUSTANG
160 #elif defined(CHIP_MAXIM)
161 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAXIM
162 #elif defined(CHIP_K5TN)
163 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KENTUCKY
164 #elif defined(CHIP_MAINZ)
165 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAINZ
166 #else
167 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
168 #endif
169
170 //-------------------------------------------------------------------------------------------------
171 // Local Defines
172 //-------------------------------------------------------------------------------------------------
173 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN)
174 #define DMD_ISDBT_TBVA_EN 1
175 #else
176 #define DMD_ISDBT_TBVA_EN 0
177 #endif
178 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr) ) )
179 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr), val) )
180
181 #define HAL_INTERN_ISDBT_DBINFO(y) //y
182 #ifndef MBRegBase
183 #define MBRegBase 0x112600UL
184 #endif
185 #ifndef MBRegBase_DMD1
186 #define MBRegBase_DMD1 0x112400UL
187 #endif
188 #ifndef DMDMcuBase
189 #define DMDMcuBase 0x103480UL
190 #endif
191
192 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_MESSI) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_KIWI)
193 #define REG_ISDBT_LOCK_STATUS 0x11F5
194 #define ISDBT_TDP_REG_BASE 0x1400
195 #define ISDBT_FDP_REG_BASE 0x1500
196 #define ISDBT_FDPEXT_REG_BASE 0x1600
197 #define ISDBT_OUTER_REG_BASE 0x1700
198 #else
199 #define REG_ISDBT_LOCK_STATUS 0x36F5
200 #define ISDBT_TDP_REG_BASE 0x3700
201 #define ISDBT_FDP_REG_BASE 0x3800
202 #define ISDBT_FDPEXT_REG_BASE 0x3900
203 #define ISDBT_OUTER_REG_BASE 0x3A00
204 #endif
205
206 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
207 #define ISDBT_MIU_CLIENTW_ADDR 0xF5
208 #define ISDBT_MIU_CLIENTR_ADDR 0xF5
209 #define ISDBT_MIU_CLIENTW_MASK 0x87
210 #define ISDBT_MIU_CLIENTR_MASK 0x87
211 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x01
212 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x02
213 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO) || \
214 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN) || \
215 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
216 #define ISDBT_MIU_CLIENTW_ADDR 0xF2
217 #define ISDBT_MIU_CLIENTR_ADDR 0xF2
218 #define ISDBT_MIU_CLIENTW_MASK 0x66
219 #define ISDBT_MIU_CLIENTR_MASK 0x66
220 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
221 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x04
222 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
223 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
224 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
225 #define ISDBT_MIU_CLIENTW_MASK 0x47
226 #define ISDBT_MIU_CLIENTR_MASK 0x46
227 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
228 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
229 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
230 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
231 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
232 #define ISDBT_MIU_CLIENTW_MASK 0x47
233 #define ISDBT_MIU_CLIENTR_MASK 0x46
234 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x04
235 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
236 #endif
237 //-------------------------------------------------------------------------------------------------
238 // Local Variables
239 //-------------------------------------------------------------------------------------------------
240
241 const MS_U8 INTERN_ISDBT_table[] = {
242 #include "DMD_INTERN_ISDBT.dat"
243 };
244
245 #ifndef UTPA2
246 static const float _LogApproxTableX[80] =
247 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
248 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
249 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
250 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
251 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
252 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
253 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
254 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
255 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
256 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
257 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
258 456767058.24, 593797175.72, 771936328.43, 1003517226.96
259 };
260
261 static const float _LogApproxTableY[80] =
262 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
263 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
264 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
265 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
266 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
267 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
268 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
269 };
270 #endif
271
272 //-------------------------------------------------------------------------------------------------
273 // Global Variables
274 //-------------------------------------------------------------------------------------------------
275
276 extern MS_U8 u8DMD_ISDBT_DMD_ID;
277
278 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
279
280 //-------------------------------------------------------------------------------------------------
281 // Local Functions
282 //-------------------------------------------------------------------------------------------------
283 #ifndef UTPA2
284
285 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)286 static float Log10Approx(float flt_x)
287 {
288 MS_U8 indx = 0;
289
290 do {
291 if (flt_x < _LogApproxTableX[indx])
292 break;
293 indx++;
294 }while (indx < 79); //stop at indx = 80
295
296 return _LogApproxTableY[indx];
297 }
298 #endif
299
_CALCULATE_SQI(float fber)300 static MS_U16 _CALCULATE_SQI(float fber)
301 {
302 float flog_ber;
303 MS_U16 u16SQI;
304
305 #ifdef MSOS_TYPE_LINUX
306 flog_ber = (float)log10((double)fber);
307 #else
308 if (fber != 0.0)
309 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
310 else
311 flog_ber = -8.0;//when fber=0 means u16SQI=100
312 #endif
313
314 //printf("dan fber = %f\n", fber);
315 //printf("dan flog_ber = %f\n", flog_ber);
316 // Part 2: transfer ber value to u16SQI value.
317 if (flog_ber <= ( - 7.0))
318 {
319 u16SQI = 100; //*quality = 100;
320 }
321 else if (flog_ber < -6.0)
322 {
323 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
324 }
325 else if (flog_ber < -5.5)
326 {
327 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
328 }
329 else if (flog_ber < -5.0)
330 {
331 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
332 }
333 else if (flog_ber < -4.5)
334 {
335 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
336 }
337 else if (flog_ber < -4.0)
338 {
339 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
340 }
341 else if (flog_ber < -3.5)
342 {
343 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
344 }
345 else if (flog_ber < -3.0)
346 {
347 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
348 }
349 else if (flog_ber < -2.5)
350 {
351 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
352 }
353 else if (flog_ber < -2.0)
354 {
355 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
356 }
357 else
358 {
359 u16SQI = 0;
360 }
361
362 return u16SQI;
363 }
364 #endif
365
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)366 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
367 {
368 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
369 }
370
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)371 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
372 {
373 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
374 }
375
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)376 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
377 {
378 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
379 }
380
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)381 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
382 {
383 MS_U8 u8CheckCount;
384 MS_U8 u8CheckFlag = 0xFF;
385 MS_U32 u32MBRegBase = MBRegBase;
386
387 if (u8DMD_ISDBT_DMD_ID == 0)
388 u32MBRegBase = MBRegBase;
389 else if (u8DMD_ISDBT_DMD_ID == 1)
390 u32MBRegBase = MBRegBase_DMD1;
391
392 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
393 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
394 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
395 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
396
397 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
398 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
399
400 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
401 {
402 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
403 if ((u8CheckFlag&0x01)==0)
404 break;
405 MsOS_DelayTask(1);
406 }
407
408 if (u8CheckFlag&0x01)
409 {
410 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
411 return FALSE;
412 }
413
414 return TRUE;
415 }
416
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)417 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
418 {
419 MS_U8 u8CheckCount;
420 MS_U8 u8CheckFlag = 0xFF;
421 MS_U32 u32MBRegBase = MBRegBase;
422
423 if (u8DMD_ISDBT_DMD_ID == 0)
424 u32MBRegBase = MBRegBase;
425 else if (u8DMD_ISDBT_DMD_ID == 1)
426 u32MBRegBase = MBRegBase_DMD1;
427
428 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
429 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
430 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
431
432 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
433 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
434
435 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
436 {
437 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
438 if ((u8CheckFlag&0x02)==0)
439 {
440 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
441 break;
442 }
443 MsOS_DelayTask(1);
444 }
445
446 if (u8CheckFlag&0x02)
447 {
448 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
449 return FALSE;
450 }
451
452 return TRUE;
453 }
454
455
456
457 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)458 static void _HAL_INTERN_ISDBT_InitClk(void)
459 {
460 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EULER--------------\n"));
461
462 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
463
464 // Init by HKMCU
465 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
466 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
467 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
468 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
469 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
470 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
472
473 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
475 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
483 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
484 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
485 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
489 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
490 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
492 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
493 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
494 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
495 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
496
497 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
498 }
499 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)500 static void _HAL_INTERN_ISDBT_InitClk(void)
501 {
502 MS_U8 u8Val = 0;
503
504 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n"));
505
506 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
507
508 // Init by HKMCU
509 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
510 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
511 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
512 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
513 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
514 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
515 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
516 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
517 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
518
519 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
520 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
521 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
522 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
523 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
530 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
533 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
534 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
535 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
536 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
537 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
539 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
540 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
541 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
542 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
543
544 u8Val = _HAL_DMD_RIU_ReadByte(0x1006F5);
545 _HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
546
547 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
548 }
549 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)550 static void _HAL_INTERN_ISDBT_InitClk(void)
551 {
552 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n"));
553
554 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
555
556 // Init by HKMCU
557 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
558 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
559 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
560 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
561 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
562 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
563 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
564
565 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
566 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
567 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
568 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
569 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
570 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
571 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
573 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
574 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
575 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
576 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
581 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
582 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
583 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
584 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
585 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
586 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
587 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
588
589 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
590 }
591 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)592 static void _HAL_INTERN_ISDBT_InitClk(void)
593 {
594 MS_U8 u8Val = 0;
595
596 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n"));
597
598 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
599
600 // Init by HKMCU
601 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
602 u8Val &= ~0x01;
603 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
604
605 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
606 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
607 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
608 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
609 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
610 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
611 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
612 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
613 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
614
615 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
616 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
617 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
618 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
619 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
620 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
624 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
625 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
626 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
627 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
630 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
632 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
633 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
634 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
635 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
636 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
637 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
638 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
639
640 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
641 }
642 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)643 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
644 {
645 MS_U8 u8Val = 0;
646
647 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n"));
648
649 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
650
651 // Init by HKMCU
652 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
653 u8Val &= ~0x01;
654 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
655
656 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
657 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
658 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
659 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
660 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
661 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
662 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
663 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
665
666 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
667 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
671 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
673 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
674 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
675 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
676 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
677 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
678 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
679 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
680 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
682 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
683 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
684 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
685 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
686 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
687 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
688 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
689 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
690
691 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
692 }
693 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)694 static void _HAL_INTERN_ISDBT_InitClk(void)
695 {
696 MS_U8 u8Val = 0;
697
698 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n"));
699
700 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
701
702 // Init by HKMCU
703 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
704 u8Val &= ~0x01;
705 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
706
707 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
708 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
709 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
710 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
711 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
712 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
713 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
715
716 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
717 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
719 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
720 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
721 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
723 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
724 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
725 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
727 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
732 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
733 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
735 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
736 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
737 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
738 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
739 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
740 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
741 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
742 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
743 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
744
745 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
746 }
747 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)748 static void _HAL_INTERN_ISDBT_InitClk(void)
749 {
750 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n"));
751
752 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
753
754 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
755 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
756 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
757 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
758 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
759 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
760 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
761 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
762
763 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
764 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
765 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
768 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
769 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
771 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
772 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
773 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
774 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
775 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
776 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
777 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
779 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
780 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
781 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
782 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
783 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
784 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
785 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
786 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
787 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
788 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
789 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
790 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
791
792 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
793 }
794 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)795 static void _HAL_INTERN_ISDBT_InitClk(void)
796 {
797 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n"));
798
799 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
800
801 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
802 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
803 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
804 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
805 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
806 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
807 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
809 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
810
811 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
812 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
813 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
814 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
815 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
816 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
818 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
819 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
822 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
823 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
824 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
828 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
829 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
830 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
831 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
832 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
833 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
834 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
835 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
836 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
837 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
838 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
839 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
840 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
841 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
842 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
843 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
844 _HAL_DMD_RIU_WriteByte(0x112091, 0x46);
845 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
846
847 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
848 }
849 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
_HAL_INTERN_ISDBT_InitClk(void)850 static void _HAL_INTERN_ISDBT_InitClk(void)
851 {
852 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUNICH--------------\n"));
853
854 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
855
856 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
857 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
858 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
859 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
860 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
861 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
862 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
863 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
864
865 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
866 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
867 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
868 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
869 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
870 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
871 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
872 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
873 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
874 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
875 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
876 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
877 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
879 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
880 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
881 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
882 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
883 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
884 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
885 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
886 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
887 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
888 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
889 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
890 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
891 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
892 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
893
894 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
895 }
896 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN)
_HAL_INTERN_ISDBT_InitClk(void)897 static void _HAL_INTERN_ISDBT_InitClk(void)
898 {
899 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MANHATTAN--------------\n"));
900
901 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
902
903 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
904 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
905 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
906 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
907 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
908 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
909 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
910 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
911 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
912
913 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
914 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
915 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
916 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
917 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
918 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
919 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
920 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
921 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
923 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
924 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
925 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
926 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
927 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
928 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
929 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
930 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
931 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
932 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
933 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
934 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
935 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
936 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
937 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
938 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
939 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
940 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
941 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
942 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
943 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
944 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
945 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
946 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
947 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
948 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
949 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
950 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
951 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
952 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
953 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
954
955 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
956 }
957 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MULAN)
_HAL_INTERN_ISDBT_InitClk(void)958 static void _HAL_INTERN_ISDBT_InitClk(void)
959 {
960 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MULAN--------------\n"));
961
962 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
963
964 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
965 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
966 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
967 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
968 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
969 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
970 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
971 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
972 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //reset ts divider
973
974 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
975 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
976 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
977 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
978 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
979 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
980 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
981 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
982 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
983 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
984 _HAL_DMD_RIU_WriteByte(0x111f24, 0x05);
985 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
986 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
987 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
988 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
989 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
990 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
991 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
992 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
993 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
994 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
995 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
996 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
997 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
998 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
999 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1000 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1001 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1002 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1003 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1004 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1005 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1006 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1007 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1008 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1009 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1010 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1011 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1012 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1013 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1014 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1015 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1016 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1017 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x88);
1018 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1019 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1020 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1021 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1022 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1023 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1024
1025 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //reset ts divider
1026
1027 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1028 }
1029 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAINZ)
_HAL_INTERN_ISDBT_InitClk(void)1030 static void _HAL_INTERN_ISDBT_InitClk(void)
1031 {
1032 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
1033 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MESSI--------------\n"));
1034 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAINZ)
1035 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MAINZ--------------\n"));
1036 #endif
1037
1038 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1039
1040 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1041 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1042 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1043 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1044 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1045 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1046 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1047 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1048 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1049
1050 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1051 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
1052 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1053 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1055 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1056 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1057 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1058 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1059 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1061 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1062 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1064 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1065 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1066 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
1067 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1068 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
1069 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1070 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1071 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
1072 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
1073 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
1074 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
1075 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
1076 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
1077 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
1078 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
1079 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1080 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
1081 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x0C);
1082 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
1083 _HAL_DMD_RIU_WriteByte(0x111f51, 0x48);
1084 _HAL_DMD_RIU_WriteByte(0x111f50, 0x44);
1085 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
1086 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
1087 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
1088 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
1089 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
1090 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
1091 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
1092 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
1093 _HAL_DMD_RIU_WriteByte(0x111f89, 0x44);
1094 _HAL_DMD_RIU_WriteByte(0x111f88, 0x44);
1095 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1096 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x44);
1097 _HAL_DMD_RIU_WriteByte(0x111f8d, 0x18);
1098 _HAL_DMD_RIU_WriteByte(0x111f8c, 0x44);
1099 _HAL_DMD_RIU_WriteByte(0x111f8f, 0x00);
1100 _HAL_DMD_RIU_WriteByte(0x111f8e, 0x44);
1101
1102 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1103 }
1104
1105 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MASERATI)
_HAL_INTERN_ISDBT_InitClk(void)1106 static void _HAL_INTERN_ISDBT_InitClk(void)
1107 {
1108 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MASERATI--------------\n"));
1109
1110 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1111
1112 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1113 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1114 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1115 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1116 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1117 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1118 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1119 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1120 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1121
1122 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1123 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1124 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1125 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1126 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1127 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1128 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1129 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1130 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1131 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1132 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1133 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1134 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1135 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1136 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1137 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1138 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1139 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1140 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1141 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1142 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1143 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1144 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1145 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1146 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1147 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1148 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1149 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1150 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1151 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1152 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1153 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1154 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1155 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1156 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1157 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1158 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1159 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1160 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1161 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1162 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1163 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1164 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1165 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1166 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1167 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1168 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1169 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1170 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1171 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1172 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1173 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1174 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1175 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1176 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1177 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1178 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1179 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1180 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1181 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1182 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1183 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1184 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1185
1186 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1187 }
1188 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MACAN)
_HAL_INTERN_ISDBT_InitClk(void)1189 static void _HAL_INTERN_ISDBT_InitClk(void)
1190 {
1191 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MACAN--------------\n"));
1192
1193 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1194
1195 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1196 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1197 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1198 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1199 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1200 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1201 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1202 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1203 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1204
1205 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1206 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1207 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1208 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1209 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1210 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1211 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1212 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1213 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1214 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1215 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1216 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1217 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1218 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1219 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1220 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1221 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1222 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1223 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1224 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1225 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1226 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1227 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1228 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1229 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1230 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1231 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1232 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1233 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1234 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1235 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1236 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1237 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1238 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1239 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1240 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1241 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1242 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1243 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1244 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1245 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1246 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1247 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1248 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1249 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1250 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1251 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1252 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1253 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1254 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1255 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1256 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1257 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1258 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1259 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1260 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1261 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1262 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1263 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1264 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1265 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1266 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1267 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1268
1269 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1270 }
1271 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG)
_HAL_INTERN_ISDBT_InitClk(void)1272 static void _HAL_INTERN_ISDBT_InitClk(void)
1273 {
1274 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUSTANG--------------\n"));
1275
1276 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1277
1278 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1279 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1280 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1281 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1282 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1283 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1284 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1285 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1286 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1287
1288 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1289 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1290 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1291 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1292 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1293 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1294 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1295 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1296 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1297 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1298 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1299 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1300 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1301 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1302 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1303 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1304 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1305 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1306 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1307 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1308 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1309 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1310 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1311 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1312 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1313 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1314 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1315 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1316 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1317 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1318 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1319 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1320 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1321 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1322 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1323 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1324 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1325 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1326 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1327 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1328 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1329 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1330 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1331 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1332 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1333 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1334 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1335 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1336 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1337 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1338 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1339 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1340 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1341 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1342 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1343 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1344 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1345 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1346 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1347 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1348 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1349 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1350 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1351
1352 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1353 }
1354 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAXIM)
_HAL_INTERN_ISDBT_InitClk(void)1355 static void _HAL_INTERN_ISDBT_InitClk(void)
1356 {
1357 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MAXIM--------------\n"));
1358
1359 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1360
1361 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1362 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1363
1364 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1365 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1366 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1367 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1368 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1369 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1370 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00); //ADC SYNC FLOW
1371 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00); //ADC SYNC FLOW
1372 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1373 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1374
1375 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00); //Add in MAXIM //ADC SYNC FLOW
1376 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00); //Add in MAXIM //ADC SYNC FLOW
1377
1378 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1379 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1380
1381 _HAL_DMD_RIU_WriteByte(0x103321, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1382 _HAL_DMD_RIU_WriteByte(0x103320, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1383
1384 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00); // DMD_ANA_ADC_SYNC CLK_W
1385
1386 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1387 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1388 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1389 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1390 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1391 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1392 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1393 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1394 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1395 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1396 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1397 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1398 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1399 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1400 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1401 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1402 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1403 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1404 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1405 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1406 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1407 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1408 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1409 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1410 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1411 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1412 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1413 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1414 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1415 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1416 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1417 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1418 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1419 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1420 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1421 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1422 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1423 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1424 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1425 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1426 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1427 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1428 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1429 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1430 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1431 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1432 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1433 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1434 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1435 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1436 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1437 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1438 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1439 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1440 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1441 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1442 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1443 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1444
1445 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1446 //_HAL_DMD_RIU_WriteByteMask(0x103480, 0x00, 0x02);
1447 }
1448 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KENTUCKY)
_HAL_INTERN_ISDBT_InitClk(void)1449 static void _HAL_INTERN_ISDBT_InitClk(void)
1450 {
1451 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_KENTUCKY--------------\n"));
1452
1453 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1454
1455 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1456 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1457 _HAL_DMD_RIU_WriteByte(0x103301, 0x30); //ts clock = 7.2M
1458 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1459 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1460 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1461 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1462 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1463 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1464 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1465
1466 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1467 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1468 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1469 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1470 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1471 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1472 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1473 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1474 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1475 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1476 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1477 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1478 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1479 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1480 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1481 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1482 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1483 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1484 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1485 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1486 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1487 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1488 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1489 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1490 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1491 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1492 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1493 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1494 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1495 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1496 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1497 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1498 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1499 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1500 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1501 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1502 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1503 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1504 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1505 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1506 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1507 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1508 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1509 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1510 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1511 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1512 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1513 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1514 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1515 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1516 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1517 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1518 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1519 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1520 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1521 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1522 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1523 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1524 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1525 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1526
1527 if ((_HAL_DMD_RIU_ReadByte(0x0e00+2*0x64) & 0x03) == 2)
1528 {
1529 _HAL_DMD_RIU_WriteByte(0x112830,0x01);
1530 _HAL_DMD_RIU_WriteByte(0x112831,0x00);
1531 _HAL_DMD_RIU_WriteByte(0x1128b2,0x11);
1532 }
1533 else
1534 {
1535 _HAL_DMD_RIU_WriteByte(0x112830,0x00);
1536 _HAL_DMD_RIU_WriteByte(0x112831,0x01);
1537 _HAL_DMD_RIU_WriteByte(0x1128b2,0x21);
1538 }
1539
1540 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1541 }
1542
1543 #else
_HAL_INTERN_ISDBT_InitClk(void)1544 static void _HAL_INTERN_ISDBT_InitClk(void)
1545 {
1546 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
1547 }
1548 #endif
1549
_HAL_INTERN_ISDBT_Ready(void)1550 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
1551 {
1552 MS_U8 udata = 0x00;
1553
1554 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1555
1556 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1557 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1558
1559 MsOS_DelayTask(1);
1560
1561 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1562
1563 if (udata) return FALSE;
1564
1565 return TRUE;
1566 }
1567
_HAL_INTERN_ISDBT_Download(void)1568 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
1569 {
1570 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
1571
1572 MS_U8 udata = 0x00;
1573 MS_U16 i = 0;
1574 MS_U16 fail_cnt = 0;
1575 MS_U8 u8TmpData;
1576 MS_U16 u16AddressOffset;
1577 const MS_U8 *ISDBT_table;
1578 MS_U16 u16Lib_size;
1579
1580 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
1581 {
1582 if (_HAL_INTERN_ISDBT_Ready())
1583 {
1584 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1585 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1586 #endif
1587 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1588 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03);
1589
1590 MsOS_DelayTask(20);
1591 return TRUE;
1592 }
1593 }
1594
1595 ISDBT_table = &INTERN_ISDBT_table[0];
1596 u16Lib_size = sizeof(INTERN_ISDBT_table);
1597
1598 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1599 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1600 #endif
1601 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1602 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1603
1604 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x01); // release MCU, madison patch
1605
1606 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1607 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1608 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1609 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1610
1611 //// Load code thru VDMCU_IF ////
1612 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
1613
1614 for (i = 0; i < u16Lib_size; i++)
1615 {
1616 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
1617 }
1618
1619 //// Content verification ////
1620 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
1621
1622 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1623 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1624
1625 for (i = 0; i < u16Lib_size; i++)
1626 {
1627 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1628
1629 if (udata != ISDBT_table[i])
1630 {
1631 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
1632 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
1633 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
1634
1635 if (fail_cnt++ > 10)
1636 {
1637 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
1638 return FALSE;
1639 }
1640 }
1641 }
1642
1643 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
1644
1645 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1646 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1647
1648 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
1649 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1650 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
1651 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1652 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
1653 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1654 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
1655 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1656 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
1657 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1658 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
1659 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1660 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
1661 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1662 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
1663 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1664 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
1665 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1666
1667 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1668 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1669
1670 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset MCU, madison patch
1671
1672 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1673 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03); // release VD_MCU
1674
1675 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
1676
1677 MsOS_DelayTask(20);
1678
1679 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
1680
1681 return TRUE;
1682 }
1683
_HAL_INTERN_ISDBT_FWVERSION(void)1684 static void _HAL_INTERN_ISDBT_FWVERSION(void)
1685 {
1686 MS_U8 data1 = 0;
1687 MS_U8 data2 = 0;
1688 MS_U8 data3 = 0;
1689
1690 _MBX_ReadReg(0x20C4, &data1);
1691 _MBX_ReadReg(0x20C5, &data2);
1692 _MBX_ReadReg(0x20C6, &data3);
1693
1694 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1695 }
1696
_HAL_INTERN_ISDBT_Exit(void)1697 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
1698 {
1699 MS_U8 u8CheckCount = 0;
1700 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1701 MS_U8 u8RegValTmp = 0;
1702
1703 u8RegValTmp = _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR);
1704 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1705 {
1706 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1707 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1708 }
1709 else
1710 {
1711 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1712 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1713 }
1714 #endif
1715 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1716
1717 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1718 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1719
1720 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1721 {
1722 MsOS_DelayTaskUs(10);
1723
1724 if (u8CheckCount++ == 0xFF)
1725 {
1726 printf(">> ISDBT Exit Fail!\n");
1727 return FALSE;
1728 }
1729 }
1730
1731 printf(">> ISDBT Exit Ok!\n");
1732
1733 return TRUE;
1734 }
1735
_HAL_INTERN_ISDBT_SoftReset(void)1736 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
1737 {
1738 MS_U8 u8Data = 0;
1739
1740 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1741 MS_U8 u8RegValTmp = 0;
1742
1743 u8RegValTmp = _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR);
1744 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1745 {
1746 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1747 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1748 }
1749 else
1750 {
1751 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1752 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1753 }
1754 #endif
1755
1756 //Reset FSM
1757 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1758
1759 while (u8Data!=0x02)
1760 {
1761 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1762 }
1763
1764 return TRUE;
1765 }
1766
_HAL_INTERN_ISDBT_SetACICoef(void)1767 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
1768 {
1769 return TRUE;
1770 }
1771
_HAL_INTERN_ISDBT_SetIsdbtMode(void)1772 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
1773 {
1774 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1775 MS_U8 u8RegValTmp = 0;
1776
1777 u8RegValTmp = _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR);
1778 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1779 {
1780 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1781 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1782 }
1783 else
1784 {
1785 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1786 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1787 }
1788 #endif
1789
1790 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
1791 return _MBX_WriteReg(0x20C0, 0x04);
1792 }
1793
_HAL_INTERN_ISDBT_SetModeClean(void)1794 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
1795 {
1796 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1797 return _MBX_WriteReg(0x20C0, 0x00);
1798 }
1799
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)1800 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
1801 {
1802 MS_BOOL bCheckPass = FALSE;
1803 MS_U8 u8Data = 0;
1804
1805 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1806
1807 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
1808 bCheckPass = TRUE;
1809
1810 return bCheckPass;
1811 }
1812
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)1813 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
1814 {
1815 MS_BOOL bCheckPass = FALSE;
1816 MS_U8 u8Data = 0;
1817
1818 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1819
1820 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
1821 bCheckPass = TRUE;
1822
1823 return bCheckPass;
1824 }
1825
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)1826 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
1827 {
1828 MS_BOOL bCheckPass = FALSE;
1829 MS_U8 u8Data = 0;
1830
1831 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1832
1833 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
1834 bCheckPass = TRUE;
1835
1836 return bCheckPass;
1837 }
1838
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)1839 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
1840 {
1841 MS_BOOL bCheckPass = FALSE;
1842 MS_U8 u8Data = 0;
1843
1844 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1845
1846 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
1847 bCheckPass = TRUE;
1848
1849 return bCheckPass;
1850 }
1851
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)1852 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
1853 {
1854 MS_BOOL bRet = TRUE;
1855 MS_U8 u8Data = 0;
1856 MS_U8 u8CodeRate = 0;
1857
1858 switch (eLayerIndex)
1859 {
1860 case E_ISDBT_Layer_A:
1861 // [10:8] reg_tmcc_cur_convolution_code_rate_a
1862 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1863 u8CodeRate = u8Data & 0x07;
1864 break;
1865 case E_ISDBT_Layer_B:
1866 // [10:8] reg_tmcc_cur_convolution_code_rate_b
1867 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1868 u8CodeRate = u8Data & 0x07;
1869 break;
1870 case E_ISDBT_Layer_C:
1871 // [10:8] reg_tmcc_cur_convolution_code_rate_c
1872 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1873 u8CodeRate = u8Data & 0x07;
1874 break;
1875 default:
1876 u8CodeRate = 15;
1877 break;
1878 }
1879
1880 switch (u8CodeRate)
1881 {
1882 case 0:
1883 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
1884 break;
1885 case 1:
1886 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
1887 break;
1888 case 2:
1889 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
1890 break;
1891 case 3:
1892 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
1893 break;
1894 case 4:
1895 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
1896 break;
1897 default:
1898 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
1899 break;
1900 }
1901
1902 return bRet;
1903 }
1904
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)1905 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
1906 {
1907 MS_BOOL bRet = TRUE;
1908 MS_U8 u8Data = 0;
1909 MS_U8 u8CP = 0;
1910
1911 // [7:6] reg_mcd_out_cp
1912 // output cp -> 00: 1/4
1913 // 01: 1/8
1914 // 10: 1/16
1915 // 11: 1/32
1916 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1917
1918 u8CP = (u8Data >> 6) & 0x03;
1919
1920 switch (u8CP)
1921 {
1922 case 0:
1923 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
1924 break;
1925 case 1:
1926 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
1927 break;
1928 case 2:
1929 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
1930 break;
1931 case 3:
1932 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
1933 break;
1934 }
1935
1936 return bRet;
1937 }
1938
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)1939 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
1940 {
1941 MS_BOOL bRet = TRUE;
1942 MS_U8 u8Data = 0;
1943 MS_U8 u8Mode = 0;
1944 MS_U8 u8Tdi = 0;
1945
1946 // [5:4] reg_mcd_out_mode
1947 // output mode -> 00: 2k
1948 // 01: 4k
1949 // 10: 8k
1950 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1951
1952 u8Mode = (u8Data >> 4) & 0x03;
1953
1954 switch (eLayerIndex)
1955 {
1956 case E_ISDBT_Layer_A:
1957 // [14:12] reg_tmcc_cur_interleaving_length_a
1958 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1959 u8Tdi = (u8Data >> 4) & 0x07;
1960 break;
1961 case E_ISDBT_Layer_B:
1962 // [14:12] reg_tmcc_cur_interleaving_length_b
1963 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1964 u8Tdi = (u8Data >> 4) & 0x07;
1965 break;
1966 case E_ISDBT_Layer_C:
1967 // [14:12] reg_tmcc_cur_interleaving_length_c
1968 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1969 u8Tdi = (u8Data >> 4) & 0x07;
1970 break;
1971 default:
1972 u8Tdi = 15;
1973 break;
1974 }
1975
1976 // u8Tdi+u8Mode*4
1977 // => 0~3: 2K
1978 // => 4~7: 4K
1979 // => 8~11:8K
1980 switch (u8Tdi+u8Mode*4)
1981 {
1982 case 0:
1983 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
1984 break;
1985 case 1:
1986 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
1987 break;
1988 case 2:
1989 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
1990 break;
1991 case 3:
1992 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
1993 break;
1994 case 4:
1995 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
1996 break;
1997 case 5:
1998 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
1999 break;
2000 case 6:
2001 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
2002 break;
2003 case 7:
2004 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
2005 break;
2006 case 8:
2007 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
2008 break;
2009 case 9:
2010 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
2011 break;
2012 case 10:
2013 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
2014 break;
2015 case 11:
2016 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
2017 break;
2018 default:
2019 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
2020 break;
2021 }
2022
2023 return bRet;
2024 }
2025
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)2026 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
2027 {
2028 MS_BOOL bRet = TRUE;
2029 MS_U8 u8Data = 0;
2030 MS_U8 u8Mode = 0;
2031
2032 // [5:4] reg_mcd_out_mode
2033 // output mode -> 00: 2k
2034 // 01: 4k
2035 // 10: 8k
2036 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
2037
2038 u8Mode = (u8Data >> 4) & 0x03;
2039
2040 switch (u8Mode)
2041 {
2042 case 0:
2043 *peIsdbtFFT = E_ISDBT_FFT_2K;
2044 break;
2045 case 1:
2046 *peIsdbtFFT = E_ISDBT_FFT_4K;
2047 break;
2048 case 2:
2049 *peIsdbtFFT = E_ISDBT_FFT_8K;
2050 break;
2051 default:
2052 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
2053 break;
2054 }
2055
2056 return bRet;
2057 }
2058
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)2059 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
2060 {
2061 MS_BOOL bRet = TRUE;
2062 MS_U8 u8Data = 0;
2063 MS_U8 u8QAM = 0;
2064
2065 switch(eLayerIndex)
2066 {
2067 case E_ISDBT_Layer_A:
2068 // [6:4] reg_tmcc_cur_carrier_modulation_a
2069 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
2070 u8QAM = (u8Data >> 4) & 0x07;
2071 break;
2072 case E_ISDBT_Layer_B:
2073 // [6:4] reg_tmcc_cur_carrier_modulation_b
2074 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
2075 u8QAM = (u8Data >> 4) & 0x07;
2076 break;
2077 case E_ISDBT_Layer_C:
2078 // [6:4] reg_tmcc_cur_carrier_modulation_c
2079 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
2080 u8QAM = (u8Data >> 4) & 0x07;
2081 break;
2082 default:
2083 u8QAM = 15;
2084 break;
2085 }
2086
2087 switch(u8QAM)
2088 {
2089 case 0:
2090 *peIsdbtConstellation = E_ISDBT_DQPSK;
2091 break;
2092 case 1:
2093 *peIsdbtConstellation = E_ISDBT_QPSK;
2094 break;
2095 case 2:
2096 *peIsdbtConstellation = E_ISDBT_16QAM;
2097 break;
2098 case 3:
2099 *peIsdbtConstellation = E_ISDBT_64QAM;
2100 break;
2101 default:
2102 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
2103 break;
2104 }
2105
2106 return bRet;
2107 }
2108
_HAL_INTERN_ISDBT_ReadIFAGC(void)2109 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
2110 {
2111 MS_U8 data = 0;
2112
2113 _MBX_ReadReg(0x28FD, &data);
2114
2115 return data;
2116 }
2117
2118 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 * pFFT_Mode,MS_S32 * pTdCfoRegValue,MS_S32 * pFdCfoRegValue,MS_S16 * pIcfoRegValue)2119 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 *pFFT_Mode, MS_S32 *pTdCfoRegValue, MS_S32 *pFdCfoRegValue, MS_S16 *pIcfoRegValue)
2120 #else
2121 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
2122 #endif
2123 {
2124 MS_BOOL bRet = TRUE;
2125 MS_U8 u8Data = 0;
2126 MS_S32 s32TdCfoRegValue = 0;
2127 MS_S32 s32FdCfoRegValue = 0;
2128 MS_S16 s16IcfoRegValue = 0;
2129 #ifndef UTPA2
2130 float fTdCfoFreq = 0.0;
2131 float fICfoFreq = 0.0;
2132 float fFdCfoFreq = 0.0;
2133 #endif
2134
2135 //Get TD CFO
2136 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2137 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
2138
2139 //read td_freq_error
2140 //Read <29,38>
2141 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2142 s32TdCfoRegValue = u8Data;
2143 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
2144 s32TdCfoRegValue |= u8Data << 8;
2145 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
2146 s32TdCfoRegValue = u8Data << 16;
2147 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
2148 s32TdCfoRegValue |= u8Data << 24;
2149
2150 if (u8Data >= 0x10)
2151 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
2152
2153 s32TdCfoRegValue >>=4;
2154
2155 //TD_cfo_Hz = RegCfoTd * fb
2156 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2157 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
2158
2159 #ifndef UTPA2
2160 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
2161 fTdCfoFreq = fTdCfoFreq * 8126980.0;
2162 #endif
2163
2164 //Get FD CFO
2165 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2166 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2167 //load
2168 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2169 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2170
2171 //read CFO_KI
2172 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
2173 s32FdCfoRegValue = u8Data;
2174 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
2175 s32FdCfoRegValue |= u8Data << 8;
2176 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
2177 s32FdCfoRegValue |= u8Data << 16;
2178 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
2179 s32FdCfoRegValue |= u8Data << 24;
2180
2181 if(u8Data >= 0x01)
2182 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
2183
2184 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2185 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2186 //load
2187 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2188 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2189
2190 #ifndef UTPA2
2191 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
2192 fFdCfoFreq = fFdCfoFreq * 8126980.0;
2193 #endif
2194
2195 //Get ICFO
2196 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
2197 s16IcfoRegValue = u8Data;
2198 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
2199 s16IcfoRegValue |= u8Data << 8;
2200 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
2201
2202 if(s16IcfoRegValue >= 0x400)
2203 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
2204
2205 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
2206
2207 #ifdef UTPA2
2208 *pFFT_Mode = u8Data;
2209 *pTdCfoRegValue = s32TdCfoRegValue;
2210 *pFdCfoRegValue = s32TdCfoRegValue;
2211 *pIcfoRegValue = s16IcfoRegValue;
2212 #else
2213 if((u8Data & 0x30) == 0x0000) // 2k
2214 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
2215 else if((u8Data & 0x0030) == 0x0010) // 4k
2216 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
2217 else //if(u16data & 0x0030 == 0x0020) // 8k
2218 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
2219
2220 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
2221
2222 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
2223 #endif
2224
2225 return bRet;
2226 }
2227
2228 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2229 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2230 #else
2231 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2232 #endif
2233 {
2234 MS_BOOL bRet = TRUE;
2235 MS_U8 u8Data = 0;
2236 MS_U16 u16BerValue = 0;
2237 MS_U32 u32BerPeriod = 0;
2238
2239 // reg_rd_freezeber
2240 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2241 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
2242
2243 if (eLayerIndex == E_ISDBT_Layer_A)
2244 {
2245 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
2246 u16BerValue=u8Data;
2247 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
2248 u16BerValue |= (u8Data << 8);
2249 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
2250 u32BerPeriod = (u8Data&0x3F);
2251 u32BerPeriod <<= 16;
2252 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
2253 u32BerPeriod |= u8Data;
2254 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
2255 u32BerPeriod |= (u8Data << 8);
2256 }
2257 else if (eLayerIndex == E_ISDBT_Layer_B)
2258 {
2259 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
2260 u16BerValue=u8Data;
2261 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
2262 u16BerValue |= (u8Data << 8);
2263 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
2264 u32BerPeriod = (u8Data&0x3F);
2265 u32BerPeriod <<= 16;
2266 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
2267 u32BerPeriod |= u8Data;
2268 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
2269 u32BerPeriod |= (u8Data << 8);
2270 }
2271 else if (eLayerIndex == E_ISDBT_Layer_C)
2272 {
2273 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
2274 u16BerValue=u8Data;
2275 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
2276 u16BerValue |= (u8Data << 8);
2277 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
2278 u32BerPeriod = (u8Data&0x003F);
2279 u32BerPeriod <<= 16;
2280 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
2281 u32BerPeriod |= u8Data;
2282 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
2283 u32BerPeriod |= (u8Data << 8);
2284 }
2285 else
2286 {
2287 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2288 bRet = FALSE;
2289 }
2290
2291 // reg_rd_freezeber
2292 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2293 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
2294
2295 u32BerPeriod <<= 8; // *256
2296
2297 if(u32BerPeriod == 0) u32BerPeriod = 1;
2298
2299 #ifdef UTPA2
2300 *pBerPeriod = u32BerPeriod;
2301 *pBerValue = u16BerValue;
2302 #else
2303 *pfber = (float)u16BerValue/u32BerPeriod;
2304 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
2305 #endif
2306
2307 return bRet;
2308 }
2309
2310 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2311 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2312 #else
2313 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2314 #endif
2315 {
2316 MS_BOOL bRet = TRUE;
2317 MS_U8 u8Data = 0;
2318 MS_U8 u8FrzData = 0;
2319 MS_U32 u32BerValue = 0;
2320 MS_U16 u16BerPeriod = 0;
2321
2322 // reg_rd_freezeber
2323 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2324 u8Data = u8FrzData | 0x01;
2325 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2326
2327 if (eLayerIndex == E_ISDBT_Layer_A)
2328 {
2329 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
2330 u32BerValue = u8Data;
2331 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
2332 u32BerValue |= u8Data << 8;
2333 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
2334 u32BerValue |= u8Data << 16;
2335 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
2336 u32BerValue |= u8Data << 24;
2337
2338 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
2339 u16BerPeriod = u8Data;
2340 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
2341 u16BerPeriod |= u8Data << 8;
2342 }
2343 else if (eLayerIndex == E_ISDBT_Layer_B)
2344 {
2345 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
2346 u32BerValue = u8Data;
2347 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
2348 u32BerValue |= u8Data << 8;
2349 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
2350 u32BerValue |= u8Data << 16;
2351 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
2352 u32BerValue |= u8Data << 24;
2353
2354 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
2355 u16BerPeriod = u8Data;
2356 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
2357 u16BerPeriod |= u8Data << 8;
2358 }
2359 else if (eLayerIndex == E_ISDBT_Layer_C)
2360 {
2361 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
2362 u32BerValue = u8Data;
2363 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
2364 u32BerValue |= u8Data << 8;
2365 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2366 u32BerValue |= u8Data << 16;
2367 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
2368 u32BerValue |= u8Data << 24;
2369
2370 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
2371 u16BerPeriod = u8Data;
2372 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
2373 u16BerPeriod |= u8Data << 8;
2374 }
2375 else
2376 {
2377 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2378 bRet = FALSE;
2379 }
2380
2381 // reg_rd_freezeber
2382 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2383
2384 if(u16BerPeriod == 0) u16BerPeriod = 1;
2385
2386 #ifdef UTPA2
2387 *pBerPeriod = u16BerPeriod;
2388 *pBerValue = u32BerValue;
2389 #else
2390 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
2391 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
2392 #endif
2393 return bRet;
2394 }
2395
2396 #ifndef UTPA2
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)2397 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
2398 {
2399 float fber;
2400 MS_BOOL bRet = TRUE;
2401 EN_ISDBT_Layer eLayerIndex;
2402 MS_U16 u16SQI;
2403
2404 // Tmp solution
2405 eLayerIndex = E_ISDBT_Layer_A;
2406
2407 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2408 {
2409 //printf("Dan Demod unlock!!!\n");
2410 u16SQI = 0;
2411 }
2412 else
2413 {
2414 // Part 1: get ber value from demod.
2415 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2416
2417 u16SQI = _CALCULATE_SQI(fber);
2418 }
2419
2420 //printf("dan SQI = %d\n", SQI);
2421 return u16SQI;
2422 }
2423
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)2424 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
2425 {
2426 float fber;
2427 MS_BOOL bRet = TRUE;
2428 EN_ISDBT_Layer eLayerIndex;
2429 MS_U16 u16SQI;
2430
2431 // Tmp solution
2432 eLayerIndex = E_ISDBT_Layer_B;
2433
2434 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2435 {
2436 //printf("Dan Demod unlock!!!\n");
2437 u16SQI = 0;
2438 }
2439 else
2440 {
2441 // Part 1: get ber value from demod.
2442 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2443
2444 u16SQI = _CALCULATE_SQI(fber);
2445 }
2446
2447 //printf("dan SQI = %d\n", SQI);
2448 return u16SQI;
2449 }
2450
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)2451 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
2452 {
2453 float fber;
2454 MS_BOOL bRet = TRUE;
2455 EN_ISDBT_Layer eLayerIndex;
2456 MS_U16 u16SQI;
2457
2458 // Tmp solution
2459 eLayerIndex = E_ISDBT_Layer_C;
2460
2461 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2462 {
2463 //printf("Dan Demod unlock!!!\n");
2464 u16SQI = 0;
2465 }
2466 else
2467 {
2468 // Part 1: get ber value from demod.
2469 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2470
2471 u16SQI = _CALCULATE_SQI(fber);
2472 }
2473
2474 //printf("dan SQI = %d\n", SQI);
2475 return u16SQI;
2476 }
2477
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)2478 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
2479 {
2480 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
2481 MS_U16 u16SQI;
2482 EN_ISDBT_Layer eLayerIndex;
2483 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
2484
2485 //Get modulation of each layer
2486 eLayerIndex = E_ISDBT_Layer_A;
2487 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
2488 eLayerIndex = E_ISDBT_Layer_B;
2489 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
2490 eLayerIndex = E_ISDBT_Layer_C;
2491 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
2492
2493 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
2494 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
2495 else
2496 s8LayerAValue = -1;
2497
2498 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
2499 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
2500 else
2501 s8LayerBValue = -1;
2502
2503 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
2504 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
2505 else
2506 s8LayerCValue = -1;
2507
2508 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
2509 if (s8LayerAValue >= s8LayerBValue)
2510 {
2511 if (s8LayerCValue >= s8LayerAValue)
2512 {
2513 //Get Layer C u16SQI
2514 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2515 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
2516 }
2517 else //A>C
2518 {
2519 //Get Layer A u16SQI
2520 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2521 //printf("dan u16SQI Layer A: %d\n", u16SQI);
2522 }
2523 }
2524 else // B >= A
2525 {
2526 if (s8LayerCValue >= s8LayerBValue)
2527 {
2528 //Get Layer C u16SQI
2529 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2530 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
2531 }
2532 else //B>C
2533 {
2534 //Get Layer B u16SQI
2535 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2536 //printf("dan u16SQI Layer B: %d\n", u16SQI);
2537 }
2538 }
2539
2540 return u16SQI;
2541 }
2542 #endif
2543
2544 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetSNR(MS_U32 * pRegSNR,MS_U16 * pRegSnrObsNum)2545 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(MS_U32 *pRegSNR, MS_U16 *pRegSnrObsNum)
2546 #else
2547 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
2548 #endif
2549 {
2550 MS_BOOL bRet = TRUE;
2551 MS_U8 u8Data = 0;
2552 MS_U32 u32RegSNR = 0;
2553 MS_U16 u16RegSnrObsNum = 0;
2554 #ifndef UTPA2
2555 float fSNRAvg = 0.0;
2556 #endif
2557
2558 //set freeze
2559 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2560 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2561 //load
2562 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2563 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2564
2565 // ==============Average SNR===============//
2566 // [26:0] reg_snr_accu
2567 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
2568 u32RegSNR = u8Data&0x07;
2569 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
2570 u32RegSNR = (u32RegSNR<<8) | u8Data;
2571 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
2572 u32RegSNR = (u32RegSNR<<8) | u8Data;
2573 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
2574 u32RegSNR = (u32RegSNR<<8) | u8Data;
2575
2576 // [12:0] reg_snr_observe_sum_num
2577 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
2578 u16RegSnrObsNum = u8Data&0x1f;
2579 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
2580 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
2581
2582 //release freeze
2583 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2584 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2585 //load
2586 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2587 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2588
2589 if (u16RegSnrObsNum == 0)
2590 u16RegSnrObsNum = 1;
2591
2592
2593 #ifdef UTPA2
2594 *pRegSNR = u32RegSNR;
2595 *pRegSnrObsNum = u16RegSnrObsNum;
2596 #else
2597 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
2598 if (fSNRAvg == 0) //protect value 0
2599 fSNRAvg = 0.01;
2600
2601 #ifdef MSOS_TYPE_LINUX
2602 *pf_snr = 10.0f*(float)log10f((double)fSNRAvg/2);
2603 #else
2604 *pf_snr = 10.0f*(float)Log10Approx((double)fSNRAvg/2);
2605 #endif
2606 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
2607 #endif
2608
2609 return bRet;
2610 }
2611
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)2612 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
2613 {
2614 MS_U8 bRet = true;
2615 MS_U8 u8Data = 0;
2616 MS_U8 u8FrzData = 0;
2617 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
2618 #if DMD_ISDBT_TBVA_EN
2619 MS_U8 bTbvaBypass = 0;
2620 MS_U8 u8TbvaLayer = 0;
2621 #endif
2622 // Read packet errors of three layers
2623 // OUTER_FUNCTION_ENABLE
2624 // [8] reg_biterr_num_pcktprd_freeze
2625 // Freeze Packet error
2626 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2627 u8Data = u8FrzData | 0x01;
2628 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2629 #if DMD_ISDBT_TBVA_EN
2630 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x10*2, &u8Data);
2631 bTbvaBypass = u8Data & 0x01;
2632 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x11*2, &u8Data);
2633 u8TbvaLayer = u8Data & 0x03;
2634 switch(eLayerIndex)
2635 {
2636 case E_ISDBT_Layer_A:
2637 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2638 if (!bTbvaBypass && u8TbvaLayer == 0)
2639 {
2640 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2641 u16PacketErrA = u8Data << 8;
2642 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2643 u16PacketErrA = u16PacketErrA | u8Data;
2644 *pu16PacketErr = u16PacketErrA;
2645 }
2646 else
2647 {
2648 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2649 u16PacketErrA = u8Data << 8;
2650 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2651 u16PacketErrA = u16PacketErrA | u8Data;
2652 *pu16PacketErr = u16PacketErrA;
2653 }
2654 break;
2655 case E_ISDBT_Layer_B:
2656 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2657 if (!bTbvaBypass && u8TbvaLayer == 1)
2658 {
2659 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2660 u16PacketErrB = u8Data << 8;
2661 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2662 u16PacketErrB = u16PacketErrB | u8Data;
2663 *pu16PacketErr = u16PacketErrB;
2664 }
2665 else
2666 {
2667 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2668 u16PacketErrB = u8Data << 8;
2669 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2670 u16PacketErrB = u16PacketErrB | u8Data;
2671 *pu16PacketErr = u16PacketErrB;
2672 }
2673 break;
2674 case E_ISDBT_Layer_C:
2675 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2676 if (!bTbvaBypass && u8TbvaLayer == 2)
2677 {
2678 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2679 u16PacketErrC = u8Data << 8;
2680 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2681 u16PacketErrC = u16PacketErrC | u8Data;
2682 *pu16PacketErr = u16PacketErrC;
2683 }
2684 else
2685 {
2686 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2687 u16PacketErrC = u8Data << 8;
2688 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2689 u16PacketErrC = u16PacketErrC | u8Data;
2690 *pu16PacketErr = u16PacketErrC;
2691 }
2692 break;
2693 default:
2694 *pu16PacketErr = 0xFFFF;
2695 break;
2696 }
2697 #else
2698 switch(eLayerIndex)
2699 {
2700 case E_ISDBT_Layer_A:
2701 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2702 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2703 u16PacketErrA = u8Data << 8;
2704 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2705 u16PacketErrA = u16PacketErrA | u8Data;
2706 *pu16PacketErr = u16PacketErrA;
2707 break;
2708 case E_ISDBT_Layer_B:
2709 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2710 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2711 u16PacketErrB = u8Data << 8;
2712 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2713 u16PacketErrB = u16PacketErrB | u8Data;
2714 *pu16PacketErr = u16PacketErrB;
2715 break;
2716 case E_ISDBT_Layer_C:
2717 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2718 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2719 u16PacketErrC = u8Data << 8;
2720 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2721 u16PacketErrC = u16PacketErrC | u8Data;
2722 *pu16PacketErr = u16PacketErrC;
2723 break;
2724 default:
2725 *pu16PacketErr = 0xFFFF;
2726 break;
2727 }
2728 #endif
2729 // Unfreeze Packet error
2730 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2731
2732 return bRet;
2733 }
2734
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2735 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2736 {
2737 return _MBX_ReadReg(u16Addr, pu8Data);
2738 }
2739
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2740 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2741 {
2742 return _MBX_WriteReg(u16Addr, u8Data);
2743 }
2744
2745 //-------------------------------------------------------------------------------------------------
2746 // Global Functions
2747 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)2748 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
2749 {
2750 MS_BOOL bResult = TRUE;
2751
2752 switch(eCmd)
2753 {
2754 case DMD_ISDBT_HAL_CMD_Exit:
2755 bResult = _HAL_INTERN_ISDBT_Exit();
2756 break;
2757 case DMD_ISDBT_HAL_CMD_InitClk:
2758 _HAL_INTERN_ISDBT_InitClk();
2759 break;
2760 case DMD_ISDBT_HAL_CMD_Download:
2761 bResult = _HAL_INTERN_ISDBT_Download();
2762 break;
2763 case DMD_ISDBT_HAL_CMD_FWVERSION:
2764 _HAL_INTERN_ISDBT_FWVERSION();
2765 break;
2766 case DMD_ISDBT_HAL_CMD_SoftReset:
2767 bResult = _HAL_INTERN_ISDBT_SoftReset();
2768 break;
2769 case DMD_ISDBT_HAL_CMD_SetACICoef:
2770 bResult = _HAL_INTERN_ISDBT_SetACICoef();
2771 break;
2772 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
2773 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
2774 break;
2775 case DMD_ISDBT_HAL_CMD_SetModeClean:
2776 bResult = _HAL_INTERN_ISDBT_SetModeClean();
2777 break;
2778 case DMD_ISDBT_HAL_CMD_Active:
2779 break;
2780 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
2781 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
2782 break;
2783 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
2784 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
2785 break;
2786 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
2787 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
2788 break;
2789 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
2790 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
2791 break;
2792 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
2793 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
2794 break;
2795 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
2796 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
2797 break;
2798 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
2799 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
2800 break;
2801 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
2802 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
2803 break;
2804 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
2805 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
2806 break;
2807 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
2808 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
2809 break;
2810 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
2811 #ifdef UTPA2
2812 bResult = _HAL_INTERN_ISDBT_GetFreqOffset(&((*((DMD_ISDBT_CFO_DATA*)pArgs)).FFT_Mode), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).TdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).FdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).IcfoRegValue));
2813 #else
2814 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
2815 #endif
2816 break;
2817 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
2818 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
2819 #ifndef UTPA2
2820 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2821 #endif
2822 break;
2823 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
2824 #ifndef UTPA2
2825 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2826 #endif
2827 break;
2828 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
2829 #ifndef UTPA2
2830 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2831 #endif
2832 break;
2833 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
2834 #ifndef UTPA2
2835 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
2836 #endif
2837 break;
2838 case DMD_ISDBT_HAL_CMD_GetSNR:
2839 #ifdef UTPA2
2840 bResult = _HAL_INTERN_ISDBT_GetSNR(&((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSNR), &((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSnrObsNum));
2841 #else
2842 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
2843 #endif
2844 break;
2845 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
2846 #ifdef UTPA2
2847 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2848 #else
2849 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2850 #endif
2851 break;
2852 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
2853 #ifdef UTPA2
2854 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2855 #else
2856 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2857 #endif
2858 break;
2859 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
2860 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
2861 break;
2862 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
2863 break;
2864 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
2865 break;
2866 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
2867 break;
2868 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
2869 break;
2870 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
2871 break;
2872 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
2873 break;
2874 case DMD_ISDBT_HAL_CMD_GET_REG:
2875 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
2876 break;
2877 case DMD_ISDBT_HAL_CMD_SET_REG:
2878 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
2879 break;
2880 default:
2881 break;
2882 }
2883
2884 return bResult;
2885 }
2886
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)2887 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
2888 {
2889 return TRUE;
2890 }
2891
2892