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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #include "ULog.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
133
134 #define TDE_REG_BASE 0x2400UL
135 #define DIV_REG_BASE 0x2500UL
136 #define TR_REG_BASE 0x2600UL
137 #define FTN_REG_BASE 0x2700UL
138 #define FTNEXT_REG_BASE 0x2800UL
139
140
141
142 #if 0//ENABLE_SCAN_ONELINE_MSG
143 #define DBG_INTERN_DVBT_ONELINE(x) x
144 #else
145 #define DBG_INTERN_DVBT_ONELINE(x) // x
146 #endif
147
148 #ifdef MS_DEBUG
149 #define DBG_INTERN_DVBT(x) x
150 #define DBG_GET_SIGNAL(x) x
151 #define DBG_INTERN_DVBT_TIME(x) x
152 #define DBG_INTERN_DVBT_LOCK(x) x
153 #else
154 #define DBG_INTERN_DVBT(x) //x
155 #define DBG_GET_SIGNAL(x) //x
156 #define DBG_INTERN_DVBT_TIME(x) // x
157 #define DBG_INTERN_DVBT_LOCK(x) //x
158 #endif
159 #define DBG_DUMP_LOAD_DSP_TIME 0
160
161 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
162 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
163 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
164 #define INTERN_DVBT_INTERNAL_DEBUG 1
165
166 #define SIGNAL_LEVEL_OFFSET 0.00
167 #define TAKEOVERPOINT -59.0
168 #define TAKEOVERRANGE 0.5
169 #define LOG10_OFFSET -0.21
170 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
171 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
172
173
174 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
175 #define TUNER_VPP 2
176 #define IF_AGC_VPP 2
177 #else
178 #define TUNER_VPP 1
179 #define IF_AGC_VPP 2
180 #endif
181
182 #if (TUNER_VPP == 1)
183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
184 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
186 #endif
187
188 /*BEG INTERN_DVBT_DSPREG_TABLE*/
189 #define D_DMD_DVBT_PARAM_VERSION 0x01
190 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
191 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
192 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
193 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
194 #define D_DMD_DVBT_OP_DCR_EN 0x01
195 #define D_DMD_DVBT_OP_IIS_EN 0x01
196 #define D_DMD_DVBT_OP_IQB_EN 0x00
197 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
198 #define D_DMD_DVBT_OP_ACI_EN 0x01
199 #define D_DMD_DVBT_OP_CCI_EN 0x01
200 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
201 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
202 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
203 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
204 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
205 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
206 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
207 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
208 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
209 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
210 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
211 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
212 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
213 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
214 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
215 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
216 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
217 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
218 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
219 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
220 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
221 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
222
223 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
224 #define D_DMD_DVBT_CFG_FC_H 0x4E
225 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
226 #define D_DMD_DVBT_CFG_FS_H 0x5D
227 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
228
229 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
230 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
231 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
232 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
233 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
234 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
235 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
236 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
237 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
238 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
239 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
240 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
241
242 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
243 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
244 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
245 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
246 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
247 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
248 #else
249 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
250 #endif
251 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
252 //#define DMD_DVBT_CHECKSUM 0x00
253 /*END INTERN_DVBT_DSPREG_TABLE*/
254 #define DVBT_FS 45474 // 24000
255 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
256 #define FC_L 0x20 // 0323 jason
257 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
258 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
259 #define SET_ZIF 0x00
260 #define IQB_EN 0x00
261
262 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
263 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
264 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
265 #define CSTL 0x02 //0:QPSK 1:16 2: 64
266 #define HIER 0x00
267 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
268 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
269 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
270 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
271 #define LP_SEL 0x00 // LP select
272 #define IQ_SWAP 0x00 //0x01
273 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
274 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
275 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
276 #define TS_SER 0
277 #define TS_INV 0
278 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
279 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
280 #define IF_INV_PWM 0x00
281 #define T_LOWIF 1
282
283 MS_U8 INTERN_DVBT_DSPREG[] =
284 {
285 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
286 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
287 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
288 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
289 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
290 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
293 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
294 /*
295 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
296 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
297 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
298 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
299 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
300 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
301 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
302 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
303 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
304 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
305 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
306 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
307 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
308 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
309 */
310 };
311 /*END INTERN_DVBT_DSPREG_TABLE*/
312 //-----------------------------------------------------------------------
313 /****************************************************************
314 *Local Variables *
315 ****************************************************************/
316 static MS_BOOL bFECLock=0;
317 static MS_BOOL bTPSLock = 0;
318 static MS_U32 u32ChkScanTimeStart = 0;
319 static MS_U32 u32FecFirstLockTime=0;
320 static MS_U32 u32FecLastLockTime=0;
321 static float fViterbiBerFiltered=-1;
322 //Global Variables
323 S_CMDPKTREG gsCmdPacket;
324 //U8 gCalIdacCh0, gCalIdacCh1;
325
326 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
327 MS_U8 INTERN_DVBT_table[] = {
328 #include "fwDMD_INTERN_DVBT.dat"
329 };
330
331 #endif
332
333 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
334 {
335 { _QPSK , _CR1Y2, -93},
336 { _QPSK , _CR2Y3, -91},
337 { _QPSK , _CR3Y4, -90},
338 { _QPSK , _CR5Y6, -89},
339 { _QPSK , _CR7Y8, -88},
340
341 { _16QAM , _CR1Y2, -87},
342 { _16QAM , _CR2Y3, -85},
343 { _16QAM , _CR3Y4, -84},
344 { _16QAM , _CR5Y6, -83},
345 { _16QAM , _CR7Y8, -82},
346
347 { _64QAM , _CR1Y2, -82},
348 { _64QAM , _CR2Y3, -80},
349 { _64QAM , _CR3Y4, -78},
350 { _64QAM , _CR5Y6, -77},
351 { _64QAM , _CR7Y8, -76},
352 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
353 };
354
355
356
357 static void INTERN_DVBT_SignalQualityReset(void);
358 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
359
INTERN_DVBT_SignalQualityReset(void)360 static void INTERN_DVBT_SignalQualityReset(void)
361 {
362 u32FecFirstLockTime=0;
363 fViterbiBerFiltered=-1;
364 }
365
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)366 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
367 {
368 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
369 MS_BOOL status = TRUE;
370 MS_U16 u16DspAddr = 0;
371
372 DBG_INTERN_DVBT(ULOGD("Utopia","INTERN_DVBT_DSPReg_Init\n"));
373
374 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
375 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
376
377 if (u8DVBT_DSPReg != NULL)
378 {
379 /*temp solution until new dsp table applied.*/
380 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
381 if (u8DVBT_DSPReg[0] >= 1)
382 {
383 u8DVBT_DSPReg+=2;
384 for (idx = 0; idx<u8Size; idx++)
385 {
386 u16DspAddr = *u8DVBT_DSPReg;
387 u8DVBT_DSPReg++;
388 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
389 u8DVBT_DSPReg++;
390 u8Mask = *u8DVBT_DSPReg;
391 u8DVBT_DSPReg++;
392 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
393 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
394 u8DVBT_DSPReg++;
395 DBG_INTERN_DVBT(ULOGD("Utopia","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
396 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
397 }
398 }
399 else
400 {
401 ULOGE("Utopia","FATAL: parameter version incorrect\n");
402 }
403 }
404
405 return status;
406 }
407
408 /***********************************************************************************
409 Subject: Command Packet Interface
410 Function: INTERN_DVBT_Cmd_Packet_Send
411 Parmeter:
412 Return: MS_BOOL
413 Remark:
414 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)415 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
416 {
417 MS_U8 status = true, indx;
418 MS_U8 reg_val=0, timeout = 0;
419 return TRUE;
420 //MsOS_ObtainMutex(_s32_Demod_DVBT_Mutex, MSOS_WAIT_FOREVER);
421 // ==== Command Phase ===================
422 DBG_INTERN_DVBT(ULOGD("Utopia","--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
423 pCmdPacket->param[0],pCmdPacket->param[1],
424 pCmdPacket->param[2],pCmdPacket->param[3],
425 pCmdPacket->param[4],pCmdPacket->param[5] ));
426
427 // wait _BIT_END clear
428 do
429 {
430 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
431 if((reg_val & _BIT_END) != _BIT_END)
432 {
433 break;
434 }
435 MsOS_DelayTask(5);
436 if (timeout++ > 200)
437 {
438 ULOGE("Utopia","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
439 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
440 return false;
441 }
442 } while (1);
443
444 // set cmd_3:0 and _BIT_START
445 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
446 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
447 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
448
449
450 //DBG_INTERN_DVBT(ULOGD("Utopia","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
451 // wait _BIT_START clear
452 do
453 {
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
455 if((reg_val & _BIT_START) != _BIT_START)
456 {
457 break;
458 }
459 MsOS_DelayTask(5);
460 if (timeout++ > 200)
461 {
462 ULOGE("Utopia","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
463 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
464 return false;
465 }
466 } while (1);
467
468 // ==== Data Phase ======================
469
470 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
471
472 for (indx = 0; indx < param_cnt; indx++)
473 {
474 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
475 //DBG_INTERN_DVBT(ULOGD("Utopia","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
476
477 // set param[indx] and _BIT_DRQ
478 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
479 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
480 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
481
482 // wait _BIT_DRQ clear
483 do
484 {
485 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
486 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
487 {
488 break;
489 }
490 MsOS_DelayTask(5);
491 if (timeout++ > 200)
492 {
493 ULOGE("Utopia","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
494 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
495 return false;
496 }
497 } while (1);
498 }
499
500 // ==== End Phase =======================
501
502 // set _BIT_END to finish command
503 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
504 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
505 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
506 return status;
507 }
508
509
510 /***********************************************************************************
511 Subject: Command Packet Interface
512 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
513 Parmeter:
514 Return: MS_BOOL
515 Remark:
516 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)517 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
518 {
519 return TRUE;
520 }
521
522 /***********************************************************************************
523 Subject: SoftStop
524 Function: INTERN_DVBT_SoftStop
525 Parmeter:
526 Return: MS_BOOL
527 Remark:
528 ************************************************************************************/
529
INTERN_DVBT_SoftStop(void)530 MS_BOOL INTERN_DVBT_SoftStop ( void )
531 {
532 #if 1
533 MS_U16 u8WaitCnt=0;
534
535 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
536 {
537 ULOGE("Utopia",">> MB Busy!\n");
538 return FALSE;
539 }
540
541 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
542
543 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
544 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
545
546 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
547 {
548 #if TEST_EMBEDED_DEMOD
549 MsOS_DelayTask(1); // << Ken 20090629
550 #endif
551 if (u8WaitCnt++ >= 0xFF)
552 {
553 ULOGE("Utopia",">> DVBT SoftStop Fail!\n");
554 return FALSE;
555 }
556 }
557
558 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
559 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
560 #endif
561 return TRUE;
562 }
563
564
565 /***********************************************************************************
566 Subject: Reset
567 Function: INTERN_DVBT_Reset
568 Parmeter:
569 Return: MS_BOOL
570 Remark:
571 ************************************************************************************/
572 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)573 MS_BOOL INTERN_DVBT_Reset ( void )
574 {
575 DBG_INTERN_DVBT(ULOGD("Utopia"," @INTERN_DVBT_reset\n"));
576
577 DBG_INTERN_DVBT_TIME(ULOGD("Utopia","INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime()));
578
579 INTERN_DVBT_SoftStop();
580
581
582 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
583 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
584 MsOS_DelayTask(5);
585 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
586 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
587 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
588 MsOS_DelayTask(5);
589
590 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
591 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
592
593 bFECLock = FALSE;
594 bTPSLock = FALSE;
595 u32ChkScanTimeStart = MsOS_GetSystemTime();
596 return TRUE;
597 }
598
599 /***********************************************************************************
600 Subject: Exit
601 Function: INTERN_DVBT_Exit
602 Parmeter:
603 Return: MS_BOOL
604 Remark:
605 ************************************************************************************/
INTERN_DVBT_Exit(void)606 MS_BOOL INTERN_DVBT_Exit ( void )
607 {
608
609 INTERN_DVBT_SoftStop();
610
611 return TRUE;
612 }
613
614 /***********************************************************************************
615 Subject: Load DSP code to chip
616 Function: INTERN_DVBT_LoadDSPCode
617 Parmeter:
618 Return: MS_BOOL
619 Remark:
620 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)621 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
622 {
623 MS_U8 udata = 0x00;
624 MS_U16 i;
625 MS_U16 fail_cnt=0;
626
627 #if (DBG_DUMP_LOAD_DSP_TIME==1)
628 MS_U32 u32Time;
629 #endif
630
631
632 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
633 BININFO BinInfo;
634 MS_BOOL bResult;
635 MS_U32 u32GEAddr;
636 MS_U8 Data;
637 MS_S8 op;
638 MS_U32 srcaddr;
639 MS_U32 len;
640 MS_U32 SizeBy4K;
641 MS_U16 u16Counter=0;
642 MS_U8 *pU8Data;
643 #endif
644
645
646
647 // MDrv_Sys_DisableWatchDog();
648
649
650 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
651 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
652 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
653 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
654 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
655 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
656
657 //// Load code thru VDMCU_IF ////
658 DBG_INTERN_DVBT(ULOGD("Utopia",">Load Code...\n"));
659 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
660 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
661 {
662 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
663 }
664 #else
665 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
666 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
667 if ( bResult != PASS )
668 {
669 return FALSE;
670 }
671 //ULOGD("Utopia","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
672
673 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
674 InfoBlock_Flash_2_Checking_Start(&BinInfo);
675 #endif
676
677 #if OBA2
678 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
679 #else
680 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
681 #endif
682
683 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
684 InfoBlock_Flash_2_Checking_End(&BinInfo);
685 #endif
686
687 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
688 SizeBy4K=BinInfo.B_Len/0x1000;
689 //ULOGD("Utopia","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
690
691 #if (DBG_DUMP_LOAD_DSP_TIME==1)
692 u32Time = msAPI_Timer_GetTime0();
693 #endif
694
695 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
696
697 for (i=0;i<=SizeBy4K;i++)
698 {
699 if(i==SizeBy4K)
700 len=BinInfo.B_Len%0x1000;
701 else
702 len=0x1000;
703
704 srcaddr = u32GEAddr+(0x1000*i);
705 //ULOGD("Utopia","\t i = %08X\n", i);
706 //ULOGD("Utopia","\t len = %08X\n", len);
707 op = 1;
708 u16Counter = 0 ;
709 //ULOGD("Utopia","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
710 while(len--)
711 {
712 u16Counter ++ ;
713 //ULOGD("Utopia","file: %s, line: %d\n", __FILE__, __LINE__);
714 //pU8Data = (U8 *)(srcaddr|0x80000000);
715 #if OBA2
716 pU8Data = (U8 *)(srcaddr);
717 #else
718 pU8Data = (U8 *)(srcaddr|0x80000000);
719 #endif
720 Data = *pU8Data;
721
722 #if 0
723 if(u16Counter < 0x100)
724 ULOGD("Utopia","0x%bx,", Data);
725 #endif
726 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
727
728 srcaddr += op;
729 }
730 // ULOGD("Utopia","\n\n\n");
731 }
732
733 #if (DBG_DUMP_LOAD_DSP_TIME==1)
734 ULOGD("Utopia","------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
735 #endif
736
737 #endif
738
739 //// Content verification ////
740 DBG_INTERN_DVBT(ULOGD("Utopia",">Verify Code...\n"));
741
742 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
743 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
744
745 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
746 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
747 {
748 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
749 if (udata != INTERN_DVBT_table[i])
750 {
751 ULOGE("Utopia",">fail add = 0x%x\n", i);
752 ULOGE("Utopia",">code = 0x%x\n", INTERN_DVBT_table[i]);
753 ULOGE("Utopia",">data = 0x%x\n", udata);
754
755 if (fail_cnt++ > 10)
756 {
757 ULOGE("Utopia",">DVB-T DSP Loadcode fail!");
758 return false;
759 }
760 }
761 }
762 #else
763 for (i=0;i<=SizeBy4K;i++)
764 {
765 if(i==SizeBy4K)
766 len=BinInfo.B_Len%0x1000;
767 else
768 len=0x1000;
769
770 srcaddr = u32GEAddr+(0x1000*i);
771 //ULOGD("Utopia","\t i = %08LX\n", i);
772 //ULOGD("Utopia","\t len = %08LX\n", len);
773 op = 1;
774 u16Counter = 0 ;
775 //ULOGD("Utopia","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
776 while(len--)
777 {
778 u16Counter ++ ;
779 //ULOGD("Utopia","file: %s, line: %d\n", __FILE__, __LINE__);
780 //pU8Data = (U8 *)(srcaddr|0x80000000);
781 #if OBA2
782 pU8Data = (U8 *)(srcaddr);
783 #else
784 pU8Data = (U8 *)(srcaddr|0x80000000);
785 #endif
786 Data = *pU8Data;
787
788 #if 0
789 if(u16Counter < 0x100)
790 ULOGD("Utopia","0x%bx,", Data);
791 #endif
792 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
793 if (udata != Data)
794 {
795 ULOGE("Utopia",">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
796 ULOGE("Utopia",">code = 0x%x\n", Data);
797 ULOGE("Utopia",">data = 0x%x\n", udata);
798
799 if (fail_cnt++ > 10)
800 {
801 ULOGE("Utopia",">DVB-T DSP Loadcode fail!");
802 return false;
803 }
804 }
805
806 srcaddr += op;
807 }
808 // ULOGD("Utopia","\n\n\n");
809 }
810 #endif
811
812 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
813 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
814 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
815 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
816
817 DBG_INTERN_DVBT(ULOGD("Utopia",">DSP Loadcode done."));
818 //while(load_data_variable);
819
820
821 return TRUE;
822 }
823
824 /***********************************************************************************
825 Subject: DVB-T CLKGEN initialized function
826 Function: INTERN_DVBT_Power_On_Initialization
827 Parmeter:
828 Return: MS_BOOL
829 Remark:
830 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)831 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
832 {
833 MS_U8 temp_val;
834 MS_U8 udatatemp = 0x00;
835 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
836 // HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
837
838 // Release vivaldi2mi_bridge reset
839 // [0] reg_vivaldi2mi_bridge_rst
840 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
841 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
842 // HAL_DMD_RIU_WriteByte(0x11208E, (HAL_DMD_RIU_ReadByte(0x11208E)&(~(BIT(0)))));
843
844 // ----------------------------------------------
845 // start demod CLKGEN setting
846 // ----------------------------------------------
847 // *** Set register at CLKGEN1
848 // enable DMD MCU clock "bit[0] set 0"
849 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
850 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
851 // CLK_DMDMCU clock setting
852 // [0] disable clock
853 // [1] invert clock
854 // [4:2]
855 // 000:170 MHz(MPLL_DIV_BUf)
856 // 001:160MHz
857 // 010:144MHz
858 // 011:123MHz
859 // 100:108MHz
860 // 101:mem_clcok
861 // 110:mem_clock div 2
862 // 111:select XTAL
863 HAL_DMD_RIU_WriteByte(0x10331f,0x00);//5566
864 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
865
866 // set parallet ts clock
867 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
868 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
869
870 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b
871 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
872 temp_val|=0x07;
873 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
874
875 HAL_DMD_RIU_WriteByte(0x103300,0x17);
876
877 // enable atsc, DVBTC ts clock
878 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
879 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
880 HAL_DMD_RIU_WriteByte(0x103309,0x00);
881 HAL_DMD_RIU_WriteByte(0x103308,0x00);
882
883 // enable dvbc adc clock
884 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
885 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
886 HAL_DMD_RIU_WriteByte(0x103315,0x00);
887 HAL_DMD_RIU_WriteByte(0x103314,0x00);
888
889 udatatemp = HAL_DMD_RIU_ReadByte(0x111f2a);//5566
890 HAL_DMD_RIU_WriteByte(0x111f2a,udatatemp&0xF8);//5566
891
892 // Reset TS divider
893 HAL_DMD_RIU_WriteByte(0x103302,0x01);
894 HAL_DMD_RIU_WriteByte(0x103302,0x00);
895
896 // enable vif DAC clock
897 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
898 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
899 // HAL_DMD_RIU_WriteByte(0x10331b,0x00);
900 // HAL_DMD_RIU_WriteByte(0x10331a,0x00);
901
902 // Select MPLLDIV17
903 // [0] : reg_atsc_adc_sel_mplldiv2
904 // [1] : reg_atsc_eq_sel_mplldiv2
905 // [2] : reg_eq25_sel_mplldiv3
906 // [3] : reg_p4_cfo_sel_eq25
907 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
908 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0003);
909 // HAL_DMD_RIU_WriteByte(0x111f28,0x03);
910
911 // *** Set register at CLKGEN_DMD
912 // enable atsc clock
913 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
914 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0000);
915 // HAL_DMD_RIU_WriteByte(0x111f03,0x04);
916 // HAL_DMD_RIU_WriteByte(0x111f02,0x04);
917 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
918 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
919 // HAL_DMD_RIU_WriteByte(0x111f05,0x00);
920 // HAL_DMD_RIU_WriteByte(0x111f04,0x00);
921 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
922 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0000);
923 // HAL_DMD_RIU_WriteByte(0x111f07,0x04);
924 // HAL_DMD_RIU_WriteByte(0x111f06,0x04);
925
926 // enable clk_atsc_adcd_sync
927 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
928 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
929 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
930 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
931
932 // enable dvbt inner clock
933 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
934 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
935 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
936 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
937
938 // enable dvbt inner clock
939 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
940 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
941 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
942 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
943
944 // enable dvbt inner clock
945 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
946 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
947 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
948 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
949
950 // enable dvbc outer clock
951 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
952 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
953 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
954 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
955
956 // enable dvbc inner-c clock
957 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
958 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
959 // HAL_DMD_RIU_WriteByte(0x111f15,0x00);
960 // HAL_DMD_RIU_WriteByte(0x111f14,0x00);
961
962 // enable dvbc eq clock
963 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
964 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
965 // HAL_DMD_RIU_WriteByte(0x111f17,0x00);
966 // HAL_DMD_RIU_WriteByte(0x111f16,0x00);
967
968 // enable sram clock
969 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
970 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
971 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
972 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
973
974 // select clock
975 // [3:0] : reg_ckg_frontend
976 // [0] : disable clock
977 // [1] : invert clock
978 // [3:2]: Select clock source
979 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
980 // 01: select clk_dmdadc (48 MHz, DVBT/C)
981 // 10: reserved
982 // 11: select DFT_CLK
983 // [7:4] : reg_ckg_tr
984 // [0] : disable clock
985 // [1] : invert clock
986 // [3:2]: Select clock source
987 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
988 // 01: select clk_dmdadc (48 MHz, DVBT/C)
989 // 10: reserved
990 // 11: select DFT_CLK
991 // [11:8]: reg_ckg_acifir
992 // [0] : disable clock
993 // [1] : invert clock
994 // [3:2]: Select clock source
995 // 00: select clk_dmplldiv17_div2 (25.41 MHz, ATSC)
996 // 01: select clk_dmdadc (48 MHz, DVBT/C)
997 // 10: clk_vif_ssc_mux (43.2~50.82 MHz, VIF)
998 // 11: select DFT_CLK
999 // [15:12]: reg_ckg_frontend_d2
1000 // [0] : disable clock
1001 // [1] : invert clock
1002 // [3:2]: Select clock source
1003 // 00: clk_dmdadc_div2
1004 // 01: clk_dmplldiv17_div4(12.705 MHz)
1005 // 10: reserved
1006 // 11: select DFT_CLK
1007 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1008 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1009 // HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1010 // HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1011
1012 // enable isdbt clock
1013 // [2:0] : reg_ckg_isdbt_inner1x
1014 // [0] : disable clock
1015 // [1] : invert clock
1016 // [3:2]: Select clock source
1017 // 00: clk_dmplldiv10_div4(21.6MHz, ISDBT only)
1018 // 01: reserved
1019 // 10: reserved
1020 // 11: DFT_CLK
1021 // [6:4]: reg_ckg_isdbt_inner2x
1022 // [0] : disable clock
1023 // [1] : invert clock
1024 // [2]: Select clock source
1025 // 00: clk_dmplldiv10_div2(43.2MHz,ISDBT only)
1026 // 01: reserved
1027 // 10: reserved
1028 // 11: DFT_CLK
1029 // [10:8] : reg_ckg_isdbt_inner4x
1030 // [0] : disable clock
1031 // [1] : invert clock
1032 // [3:2]: Select clock source
1033 // 00: clk_dmplldiv10(86.4 MHz, DVBT only)
1034 // 01: reserved
1035 // 10: reserved
1036 // 11: DFT_CLK
1037 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1038 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1039 // HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1040 // HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1041
1042
1043 // enable isdbt outer clock
1044 // [3:0] : reg_ckg_isdbt_outer1x
1045 // [0] : disable clock
1046 // [1] : invert clock
1047 // [3:2]: Select clock source
1048 // 00: isdbt_clk6_lat (6 MHz)
1049 // 01: isdbt_clk8_lat (8 MHz)
1050 // 10: reserved
1051 // 11: DFT_CLK
1052 // [6:4]: reg_ckg_isdbt_outer4x
1053 // [0] : disable clock
1054 // [1] : invert clock
1055 // [3:2]: Select clock source
1056 // 00: isdbt_clk24_lat(24 MHz)
1057 // 01: isdbt_clk32_lat(32 MHz)
1058 // 10: reserved
1059 // 11: DFT_CLK
1060 // [10:8]: reg_ckg_isdbt_outer6x
1061 // [0] : disable clock
1062 // [1] : invert clock
1063 // [2] : Select clock source
1064 // 00: isdbt_clk36_lat(36 MHz)
1065 // 01: isdbt_clk48_lat(48 MHz)
1066 // 10: reserved
1067 // 11: DFT_CLK
1068 // [14:12]: reg_ckg_isdbt_outer12x
1069 // [0] : disable clock
1070 // [1] : invert clock
1071 // [2] : Select clock source
1072 // 00: isdbt_clk72_lat(72 MHz)
1073 // 01: isdbt_clk96_lat(96 MHz)
1074 // 10: reserved
1075 // 11: DFT_CLK
1076 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1077 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1078 // HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1079 // HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1080
1081 // Enable ISDBT clk_outer_div
1082 // reg_clk_isdbt_outer_div_en[0]
1083 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1084 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1085 // HAL_DMD_RIU_WriteByte(0x111f46,0x01);
1086
1087 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1088 // [1:0] : reg_ckg_dvbtc_sram4_isdbt_inner4x
1089 // [0]: disable clock
1090 // [1]: invert clock
1091 // [5:4] : reg_ckg_dvbtc_sram4_isdbt_outer6x
1092 // [0]: disable clock
1093 // [1]: invert clock
1094 // [9:8] : reg_ckg_adc1x_eq1x
1095 // [0]: disable clock
1096 // [1]: invert clock
1097 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1098 // [0]: disable clock
1099 // [1]: invert clock
1100 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1101 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1102 HAL_DMD_RIU_WriteByte(0x111f49,0x00);
1103 HAL_DMD_RIU_WriteByte(0x111f48,0x00);
1104
1105 // [1:0] : reg_ckg_isdbt_outer6x_dvbt_inner1x
1106 // [0]: disable clock
1107 // [1]: invert clock
1108 // [5:4] : reg_ckg_isdbt_outer6x_dvbt_inner2x
1109 // [0]: disable clock
1110 // [1]: invert clock
1111 // [9:8] : reg_ckg_isdbt_outer6x_dvbt_outer2x
1112 // [0]: disable clock
1113 // [1]: invert clock
1114 // [13:12]: reg_ckg_isdbt_outer6x_dvbt_outer2x_c
1115 // [0]: disable clock
1116 // [1]: invert clock
1117 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1118 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1119 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1120 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1121
1122 // enable isdbt outer clock_rs
1123 // [7:4] : reg_ckg_isdbt_outer_rs
1124 // [0] : disable clock
1125 // [1] : invert clock
1126 // [3:2]: Select clock source
1127 // 00: isdbt_clk36_lat (36 MHz)
1128 // 01: isdbt_clk48_lat (48 MHz)
1129 // 10: clk_dmplldiv3_div4(72 MHz)
1130 // 11: isdbt_clk96_buf (96 MHz)
1131 // enable share isdbt &dvbt logic clock
1132 // [1:0] : reg_ckg_isdbt_inner2x_dvbt_inner2x
1133 // [0]: disable clock
1134 // [1]: invert clock
1135 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1136 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1137 // HAL_DMD_RIU_WriteByte(0x111f4c,0x00);
1138 HAL_DMD_RIU_WriteByte(0x111f4d,0x00);
1139 HAL_DMD_RIU_WriteByte(0x111f4c,0x10);
1140
1141 // enable vif clock
1142 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1143 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1144 // HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1145 // HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1146
1147 // enable DEMODE-DMA clock
1148 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1149 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1150 // HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1151 // HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1152
1153 // select clock
1154 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1155 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1156 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1157 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1158
1159
1160 // [15:12]: reg_ckg_dtmb_sram_dump
1161 // [0] : disable clock
1162 // [1] : invert clock
1163 // [3:2]: Select clock source
1164 // 00: dtmb_clk18_buf(16 MHz)
1165 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1166 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1167 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1168 HAL_DMD_RIU_WriteByte(0x111f71,0x18);
1169 HAL_DMD_RIU_WriteByte(0x111f70,0x81);
1170
1171 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1172 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1173
1174 HAL_DMD_RIU_WriteByte(0x111f4f,0x0c);
1175 HAL_DMD_RIU_WriteByte(0x111f4e,0x40);
1176
1177 HAL_DMD_RIU_WriteByte(0x111f51,0x48);
1178 HAL_DMD_RIU_WriteByte(0x111f50,0x44);
1179
1180 // Enable SAWLESS clock
1181 // reg_ckg_adcd_d2 @0x12[3:0]
1182 // reg_ckg_adcd_d4 @0x12[7:4]
1183 // reg_ckg_adcd_d6 @0x12[11:8]
1184 // reg_ckg_adcd_d12@0x12[15:12]
1185 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1186 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1187 // wriu 0x111f25 0x00
1188 // wriu 0x111f24 0x00
1189 // HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1190 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1191
1192 // ----------------------------------------------
1193 // start demod CLKGEN setting
1194 // ----------------------------------------------
1195
1196 // reg_allpad_in=0
1197 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1198 // `RIU_W((`RIUBASE_CHIP>>1)+7'h50, 2'b11, 16'h0000);
1199 // HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1200 // HAL_DMD_RIU_WriteByte(0x101ea0,0x00);
1201
1202 // reg_ts1config=2
1203 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1204 // `RIU_W((`RIUBASE_CHIP>>1)+7'h57, 2'b11, 16'h1000);
1205 //HAL_DMD_RIU_WriteByte(0x101eaf,0x10);
1206 //HAL_DMD_RIU_WriteByte(0x101eae,0x00);
1207
1208 // select DMD MCU
1209 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1210 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1211 // begin BY temp patch
1212 // HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1213 // HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1214 // end
1215 // HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1216
1217 // wriu 0x111f81 0x00
1218 // wriu 0x111f80 0x00
1219 // wriu 0x111f83 0x00
1220 // wriu 0x111f82 0x00
1221 // wriu 0x111f85 0x00
1222 // wriu 0x111f84 0x00
1223 // wriu 0x111f87 0x00
1224 // wriu 0x111f86 0x00
1225 // wriu 0x111f89 0x44
1226 // wriu 0x111f88 0x44
1227 // wriu 0x111f8b 0x00
1228 // wriu 0x111f8a 0x44
1229
1230 HAL_DMD_RIU_WriteByte(0x111f81,0x00);
1231 HAL_DMD_RIU_WriteByte(0x111f80,0x00);
1232
1233 HAL_DMD_RIU_WriteByte(0x111f83,0x00);
1234 HAL_DMD_RIU_WriteByte(0x111f82,0x00);
1235
1236 HAL_DMD_RIU_WriteByte(0x111f85,0x00);
1237 HAL_DMD_RIU_WriteByte(0x111f84,0x00);
1238
1239 HAL_DMD_RIU_WriteByte(0x111f87,0x00);
1240 HAL_DMD_RIU_WriteByte(0x111f86,0x00);
1241
1242 HAL_DMD_RIU_WriteByte(0x111f89,0x44);
1243 HAL_DMD_RIU_WriteByte(0x111f88,0x44);
1244
1245 HAL_DMD_RIU_WriteByte(0x111f8b,0x00);
1246 HAL_DMD_RIU_WriteByte(0x111f8a,0x44);
1247
1248 HAL_DMD_RIU_WriteByte(0x111f8d,0x18);
1249 HAL_DMD_RIU_WriteByte(0x111f8c,0x00);
1250
1251 HAL_DMD_RIU_WriteByte(0x111f8f,0x00);
1252 HAL_DMD_RIU_WriteByte(0x111f8e,0x40);
1253 // ----------------------------------------------
1254 // Turn TSP
1255 // ----------------------------------------------
1256 // turn on ts1_clk, ts0_clk
1257 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1258 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28, 2'b11, 16'h0000);
1259 // check TSP work or not
1260 //HAL_DMD_RIU_WriteByte(0x100b51,0x00);
1261 //HAL_DMD_RIU_WriteByte(0x100b50,0x00);
1262
1263 // stream2miu_en, activate rst_wadr
1264 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1265 // HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1266 // stream2miu_en, turn off rst_wadr
1267 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1268 // wriu 0x000e13 0x01
1269 //HAL_DMD_RIU_WriteByte(0x000e13,0x01);
1270 // udatatemp = HAL_DMD_RIU_ReadByte(0x000e13);
1271 // HAL_DMD_RIU_WriteByte(0x000e13, udatatemp&0xFB);//Set 0e12,Bit10=0,
1272 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1273 }
1274
1275 /***********************************************************************************
1276 Subject: Power on initialized function
1277 Function: INTERN_DVBT_Power_On_Initialization
1278 Parmeter:
1279 Return: MS_BOOL
1280 Remark:
1281 ************************************************************************************/
1282
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)1283 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
1284 {
1285 MS_U16 status = true;
1286 MS_U8 cData = 0;
1287 //U8 cal_done;
1288 DBG_INTERN_DVBT(ULOGD("Utopia","INTERN_DVBT_Power_On_Initialization\n"));
1289
1290 #if defined(PWS_ENABLE)
1291 Mapi_PWS_Stop_VDMCU();
1292 #endif
1293
1294 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
1295 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1296 //// Firmware download //////////
1297 DBG_INTERN_DVBT(ULOGD("Utopia","INTERN_DVBT Load DSP...\n"));
1298 //MsOS_DelayTask(100);
1299
1300
1301 {
1302 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1303 {
1304 ULOGE("Utopia","DVB-T Load DSP Code Fail\n");
1305 return FALSE;
1306 }
1307 else
1308 {
1309 DBG_INTERN_DVBT(ULOGD("Utopia","DVB-T Load DSP Code OK\n"));
1310 }
1311 }
1312
1313
1314 //// MCU Reset //////////
1315 DBG_INTERN_DVBT(ULOGD("Utopia","INTERN_DVBT Reset...\n"));
1316 if (INTERN_DVBT_Reset() == FALSE)
1317 {
1318 DBG_INTERN_DVBT(ULOGE("Utopia","Fail\n"));
1319 return FALSE;
1320 }
1321 else
1322 {
1323 DBG_INTERN_DVBT(ULOGD("Utopia","OK\n"));
1324 }
1325
1326 // reset FDP
1327 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1328 // SRAM setting, DVB-T use it.
1329 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1330 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1331 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1332
1333 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1334 return status;
1335 }
1336
1337 /************************************************************************************************
1338 Subject: Driving control
1339 Function: INTERN_DVBT_Driving_Control
1340 Parmeter: bInversionEnable : TRUE For High
1341 Return: void
1342 Remark:
1343 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1344 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1345 {
1346 MS_U8 u8Temp;
1347
1348 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1349
1350 if (bEnable)
1351 {
1352 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1353 }
1354 else
1355 {
1356 u8Temp = u8Temp & (~0x01);
1357 }
1358
1359 DBG_INTERN_DVBT(ULOGD("Utopia","---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1360 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1361 }
1362 /************************************************************************************************
1363 Subject: Clk Inversion control
1364 Function: INTERN_DVBT_Clk_Inversion_Control
1365 Parmeter: bInversionEnable : TRUE For Inversion Action
1366 Return: void
1367 Remark:
1368 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1369 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1370 {
1371 MS_U8 u8Temp;
1372
1373 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1374
1375 if (bInversionEnable)
1376 {
1377 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1378 }
1379 else
1380 {
1381 u8Temp = u8Temp & (~0x02);
1382 }
1383
1384 DBG_INTERN_DVBT(ULOGD("Utopia","---> Inversion(Bit9) = 0x%x \n",u8Temp));
1385 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1386 }
1387 /************************************************************************************************
1388 Subject: Transport stream serial/parallel control
1389 Function: INTERN_DVBT_Serial_Control
1390 Parmeter: bEnable : TRUE For serial
1391 Return: MS_BOOL :
1392 Remark:
1393 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1394 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1395 {
1396 MS_U8 status = true;
1397 MS_U8 temp_val;
1398 DBG_INTERN_DVBT(ULOGD("Utopia"," @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk));
1399
1400 return status;
1401 if (u8TSClk == 0xFF) u8TSClk=0x13;
1402 if (bEnable) //Serial mode for TS pad
1403 {
1404 // serial
1405 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1406 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1407
1408 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1409 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1410 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1411
1412 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1413 temp_val|=0x04;
1414 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1415 #else
1416 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1417 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1418 temp_val|=0x07;
1419 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1420 #endif
1421 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1422 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1423
1424 //// INTERN_DVBT TS Control: Serial //////////
1425 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1426
1427 gsCmdPacket.param[0] = TS_SERIAL;
1428 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1429 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1430 #else
1431 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1432 #endif
1433 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1434 }
1435 else
1436 {
1437 //parallel
1438 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1439 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1440
1441 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1442 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1443 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1444 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1445 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1446 temp_val|=0x05;
1447 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1448 #else
1449 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1450 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1451 temp_val|=0x07;
1452 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1453 #endif
1454
1455 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1456 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1457
1458 //// INTERN_DVBT TS Control: Parallel //////////
1459 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1460
1461 gsCmdPacket.param[0] = TS_PARALLEL;
1462 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1463 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1464 #else
1465 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1466 #endif
1467 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1468 }
1469
1470 DBG_INTERN_DVBT(ULOGD("Utopia","---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1471
1472 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1473 return status;
1474 }
1475
1476 /************************************************************************************************
1477 Subject: TS1 output control
1478 Function: INTERN_DVBT_PAD_TS1_Enable
1479 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1480 Return: void
1481 Remark:
1482 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1483 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1484 {
1485 DBG_INTERN_DVBT(ULOGD("Utopia"," @INTERN_DVBT_TS1_Enable... \n"));
1486
1487 if(flag) // PAD_TS1 Enable TS CLK PAD
1488 {
1489 //ULOGD("Utopia","=== TS1_Enable ===\n");
1490 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1491 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1492 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1493 }
1494 else // PAD_TS1 Disable TS CLK PAD
1495 {
1496 //ULOGD("Utopia","=== TS1_Disable ===\n");
1497 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1498 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1499 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1500 }
1501 }
1502
1503 /************************************************************************************************
1504 Subject: channel change config
1505 Function: INTERN_DVBT_Config
1506 Parmeter: BW: bandwidth
1507 Return: MS_BOOL :
1508 Remark:
1509 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1510 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1511 {
1512 MS_U8 bandwidth;
1513 MS_U8 status = true;
1514
1515 DBG_INTERN_DVBT(ULOGD("Utopia"," @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap));
1516 DBG_INTERN_DVBT_TIME(ULOGD("Utopia","INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime()));
1517
1518 if (u8TSClk == 0xFF) u8TSClk=0x13;
1519 switch(BW)
1520 {
1521 case E_DMD_RF_CH_BAND_6MHz:
1522 bandwidth = 1;
1523 break;
1524 case E_DMD_RF_CH_BAND_7MHz:
1525 bandwidth = 2;
1526 break;
1527 case E_DMD_RF_CH_BAND_8MHz:
1528 default:
1529 bandwidth = 3;
1530 break;
1531 }
1532
1533 status &= INTERN_DVBT_Reset();
1534
1535 // BW mode
1536 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1537 // TS mode
1538 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1539 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1540 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1541 // Hierarchy mode
1542 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1543 // FC
1544 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1545 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1546 // FS
1547 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1548 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1549 // IQSwap
1550 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1551
1552 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1553 // Fif
1554 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1555 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1556
1557 return status;
1558 }
1559 /************************************************************************************************
1560 Subject: enable hw to lock channel
1561 Function: INTERN_DVBT_Active
1562 Parmeter: bEnable
1563 Return: MS_BOOL
1564 Remark:
1565 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1566 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1567 {
1568 MS_U8 status = true;
1569
1570 DBG_INTERN_DVBT(ULOGD("Utopia"," @INTERN_DVBT_active\n"));
1571
1572 //// INTERN_DVBT Finite State Machine on/off //////////
1573 #if 0
1574 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1575
1576 gsCmdPacket.param[0] = (MS_U8)bEnable;
1577 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1578 #else
1579 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1580 #endif
1581 INTERN_DVBT_SignalQualityReset();
1582
1583 return status;
1584 }
1585 /************************************************************************************************
1586 Subject: Return lock status
1587 Function: INTERN_DVBT_Lock
1588 Parmeter: eStatus :
1589 Return: MS_BOOL
1590 Remark:
1591 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1592 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1593 {
1594 float fBER=0.0f;
1595
1596 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1597 {
1598 if (bFECLock == FALSE)
1599 {
1600 u32FecFirstLockTime = MsOS_GetSystemTime();
1601 DBG_INTERN_DVBT(ULOGD("Utopia","++++++++[utopia]dvbt lock\n"));
1602 }
1603
1604 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1605 {
1606 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1607 {
1608 if(fViterbiBerFiltered <= 0.0)
1609 fViterbiBerFiltered = fBER;
1610 else
1611 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1612 }
1613 DBG_INTERN_DVBT(ULOGD("Utopia","[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1614 }
1615 u32FecLastLockTime = MsOS_GetSystemTime();
1616 bFECLock = TRUE;
1617 return E_DMD_LOCK;
1618 }
1619 else
1620 {
1621 INTERN_DVBT_SignalQualityReset();
1622 if (bFECLock == TRUE)
1623 {
1624 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1625 {
1626 return E_DMD_LOCK;
1627 }
1628 }
1629 bFECLock = FALSE;
1630 }
1631
1632 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1633 {
1634 ULOGD("Utopia","==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1635 return E_DMD_UNLOCK;
1636 }
1637
1638 if(!bTPSLock)
1639 {
1640 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1641 {
1642 DBG_INTERN_DVBT(ULOGD("Utopia","==> INTERN_DVBT_Lock -- TPSLock \n"););
1643 bTPSLock = TRUE;
1644 }
1645 }
1646 if(bTPSLock)
1647 {
1648 DBG_INTERN_DVBT(ULOGD("Utopia","TPSLock %ld\n",MsOS_GetSystemTime()));
1649 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1650 {
1651 return E_DMD_CHECKING;
1652 }
1653 }
1654 else
1655 {
1656 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1657 {
1658 return E_DMD_CHECKING;
1659 }
1660 }
1661 return E_DMD_UNLOCK;
1662
1663 }
1664
1665
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1666 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1667 {
1668 MS_U16 u16Address = 0;
1669 MS_U8 cData = 0;
1670 MS_U8 cBitMask = 0;
1671
1672 switch( eStatus )
1673 {
1674 case E_DMD_COFDM_FEC_LOCK:
1675 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1676
1677 if (cData == 0x0B)
1678 {
1679 return TRUE;
1680 }
1681 else
1682 {
1683 return FALSE; // continuously un-lock
1684 }
1685 break;
1686
1687 case E_DMD_COFDM_PSYNC_LOCK:
1688 u16Address = 0x232C; //FEC: P-sync Lock,
1689 cBitMask = BIT(1);
1690 break;
1691
1692 case E_DMD_COFDM_TPS_LOCK:
1693 u16Address = 0x2222; //TPS HW Lock,
1694 cBitMask = BIT(1);
1695 break;
1696
1697 case E_DMD_COFDM_DCR_LOCK:
1698 u16Address = 0x2737; //DCR Lock,
1699 cBitMask = BIT(0);
1700 break;
1701
1702 case E_DMD_COFDM_AGC_LOCK:
1703 u16Address = 0x271D; //AGC Lock,
1704 cBitMask = BIT(0);
1705 break;
1706
1707 case E_DMD_COFDM_MODE_DET:
1708 u16Address = 0x24CF; //Mode CP Detect,
1709 cBitMask = BIT(4);
1710 break;
1711
1712 case E_DMD_COFDM_TPS_EVER_LOCK:
1713 u16Address = 0x20C0; //TPS Ever Lock,
1714 cBitMask = BIT(3);
1715 break;
1716
1717 case E_DMD_COFDM_NO_CHANNEL:
1718 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1719 cBitMask = BIT(7);
1720 break;
1721
1722 default:
1723 return FALSE;
1724 }
1725
1726 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1727 return FALSE;
1728
1729 if ((cData & cBitMask) == cBitMask)
1730 {
1731 return TRUE;
1732 }
1733
1734 return FALSE;
1735
1736 }
1737
1738 /****************************************************************************
1739 Subject: To get the Post viterbi BER
1740 Function: INTERN_DVBT_GetPostViterbiBer
1741 Parmeter: Quility
1742 Return: E_RESULT_SUCCESS
1743 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1744 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1745 We will not read the Period, and have the "/256/8"
1746 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1747 MS_BOOL INTERN_DVBT_GetPostViterbiBer(float *ber)
1748 {
1749 MS_BOOL status = true;
1750 MS_U8 reg=0, reg_frz=0;
1751 MS_U16 BitErrPeriod;
1752 MS_U32 BitErr;
1753 MS_U16 PktErr;
1754
1755 /////////// Post-Viterbi BER /////////////
1756
1757 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1758 {
1759 *ber = (float)-1.0;
1760 return false;
1761 }
1762 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1763 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1764 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1765
1766 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1767 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1768 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1769 BitErrPeriod = reg;
1770
1771 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1772 BitErrPeriod = (BitErrPeriod << 8)|reg;
1773
1774 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1775 // 0x6b [15:8] reg_bit_err_num_15_8
1776 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1777 // 0x6d [15:8] reg_bit_err_num_31_24
1778 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1779 BitErr = reg;
1780
1781 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1782 BitErr = (BitErr << 8)|reg;
1783
1784 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1785 BitErr = (BitErr << 8)|reg;
1786
1787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1788 BitErr = (BitErr << 8)|reg;
1789
1790 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1791 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1792 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1793 PktErr = reg;
1794
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1796 PktErr = (PktErr << 8)|reg;
1797
1798 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1799 reg_frz=reg_frz&(~0x03);
1800 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1801
1802 if (BitErrPeriod == 0 ) //protect 0
1803 BitErrPeriod = 1;
1804
1805 if (BitErr <=0 )
1806 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1807 else
1808 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1809
1810
1811 DBG_GET_SIGNAL(ULOGD("Utopia","INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1812 DBG_GET_SIGNAL(ULOGD("Utopia","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1813
1814 return status;
1815 }
1816
1817 /****************************************************************************
1818 Subject: To get the Pre viterbi BER
1819 Function: INTERN_DVBT_GetPreViterbiBer
1820 Parmeter: ber
1821 Return: E_RESULT_SUCCESS
1822 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1823 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1824 We will not read the Period, and have the "/256/8"
1825 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1826 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1827 {
1828 MS_U8 status = true;
1829 MS_U8 reg=0, reg_frz=0;
1830 MS_U16 BitErrPeriod;
1831 MS_U32 BitErr;
1832 MS_BOOL BEROver;
1833
1834 // bank 7 0x10 [3] reg_rd_freezeber
1835 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1836 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1837
1838 // bank 7 0x16 [7:0] reg_ber_timerl
1839 // [15:8] reg_ber_timerm
1840 // bank 7 0x18 [5:0] reg_ber_timerh
1841 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1842 BitErrPeriod = reg&0x3f;
1843
1844 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1845 BitErrPeriod = (BitErrPeriod << 8)|reg;
1846
1847 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1848 BitErrPeriod = (BitErrPeriod << 8)|reg;
1849
1850 // bank 7 0x1e [7:0] reg_ber_7_0
1851 // [15:8] reg_ber_15_8
1852 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1853 BitErr = reg;
1854
1855 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1856 BitErr = (BitErr << 8)|reg;
1857
1858 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1859 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1860 if (reg & 0x10)
1861 BEROver = true;
1862 else
1863 BEROver = false;
1864
1865 if (BitErrPeriod ==0 )//protect 0
1866 BitErrPeriod=1;
1867
1868 if (BEROver)
1869 {
1870 *ber = 1;
1871 ULOGD("Utopia","BER is over\n");
1872 }
1873 else
1874 {
1875 if (BitErr <=0 )
1876 *ber=0.5 / (float)(BitErrPeriod * 256);
1877 else
1878 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1879 }
1880
1881 // bank 7 0x10 [3] reg_rd_freezeber
1882 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1883
1884 return status;
1885 }
1886
1887 /****************************************************************************
1888 Subject: To get the Packet error
1889 Function: INTERN_DVBT_GetPacketErr
1890 Parmeter: pktErr
1891 Return: E_RESULT_SUCCESS
1892 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1893 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1894 We will not read the Period, and have the "/256/8"
1895 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1896 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1897 {
1898 MS_BOOL status = true;
1899 MS_U8 reg = 0, reg_frz = 0;
1900 MS_U16 PktErr;
1901
1902 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1903 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1904 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1905
1906 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1907 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1908 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1909 PktErr = reg;
1910
1911 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1912 PktErr = (PktErr << 8)|reg;
1913
1914 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1915 reg_frz=reg_frz&(~0x03);
1916 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1917
1918 DBG_GET_SIGNAL(ULOGD("Utopia","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1919
1920 *u16PktErr = PktErr;
1921
1922 return status;
1923 }
1924
1925 /****************************************************************************
1926 Subject: To get the DVBT parameter
1927 Function: INTERN_DVBT_Get_TPS_Info
1928 Parmeter: point to return parameter
1929 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1930 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1931 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1932 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1933 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1934 FFT ( b14) : 0~1 => 2K, 8K
1935 Priority(bit 15) : 0~1=> HP,LP
1936 Return: TRUE
1937 FALSE
1938 Remark: The TPS parameters will be available after TPS lock
1939 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1940 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1941 {
1942 MS_U8 u8Temp;
1943
1944 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1945 return FALSE;
1946
1947 if ((u8Temp& 0x02) != 0x02)
1948 {
1949 return FALSE; //TPS unlock
1950 }
1951 else
1952 {
1953 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1954 return FALSE;
1955
1956 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1957 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1958
1959 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1960 return FALSE;
1961
1962 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1963 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1964
1965 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1966 return FALSE;
1967
1968 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1969 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1970
1971 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1972 return FALSE;
1973
1974 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
1975
1976 }
1977 return TRUE;
1978 }
1979
1980
1981 /****************************************************************************
1982 Subject: Read the signal to noise ratio (SNR)
1983 Function: INTERN_DVBT_GetSNR
1984 Parmeter: None
1985 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1986 Remark:
1987 *****************************************************************************/
INTERN_DVBT_GetSNR(void)1988 float INTERN_DVBT_GetSNR (void)
1989 {
1990 MS_U8 status = true;
1991 MS_U8 reg=0, reg_frz=0;
1992 MS_U32 noise_power;
1993 float snr;
1994
1995 // bank 6 0xfe [0] reg_fdp_freeze
1996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
1997 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
1998
1999 // bank 6 0xff [0] reg_fdp_load
2000 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2001
2002 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
2003 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
2004 noise_power = reg & 0x07;
2005
2006 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
2007 noise_power = (noise_power << 8)|reg;
2008
2009 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
2010 noise_power = (noise_power << 8)|reg;
2011
2012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
2013 noise_power = (noise_power << 8)|reg;
2014
2015 // bank 6 0x26 [5:4] reg_transmission_mode
2016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2017
2018 // bank 6 0xfe [0] reg_fdp_freeze
2019 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
2020
2021 // bank 6 0xff [0] reg_fdp_load
2022 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2023
2024 #if 1 // copy from utopia2\mxlib\hal\miami\demod\halDMD_INTERN_DVBT.c
2025 noise_power = noise_power/2;
2026 noise_power /=1280;
2027 // noisepower = (rand()%256)*256;
2028 if (noise_power==0)//protect value 0
2029 noise_power=1;
2030
2031 #ifdef MSOS_TYPE_LINUX
2032 snr = 10*log10f((float)noise_power);
2033 #else
2034 snr = 10*Log10Approx((float)noise_power);
2035 #endif
2036
2037
2038 #else
2039 noise_power = noise_power/2;
2040
2041 if ((reg&0x30)==0x00) //2K
2042 {
2043 if (noise_power<1512)
2044 snr = 0;
2045 else
2046 #ifdef MSOS_TYPE_LINUX
2047 snr = 10*log10f((float)noise_power/1512);
2048 #else
2049 snr = 10*Log10Approx((float)noise_power/1512);
2050 #endif
2051 }
2052 //else if ((reg&0x30)==0x10)//8K
2053 else
2054 {
2055 if (noise_power<6048)
2056 snr = 0;
2057 else
2058 #ifdef MSOS_TYPE_LINUX
2059 snr = 10*log10f((float)noise_power/6048);
2060 #else
2061 snr = 10*Log10Approx((float)noise_power/6048);
2062 #endif
2063 }
2064 /* ignore 4K
2065 else //4K
2066 {
2067 if (noise_power<3024)
2068 snr = 0;
2069 else
2070 snr = 10*Log10Approx(noise_power/3024);
2071 }
2072 */
2073 #endif
2074
2075 if (status == true)
2076 return snr;
2077 else
2078 return -1;
2079
2080 }
2081
2082 /****************************************************************************
2083 Subject: To check if Hierarchy on
2084 Function: INTERN_DVBT_Is_HierarchyOn
2085 Parmeter:
2086 Return: BOOLEAN
2087 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)2088 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
2089 {
2090 MS_U16 u16_tmp;
2091
2092 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
2093 return FALSE;
2094 //ULOGD("Utopia","u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
2095 if(u16_tmp&0x38)
2096 {
2097 return TRUE;
2098 }
2099 return FALSE;
2100 }
2101
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2102 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2103 {
2104 MS_U8 status = true;
2105 float ch_power_db = 0.0f;
2106 float ch_power_ref = 11.0f;
2107 float ch_power_rel = 0.0f;
2108 MS_U8 u8_index = 0;
2109 MS_U16 tps_info_qam,tps_info_cr;
2110
2111 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2112 {
2113 *strength = 0;
2114 return TRUE;
2115 }
2116 DBG_INTERN_DVBT_TIME(ULOGD("Utopia","INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2117
2118 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
2119 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
2120 /* Actually, it's more reasonable, that signal level depended on cable input power level
2121 * thougth the signal isn't dvb-t signal.
2122 */
2123
2124 // use pointer of IFAGC table to identify
2125 // case 1: RFAGC from SAR, IFAGC controlled by demod
2126 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2127 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2128 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
2129 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2130 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2131 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
2132 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
2133
2134
2135 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
2136 ULOGE("Utopia","[dvbt]TPS qam parameter retrieve failure\n");
2137
2138 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
2139 ULOGE("Utopia","[dvbt]TPS cr parameter retrieve failure\n");
2140
2141
2142 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2143 {
2144 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
2145 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
2146 {
2147 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2148 break;
2149 }
2150 else
2151 {
2152 u8_index++;
2153 }
2154 }
2155
2156 if (ch_power_ref > 10.0f)
2157 *strength = 0;
2158 else
2159 {
2160 ch_power_rel = ch_power_db - ch_power_ref;
2161
2162 if ( ch_power_rel < -15.0f )
2163 {
2164 *strength = 0;
2165 }
2166 else if ( ch_power_rel < 0.0f )
2167 {
2168 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2169 }
2170 else if ( ch_power_rel < 20 )
2171 {
2172 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2173 }
2174 else if ( ch_power_rel < 35.0f )
2175 {
2176 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2177 }
2178 else
2179 {
2180 *strength = 100;
2181 }
2182 }
2183
2184 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2185 {
2186 *strength = 0;
2187 return TRUE;
2188 }
2189
2190 DBG_GET_SIGNAL(ULOGD("Utopia",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2191 DBG_GET_SIGNAL(ULOGD("Utopia",">>> SSI = %d <<<\n", (int)*strength));
2192
2193 return status;
2194 }
2195
2196 /****************************************************************************
2197 Subject: To get the DVT Signal quility
2198 Function: INTERN_DVBT_GetSignalQuality
2199 Parmeter: Quility
2200 Return: E_RESULT_SUCCESS
2201 E_RESULT_FAILURE
2202 Remark: Here we have 4 level range
2203 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2204 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2205 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2206 <4>.4th Range => Quality <10
2207 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2208 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2209 {
2210 float ber_sqi;
2211 float fber;
2212 float cn_rec = 0;
2213 float cn_nordig_p1 = 0;
2214 float cn_rel = 0;
2215
2216 MS_U8 status = true;
2217 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
2218 MS_U16 u16_tmp;
2219
2220 DBG_INTERN_DVBT_TIME(ULOGD("Utopia","INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2221
2222 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
2223 {
2224
2225 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2226 {
2227 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2228 }
2229 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
2230 if(fViterbiBerFiltered<= 0.0)
2231 {
2232 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
2233 {
2234 DBG_INTERN_DVBT(ULOGE("Utopia","GetPostViterbiBer Fail!\n"));
2235 return FALSE;
2236 }
2237 fViterbiBerFiltered = fber;
2238 }
2239 else
2240 {
2241 fber = fViterbiBerFiltered;
2242 }
2243
2244 if (fber > 1.0E-3)
2245 ber_sqi = 0.0;
2246 else if (fber > 8.5E-7)
2247 #ifdef MSOS_TYPE_LINUX
2248 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2249 #else
2250 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2251 #endif
2252 else
2253 ber_sqi = 100.0;
2254
2255 cn_rec = INTERN_DVBT_GetSNR();
2256
2257 if (cn_rec == -1) //get SNR return fail
2258 status = false;
2259
2260 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2261 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2262 tps_cnstl = 0xff;
2263 tps_cr = 0xff;
2264 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
2265 tps_cnstl = (MS_U8)u16_tmp&0x07;
2266 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
2267 tps_cr = (MS_U8)u16_tmp&0x07;
2268
2269 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
2270 {
2271 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
2272 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
2273 {
2274 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
2275 break;
2276 }
2277 }
2278
2279 // 0,5, snr offset
2280 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
2281
2282 // patch....
2283 // Noridg SQI,
2284 // 64QAM, CR34, GI14, SNR 22dB.
2285 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
2286 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
2287 {
2288 cn_rel += 1.5f;
2289 }
2290
2291 if (cn_rel < -7.0f)
2292 {
2293 *quality = 0;
2294 }
2295 else if (cn_rel < 3.0)
2296 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
2297 else
2298 *quality = (MS_U16)ber_sqi;
2299 }
2300 else
2301 {
2302 *quality = 0;
2303 }
2304
2305 DBG_GET_SIGNAL(ULOGD("Utopia","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2306 DBG_GET_SIGNAL(ULOGD("Utopia","BER = %8.3e\n", fber));
2307 DBG_GET_SIGNAL(ULOGD("Utopia","Signal Quility = %d\n", *quality));
2308 return status;
2309 }
2310
2311 /****************************************************************************
2312 Subject: To get the Cell ID
2313 Function: INTERN_DVBT_Get_CELL_ID
2314 Parmeter: point to return parameter cell_id
2315
2316 Return: TRUE
2317 FALSE
2318 Remark:
2319 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2320 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2321 {
2322 MS_U8 status = true;
2323 MS_U8 value1=0;
2324 MS_U8 value2=0;
2325
2326 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2327 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2328
2329 *cell_id = ((MS_U16)value1<<8)|value2;
2330 return status;
2331 }
2332 /*
2333 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2334 {
2335 #define SQI_LOOP_NUM 50
2336 U8 inn = 0;
2337 WORD sqi = 0;
2338 WORD ave_sqi = 0;
2339 WORD ave_num = 0;
2340 while(inn++<SQI_LOOP_NUM)
2341 {
2342 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2343 {
2344 ULOGD("Utopia","[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2345 ave_sqi+=sqi;
2346 ave_num++;
2347 }
2348 MsOS_DelayTask(50);
2349 }
2350
2351 if(ave_num != 0 )
2352 *quality = ave_sqi/ave_num;
2353
2354 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2355 }
2356 */
2357 /****************************************************************************
2358 Subject: To get the DVBT Carrier Freq Offset
2359 Function: INTERN_DVBT_Get_FreqOffset
2360 Parmeter: Frequency offset (in KHz), bandwidth
2361 Return: E_RESULT_SUCCESS
2362 E_RESULT_FAILURE
2363 Remark:
2364 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2365 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2366 {
2367 float N, FreqB;
2368 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2369 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2370 MS_U8 reg_frz=0, reg=0;
2371 MS_U8 status;
2372
2373 FreqB = (float)u8BW * 8 / 7;
2374
2375 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2376
2377 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2378
2379 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2380 RegCfoTd = reg;
2381
2382 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2383 RegCfoTd = (RegCfoTd << 8)|reg;
2384
2385 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2386 RegCfoTd = (RegCfoTd << 8)|reg;
2387
2388 FreqCfoTd = (float)RegCfoTd;
2389
2390 if (RegCfoTd & 0x800000)
2391 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2392
2393 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2394
2395 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2396
2397 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2398 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2399
2400 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2401
2402 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2403 RegCfoFd = reg;
2404
2405 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2406 RegCfoFd = (RegCfoFd << 8)|reg;
2407
2408 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2409 RegCfoFd = (RegCfoFd << 8)|reg;
2410
2411 FreqCfoFd = (float)RegCfoFd;
2412
2413 if (RegCfoFd & 0x800000)
2414 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2415
2416 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2417
2418 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2419 RegIcfo = reg & 0x07;
2420
2421 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2422 RegIcfo = (RegIcfo << 8)|reg;
2423
2424 FreqIcfo = (float)RegIcfo;
2425
2426 if (RegIcfo & 0x400)
2427 FreqIcfo = FreqIcfo - (float)0x800;
2428
2429 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2430 reg = reg & 0x30;
2431
2432 switch (reg)
2433 {
2434 case 0x00: N = 2048; break;
2435 case 0x20: N = 4096; break;
2436 case 0x10:
2437 default: N = 8192; break;
2438 }
2439
2440 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2441 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2442 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2443 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2444 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2445 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2446 // DBG_GET_SIGNAL(ULOGD("Utopia","FCFO = %f\n", FreqCfoFd));
2447 // DBG_GET_SIGNAL(ULOGD("Utopia","TCFO = %f\n", FreqCfoTd));
2448 // DBG_GET_SIGNAL(ULOGD("Utopia","ICFO = %f\n", FreqIcfo));
2449 DBG_GET_SIGNAL(ULOGD("Utopia","CFOE = %f\n", *pFreqOff));
2450
2451 if (status == TRUE)
2452 return TRUE;
2453 else
2454 return FALSE;
2455 }
2456
2457
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2458 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2459 {
2460
2461 bPowerOn = bPowerOn;
2462 }
2463
INTERN_DVBT_Power_Save(void)2464 MS_BOOL INTERN_DVBT_Power_Save(void)
2465 {
2466
2467 return TRUE;
2468 }
2469
2470 /****************************************************************************
2471 Subject: To get the DVBT constellation parameter
2472 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2473 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2474 Return: TRUE
2475 FALSE
2476 Remark: The TPS parameters will be available after TPS lock
2477 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2478 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2479 {
2480 MS_U8 tps_param;
2481
2482 //@@++ Arki 20100125
2483 if (eSignalType == TS_MODUL_MODE)
2484 {
2485 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2486 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2487 }
2488
2489 if (eSignalType == TS_CODE_RATE)
2490 {
2491 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2492 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2493 }
2494
2495 if (eSignalType == TS_GUARD_INTERVAL)
2496 {
2497 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2498 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2499 }
2500
2501 if (eSignalType == TS_FFX_VALUE)
2502 {
2503 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2504 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2505 }
2506 //@@-- Arki 20100125
2507 return TRUE;
2508 }
2509
INTERN_DVBT_Version(MS_U16 * ver)2510 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2511 {
2512
2513 MS_U8 status = true;
2514 MS_U8 tmp = 0;
2515 MS_U16 u16_INTERN_DVBT_Version;
2516
2517 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2518 u16_INTERN_DVBT_Version = tmp;
2519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2520 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2521 *ver = u16_INTERN_DVBT_Version;
2522
2523 return status;
2524 }
2525
INTERN_DVBT_Version_minor(MS_U8 * ver2)2526 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2527 {
2528
2529 MS_U8 status = true;
2530
2531 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2532
2533 return status;
2534 }
2535
2536
INTERN_DVBT_Show_Demod_Version(void)2537 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2538 {
2539
2540 MS_BOOL status = true;
2541 MS_U16 u16_INTERN_DVBT_Version;
2542 MS_U8 u8_minor_ver = 0;
2543
2544 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2545 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2546 ULOGD("Utopia","[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2547
2548 return status;
2549 }
2550
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2551 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2552 {
2553 MS_U8 u8_index = 0;
2554 MS_BOOL bRet = false;
2555
2556 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2557 {
2558 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2559 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2560 {
2561 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2562 bRet = true;
2563 break;
2564 }
2565 else
2566 {
2567 u8_index++;
2568 }
2569 }
2570 return bRet;
2571 }
2572
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2573 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2574 {
2575 MS_U8 u8_index = 0;
2576 MS_BOOL bRet = false;
2577
2578 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2579 {
2580 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2581 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2582 {
2583 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2584 bRet = true;
2585 break;
2586 }
2587 else
2588 {
2589 u8_index++;
2590 }
2591 }
2592 return bRet;
2593 }
2594
2595
2596 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2597 void INTERN_DVBT_get_demod_state(MS_U8* state)
2598 {
2599 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2600 return;
2601 }
2602
INTERN_DVBT_Show_ChannelLength(void)2603 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2604 {
2605 MS_U8 status = true;
2606 MS_U8 tmp = 0;
2607 MS_U16 len = 0;
2608 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2609 len = tmp;
2610 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2611 len = (len<<8)|tmp;
2612 ULOGD("Utopia","[dvbt]Hw_channel=%d\n",len);
2613 return status;
2614 }
2615
INTERN_DVBT_Show_SW_ChannelLength(void)2616 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2617 {
2618 MS_U8 status = true;
2619 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2620 MS_U16 sw_len = 0;
2621 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2622 sw_len = tmp;
2623 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2624 sw_len = (sw_len<<8)|tmp;
2625 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2626 peak_num = tmp;
2627 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2628 insideGI = tmp&0x01;
2629 stoptracking = (tmp&0x02)>>1;
2630 flag_short_echo = (tmp&0x0C)>>2;
2631 fsa_mode = (tmp&0x30)>>4;
2632
2633 ULOGD("Utopia","[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2634 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2635
2636 return status;
2637 }
2638
INTERN_DVBT_Show_ACI_CI(void)2639 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2640 {
2641
2642 #define BIT4 0x10
2643 MS_U8 status = true;
2644 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2645
2646 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2647 digACI = (tmp&BIT4)>>4;
2648
2649 // get flag_CI
2650 // 0: No interference
2651 // 1: CCI
2652 // 2: in-band ACI
2653 // 3: N+1 ACI
2654 // flag_ci = (tmp&0xc0)>>6;
2655 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2656 flag_CI = (tmp&0xC0)>>6;
2657 td_coef = (tmp&0x0C)>>2;
2658
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2660
2661 ULOGD("Utopia","[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2662
2663 return status;
2664 }
2665
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2666 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2667 {
2668 MS_U8 status = true;
2669 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2670 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2671 fd = tmp;
2672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2673 ch_len = tmp;
2674 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2675 snr_sel = (tmp>>4)&0x03;
2676 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2677 pertone_num = tmp;
2678
2679 ULOGD("Utopia","[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2680
2681 return status;
2682 }
2683
INTERN_DVBT_Get_CFO(void)2684 MS_BOOL INTERN_DVBT_Get_CFO(void)
2685 {
2686
2687 float N = 0, FreqB = 0;
2688 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2689 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2690 MS_U8 reg_frz = 0, reg = 0;
2691 MS_U8 status = 0;
2692 MS_U8 u8BW = 8;
2693
2694 FreqB = (float)u8BW * 8 / 7;
2695
2696 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2697
2698 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2699
2700 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2701 RegCfoTd = reg;
2702
2703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2704 RegCfoTd = (RegCfoTd << 8)|reg;
2705
2706 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2707 RegCfoTd = (RegCfoTd << 8)|reg;
2708
2709 FreqCfoTd = (float)RegCfoTd;
2710
2711 if (RegCfoTd & 0x800000)
2712 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2713
2714 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2715
2716 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2717
2718 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2720
2721 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2722
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2724 RegCfoFd = reg;
2725
2726 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2727 RegCfoFd = (RegCfoFd << 8)|reg;
2728
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2730 RegCfoFd = (RegCfoFd << 8)|reg;
2731
2732 FreqCfoFd = (float)RegCfoFd;
2733
2734 if (RegCfoFd & 0x800000)
2735 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2736
2737 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2738
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2740 RegIcfo = reg & 0x07;
2741
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2743 RegIcfo = (RegIcfo << 8)|reg;
2744
2745 FreqIcfo = (float)RegIcfo;
2746
2747 if (RegIcfo & 0x400)
2748 FreqIcfo = FreqIcfo - (float)0x800;
2749
2750 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2751 reg = reg & 0x30;
2752
2753 switch (reg)
2754 {
2755 case 0x00: N = 2048; break;
2756 case 0x20: N = 4096; break;
2757 case 0x10:
2758 default: N = 8192; break;
2759 }
2760
2761 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2762 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2763 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2764 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2765 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2766
2767 ULOGD("Utopia","[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2768
2769 return status;
2770
2771 }
INTERN_DVBT_Get_SFO(void)2772 MS_BOOL INTERN_DVBT_Get_SFO(void)
2773 {
2774 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2775 MS_BOOL status = true;
2776 MS_U8 reg = 0;
2777 float FreqB = 9.143, FreqS = 45.473; //20.48
2778 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2779 float sfo_value = 0;
2780
2781 // get Reg_TDP_SFO,
2782 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2783 Reg_TDP_SFO = reg;
2784 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2785 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2786 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2787 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2788
2789 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2790
2791 // get Reg_FDP_SFO,
2792 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2793 Reg_FDP_SFO = reg;
2794 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2795 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2796 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2797 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2798
2799 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2800
2801 // get Reg_FSA_SFO,
2802 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2803 Reg_FSA_SFO = reg;
2804 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2805 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2806 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2807 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2808
2809 // get Reg_FSA_IN,
2810 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2811 Reg_FSA_IN = reg;
2812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2813 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2814 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2815
2816 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2817 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2818
2819 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2820 // ULOGD("Utopia","\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2821 ULOGD("Utopia","[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2822
2823
2824 return status;
2825 }
2826
INTERN_DVBT_Get_SYA_status(void)2827 void INTERN_DVBT_Get_SYA_status(void)
2828 {
2829 MS_U8 status = true;
2830 MS_U8 sya_k = 0,reg = 0;
2831 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2832
2833 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2834 sya_k = reg;
2835
2836 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2837 sya_th = reg;
2838 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2839 sya_th = (sya_th<<8)|reg;
2840
2841 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2842 sya_offset = reg;
2843 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2844 sya_offset = (sya_offset<<8)|reg;
2845
2846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2847 len_m = reg;
2848 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2849 len_m = (len_m<<8)|reg;
2850
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2852 len_b = reg;
2853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2854 len_b = (len_b<<8)|reg;
2855
2856
2857 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2858 len_a = reg;
2859 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2860 len_a = (len_a<<8)|reg;
2861
2862
2863 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2864 tracking_reg = reg;
2865
2866
2867 ULOGD("Utopia","[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2868 ULOGD("Utopia","[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2869
2870 return;
2871 }
2872
INTERN_DVBT_Get_cci_status(void)2873 void INTERN_DVBT_Get_cci_status(void)
2874 {
2875 MS_U8 status = true;
2876 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2877
2878 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2879 cci_fsweep = reg;
2880
2881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2882 cci_kp = reg;
2883
2884 ULOGD("Utopia","[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2885
2886 return;
2887 }
2888
INTERN_DVBT_Show_PRESFO_Info(void)2889 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2890 {
2891 MS_U8 tmp = 0;
2892 MS_BOOL status = TRUE;
2893 ULOGD("Utopia","\n[SFO]");
2894 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2895 ULOGD("Utopia","[%x]",tmp);
2896 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2897 ULOGD("Utopia","[%x]",tmp);
2898 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2899 ULOGD("Utopia","[%x]",tmp);
2900 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2901 ULOGD("Utopia","[%x]",tmp);
2902 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2903 ULOGD("Utopia","[%x]",tmp);
2904 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2905 ULOGD("Utopia","[%x]",tmp);
2906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2907 ULOGD("Utopia","[%x]",tmp);
2908 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2909 ULOGD("Utopia","[%x][End]",tmp);
2910
2911 return status;
2912 }
2913
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2914 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2915 {
2916 MS_BOOL status = true;
2917
2918 *locktime = 0xffff;
2919 ULOGE("Utopia","[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2920
2921 status = false;
2922 return status;
2923 }
2924
2925
INTERN_DVBT_Show_Lock_Time_Info(void)2926 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2927 {
2928 MS_U16 locktime = 0;
2929 MS_BOOL status = TRUE;
2930 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2931 ULOGD("Utopia","[DVBT]lock_time = %d ms\n",locktime);
2932 return status;
2933 }
2934
INTERN_DVBT_Show_BER_Info(void)2935 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2936 {
2937 MS_U8 tmp = 0;
2938 MS_BOOL status = TRUE;
2939 ULOGD("Utopia","\n[BER]");
2940 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2941 ULOGD("Utopia","[%x,",tmp);
2942 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2943 ULOGD("Utopia","%x]",tmp);
2944 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2945 ULOGD("Utopia","[%x,",tmp);
2946 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2947 ULOGD("Utopia","%x]",tmp);
2948 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2949 ULOGD("Utopia","[%x,",tmp);
2950 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2951 ULOGD("Utopia","%x][End]",tmp);
2952
2953 return status;
2954
2955 }
2956
2957
INTERN_DVBT_Show_AGC_Info(void)2958 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2959 {
2960 MS_U8 tmp = 0;
2961 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2962 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2963 MS_U16 if_agc_err = 0;
2964 MS_BOOL status = TRUE;
2965 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2966
2967 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2968 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2969 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2970 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2971 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2972 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2973
2974
2975 // select IF gain to read
2976 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2977 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2978
2979 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2980 if_agc_gain = tmp;
2981 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2982 if_agc_gain = (if_agc_gain<<8)|tmp;
2983
2984
2985 // select d1 gain to read.
2986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2987 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2988
2989 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2990 d1_gain = tmp;
2991 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2992 d1_gain = (d1_gain<<8)|tmp;
2993
2994 // select d2 gain to read.
2995 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2996 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2997
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2999 d2_gain = tmp;
3000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3001 d2_gain = (d2_gain<<8)|tmp;
3002
3003 // select IF gain err to read
3004 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3005 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3006
3007 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3008 if_agc_err = tmp;
3009 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3010 if_agc_err = (if_agc_err<<8)|tmp;
3011
3012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3013 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3014 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3015
3016
3017
3018 ULOGD("Utopia","[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3019 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3020
3021 ULOGD("Utopia","[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3022 ULOGD("Utopia","[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3023
3024 return status;
3025
3026 }
3027
INTERN_DVBT_Show_WIN_Info(void)3028 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
3029 {
3030 MS_U8 tmp = 0;
3031 MS_U8 trigger = 0;
3032 MS_U16 win_len = 0;
3033
3034 MS_BOOL status = TRUE;
3035
3036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3037 win_len = tmp;
3038 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3039 win_len = (win_len<<8)|tmp;
3040
3041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3042
3043 ULOGD("Utopia","[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3044
3045 return status;
3046 }
3047
INTERN_DVBT_Show_td_coeff(void)3048 void INTERN_DVBT_Show_td_coeff(void)
3049 {
3050 MS_U8 status = true;
3051 MS_U8 w1 = 0,w2 = 0,reg = 0;
3052
3053 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3054 w1 = reg;
3055
3056 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3057 w2 = reg;
3058
3059 ULOGD("Utopia","[td]w1=0x%x, w2=0x%x\n",w1,w2);
3060
3061 return;
3062 }
3063
3064 /********************************************************
3065 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
3066 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
3067 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3068 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
3069 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
3070 * FFT ( b14) : 0~1 => 2K, 8K
3071 ********************************/
INTERN_DVBT_Show_Modulation_info(void)3072 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
3073 {
3074 MS_U16 tps_info;
3075
3076 // ULOGD("Utopia","[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
3077
3078 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
3079 {
3080 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
3081 MS_U8 constel = tps_info&0x0007;
3082 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
3083 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
3084 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
3085 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
3086
3087 ULOGD("Utopia","tps=0x%x ",tps_info);
3088
3089 switch(fft)
3090 {
3091 case 0:
3092 ULOGD("Utopia","mode = 2K,");
3093 break;
3094 case 1:
3095 ULOGD("Utopia","mode = 8K,");
3096 break;
3097 default:
3098 ULOGE("Utopia","mode = unknow,");
3099 break;
3100 }
3101 switch(constel)
3102 {
3103 case 0:
3104 ULOGD("Utopia"," QPSK, ");
3105 break;
3106 case 1:
3107 ULOGD("Utopia","16QAM, ");
3108 break;
3109 case 2:
3110 ULOGD("Utopia","64QAM, ");
3111 break;
3112 default:
3113 ULOGE("Utopia","unknow QAM, ");
3114 break;
3115 }
3116 switch(gi)
3117 {
3118 case 0:
3119 ULOGD("Utopia","GI=1/32, ");
3120 break;
3121 case 1:
3122 ULOGD("Utopia","GI=1/16, ");
3123 break;
3124 case 2:
3125 ULOGD("Utopia","GI= 1/8, ");
3126 break;
3127 case 3:
3128 ULOGD("Utopia","GI= 1/4, ");
3129 break;
3130 default:
3131 ULOGE("Utopia","unknow GI, ");
3132 break;
3133 }
3134
3135 switch(hp_cr)
3136 {
3137 case 0:
3138 ULOGD("Utopia","HP_CR=1/2, ");
3139 break;
3140 case 1:
3141 ULOGD("Utopia","HP_CR=2/3, ");
3142 break;
3143 case 2:
3144 ULOGD("Utopia","HP_CR=3/4, ");
3145 break;
3146 case 3:
3147 ULOGD("Utopia","HP_CR=5/6, ");
3148 break;
3149 case 4:
3150 ULOGD("Utopia","HP_CR=7/8, ");
3151 break;
3152 default:
3153 ULOGE("Utopia","unknow hp_cr, ");
3154 break;
3155 }
3156
3157 switch(lp_cr)
3158 {
3159 case 0:
3160 ULOGD("Utopia","LP_CR=1/2, ");
3161 break;
3162 case 1:
3163 ULOGD("Utopia","LP_CR=2/3, ");
3164 break;
3165 case 2:
3166 ULOGD("Utopia","LP_CR=3/4, ");
3167 break;
3168 case 3:
3169 ULOGD("Utopia","LP_CR=5/6, ");
3170 break;
3171 case 4:
3172 ULOGD("Utopia","LP_CR=7/8, ");
3173 break;
3174 default:
3175 ULOGE("Utopia","unknow lp_cr, ");
3176 break;
3177 }
3178
3179 ULOGD("Utopia"," Hiearchy=0x%x\n",hiearchy);
3180
3181 // ULOGD("Utopia","\n");
3182 return TRUE;
3183 }
3184 else
3185 {
3186 ULOGE("Utopia","INVALID\n");
3187 return FALSE;
3188 }
3189 }
3190
3191
3192
3193
INTERN_DVBT_Show_BER_PacketErr(void)3194 void INTERN_DVBT_Show_BER_PacketErr(void)
3195 {
3196 float f_ber = 0;
3197 MS_U16 packetErr = 0;
3198 INTERN_DVBT_GetPostViterbiBer(&f_ber);
3199 INTERN_DVBT_GetPacketErr(&packetErr);
3200
3201 ULOGE("Utopia","[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3202 return;
3203 }
3204
INTERN_DVBT_Show_Lock_Info(void)3205 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
3206 {
3207
3208 ULOGE("Utopia","[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
3209 return false;
3210 }
3211
3212
INTERN_DVBT_Show_Demod_Info(void)3213 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
3214 {
3215 MS_U8 demod_state = 0;
3216 MS_BOOL status = true;
3217 static MS_U8 counter = 0;
3218
3219 INTERN_DVBT_get_demod_state(&demod_state);
3220
3221 ULOGD("Utopia","==========[dvbt]state=%d\n",demod_state);
3222 if (demod_state < 5)
3223 {
3224 INTERN_DVBT_Show_Demod_Version();
3225 INTERN_DVBT_Show_AGC_Info();
3226 INTERN_DVBT_Show_ACI_CI();
3227 }
3228 else if(demod_state < 8)
3229 {
3230 INTERN_DVBT_Show_Demod_Version();
3231 INTERN_DVBT_Show_AGC_Info();
3232 INTERN_DVBT_Show_ACI_CI();
3233 INTERN_DVBT_Show_ChannelLength();
3234 INTERN_DVBT_Get_CFO();
3235 INTERN_DVBT_Get_SFO();
3236 INTERN_DVBT_Show_td_coeff();
3237 }
3238 else if(demod_state < 11)
3239 {
3240 INTERN_DVBT_Show_Demod_Version();
3241 INTERN_DVBT_Show_AGC_Info();
3242 INTERN_DVBT_Show_ACI_CI();
3243 INTERN_DVBT_Show_ChannelLength();
3244 INTERN_DVBT_Get_CFO();
3245 INTERN_DVBT_Get_SFO();
3246 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3247 INTERN_DVBT_Get_SYA_status();
3248 INTERN_DVBT_Show_td_coeff();
3249 }
3250 else if((demod_state == 11) && ((counter%4) == 0))
3251 {
3252 INTERN_DVBT_Show_Demod_Version();
3253 INTERN_DVBT_Show_AGC_Info();
3254 INTERN_DVBT_Show_ACI_CI();
3255 INTERN_DVBT_Show_ChannelLength();
3256 INTERN_DVBT_Get_CFO();
3257 INTERN_DVBT_Get_SFO();
3258 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3259 INTERN_DVBT_Get_SYA_status();
3260 INTERN_DVBT_Show_td_coeff();
3261 INTERN_DVBT_Show_Modulation_info();
3262 INTERN_DVBT_Show_BER_PacketErr();
3263 }
3264 else
3265 status = false;
3266
3267 ULOGD("Utopia","===========================\n");
3268 counter++;
3269
3270 return status;
3271 }
3272 #endif
3273
3274