1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #include <stdio.h>
101 #include <math.h>
102
103 #include "drvDMD_DTMB.h"
104
105 #include "MsTypes.h"
106 #if DMD_DTMB_UTOPIA_EN || DMD_DTMB_UTOPIA2_EN
107 #include "drvDMD_common.h"
108 #include "halDMD_INTERN_common.h"
109 #endif
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114
115 #define DMD_DTMB_CHIP_NIKON 0x00
116 #define DMD_DTMB_CHIP_NASA 0x01
117 #define DMD_DTMB_CHIP_MADISON 0x02
118 #define DMD_DTMB_CHIP_MONACO 0x03
119 #define DMD_DTMB_CHIP_MUJI 0x04
120 #define DMD_DTMB_CHIP_MONET 0x05
121 #define DMD_DTMB_CHIP_MANHATTAN 0x06
122 #define DMD_DTMB_CHIP_MESSI 0x07
123
124 #if defined(nikon)
125 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
126 #elif defined(nasa)
127 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
128 #elif defined(madison)
129 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
130 #elif defined(monaco)
131 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
132 #elif defined(muji)
133 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
134 #elif defined(monet)
135 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
136 #elif defined(manhattan)
137 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
138 #elif defined(messi)
139 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
140 #else
141 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
142 #endif
143
144 //-------------------------------------------------------------------------------------------------
145 // Local Defines
146 //-------------------------------------------------------------------------------------------------
147
148 #define HAL_INTERN_DTMB_DBINFO(y) //y
149
150 //#define MBRegBase 0x112600
151 //#define DMDMcuBase 0x103480
152
153 #define DTMB_REG_BASE 0x2600
154
155 #define DTMB_ACI_COEF_SIZE 112
156
157 //-------------------------------------------------------------------------------------------------
158 // Local Variables
159 //-------------------------------------------------------------------------------------------------
160
161 const MS_U8 INTERN_DTMB_table[] = {
162 #include "DMD_INTERN_DTMB.dat"
163 };
164
165 const MS_U8 INTERN_DTMB_6M_table[] = {
166 #include "DMD_INTERN_DTMB_6M.dat"
167 };
168
169 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
170 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
171 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
172 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
173 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
174
175 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
176 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
177 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
178 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
179 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
180
181 //-------------------------------------------------------------------------------------------------
182 // Global Variables
183 //-------------------------------------------------------------------------------------------------
184
185 extern MS_U8 u8DMD_DTMB_DMD_ID;
186
187 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
188
189 //-------------------------------------------------------------------------------------------------
190 // Local Functions
191 //-------------------------------------------------------------------------------------------------
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)192 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
193 {
194 MS_U8 u8CheckCount;
195 MS_U8 u8CheckFlag;
196
197 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
198 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
199 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
200 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
201
202 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
203 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
204
205 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
206 {
207 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
208 if ((u8CheckFlag&0x01)==0)
209 break;
210 MsOS_DelayTask(1);
211 }
212
213 if (u8CheckFlag&0x01)
214 {
215 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
216 return FALSE;
217 }
218
219 return TRUE;
220 }
221
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)222 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
223 {
224 MS_U8 u8CheckCount;
225 MS_U8 u8CheckFlag;
226
227 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
228 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
229 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
230
231 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
232 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
233
234 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
235 {
236 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
237 if ((u8CheckFlag&0x02)==0)
238 {
239 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
240 break;
241 }
242 MsOS_DelayTask(1);
243 }
244
245 if (u8CheckFlag&0x02)
246 {
247 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
248 return FALSE;
249 }
250
251 return TRUE;
252 }
253
254 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)255 static void _HAL_INTERN_DTMB_InitClk(void)
256 {
257 MS_U8 u8Val = 0;
258
259 printf("--------------DMD_DTMB_CHIP_NIKON--------------\n");
260
261 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
262 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
263
264 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
265 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
266 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
267 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
268 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
269 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
270 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
271 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
272
273 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
274 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
275 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
276 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
277 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
278 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
279 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
280 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
281 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
282 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
283 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
284 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
285 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
286 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
287 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
288 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
289 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
290 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
291 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
292 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
293 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
294 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
295 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
296 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
297 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
298 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
299 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
300 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
301 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
302
303 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
304 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
305 }
306 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)307 static void _HAL_INTERN_DTMB_InitClk(void)
308 {
309 MS_U8 u8Val = 0;
310
311 printf("--------------DMD_DTMB_CHIP_NASA--------------\n");
312
313 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
314 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
315
316 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
317 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
318 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
319 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
320 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
321 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
322 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
323 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
324
325 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
326 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
327 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
328 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
329 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
330 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
331 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
332 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
333 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
334 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
335 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
336 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
337 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
338 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
339 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
340 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
341 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
342 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
343 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
344 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
345 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
346 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
347 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
348 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
349 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
350 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
351 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
352 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
353 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
354
355 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
356 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
357 }
358 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)359 static void _HAL_INTERN_DTMB_InitClk(void)
360 {
361 MS_U8 u8Val = 0;
362
363 printf("--------------DMD_DTMB_CHIP_MADISON--------------\n");
364
365 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
366 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
367
368 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
369 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
370 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
371 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
372 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
373 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
374 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
375 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
376
377 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
378 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
379
380 //carl
381 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
382 HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
383 HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
384 HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
385
386 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
387 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
388 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
389 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
390 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
391 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
392 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
393 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
394
395 //carl
396 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
397 HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
398
399 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
400 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
401 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
402 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
403 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
404 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
405 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
406 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
407 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
408 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
409 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
410 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
411 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
412 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
413 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
414 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
415 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
416 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
417 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
418
419 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
420 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
421 }
422 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)423 static void _HAL_INTERN_DTMB_InitClk(void)
424 {
425 MS_U8 u8Val = 0;
426
427 printf("--------------DMD_DTMB_CHIP_MONACO--------------\n");
428
429 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
430 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
431
432 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
433 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
434
435 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
436 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
437
438 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
439 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
440 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
441 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
442
443 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
444 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
445
446 //carl
447 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
448 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
449
450 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
451 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
452 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
453 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
454 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
455 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
456 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
457 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
458 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
459 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
460
461 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
462 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
463 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
464 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
465
466 //carl
467 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
468 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
469 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
470 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
471
472 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
473 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
474
475 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
476
477 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
478 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
479 }
480 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)481 static void _HAL_INTERN_DTMB_InitClk(void)
482 {
483 MS_U8 u8Val = 0;
484
485 printf("--------------DMD_DTMB_CHIP_MUJI--------------\n");
486
487 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
488 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
489
490 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
491 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
492
493 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
494 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
495
496 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
497 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
498 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
499 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
500 HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
501 HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
502
503 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
504 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
505
506 //carl
507 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
508 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
509
510 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
511 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
512 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
513 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
514 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
515 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
516 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
517 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
518 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
519 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
520
521 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
522 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
523 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
524 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
525
526 //carl
527 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
528 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
529 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
530 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
531
532 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
533 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
534
535 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
536
537 HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
538 HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
539
540 HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
541 HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
542
543 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
544 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
545 }
546 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)547 static void _HAL_INTERN_DTMB_InitClk(void)
548 {
549 MS_U8 u8Val = 0;
550
551 printf("--------------DMD_DTMB_CHIP_MONET--------------\n");
552
553 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
554 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
555
556 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
557 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
558
559 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
560 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
561
562 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
563 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
564 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
565 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
566 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
567 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
568
569 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
570 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
571
572 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
573 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
574
575 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
576 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
577 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
578 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
579
580 HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
581 HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
582
583 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
584 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
585 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
586 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
587 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
588 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
589
590 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
591 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
592 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
593 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
594
595 //carl
596 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
597 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
598
599 HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
600 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
601
602
603 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
604 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
605
606 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
607 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
608
609 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
610 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
611
612 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
613 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
614
615 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
616 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
617
618 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
619 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
620 }
621 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)622 static void _HAL_INTERN_DTMB_InitClk(void)
623 {
624 MS_U8 u8Val = 0;
625
626 printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n");
627
628 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
629 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
630
631 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
632 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
633
634 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
635 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
636
637 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
638 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
639 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
640 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
641 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
642 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
643
644 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
645 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
646
647 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
648 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
649
650 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
651 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
652 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
653 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
654
655 // HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
656 // HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
657
658 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
659 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
660 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
661 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
662 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
663 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
664
665 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
666 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
667 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
668 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
669
670 //carl
671 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
672 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
673
674 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
675 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
676
677
678 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
679 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
680
681 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
682 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
683
684 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
685 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
686
687 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
688 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
689
690 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
691 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
692
693 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
694 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
695
696 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
697 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
698
699 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
700 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
701
702 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
703 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
704
705 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
706 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
707
708
709 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
710 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
711
712 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
713 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
714 }
715 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI)
_HAL_INTERN_DTMB_InitClk(void)716 static void _HAL_INTERN_DTMB_InitClk(void)
717 {
718 MS_U8 u8Val = 0;
719
720 printf("--------------DMD_DTMB_CHIP_MESSI--------------\n");
721
722 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
723 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
724
725 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
726 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
727
728 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
729 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
730
731 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
732 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
733 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
734 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
735 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
736 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
737
738 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
739 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
740
741 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
742 //HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
743 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
744
745 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
746 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
747 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
748 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
749
750 // HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
751 // HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
752
753 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
754 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
755 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
756 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
757 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
758 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
759
760 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
761 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
762 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
763 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
764
765 //carl
766 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
767 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
768
769 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
770 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
771
772
773 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
774 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
775
776 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
777 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
778
779 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
780 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
781
782 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
783 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
784
785 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
786 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
787
788 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
789 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
790
791 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
792 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
793
794 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
795 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
796
797 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
798 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
799
800 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
801 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
802
803
804 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
805 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
806
807 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
808 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
809 }
810 #else
_HAL_INTERN_DTMB_InitClk(void)811 static void _HAL_INTERN_DTMB_InitClk(void)
812 {
813 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
814 }
815 #endif
816
_HAL_INTERN_DTMB_Ready(void)817 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
818 {
819 MS_U8 udata = 0x00;
820
821 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
822
823 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
824 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
825
826 MsOS_DelayTask(1);
827
828 udata = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
829
830 if (udata) return FALSE;
831
832 return TRUE;
833 }
834
_HAL_INTERN_DTMB_Download(void)835 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
836 {
837 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
838
839 MS_U8 udata = 0x00;
840 MS_U16 i = 0;
841 MS_U16 fail_cnt = 0;
842 MS_U8 u8TmpData;
843 MS_U16 u16AddressOffset;
844 const MS_U8 *DTMB_table;
845 MS_U16 u16Lib_size;
846
847 if (pRes->sDMD_DTMB_PriData.bDownloaded)
848 {
849 if (_HAL_INTERN_DTMB_Ready())
850 {
851 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
852 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
853 MsOS_DelayTask(20);
854 return TRUE;
855 }
856 }
857
858 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
859 {
860 DTMB_table = &INTERN_DTMB_6M_table[0];
861 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
862 }
863 else
864 {
865 DTMB_table = &INTERN_DTMB_table[0];
866 u16Lib_size = sizeof(INTERN_DTMB_table);
867 }
868
869 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
870 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
871
872 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
873
874 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
875 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
876 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
877 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
878
879 //// Load code thru VDMCU_IF ////
880 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
881
882 for (i = 0; i < u16Lib_size; i++)
883 {
884 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
885 }
886
887 //// Content verification ////
888 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
889
890 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
891 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
892
893 for (i = 0; i < u16Lib_size; i++)
894 {
895 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
896
897 if (udata != DTMB_table[i])
898 {
899 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
900 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
901 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
902
903 if (fail_cnt++ > 10)
904 {
905 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
906 return FALSE;
907 }
908 }
909 }
910
911 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
912
913 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
914 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
915
916 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
917 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
918 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
919 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
920 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
921 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
922 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
923 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
924 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
925 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
926 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
927 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
928 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
929 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
930 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
931 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
932 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
933 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
934 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
935 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
936
937 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
938 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
939
940 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
941
942 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
943 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
944
945 pRes->sDMD_DTMB_PriData.bDownloaded = true;
946
947 MsOS_DelayTask(20);
948
949 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
950
951 return TRUE;
952 }
953
_HAL_INTERN_DTMB_FWVERSION(void)954 static void _HAL_INTERN_DTMB_FWVERSION(void)
955 {
956 MS_U8 data1,data2,data3;
957
958 _MBX_ReadReg(0x20C4, &data1);
959 _MBX_ReadReg(0x20C5, &data2);
960 _MBX_ReadReg(0x20C6, &data3);
961
962 HAL_INTERN_DTMB_DBINFO(printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
963 }
964
_HAL_INTERN_DTMB_Exit(void)965 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
966 {
967 MS_U8 u8CheckCount = 0;
968
969 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
970
971 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
972 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
973
974 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
975 {
976 MsOS_DelayTaskUs(10);
977
978 if (u8CheckCount++ == 0xFF)
979 {
980 printf(">> DTMB Exit Fail!\n");
981 return FALSE;
982 }
983 }
984
985 printf(">> DTMB Exit Ok!\n");
986
987 return TRUE;
988 }
989
_HAL_INTERN_DTMB_SoftReset(void)990 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
991 {
992 MS_U8 u8Data = 0;
993
994 //Reset FSM
995 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
996
997 while (u8Data!=0x02)
998 {
999 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1000 }
1001
1002 return TRUE;
1003 }
1004
_HAL_INTERN_DTMB_SetACICoef(void)1005 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1006 {
1007 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1008
1009 MS_U8 *ACI_table;
1010 MS_U8 i;
1011 MS_U16 u16AddressOffset;
1012
1013 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1014 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1015 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1016 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1017 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1018 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1019 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1020 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1021 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1022
1023 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1024 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1025
1026 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1027
1028 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1029 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1030 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1031 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1032
1033 //SET SR value
1034 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1035 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1036 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1037 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1038
1039 //set ACI coefficient
1040 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1041 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1042 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1043 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1044 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1045 {
1046 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1047 }
1048
1049 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1050 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1051
1052 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1053
1054 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1055 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1056
1057 MsOS_DelayTask(20);
1058
1059 return TRUE;
1060 }
1061
_HAL_INTERN_DTMB_SetDtmbMode(void)1062 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1063 {
1064 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1065 return _MBX_WriteReg(0x20C0, 0x04);
1066 }
1067
_HAL_INTERN_DTMB_SetModeClean(void)1068 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1069 {
1070 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1071 return _MBX_WriteReg(0x20C0, 0x00);
1072 }
1073
_HAL_INTERN_DTMB_Set_QAM_SR(void)1074 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1075 {
1076 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1077 return _MBX_WriteReg(0x20C0, 0x04);
1078 }
1079
_HAL_INTERN_DTMB_AGCLock(void)1080 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1081 {
1082 MS_U8 data = 0;
1083
1084 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1085
1086 if (data&0x01)
1087 {
1088 return TRUE;
1089 }
1090 else
1091 {
1092 return FALSE;
1093 }
1094 }
1095
_HAL_INTERN_DTMB_PNP_Lock(void)1096 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1097 {
1098 MS_U8 data = 0;
1099 MS_U8 data1 = 0;
1100
1101 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1102 _MBX_ReadReg(0x37BA, &data);
1103 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1104 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1105 _MBX_ReadReg(0x3BBA, &data);
1106 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1107 #else
1108 _MBX_ReadReg(0x22BA, &data);
1109 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1110 #endif
1111
1112 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1113 {
1114 return TRUE;
1115 }
1116 else
1117 {
1118 return FALSE;
1119 }
1120 }
1121
_HAL_INTERN_DTMB_FEC_Lock(void)1122 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1123 {
1124 MS_U8 u8state=0;
1125
1126
1127 _MBX_ReadReg(0x20C1, &u8state);
1128
1129 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1130 {
1131 return TRUE;
1132 }
1133 else
1134 {
1135 return FALSE;
1136 }
1137 }
1138
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1139 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1140 {
1141 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1142
1143 MS_U8 CM, QAM, IL, CR, SiNR;
1144 MS_U8 data_L = 0;
1145 MS_U8 data_H = 0;
1146
1147 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1148 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1149 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1150 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1151 {
1152 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1153 _MBX_ReadReg(0x3790, &data_L);
1154 _MBX_ReadReg(0x3791, &data_H);
1155 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1156 _MBX_ReadReg(0x3B90, &data_L);
1157 _MBX_ReadReg(0x3B91, &data_H);
1158 #else
1159 _MBX_ReadReg(0x2290, &data_L);
1160 _MBX_ReadReg(0x2291, &data_H);
1161 #endif
1162
1163 if (data_L & 0x1)
1164 {
1165 CR = (data_L >> 6) & 0x03;
1166 IL = (data_L >> 3) & 0x01;
1167 QAM = (data_L >> 4) & 0x03;
1168 SiNR = (data_L >> 2) & 0x01;
1169 CM = (data_L >> 1) & 0x01;
1170 }
1171 else
1172 {
1173 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1174 _MBX_ReadReg(0x379E, &data_L);
1175 _MBX_ReadReg(0x379F, &data_H);
1176 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1177 _MBX_ReadReg(0x3B9E, &data_L);
1178 _MBX_ReadReg(0x3B9F, &data_H);
1179 #else
1180 _MBX_ReadReg(0x229E, &data_L);
1181 _MBX_ReadReg(0x229F, &data_H);
1182 #endif
1183
1184 CR = (data_H >> 4) & 0x03;
1185 IL = (data_H >> 6) & 0x01;
1186 QAM = (data_H >> 2) & 0x03;
1187 SiNR = (data_H >> 1) & 0x01;
1188 CM = (data_H) & 0x01;
1189 }
1190
1191 if (CR == 0)
1192 psDtmbGetModulation->fSiCodeRate = 0.4;
1193 else if (CR == 1)
1194 psDtmbGetModulation->fSiCodeRate = 0.6;
1195 else if (CR == 2)
1196 psDtmbGetModulation->fSiCodeRate = 0.8;
1197
1198 if (IL == 0)
1199 psDtmbGetModulation->u8SiInterLeaver = 240;
1200 else
1201 psDtmbGetModulation->u8SiInterLeaver = 720;
1202
1203 if (QAM == 0)
1204 psDtmbGetModulation->u8SiQamMode = 4;
1205 else if (QAM == 1)
1206 psDtmbGetModulation->u8SiQamMode = 16;
1207 else if (QAM == 2)
1208 psDtmbGetModulation->u8SiQamMode = 32;
1209 else if (QAM == 3)
1210 psDtmbGetModulation->u8SiQamMode = 64;
1211
1212 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1213 psDtmbGetModulation->u8SiNR = SiNR;
1214 }
1215 else
1216 {
1217 }
1218
1219 return TRUE;
1220 }
1221
_HAL_INTERN_DTMB_ReadIFAGC(void)1222 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1223 {
1224 MS_U8 data = 0;
1225
1226 _MBX_ReadReg(0x28FD, &data);
1227
1228 return data;
1229 }
1230
_HAL_INTERN_DTMB_ReadFrequencyOffset(void)1231 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1232 {
1233 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1234
1235 MS_U8 u8Data = 0;
1236 MS_S16 fftfirstCfo = 0;
1237 MS_S8 fftSecondCfo = 0;
1238 MS_S16 sr = 0;
1239
1240 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1241 _MBX_ReadReg(0x384D, &u8Data);
1242 fftfirstCfo = u8Data;
1243 _MBX_ReadReg(0x384C, &u8Data);
1244 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1245
1246 _MBX_ReadReg(0x3850, &u8Data);
1247 fftSecondCfo = u8Data;
1248 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1249 _MBX_ReadReg(0x3C4D, &u8Data);
1250 fftfirstCfo = u8Data;
1251 _MBX_ReadReg(0x3C4C, &u8Data);
1252 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1253
1254 _MBX_ReadReg(0x3C50, &u8Data);
1255 fftSecondCfo = u8Data;
1256 #else
1257 _MBX_ReadReg(0x234D, &u8Data);
1258 fftfirstCfo = u8Data;
1259 _MBX_ReadReg(0x234C, &u8Data);
1260 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1261
1262 _MBX_ReadReg(0x2350, &u8Data);
1263 fftSecondCfo = u8Data;
1264 #endif
1265
1266 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1267 sr = 5670;
1268 else sr = 7560;
1269
1270 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1271 }
1272
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1273 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1274 {
1275 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1276
1277 MS_U8 data = 0;
1278 MS_U8 level = 0;
1279 MS_U32 snr = 0;
1280
1281 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1282 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1283 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1284 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1285 {
1286 if (!_HAL_INTERN_DTMB_FEC_Lock())
1287 level = 0;
1288 else
1289 {
1290 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1291 _MBX_ReadReg(0x37DA, &data);
1292 snr = data&0x3F;
1293 _MBX_ReadReg(0x37D9, &data);
1294 snr = (snr<<8)|data;
1295 _MBX_ReadReg(0x37D8, &data);
1296 snr = (snr<<8)|data;
1297 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1298 _MBX_ReadReg(0x3BDA, &data);
1299 snr = data&0x3F;
1300 _MBX_ReadReg(0x3BD9, &data);
1301 snr = (snr<<8)|data;
1302 _MBX_ReadReg(0x3BD8, &data);
1303 snr = (snr<<8)|data;
1304 #else
1305 _MBX_ReadReg(0x22DA, &data);
1306 snr = data&0x3F;
1307 _MBX_ReadReg(0x22D9, &data);
1308 snr = (snr<<8)|data;
1309 _MBX_ReadReg(0x22D8, &data);
1310 snr = (snr<<8)|data;
1311 #endif
1312
1313 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1314 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1315 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1316 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1317 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1318 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1319 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1320 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1321 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1322 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1323 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1324 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1325 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1326 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1327 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1328 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1329 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1330 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1331 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1332 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1333 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1334 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1335 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1336 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1337 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1338 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1339 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1340 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1341 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1342 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1343 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1344 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1345 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1346 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1347 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1348 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1349 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1350 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1351 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1352 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1353 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1354 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1355 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1356 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1357 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1358 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1359 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1360 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1361 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1362 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1363 }
1364 }
1365 else
1366 {
1367 level = 0;
1368 }
1369
1370 return level*2;
1371 }
1372
_HAL_INTERN_DTMB_GetPreLdpcBer(float * pber)1373 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1374 {
1375 MS_U8 u8Data=0;
1376 MS_U32 BitErr;
1377 MS_U16 error_window;
1378
1379 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1380 _MBX_ReadReg(0x2D3B, &u8Data);
1381 BitErr = u8Data;
1382 _MBX_ReadReg(0x2D3A, &u8Data);
1383 BitErr = (BitErr << 8)|u8Data;
1384 _MBX_ReadReg(0x2D39, &u8Data);
1385 BitErr = (BitErr << 8)|u8Data;
1386 _MBX_ReadReg(0x2D38, &u8Data);
1387 BitErr = (BitErr << 8)|u8Data;
1388 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1389 _MBX_ReadReg(0x3F3B, &u8Data);
1390 BitErr = u8Data;
1391 _MBX_ReadReg(0x3F3A, &u8Data);
1392 BitErr = (BitErr << 8)|u8Data;
1393 _MBX_ReadReg(0x3F39, &u8Data);
1394 BitErr = (BitErr << 8)|u8Data;
1395 _MBX_ReadReg(0x3F38, &u8Data);
1396 BitErr = (BitErr << 8)|u8Data;
1397 #else
1398 _MBX_ReadReg(0x263B, &u8Data);
1399 BitErr = u8Data;
1400 _MBX_ReadReg(0x263A, &u8Data);
1401 BitErr = (BitErr << 8)|u8Data;
1402 _MBX_ReadReg(0x2639, &u8Data);
1403 BitErr = (BitErr << 8)|u8Data;
1404 _MBX_ReadReg(0x2638, &u8Data);
1405 BitErr = (BitErr << 8)|u8Data;
1406 #endif
1407
1408 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1409 _MBX_ReadReg(0x2D2F, &u8Data);
1410 error_window = u8Data;
1411 _MBX_ReadReg(0x2D2E, &u8Data);
1412 error_window = (error_window << 8)|u8Data;
1413 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1414 _MBX_ReadReg(0x3F2F, &u8Data);
1415 error_window = u8Data;
1416 _MBX_ReadReg(0x3F2E, &u8Data);
1417 error_window = (error_window << 8)|u8Data;
1418 #else
1419 _MBX_ReadReg(0x262F, &u8Data);
1420 error_window = u8Data;
1421 _MBX_ReadReg(0x262E, &u8Data);
1422 error_window = (error_window << 8)|u8Data;
1423 #endif
1424
1425 *pber=(float)BitErr/7488.0/(float)error_window;
1426
1427 return TRUE;
1428 }
1429
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)1430 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
1431 {
1432 return _MBX_ReadReg(u16Addr, pu8Data);
1433 }
1434
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)1435 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
1436 {
1437 return _MBX_WriteReg(u16Addr, u8Data);
1438 }
1439
1440 //-------------------------------------------------------------------------------------------------
1441 // Global Functions
1442 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)1443 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
1444 {
1445 MS_BOOL bResult = TRUE;
1446
1447 switch(eCmd)
1448 {
1449 case DMD_DTMB_HAL_CMD_Exit:
1450 bResult = _HAL_INTERN_DTMB_Exit();
1451 break;
1452 case DMD_DTMB_HAL_CMD_InitClk:
1453 _HAL_INTERN_DTMB_InitClk();
1454 break;
1455 case DMD_DTMB_HAL_CMD_Download:
1456 bResult = _HAL_INTERN_DTMB_Download();
1457 break;
1458 case DMD_DTMB_HAL_CMD_FWVERSION:
1459 _HAL_INTERN_DTMB_FWVERSION();
1460 break;
1461 case DMD_DTMB_HAL_CMD_SoftReset:
1462 bResult = _HAL_INTERN_DTMB_SoftReset();
1463 break;
1464 case DMD_DTMB_HAL_CMD_SetACICoef:
1465 bResult = _HAL_INTERN_DTMB_SetACICoef();
1466 break;
1467 case DMD_DTMB_HAL_CMD_SetDTMBMode:
1468 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
1469 break;
1470 case DMD_DTMB_HAL_CMD_SetModeClean:
1471 bResult = _HAL_INTERN_DTMB_SetModeClean();
1472 break;
1473 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
1474 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
1475 break;
1476 case DMD_DTMB_HAL_CMD_Active:
1477 break;
1478 case DMD_DTMB_HAL_CMD_AGCLock:
1479 bResult = _HAL_INTERN_DTMB_AGCLock();
1480 break;
1481 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
1482 bResult = _HAL_INTERN_DTMB_PNP_Lock();
1483 break;
1484 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
1485 bResult = _HAL_INTERN_DTMB_FEC_Lock();
1486 break;
1487 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
1488 break;
1489 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
1490 break;
1491 case DMD_DTMB_HAL_CMD_GetModulation:
1492 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
1493 case DMD_DTMB_HAL_CMD_ReadIFAGC:
1494 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
1495 break;
1496 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
1497 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
1498 break;
1499 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
1500 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
1501 break;
1502 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
1503 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
1504 break;
1505 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
1506 break;
1507 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
1508 break;
1509 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
1510 break;
1511 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
1512 break;
1513 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
1514 break;
1515 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
1516 break;
1517 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
1518 break;
1519 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
1520 break;
1521 case DMD_DTMB_HAL_CMD_GET_REG:
1522 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
1523 break;
1524 case DMD_DTMB_HAL_CMD_SET_REG:
1525 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
1526 break;
1527 default:
1528 break;
1529 }
1530
1531 return bResult;
1532 }
1533
MDrv_DMD_DTMB_Initial_Hal_Interface(void)1534 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
1535 {
1536 return TRUE;
1537 }
1538
1539