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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 #include "MsCommon.h"
103 #include "MsIRQ.h"
104 #include "MsOS.h"
105 #include "MsTypes.h"
106 #include "drvMMIO.h"
107 #include "drvDMD_common.h"
108 #include "drvDMD_VD_MBX.h"
109 #include "halDMD_INTERN_common.h"
110
111 #include "ULog.h"
112
113 #if defined (__aeon__) // Non-OS
114 #define BASEADDR_RIU 0xA0000000UL
115 //#elif ( OS_TYPE == linux ) // Linux
116 // #define RIU_BASE u32RegOSBase // MDrv_MIOMap_GetBASE(u32RegOSBase, puSize, MAP_NONPM_BANK)
117 #else // ecos
118 #define BASEADDR_RIU 0xBF800000UL
119 #endif
120
121 #define RIU_MACRO_START do {
122 #define RIU_MACRO_END } while (0)
123
124 // Address bus of RIU is 16 bits.
125 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_DMD.virtDMDBaseAddr + (addr) ) )
126 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_DMD.virtDMDBaseAddr + (addr) ) )
127 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_DMD.virtDMDBaseAddr + (addr), val) }
128 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_DMD.virtDMDBaseAddr + (addr), val) }
129
130 //=============================================================
131 // Standard Form
132
133 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
134
135 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
136
137 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
138
139 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
140 RIU_MACRO_START \
141 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
142 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
143 RIU_MACRO_END
144
145 #define RIU_WriteByte( u32Reg, u8Val ) \
146 RIU_MACRO_START \
147 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
148 RIU_MACRO_END
149
150 #define RIU_Write2Byte( u32Reg, u16Val ) \
151 RIU_MACRO_START \
152 if ( ((u32Reg) & 0x01) ) \
153 { \
154 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
156 } \
157 else \
158 { \
159 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
160 } \
161 RIU_MACRO_END
162
163 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
164 RIU_MACRO_START \
165 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
166 RIU_MACRO_END
167
168
169 typedef struct
170 {
171 MS_VIRT virtDMDBaseAddr;
172 MS_BOOL bBaseAddrInitialized;
173 } hal_DMD_t;
174
175 static hal_DMD_t _hal_DMD = // TODO: review, it would be init in Config()
176 {
177 .virtDMDBaseAddr = BASEADDR_RIU,
178 .bBaseAddrInitialized = 0,
179 };
180
181 extern s_I2C_Interface_func sI2cInterfaceFunc;
182
HAL_DMD_RegInit(void)183 MS_BOOL HAL_DMD_RegInit (void)
184 {
185 MS_VIRT virtNonPMBank;
186 MS_PHY phyNonPMBankSize;
187
188
189 ULOGD("DEMOD","bryan check DMD init!!\n");
190 if (!MDrv_MMIO_GetBASE( &virtNonPMBank, &phyNonPMBankSize, MS_MODULE_PM))
191 {
192 #ifdef MS_DEBUG
193 ULOGD("DEMOD","HAL_DMD_RegInit failure to get MS_MODULE_PM\n");
194 #endif
195 _hal_DMD.virtDMDBaseAddr = BASEADDR_RIU; // TODO what to do if failed??
196 _hal_DMD.bBaseAddrInitialized = 0;
197 return FALSE;
198 }
199
200 //HAL_ParFlash_Config(u32NonPMBank);
201 _hal_DMD.virtDMDBaseAddr=virtNonPMBank;
202 _hal_DMD.bBaseAddrInitialized = 1;
203 return TRUE;
204 }
205
HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)206 MS_U8 HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
207 {
208 if (_hal_DMD.bBaseAddrInitialized)
209 {
210 return RIU_ReadByte(u32Addr);
211 }
212 else
213 {
214 #ifdef MS_DEBUG
215 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
216 #endif
217 }
218 return 0;
219 }
220
HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr,MS_U8 u8Mask)221 MS_U8 HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr, MS_U8 u8Mask)
222 {
223 if (_hal_DMD.bBaseAddrInitialized)
224 {
225 return RIU_ReadRegBit(u32Addr, u8Mask);
226 }
227 else
228 {
229 #ifdef MS_DEBUG
230 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
231 #endif
232 }
233 return 0;
234 }
HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * pu8Data)235 MS_U8 HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *pu8Data)
236 {
237
238 MS_BOOL bRet=TRUE;
239 MS_U8 u8MsbData[6] = {0};
240
241 u8MsbData[0] = 0x10;
242 u8MsbData[1] = 0x00;
243 u8MsbData[2] = 0x00;
244 u8MsbData[3] = (u32Addr >> 8) &0xff;
245 u8MsbData[4] = u32Addr &0xff;
246
247 u8MsbData[0] = 0x35;
248 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
249
250 u8MsbData[0] = 0x10;
251 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 5, u8MsbData);
252 bRet &= sI2cInterfaceFunc.I2C_ReadBytes(u16SlaveAddr, 0, 0, 1, pu8Data);
253
254 u8MsbData[0] = 0x34;
255 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
256
257 return bRet;
258 }
HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)259 MS_U16 HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)
260 {
261 if (_hal_DMD.bBaseAddrInitialized)
262 {
263 return RIU_Read2Byte(u32Addr);
264 }
265 else
266 {
267 #ifdef MS_DEBUG
268 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
269 #endif
270 }
271 return 0;
272 }
273
HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 u8Data)274 MS_U8 HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 u8Data)
275 {
276 MS_BOOL bRet=TRUE;
277 MS_U8 u8MsbData[6] = {0};
278
279 u8MsbData[0] = 0x10;
280 u8MsbData[1] = 0x00;
281 u8MsbData[2] = 0x00;
282 u8MsbData[3] = (u32Addr >> 8) &0xff;
283 u8MsbData[4] = u32Addr &0xff;
284 u8MsbData[5] = u8Data;
285
286 u8MsbData[0] = 0x35;
287 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
288 u8MsbData[0] = 0x10;
289 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 6, u8MsbData);
290 u8MsbData[0] = 0x34;
291 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
292
293 return bRet;
294 }
HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * u8Data,MS_U8 u8Len)295 MS_U8 HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *u8Data, MS_U8 u8Len)
296 {
297 MS_BOOL bRet=TRUE;
298 MS_U16 index;
299 MS_U8 Data[0x80+5];
300
301 Data[0] = 0x10;
302 Data[1] = 0x00;
303 Data[2] = 0x00;
304 Data[3] = (u32Addr >> 8) &0xff;
305 Data[4] = u32Addr &0xff;
306
307 for(index = 0; index < u8Len ; index++)
308 {
309 Data[5+index] = u8Data[index];
310 }
311
312 Data[0] = 0x35;
313 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
314 Data[0] = 0x10;
315 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
316 sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, (5 + u8Len), Data);
317 Data[0] = 0x34;
318 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
319
320 return bRet;
321 }
322
HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr,MS_U8 ch_num)323 MS_BOOL HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr, MS_U8 ch_num)
324 {
325 MS_BOOL bRet=TRUE;
326 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
327 //Exit
328 Data[0] = 0x34;
329 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
330 Data[0]=(ch_num & 0x01)? 0x36 : 0x45;
331 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
332 //Init
333 Data[0] = 0x53;
334 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 5, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 5);
335 Data[0]=(ch_num & 0x04)? 0x80 : 0x81;
336 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
337 if ((ch_num==4)||(ch_num==5)||(ch_num==1))
338 Data[0]=0x82;
339 else
340 Data[0] = 0x83;
341 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
342
343 if ((ch_num==4)||(ch_num==5))
344 Data[0]=0x85;
345 else
346 Data[0] = 0x84;
347
348 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
349 Data[0]=(ch_num & 0x01)? 0x51 : 0x53;
350 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
351 Data[0]=(ch_num & 0x01)? 0x37 : 0x7F;
352 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
353 Data[0] = 0x35;
354 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
355 Data[0] = 0x71;
356 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
357 // MsOS_ReleaseMutex(_s32MutexId);
358 return bRet;
359 }
360
HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr,MS_U8 ch_num)361 MS_BOOL HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr, MS_U8 ch_num)
362 {
363 MS_BOOL bRet=TRUE;
364 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
365 Data[0] = (ch_num & 0x01)? 0x81 : 0x80;
366 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
367 Data[0] = (ch_num & 0x02)? 0x83 : 0x82;
368 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
369 Data[0] = (ch_num & 0x04)? 0x85 : 0x84;
370 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
371
372 return bRet;
373 }
HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)374 void HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
375 {
376 if (_hal_DMD.bBaseAddrInitialized)
377 {
378 RIU_WriteByte(u32Addr, u8Value);
379 }
380 else
381 {
382 #ifdef MS_DEBUG
383 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
384 #endif
385 }
386 }
387
HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr,MS_BOOL bEnable,MS_U8 u8Mask)388 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask)
389 {
390 if (_hal_DMD.bBaseAddrInitialized)
391 {
392 RIU_WriteRegBit(u32Addr, bEnable, u8Mask);
393 }
394 else
395 {
396 #ifdef MS_DEBUG
397 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
398 #endif
399 }
400 }
401
HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)402 void HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
403 {
404 if (_hal_DMD.bBaseAddrInitialized)
405 {
406 RIU_WriteByteMask(u32Addr, u8Value, u8Mask);
407 }
408 else
409 {
410 #ifdef MS_DEBUG
411 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
412 #endif
413 }
414 }
415
HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr,MS_U16 u16Value)416 void HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr, MS_U16 u16Value)
417 {
418 if (_hal_DMD.bBaseAddrInitialized)
419 {
420 RIU_Write2Byte(u32Addr, u16Value);
421 }
422 else
423 {
424 #ifdef MS_DEBUG
425 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
426 #endif
427 }
428 }
429
430 //waiting add
HAL_DMD_IFAGC_RegRead(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)431 MS_BOOL HAL_DMD_IFAGC_RegRead(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
432 {
433 MS_U8 status = true;
434 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0;
435 // bank 5 0x24 [15:0] reg_agc_gain2_out
436 // use only high byte value
437
438 // select IF gain to read
439 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03);
440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, ®_frz);
441 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80);
442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, ®_tmp);
443 *ifagc_reg = reg_tmp;
444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, ®_tmp);
445 *ifagc_reg_lsb = reg_tmp;
446 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz);
447
448 #ifdef MS_DEBUG
449 ULOGD("DEMOD","SSI_IFAGC_H = 0x%x 0x%x\n", *ifagc_reg,*ifagc_reg_lsb);
450 #endif
451
452 *ifagc_err = 0;
453 if(*ifagc_reg == 0xff)
454 {
455 // bank 5 0x04 [15] reg_tdp_lat
456 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00);
457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, ®_frz);
458 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80);
459
460 // bank 5 0x2c [9:0] reg_agc_error
461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, ®_tmp);
462 // if_agc_err = reg_tmp & 0x03;
463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, ®_tmp2);
464 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
465
466 if(reg_tmp&0x2)
467 {
468 *ifagc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
469 }
470 else
471 {
472 *ifagc_err = reg_tmp<<8|reg_tmp2;
473 }
474
475 // release latch
476 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz);
477 }
478
479
480 return status;
481 }
482
483 //waiting mark
484 #if(0)
HAL_DMD_GetRFLevel(float * fRFPowerDbmResult,float fRFPowerDbm,MS_U8 u8SarValue,DMD_RFAGC_SSI * pRfagcSsi,MS_U16 u16RfagcSsi_Size,DMD_IFAGC_SSI * pIfagcSsi_HiRef,MS_U16 u16IfagcSsi_HiRef_Size,DMD_IFAGC_SSI * pIfagcSsi_LoRef,MS_U16 u16IfagcSsi_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_LoRef,MS_U16 u16IfagcErr_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_HiRef,MS_U16 u16IfagcErr_HiRef_Size)485 MS_BOOL HAL_DMD_GetRFLevel(float *fRFPowerDbmResult, float fRFPowerDbm, MS_U8 u8SarValue,
486 DMD_RFAGC_SSI *pRfagcSsi, MS_U16 u16RfagcSsi_Size,
487 DMD_IFAGC_SSI *pIfagcSsi_HiRef, MS_U16 u16IfagcSsi_HiRef_Size,
488 DMD_IFAGC_SSI *pIfagcSsi_LoRef, MS_U16 u16IfagcSsi_LoRef_Size,
489 DMD_IFAGC_ERR *pIfagcErr_LoRef, MS_U16 u16IfagcErr_LoRef_Size,
490 DMD_IFAGC_ERR *pIfagcErr_HiRef, MS_U16 u16IfagcErr_HiRef_Size)
491 {
492 DMD_IFAGC_SSI *ifagc_ssi;
493 DMD_IFAGC_ERR *ifagc_err;
494 float ch_power_db=0.0f;
495 float ch_power_rf=0.0f;
496 float ch_power_if=0.0f, ch_power_ifa = 0.0f, ch_power_ifb =0.0f;
497 float ch_power_takeover=0.0f;
498 MS_U16 if_agc_err = 0;
499 MS_U8 status = true;
500 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0,rf_agc_val =0,if_agc_val =0, if_agc_vala =0, if_agc_valb =0, if_agc_val_lsb =0, i;
501 MS_U8 ssi_tbl_len = 0, err_tbl_len = 0;
502
503 if ((pIfagcSsi_HiRef != NULL) && (pIfagcSsi_LoRef !=NULL))
504 {
505 // get RFAGC level
506 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
507 {
508 rf_agc_val = u8SarValue;
509
510 ch_power_rf=pRfagcSsi[u16RfagcSsi_Size-1].power_db;
511 if (rf_agc_val >=pRfagcSsi[0].sar3_val)
512 {
513 float ch_power_rfa = 0, ch_power_rfb =0;
514 MS_U8 rf_agc_vala =0, rf_agc_valb =0;
515 for(i = 1; i < u16RfagcSsi_Size; i++)
516 {
517 if (rf_agc_val < pRfagcSsi[i].sar3_val)
518 {
519 rf_agc_valb = pRfagcSsi[i].sar3_val;
520 ch_power_rfb = pRfagcSsi[i].power_db;
521
522 i--;
523 rf_agc_vala = pRfagcSsi[i].sar3_val;
524 ch_power_rfa=pRfagcSsi[i].power_db;
525 while ((i>1) && (rf_agc_vala==pRfagcSsi[i-1].sar3_val))
526 {
527 ch_power_rfa=pRfagcSsi[i-1].power_db;
528 i--;
529 }
530 ch_power_rf = ch_power_rfa+(ch_power_rfb-ch_power_rfa)*(float)(rf_agc_val-rf_agc_vala)/(rf_agc_valb-rf_agc_vala);
531 break;
532 }
533 }
534 #ifdef MS_DEBUG
535 ULOGD("DEMOD","RF Level from SAR:%f\n", ch_power_rf);
536 ULOGD("DEMOD","SSI_RFAGC (SAR-4) = 0x%x\n", rf_agc_val);
537 ULOGD("DEMOD","rf prev %f %x\n", ch_power_rfa, rf_agc_vala);
538 ULOGD("DEMOD","rf next %f %x\n", ch_power_rfb, rf_agc_valb);
539 #endif
540 }
541 }
542 else
543 {
544 #ifdef MS_DEBUG
545 ULOGD("DEMOD","RF Level from tuner: %f\n",fRFPowerDbm);
546 #endif
547 ch_power_rf = fRFPowerDbm;
548 }
549
550 // get IFAGC status
551 {
552 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13, ®_tmp);
553
554 #ifdef MS_DEBUG
555 ULOGD("DEMOD","AGC_REF = %d\n", (MS_U16)reg_tmp);
556 #endif
557
558 if (reg_tmp > 200)
559 {
560 ifagc_ssi = pIfagcSsi_HiRef;
561 ssi_tbl_len = u16IfagcSsi_HiRef_Size;
562 ifagc_err = pIfagcErr_HiRef;
563 err_tbl_len = u16IfagcErr_HiRef_Size;
564 }
565 else
566 {
567 ifagc_ssi = pIfagcSsi_LoRef;
568 ssi_tbl_len = u16IfagcSsi_LoRef_Size;
569 ifagc_err = pIfagcErr_LoRef;
570 err_tbl_len = u16IfagcErr_LoRef_Size;
571 }
572
573 // bank 5 0x24 [15:0] reg_agc_gain2_out
574 // use only high byte value
575
576 // select IF gain to read
577 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
578 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
579 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
580 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
581 if_agc_val = reg_tmp;
582 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp);
583 if_agc_val_lsb = reg_tmp;
584 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
585 #ifdef MS_DEBUG
586 ULOGD("DEMOD","SSI_IFAGC_H = 0x%x 0x%x\n", if_agc_val,if_agc_val_lsb);
587 #endif
588
589 ch_power_if=ifagc_ssi[0].power_db;
590 if (if_agc_val >=ifagc_ssi[0].agc_val)
591 {
592 for(i = 1; i < ssi_tbl_len; i++)
593 {
594 if (if_agc_val < ifagc_ssi[i].agc_val)
595 {
596 if_agc_valb = ifagc_ssi[i].agc_val;
597 ch_power_ifb = ifagc_ssi[i].power_db;
598
599 i--;
600 if_agc_vala = ifagc_ssi[i].agc_val;
601 ch_power_ifa=ifagc_ssi[i].power_db;
602 while ((i>1) && (if_agc_vala==ifagc_ssi[i-1].agc_val))
603 {
604 ch_power_ifa=ifagc_ssi[i-1].power_db;
605 i--;
606 }
607 ch_power_if = ch_power_ifa+(ch_power_ifb-ch_power_ifa)*(float)((if_agc_val-if_agc_vala)*256+if_agc_val_lsb)/((if_agc_valb-if_agc_vala)*256);
608 break;
609 }
610 }
611 }
612 #ifdef MS_DEBUG
613 ULOGD("DEMOD","if prev %f %x\n", ch_power_ifa, if_agc_vala);
614 ULOGD("DEMOD","if next %f %x\n", ch_power_ifb, if_agc_valb);
615 #endif
616
617 for(i = 0; i < ssi_tbl_len; i++)
618 {
619 if (ifagc_ssi[i].agc_val <= ifagc_ssi[i+1].agc_val)
620 {
621 ch_power_takeover = ifagc_ssi[i+1].power_db;
622 break;
623 }
624 }
625
626 #ifdef MS_DEBUG
627 ULOGD("DEMOD","ch_power_rf = %f\n", ch_power_rf);
628 ULOGD("DEMOD","ch_power_if = %f\n", ch_power_if);
629 ULOGD("DEMOD","ch_power_takeover = %f\n", ch_power_takeover);
630 #endif
631
632 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_rf : ch_power_if;
633
634 if(ch_power_rf > (ch_power_takeover + 0.5))
635 {
636 ch_power_db = ch_power_rf;
637 }
638 else if(ch_power_if < (ch_power_takeover - 0.5))
639 {
640 ch_power_db = ch_power_if;
641 }
642 else
643 {
644 ch_power_db = (ch_power_if + ch_power_rf)/2;
645 }
646
647 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_if : ch_power_rf;
648
649 ///////// IF-AGC Error for Add. Attnuation /////////////
650 if(if_agc_val == 0xff)
651 {
652 #if 0
653 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
654 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, ®_tmp);
655 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (reg_tmp&0xf0));
656 #endif
657 #endif
658 // bank 5 0x04 [15] reg_tdp_lat
659 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00);
660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
661 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
662 #if 0
663 //#if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
664 // bank 5 0x2c [9:0] reg_agc_error
665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, ®_tmp);
666 // if_agc_err = reg_tmp & 0x03;
667 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, ®_tmp2);
668 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
669 //#else
670 #endif
671 // bank 5 0x2c [9:0] reg_agc_error
672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
673 // if_agc_err = reg_tmp & 0x03;
674 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp2);
675 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
676 //#endif
677
678 if(reg_tmp&0x2)
679 {
680 if_agc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
681 }
682 else
683 {
684 if_agc_err = reg_tmp<<8|reg_tmp2;
685 }
686
687 // release latch
688 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
689
690 for(i = 0; i < err_tbl_len; i++)
691 {
692 if ( if_agc_err <= ifagc_err[i].agc_err ) // signed char comparison
693 {
694 ch_power_db += ifagc_err[i].attn_db;
695 break;
696 }
697 }
698 #ifdef MS_DEBUG
699 ULOGD("DEMOD","if_agc_err = 0x%x\n", if_agc_err);
700 #endif
701 }
702
703 // BY 20110812 temporaily remove ch_power_db += SIGNAL_LEVEL_OFFSET;
704 }
705 }
706 else
707 {
708 #ifdef MS_DEBUG
709 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
710 {
711 ULOGD("DEMOD","Error!! please add AGC table\n");
712 }
713 #endif
714 ch_power_db = fRFPowerDbm;
715 }
716 *fRFPowerDbmResult=ch_power_db;
717 return status;
718 }
719 #endif
720
721 //waiting mark
722 #if(0)
HAL_DMD_GetNordigSSI(float fPrel,MS_U16 * strength)723 void HAL_DMD_GetNordigSSI(float fPrel, MS_U16 *strength)
724 {
725 if (fPrel<-15.0f)
726 {
727 *strength = 0;
728 }
729 else if (fPrel<0.0f)
730 {
731 *strength = (MS_U16)((2.0f/3.0f)*(fPrel+15.0f));
732 }
733 else if (fPrel<20.0f)
734 {
735 *strength = (MS_U16)(4.0f*fPrel+10.0f);
736 }
737 else if (fPrel<35.0f)
738 {
739 *strength = (MS_U16)((2.0f/3.0f)*(fPrel-20.0f)+90.0f);
740 }
741 else
742 {
743 *strength = 100;
744 }
745
746 }
747 #endif
748 /*
749 from Steven.Hung
750 2. �n��T12 TS1 TS bus tristate
751 Set Bank CHIPTOP, 0x57[13:11]=3��h0; (reg_ts1config[2:0]=0)
752 3. �n��T12 IFAGC tristate
753 Set Bank CHIPTOP, 0x2[12]=1��h1; (reg_if_agc_pad_oen=1)
754 */
HAL_DMD_TS1_Tristate(MS_BOOL bEnable)755 void HAL_DMD_TS1_Tristate(MS_BOOL bEnable)
756 {
757 #ifdef MS_DEBUG
758 ULOGD("DEMOD","HAL_DMD_TS1_Tristate %d\n",bEnable);
759 #endif
760 if (bEnable)
761 {
762 HAL_DMD_RIU_WriteByteMask(0x101EAF, 0, BMASK(5:3));
763 }
764 else
765 {
766 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3));
767 }
768 }
769
HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)770 void HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)
771 {
772 MS_U8 u8RegMuxBackup = 0;
773
774 #ifdef MS_DEBUG
775 ULOGD("DEMOD","HAL_DMD_RFAGC_Tristate %d\n",bEnable);
776 #endif
777 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
778 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
779 if (bEnable)
780 {
781 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0)));
782
783 }
784 else
785 {
786 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0)));
787 }
788 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
789 }
790
HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)791 void HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)
792 {
793 MS_U8 u8RegMuxBackup = 0;
794
795 #ifdef MS_DEBUG
796 ULOGD("DEMOD","HAL_DMD_IFAGC_Tristate %d\n",bEnable);
797 #endif
798 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
799 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
800 if (bEnable)
801 {
802 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4)));
803 }
804 else
805 {
806 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4)));
807 }
808 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
809 }
810
HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)811 void HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)
812 {
813 #ifdef MS_DEBUG
814 ULOGD("DEMOD","HAL_DMD_IFAGC_TS_Tristate %d\n",bEnable);
815 #endif
816 HAL_DMD_TS1_Tristate(bEnable);
817 HAL_DMD_IFAGC_Tristate(bEnable);
818 }
819
820 #if(0)
HAL_DMD_TS_GetClockRate(float * fTS_CLK)821 MS_BOOL HAL_DMD_TS_GetClockRate(float *fTS_CLK)
822 {
823 // from Raymond
824 *fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x103300)&BMASK(4:0))+1));
825 return TRUE;
826 }
827 #endif
HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)828 static void HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
829 {
830 if (u8PadSel==0)
831 {
832 HAL_DMD_RIU_WriteByteMask(0x112802, 4<<4, BMASK(6:4));
833 }
834 else
835 {
836 if (bPGAEnable)
837 {
838 HAL_DMD_RIU_WriteByteMask(0x112802, 1<<4, BMASK(6:4));
839 }
840 else
841 {
842 HAL_DMD_RIU_WriteByteMask(0x112802, 2<<4, BMASK(6:4));
843 }
844 }
845 }
846
HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)847 static void HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
848 {
849 if (u8PadSel==0)
850 {
851 HAL_DMD_RIU_WriteByteMask(0x112803, 4, BMASK(2:0));
852 }
853 else
854 {
855 if (bPGAEnable)
856 {
857 HAL_DMD_RIU_WriteByteMask(0x112803, 1, BMASK(2:0));
858 }
859 else
860 {
861 HAL_DMD_RIU_WriteByteMask(0x112803, 2, BMASK(2:0));
862 }
863 }
864 }
865
866
HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)867 static void HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)
868 {
869 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA
870 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping
871 }
872
HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)873 static void HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)
874 {
875 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA
876 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping
877 }
878
879 /************************************************************************************************
880 Subject: ADC I/Q Switch (After Init CLKGen)
881 Function: HAL_DMD_ADC_IQ_Switch
882 Parmeter: u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
883 Parmeter: u8PadSel : 0=Normal, 1=analog pad
884 Parmeter: bPGAEnable : 0=disable, 1=enable
885 Parmeter: u8PGAGain : default 5
886 Return: MS_BOOL :
887 Remark:
888 *************************************************************************************************/
HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain)889 MS_BOOL HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain)
890 {
891 MS_U8 u8RegMuxBackup = 0;
892 u8PGAGain=u8PGAGain;
893 #ifdef MS_DEBUG
894 ULOGD("DEMOD","HAL_DMD_ADC_IQ_Switch %d %d %d %d\n",u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
895 #endif
896
897 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
898 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
899 #ifdef MS_DEBUG
900 ULOGD("DEMOD","before 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
901 #endif
902 switch(u8ADCIQMode)
903 {
904 case 0://Normal case, I path
905 default:
906 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC
907 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
909 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q
910 HAL_DMD_ADC_IMUX_Sel(u8PadSel, bPGAEnable);
911 HAL_DMD_SIF_PGA_Ctl(bPGAEnable);
912 HAL_DMD_VIF_PGA_Ctl(FALSE);
913 break;
914 case 1://VIF, Q path, for internal signal saw
915 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC
916 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(1)); // power on Q ADC
917 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
918 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(5)); // ADC clock out select 0:I, 1:Q
919 HAL_DMD_ADC_QMUX_Sel(u8PadSel, bPGAEnable);
920 HAL_DMD_SIF_PGA_Ctl(FALSE);
921 HAL_DMD_VIF_PGA_Ctl(bPGAEnable);
922 break;
923 case 2://both IQ, for ZIF tuner
924 break;
925 }
926 #ifdef MS_DEBUG
927 ULOGD("DEMOD","after 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
928 #endif
929 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
930 return TRUE;
931 }
932
933 /************************************************************************************************
934 Subject: HAL_DMD_TSO_Clk_Control
935 Function: ts output clock frequency and phase configure
936 Parmeter: u8cmd_array, clock div, 0x01, div (0x00~0x1f),
937 clock phase inv, 0x02, inv_en (0,1),
938 clock phase tuning, 0x03, phase_tuning_en (0,1), tuning_num (0x00~0x1f)
939 Return: MS_BOOL
940 Remark:
941 *************************************************************************************************/
HAL_DMD_TSO_Clk_Control(MS_U8 * u8cmd_array)942 MS_BOOL HAL_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array)
943 {
944 MS_U8 u8Temp;
945
946 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
947
948 if ( (u8Temp&0x01) == 0x00)
949 {
950 ULOGD("DEMOD","[utopia][halDMD]Error!!!, we shall select clk_dmplldiv3\n");
951 return false;
952 }
953 switch (u8cmd_array[0])
954 {
955 case 0x01: // clock frequency,div
956 {
957 MS_U8 u8data = 0;
958 u8data = HAL_DMD_RIU_ReadByte(0x103300);
959 u8data &= (0xff-0x1f);
960 u8data |= (u8cmd_array[1]&0x1f);
961 HAL_DMD_RIU_WriteByte(0x103300, u8data);
962 }
963 break;
964 case 0x02: // clock phase inv or not.
965 {
966 MS_U8 u8data = 0;
967 u8data = HAL_DMD_RIU_ReadByte(0x103301);
968 u8data &= (0xff-0x02);
969 u8data |= ((u8cmd_array[1]&0x01)<<1);
970 HAL_DMD_RIU_WriteByte(0x103301, u8data);
971 }
972 break;
973 case 0x03:
974 {
975 MS_U8 u8data = 0;
976
977 u8data = HAL_DMD_RIU_ReadByte(0x103301);
978 u8data &= (0xff-0x10);
979 u8data |= ((u8cmd_array[1]&0x01)<<4);
980 HAL_DMD_RIU_WriteByte(0x103301, u8data);
981
982 u8data = HAL_DMD_RIU_ReadByte(0x103300+(0x05<<1)+1);
983 u8data &= (0xff-0x1f);
984 u8data |= (u8cmd_array[2]&0x1f);
985 HAL_DMD_RIU_WriteByte(0x103300+(0x05<<1)+1, u8data);
986 }
987 break;
988 default:
989 ULOGD("DEMOD","[utopia][halDMD]Error!!!, cmd invalid\n");
990 break;
991
992 }
993 #ifdef MS_DEBUG
994 ULOGD("DEMOD","0x103300: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103300));
995 ULOGD("DEMOD","0x103301: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103301));
996 ULOGD("DEMOD","0x10330B: 0x%x\n",HAL_DMD_RIU_ReadByte(0x10330B));
997 #endif
998 return true;
999 }
1000
1001 /****************************************************************************
1002 Subject: Function providing approx. result of Log10(X)
1003 Function: Log10Approx
1004 Parmeter: Operand X in float
1005 Return: Approx. value of Log10(X) in float
1006 Remark: Ouput range from 0.0, 0.3 to 9.6 (input 1 to 2^32)
1007 *****************************************************************************/
1008 /*
1009 #if(0)
1010 #if 1
1011 const float _LogApproxTableX[80] =
1012 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
1013 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
1014 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
1015 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
1016 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
1017 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
1018 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
1019 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
1020 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
1021 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
1022 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
1023 456767058.24, 593797175.72, 771936328.43, 1003517226.96
1024 };
1025
1026 const float _LogApproxTableY[80] =
1027 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
1028 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
1029 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
1030 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
1031 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
1032 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
1033 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
1034 };
1035
1036 float Log10Approx(float flt_x)
1037 {
1038 MS_U8 indx = 0;
1039
1040 do {
1041 if (flt_x < _LogApproxTableX[indx])
1042 break;
1043 indx++;
1044 }while (indx < 79); //stop at indx = 80
1045
1046 return _LogApproxTableY[indx];
1047 }
1048 #else
1049 float Log10Approx(float flt_x)
1050 {
1051 MS_U32 u32_temp = 1;
1052 MS_U8 indx = 0;
1053
1054 do {
1055 u32_temp = u32_temp << 1;
1056 if (flt_x < (float)u32_temp)
1057 break;
1058 }while (++indx < 32);
1059
1060 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
1061 return (float)0.3 * indx;
1062 }
1063 #endif
1064 #endif
1065 */