1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ISDBT.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ISDBT_CHIP_EULER 0x00
112 #define DMD_ISDBT_CHIP_NUGGET 0x01
113 #define DMD_ISDBT_CHIP_KAPPA 0x02
114 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
115 #define DMD_ISDBT_CHIP_NAPOLI 0x04
116 #define DMD_ISDBT_CHIP_MONACO 0x05
117 #define DMD_ISDBT_CHIP_MIAMI 0x06
118 #define DMD_ISDBT_CHIP_MUJI 0x07
119 #define DMD_ISDBT_CHIP_MUNICH 0x08
120 #define DMD_ISDBT_CHIP_MANHATTAN 0x09
121 #define DMD_ISDBT_CHIP_MULAN 0x0A
122 #define DMD_ISDBT_CHIP_MESSI 0x0B
123 #define DMD_ISDBT_CHIP_MASERATI 0x0C
124 #define DMD_ISDBT_CHIP_KIWI 0x0D
125 #define DMD_ISDBT_CHIP_MACAN 0x0E
126 #define DMD_ISDBT_CHIP_MUSTANG 0x0F
127 #define DMD_ISDBT_CHIP_MAXIM 0x10
128 #if defined(CHIP_EULER)
129 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
130 #elif defined(CHIP_NUGGET)
131 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
132 #elif defined(CHIP_KAPPA)
133 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
134 #elif defined(CHIP_EINSTEIN)
135 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
136 #elif defined(CHIP_NAPOLI)
137 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
138 #elif defined(CHIP_MIAMI)
139 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
140 #elif defined(CHIP_MUJI)
141 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
142 #elif defined(CHIP_MUNICH)
143 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUNICH
144 #elif defined(CHIP_MANHATTAN)
145 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MANHATTAN
146 #elif defined(CHIP_MULAN)
147 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MULAN
148 #elif defined(CHIP_MESSI)
149 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MESSI
150 #elif defined(CHIP_MASERATI)
151 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MASERATI
152 #elif defined(CHIP_KIWI)
153 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KIWI
154 #elif defined(CHIP_MACAN)
155 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MACAN
156 #elif defined(CHIP_MUSTANG)
157 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUSTANG
158 #elif defined(CHIP_MAXIM)
159 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAXIM
160 #else
161 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
162 #endif
163
164 //-------------------------------------------------------------------------------------------------
165 // Local Defines
166 //-------------------------------------------------------------------------------------------------
167 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN)
168 #define DMD_ISDBT_TBVA_EN 1
169 #else
170 #define DMD_ISDBT_TBVA_EN 0
171 #endif
172 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr) ) )
173 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr), val) )
174
175 #define HAL_INTERN_ISDBT_DBINFO(y) //y
176 #ifndef MBRegBase
177 #define MBRegBase 0x112600UL
178 #endif
179 #ifndef MBRegBase_DMD1
180 #define MBRegBase_DMD1 0x112400UL
181 #endif
182 #ifndef DMDMcuBase
183 #define DMDMcuBase 0x103480UL
184 #endif
185
186 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_MESSI) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_KIWI)
187 #define REG_ISDBT_LOCK_STATUS 0x11F5
188 #define ISDBT_TDP_REG_BASE 0x1400
189 #define ISDBT_FDP_REG_BASE 0x1500
190 #define ISDBT_FDPEXT_REG_BASE 0x1600
191 #define ISDBT_OUTER_REG_BASE 0x1700
192 #else
193 #define REG_ISDBT_LOCK_STATUS 0x36F5
194 #define ISDBT_TDP_REG_BASE 0x3700
195 #define ISDBT_FDP_REG_BASE 0x3800
196 #define ISDBT_FDPEXT_REG_BASE 0x3900
197 #define ISDBT_OUTER_REG_BASE 0x3A00
198 #endif
199
200 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
201 #define ISDBT_MIU_CLIENTW_ADDR 0xF5
202 #define ISDBT_MIU_CLIENTR_ADDR 0xF5
203 #define ISDBT_MIU_CLIENTW_MASK 0x87
204 #define ISDBT_MIU_CLIENTR_MASK 0x87
205 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x01
206 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x02
207 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO) || \
208 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN) || \
209 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
210 #define ISDBT_MIU_CLIENTW_ADDR 0xF2
211 #define ISDBT_MIU_CLIENTR_ADDR 0xF2
212 #define ISDBT_MIU_CLIENTW_MASK 0x66
213 #define ISDBT_MIU_CLIENTR_MASK 0x66
214 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
215 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x04
216 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
217 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
218 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
219 #define ISDBT_MIU_CLIENTW_MASK 0x47
220 #define ISDBT_MIU_CLIENTR_MASK 0x46
221 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
222 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
223 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
224 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
225 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
226 #define ISDBT_MIU_CLIENTW_MASK 0x47
227 #define ISDBT_MIU_CLIENTR_MASK 0x46
228 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x04
229 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
230 #endif
231 //-------------------------------------------------------------------------------------------------
232 // Local Variables
233 //-------------------------------------------------------------------------------------------------
234
235 const MS_U8 INTERN_ISDBT_table[] = {
236 #include "DMD_INTERN_ISDBT.dat"
237 };
238
239 #ifndef UTPA2
240 static const float _LogApproxTableX[80] =
241 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
242 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
243 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
244 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
245 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
246 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
247 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
248 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
249 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
250 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
251 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
252 456767058.24, 593797175.72, 771936328.43, 1003517226.96
253 };
254
255 static const float _LogApproxTableY[80] =
256 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
257 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
258 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
259 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
260 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
261 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
262 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
263 };
264 #endif
265
266 //-------------------------------------------------------------------------------------------------
267 // Global Variables
268 //-------------------------------------------------------------------------------------------------
269
270 extern MS_U8 u8DMD_ISDBT_DMD_ID;
271
272 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
273
274 //-------------------------------------------------------------------------------------------------
275 // Local Functions
276 //-------------------------------------------------------------------------------------------------
277 #ifndef UTPA2
278
279 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)280 static float Log10Approx(float flt_x)
281 {
282 MS_U8 indx = 0;
283
284 do {
285 if (flt_x < _LogApproxTableX[indx])
286 break;
287 indx++;
288 }while (indx < 79); //stop at indx = 80
289
290 return _LogApproxTableY[indx];
291 }
292 #endif
293
_CALCULATE_SQI(float fber)294 static MS_U16 _CALCULATE_SQI(float fber)
295 {
296 float flog_ber;
297 MS_U16 u16SQI;
298
299 #ifdef MSOS_TYPE_LINUX
300 flog_ber = (float)log10((double)fber);
301 #else
302 if (fber != 0.0)
303 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
304 else
305 flog_ber = -8.0;//when fber=0 means u16SQI=100
306 #endif
307
308 //printf("dan fber = %f\n", fber);
309 //printf("dan flog_ber = %f\n", flog_ber);
310 // Part 2: transfer ber value to u16SQI value.
311 if (flog_ber <= ( - 7.0))
312 {
313 u16SQI = 100; //*quality = 100;
314 }
315 else if (flog_ber < -6.0)
316 {
317 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
318 }
319 else if (flog_ber < -5.5)
320 {
321 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
322 }
323 else if (flog_ber < -5.0)
324 {
325 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
326 }
327 else if (flog_ber < -4.5)
328 {
329 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
330 }
331 else if (flog_ber < -4.0)
332 {
333 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
334 }
335 else if (flog_ber < -3.5)
336 {
337 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
338 }
339 else if (flog_ber < -3.0)
340 {
341 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
342 }
343 else if (flog_ber < -2.5)
344 {
345 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
346 }
347 else if (flog_ber < -2.0)
348 {
349 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
350 }
351 else
352 {
353 u16SQI = 0;
354 }
355
356 return u16SQI;
357 }
358 #endif
359
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)360 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
361 {
362 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
363 }
364
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)365 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
366 {
367 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
368 }
369
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)370 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
371 {
372 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
373 }
374
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)375 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
376 {
377 MS_U8 u8CheckCount;
378 MS_U8 u8CheckFlag = 0xFF;
379 MS_U32 u32MBRegBase = MBRegBase;
380
381 if (u8DMD_ISDBT_DMD_ID == 0)
382 u32MBRegBase = MBRegBase;
383 else if (u8DMD_ISDBT_DMD_ID == 1)
384 u32MBRegBase = MBRegBase_DMD1;
385
386 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
387 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
388 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
389 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
390
391 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
392 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
393
394 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
395 {
396 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
397 if ((u8CheckFlag&0x01)==0)
398 break;
399 MsOS_DelayTask(1);
400 }
401
402 if (u8CheckFlag&0x01)
403 {
404 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
405 return FALSE;
406 }
407
408 return TRUE;
409 }
410
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)411 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
412 {
413 MS_U8 u8CheckCount;
414 MS_U8 u8CheckFlag = 0xFF;
415 MS_U32 u32MBRegBase = MBRegBase;
416
417 if (u8DMD_ISDBT_DMD_ID == 0)
418 u32MBRegBase = MBRegBase;
419 else if (u8DMD_ISDBT_DMD_ID == 1)
420 u32MBRegBase = MBRegBase_DMD1;
421
422 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
423 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
424 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
425
426 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
427 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
428
429 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
430 {
431 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
432 if ((u8CheckFlag&0x02)==0)
433 {
434 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
435 break;
436 }
437 MsOS_DelayTask(1);
438 }
439
440 if (u8CheckFlag&0x02)
441 {
442 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
443 return FALSE;
444 }
445
446 return TRUE;
447 }
448
449
450
451 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)452 static void _HAL_INTERN_ISDBT_InitClk(void)
453 {
454 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EULER--------------\n"));
455
456 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
457
458 // Init by HKMCU
459 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
460 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
461 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
462 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
463 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
464 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
465 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
466
467 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
468 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
469 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
470 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
472 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
473 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
475 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
483 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
484 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
485 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
489 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
490
491 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
492 }
493 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)494 static void _HAL_INTERN_ISDBT_InitClk(void)
495 {
496 MS_U8 u8Val = 0;
497
498 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n"));
499
500 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
501
502 // Init by HKMCU
503 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
504 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
505 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
506 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
507 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
508 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
509 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
510 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
511 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
512
513 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
514 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
515 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
516 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
517 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
519 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
520 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
521 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
522 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
523 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
530 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
533 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
534 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
535 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
536 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
537
538 u8Val = _HAL_DMD_RIU_ReadByte(0x1006F5);
539 _HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
540
541 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
542 }
543 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)544 static void _HAL_INTERN_ISDBT_InitClk(void)
545 {
546 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n"));
547
548 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
549
550 // Init by HKMCU
551 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
552 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
553 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
554 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
555 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
556 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
557 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
558
559 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
560 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
561 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
562 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
563 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
564 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
565 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
566 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
567 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
568 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
569 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
570 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
571 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
573 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
574 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
575 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
576 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
581 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
582
583 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
584 }
585 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)586 static void _HAL_INTERN_ISDBT_InitClk(void)
587 {
588 MS_U8 u8Val = 0;
589
590 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n"));
591
592 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
593
594 // Init by HKMCU
595 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
596 u8Val &= ~0x01;
597 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
598
599 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
600 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
601 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
602 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
603 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
604 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
605 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
606 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
607 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
608
609 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
610 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
611 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
612 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
613 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
614 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
615 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
616 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
617 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
618 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
619 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
620 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
624 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
625 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
626 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
627 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
630 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
632 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
633
634 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
635 }
636 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)637 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
638 {
639 MS_U8 u8Val = 0;
640
641 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n"));
642
643 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
644
645 // Init by HKMCU
646 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
647 u8Val &= ~0x01;
648 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
649
650 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
651 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
652 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
653 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
654 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
655 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
656 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
657 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
658 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
659
660 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
661 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
662 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
663 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
666 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
667 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
671 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
673 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
674 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
675 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
676 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
677 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
678 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
679 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
680 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
682 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
683 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
684
685 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
686 }
687 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)688 static void _HAL_INTERN_ISDBT_InitClk(void)
689 {
690 MS_U8 u8Val = 0;
691
692 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n"));
693
694 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
695
696 // Init by HKMCU
697 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
698 u8Val &= ~0x01;
699 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
700
701 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
702 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
703 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
704 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
705 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
706 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
707 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
708 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
709
710 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
711 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
712 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
713 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
716 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
717 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
719 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
720 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
721 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
723 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
724 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
725 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
727 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
732 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
733 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
734 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
735 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
736 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
737 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
738
739 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
740 }
741 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)742 static void _HAL_INTERN_ISDBT_InitClk(void)
743 {
744 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n"));
745
746 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
747
748 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
749 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
750 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
751 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
752 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
753 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
754 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
755 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
756
757 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
758 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
759 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
760 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
761 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
762 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
763 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
764 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
765 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
768 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
769 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
771 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
772 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
773 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
774 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
775 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
776 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
777 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
779 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
780 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
781 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
782 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
783 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
784 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
785
786 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
787 }
788 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)789 static void _HAL_INTERN_ISDBT_InitClk(void)
790 {
791 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n"));
792
793 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
794
795 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
796 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
797 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
798 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
799 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
800 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
803 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
804
805 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
806 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
807 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
809 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
810 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
811 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
812 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
813 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
814 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
815 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
816 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
818 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
819 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
822 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
823 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
824 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
828 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
829 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
830 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
831 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
832 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
833 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
834 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
835 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
836 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
837 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
838 _HAL_DMD_RIU_WriteByte(0x112091, 0x46);
839 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
840
841 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
842 }
843 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
_HAL_INTERN_ISDBT_InitClk(void)844 static void _HAL_INTERN_ISDBT_InitClk(void)
845 {
846 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUNICH--------------\n"));
847
848 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
849
850 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
851 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
852 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
853 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
854 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
855 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
856 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
857 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
858
859 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
860 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
861 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
862 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
863 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
864 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
865 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
866 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
867 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
868 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
869 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
870 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
871 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
872 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
873 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
874 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
875 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
876 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
877 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
879 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
880 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
881 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
882 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
883 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
884 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
885 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
886 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
887
888 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
889 }
890 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN)
_HAL_INTERN_ISDBT_InitClk(void)891 static void _HAL_INTERN_ISDBT_InitClk(void)
892 {
893 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MANHATTAN--------------\n"));
894
895 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
896
897 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
898 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
899 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
900 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
901 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
902 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
903 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
904 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
905 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
906
907 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
908 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
909 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
910 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
911 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
912 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
913 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
914 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
915 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
916 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
917 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
918 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
919 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
920 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
921 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
923 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
924 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
925 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
926 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
927 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
928 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
929 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
930 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
931 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
932 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
933 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
934 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
935 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
936 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
938 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
939 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
940 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
941 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
942 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
943 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
944 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
945 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
946 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
947 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
948
949 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
950 }
951 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MULAN)
_HAL_INTERN_ISDBT_InitClk(void)952 static void _HAL_INTERN_ISDBT_InitClk(void)
953 {
954 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MULAN--------------\n"));
955
956 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
957
958 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
959 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
960 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
961 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
962 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
963 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
964 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
965 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
966 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //reset ts divider
967
968 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
969 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
970 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
971 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
972 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
973 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
974 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
975 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
976 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
977 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
978 _HAL_DMD_RIU_WriteByte(0x111f24, 0x05);
979 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
980 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
981 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
982 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
983 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
984 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
985 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
986 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
987 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
988 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
989 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
990 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
991 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
992 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
993 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
994 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
995 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
996 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
997 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
998 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
999 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1000 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1001 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1002 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1003 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1004 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1005 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1006 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1007 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1008 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1009 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1010 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1011 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x88);
1012 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1013 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1014 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1015 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1016 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1017 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1018
1019 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //reset ts divider
1020
1021 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1022 }
1023 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
_HAL_INTERN_ISDBT_InitClk(void)1024 static void _HAL_INTERN_ISDBT_InitClk(void)
1025 {
1026 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MESSI--------------\n"));
1027
1028 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1029
1030 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1031 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1032 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1033 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1034 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1035 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1036 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1037 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1038 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1039
1040 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1041 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
1042 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1043 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1044 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1045 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1046 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1047 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1048 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1049 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1050 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1051 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1052 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1053 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1055 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1056 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
1057 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1058 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
1059 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1061 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
1062 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
1064 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
1065 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
1066 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
1067 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
1068 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
1069 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1070 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
1071 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x0C);
1072 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
1073 _HAL_DMD_RIU_WriteByte(0x111f51, 0x48);
1074 _HAL_DMD_RIU_WriteByte(0x111f50, 0x44);
1075 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
1076 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
1077 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
1078 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
1079 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
1080 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
1081 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
1082 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
1083 _HAL_DMD_RIU_WriteByte(0x111f89, 0x44);
1084 _HAL_DMD_RIU_WriteByte(0x111f88, 0x44);
1085 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1086 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x44);
1087 _HAL_DMD_RIU_WriteByte(0x111f8d, 0x18);
1088 _HAL_DMD_RIU_WriteByte(0x111f8c, 0x44);
1089 _HAL_DMD_RIU_WriteByte(0x111f8f, 0x00);
1090 _HAL_DMD_RIU_WriteByte(0x111f8e, 0x44);
1091
1092 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1093 }
1094
1095 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MASERATI)
_HAL_INTERN_ISDBT_InitClk(void)1096 static void _HAL_INTERN_ISDBT_InitClk(void)
1097 {
1098 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MASERATI--------------\n"));
1099
1100 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1101
1102 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1103 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1104 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1105 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1106 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1107 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1108 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1109 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1110 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1111
1112 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1113 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1114 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1115 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1116 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1117 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1118 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1119 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1120 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1121 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1122 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1123 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1124 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1125 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1126 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1127 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1128 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1129 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1130 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1131 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1132 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1133 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1134 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1135 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1136 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1137 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1138 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1139 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1140 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1141 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1142 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1143 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1144 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1145 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1146 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1147 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1148 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1149 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1150 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1151 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1152 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1153 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1154 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1155 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1156 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1157 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1158 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1159 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1160 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1161 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1162 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1163 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1164 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1165 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1166 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1167 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1168 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1169 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1170 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1171 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1172 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1173 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1174 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1175
1176 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1177 }
1178 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MACAN)
_HAL_INTERN_ISDBT_InitClk(void)1179 static void _HAL_INTERN_ISDBT_InitClk(void)
1180 {
1181 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MACAN--------------\n"));
1182
1183 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1184
1185 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1186 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1187 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1188 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1189 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1190 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1191 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1192 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1193 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1194
1195 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1196 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1197 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1198 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1199 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1200 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1201 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1202 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1203 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1204 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1205 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1206 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1207 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1208 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1209 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1210 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1211 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1212 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1213 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1214 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1215 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1216 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1217 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1218 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1219 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1220 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1221 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1222 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1223 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1224 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1225 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1226 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1227 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1228 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1229 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1230 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1231 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1232 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1233 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1234 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1235 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1236 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1237 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1238 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1239 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1240 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1241 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1242 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1243 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1244 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1245 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1246 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1247 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1248 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1249 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1250 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1251 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1252 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1253 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1254 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1255 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1256 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1257 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1258
1259 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1260 }
1261 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG)
_HAL_INTERN_ISDBT_InitClk(void)1262 static void _HAL_INTERN_ISDBT_InitClk(void)
1263 {
1264 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUSTANG--------------\n"));
1265
1266 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1267
1268 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1269 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1270 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1271 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1272 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1273 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1274 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1275 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1276 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1277
1278 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1279 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1280 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1281 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1282 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1283 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1284 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1285 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1286 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1287 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1288 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1289 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1290 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1291 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1292 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1293 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1294 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1295 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1296 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1297 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1298 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1299 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1300 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1301 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1302 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1303 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1304 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1305 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1306 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1307 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1308 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1309 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1310 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1311 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1312 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1313 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1314 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1315 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1316 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1317 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1318 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1319 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1320 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1321 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1322 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1323 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1324 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1325 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1326 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1327 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1328 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1329 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1330 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1331 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1332 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1333 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1334 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1335 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1336 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1337 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1338 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1339 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1340 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1341
1342 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1343 }
1344 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAXIM)
_HAL_INTERN_ISDBT_InitClk(void)1345 static void _HAL_INTERN_ISDBT_InitClk(void)
1346 {
1347 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MAXIM--------------\n"));
1348
1349 // SRAM End Address
1350 _HAL_DMD_RIU_WriteByte(0x111707,0xff);
1351 _HAL_DMD_RIU_WriteByte(0x111706,0xff);
1352
1353 // DRAM Disable
1354 _HAL_DMD_RIU_WriteByte(0x111718,_HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
1355
1356 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1357
1358 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1359 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1360
1361 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1362 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1363 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1364 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1365 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1366 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1367 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00); //ADC SYNC FLOW
1368 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00); //ADC SYNC FLOW
1369 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1370 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1371
1372 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00); //Add in MAXIM //ADC SYNC FLOW
1373 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00); //Add in MAXIM //ADC SYNC FLOW
1374
1375 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1376 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1377
1378 _HAL_DMD_RIU_WriteByte(0x103321, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1379 _HAL_DMD_RIU_WriteByte(0x103320, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1380
1381 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00); // DMD_ANA_ADC_SYNC CLK_W
1382
1383 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1384 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1385 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1386 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1387 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1388 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1389 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1390 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1391 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1392 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1393 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1394 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1395 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1396 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1397 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1398 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1399 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1400 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1401 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1402 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1403 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1404 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1405 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1406 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1407 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1408 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1409 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1410 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1411 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1412 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1413 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1414 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1415 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1416 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1417 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1418 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1419 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1420 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1421 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1422 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1423 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1424 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1425 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1426 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1427 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1428 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1429 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1430 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1431 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1432 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1433 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1434 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1435 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1436 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1437 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1438 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1439 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1440 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1441
1442 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1443 //_HAL_DMD_RIU_WriteByteMask(0x103480, 0x00, 0x02);
1444 }
1445 #else
_HAL_INTERN_ISDBT_InitClk(void)1446 static void _HAL_INTERN_ISDBT_InitClk(void)
1447 {
1448 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
1449 }
1450 #endif
1451
_HAL_INTERN_ISDBT_Ready(void)1452 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
1453 {
1454 MS_U8 udata = 0x00;
1455
1456 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1457
1458 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1459 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1460
1461 MsOS_DelayTask(1);
1462
1463 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1464
1465 if (udata) return FALSE;
1466
1467 return TRUE;
1468 }
1469
_HAL_INTERN_ISDBT_Download(void)1470 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
1471 {
1472 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
1473
1474 MS_U8 udata = 0x00;
1475 MS_U16 i = 0;
1476 MS_U16 fail_cnt = 0;
1477 MS_U8 u8TmpData;
1478 MS_U16 u16AddressOffset;
1479 const MS_U8 *ISDBT_table;
1480 MS_U16 u16Lib_size;
1481
1482 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
1483 {
1484 if (_HAL_INTERN_ISDBT_Ready())
1485 {
1486 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1487 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1488 #endif
1489 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1490 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03);
1491
1492 MsOS_DelayTask(20);
1493 return TRUE;
1494 }
1495 }
1496
1497 ISDBT_table = &INTERN_ISDBT_table[0];
1498 u16Lib_size = sizeof(INTERN_ISDBT_table);
1499
1500 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1501 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1502 #endif
1503 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1504 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1505
1506 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x01); // release MCU, madison patch
1507
1508 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1509 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1510 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1511 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1512
1513 //// Load code thru VDMCU_IF ////
1514 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
1515
1516 for (i = 0; i < u16Lib_size; i++)
1517 {
1518 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
1519 }
1520
1521 //// Content verification ////
1522 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
1523
1524 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1525 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1526
1527 for (i = 0; i < u16Lib_size; i++)
1528 {
1529 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1530
1531 if (udata != ISDBT_table[i])
1532 {
1533 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
1534 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
1535 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
1536
1537 if (fail_cnt++ > 10)
1538 {
1539 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
1540 return FALSE;
1541 }
1542 }
1543 }
1544
1545 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
1546
1547 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1548 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1549
1550 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
1551 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1552 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
1553 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1554 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
1555 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1556 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
1557 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1558 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
1559 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1560 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
1561 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1562 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
1563 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1564 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
1565 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1566 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
1567 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1568
1569 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1570 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1571
1572 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset MCU, madison patch
1573
1574 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1575 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03); // release VD_MCU
1576
1577 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
1578
1579 MsOS_DelayTask(20);
1580
1581 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
1582
1583 return TRUE;
1584 }
1585
_HAL_INTERN_ISDBT_FWVERSION(void)1586 static void _HAL_INTERN_ISDBT_FWVERSION(void)
1587 {
1588 MS_U8 data1 = 0;
1589 MS_U8 data2 = 0;
1590 MS_U8 data3 = 0;
1591
1592 _MBX_ReadReg(0x20C4, &data1);
1593 _MBX_ReadReg(0x20C5, &data2);
1594 _MBX_ReadReg(0x20C6, &data3);
1595
1596 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1597 }
1598
_HAL_INTERN_ISDBT_Exit(void)1599 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
1600 {
1601 MS_U8 u8CheckCount = 0;
1602 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1603 MS_U8 u8RegValTmp = 0;
1604
1605 _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR, &u8RegValTmp);
1606 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1607 {
1608 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1609 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1610 }
1611 else
1612 {
1613 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1614 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1615 }
1616 #endif
1617 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1618
1619 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1620 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1621
1622 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1623 {
1624 MsOS_DelayTaskUs(10);
1625
1626 if (u8CheckCount++ == 0xFF)
1627 {
1628 printf(">> ISDBT Exit Fail!\n");
1629 return FALSE;
1630 }
1631 }
1632
1633 printf(">> ISDBT Exit Ok!\n");
1634
1635 return TRUE;
1636 }
1637
_HAL_INTERN_ISDBT_SoftReset(void)1638 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
1639 {
1640 MS_U8 u8Data = 0;
1641
1642 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1643 MS_U8 u8RegValTmp = 0;
1644
1645 _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR, &u8RegValTmp);
1646 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1647 {
1648 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1649 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1650 }
1651 else
1652 {
1653 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1654 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1655 }
1656 #endif
1657
1658 //Reset FSM
1659 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1660
1661 while (u8Data!=0x02)
1662 {
1663 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1664 }
1665
1666 return TRUE;
1667 }
1668
_HAL_INTERN_ISDBT_SetACICoef(void)1669 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
1670 {
1671 return TRUE;
1672 }
1673
_HAL_INTERN_ISDBT_SetIsdbtMode(void)1674 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
1675 {
1676 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1677 MS_U8 u8RegValTmp = 0;
1678
1679 _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR, &u8RegValTmp);
1680 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1681 {
1682 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1683 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1684 }
1685 else
1686 {
1687 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1688 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1689 }
1690 #endif
1691
1692 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
1693 return _MBX_WriteReg(0x20C0, 0x04);
1694 }
1695
_HAL_INTERN_ISDBT_SetModeClean(void)1696 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
1697 {
1698 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1699 return _MBX_WriteReg(0x20C0, 0x00);
1700 }
1701
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)1702 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
1703 {
1704 MS_BOOL bCheckPass = FALSE;
1705 MS_U8 u8Data = 0;
1706
1707 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1708
1709 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
1710 bCheckPass = TRUE;
1711
1712 return bCheckPass;
1713 }
1714
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)1715 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
1716 {
1717 MS_BOOL bCheckPass = FALSE;
1718 MS_U8 u8Data = 0;
1719
1720 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1721
1722 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
1723 bCheckPass = TRUE;
1724
1725 return bCheckPass;
1726 }
1727
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)1728 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
1729 {
1730 MS_BOOL bCheckPass = FALSE;
1731 MS_U8 u8Data = 0;
1732
1733 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1734
1735 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
1736 bCheckPass = TRUE;
1737
1738 return bCheckPass;
1739 }
1740
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)1741 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
1742 {
1743 MS_BOOL bCheckPass = FALSE;
1744 MS_U8 u8Data = 0;
1745
1746 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1747
1748 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
1749 bCheckPass = TRUE;
1750
1751 return bCheckPass;
1752 }
1753
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)1754 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
1755 {
1756 MS_BOOL bRet = TRUE;
1757 MS_U8 u8Data = 0;
1758 MS_U8 u8CodeRate = 0;
1759
1760 switch (eLayerIndex)
1761 {
1762 case E_ISDBT_Layer_A:
1763 // [10:8] reg_tmcc_cur_convolution_code_rate_a
1764 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1765 u8CodeRate = u8Data & 0x07;
1766 break;
1767 case E_ISDBT_Layer_B:
1768 // [10:8] reg_tmcc_cur_convolution_code_rate_b
1769 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1770 u8CodeRate = u8Data & 0x07;
1771 break;
1772 case E_ISDBT_Layer_C:
1773 // [10:8] reg_tmcc_cur_convolution_code_rate_c
1774 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1775 u8CodeRate = u8Data & 0x07;
1776 break;
1777 default:
1778 u8CodeRate = 15;
1779 break;
1780 }
1781
1782 switch (u8CodeRate)
1783 {
1784 case 0:
1785 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
1786 break;
1787 case 1:
1788 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
1789 break;
1790 case 2:
1791 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
1792 break;
1793 case 3:
1794 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
1795 break;
1796 case 4:
1797 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
1798 break;
1799 default:
1800 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
1801 break;
1802 }
1803
1804 return bRet;
1805 }
1806
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)1807 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
1808 {
1809 MS_BOOL bRet = TRUE;
1810 MS_U8 u8Data = 0;
1811 MS_U8 u8CP = 0;
1812
1813 // [7:6] reg_mcd_out_cp
1814 // output cp -> 00: 1/4
1815 // 01: 1/8
1816 // 10: 1/16
1817 // 11: 1/32
1818 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1819
1820 u8CP = (u8Data >> 6) & 0x03;
1821
1822 switch (u8CP)
1823 {
1824 case 0:
1825 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
1826 break;
1827 case 1:
1828 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
1829 break;
1830 case 2:
1831 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
1832 break;
1833 case 3:
1834 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
1835 break;
1836 }
1837
1838 return bRet;
1839 }
1840
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)1841 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
1842 {
1843 MS_BOOL bRet = TRUE;
1844 MS_U8 u8Data = 0;
1845 MS_U8 u8Mode = 0;
1846 MS_U8 u8Tdi = 0;
1847
1848 // [5:4] reg_mcd_out_mode
1849 // output mode -> 00: 2k
1850 // 01: 4k
1851 // 10: 8k
1852 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1853
1854 u8Mode = (u8Data >> 4) & 0x03;
1855
1856 switch (eLayerIndex)
1857 {
1858 case E_ISDBT_Layer_A:
1859 // [14:12] reg_tmcc_cur_interleaving_length_a
1860 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1861 u8Tdi = (u8Data >> 4) & 0x07;
1862 break;
1863 case E_ISDBT_Layer_B:
1864 // [14:12] reg_tmcc_cur_interleaving_length_b
1865 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1866 u8Tdi = (u8Data >> 4) & 0x07;
1867 break;
1868 case E_ISDBT_Layer_C:
1869 // [14:12] reg_tmcc_cur_interleaving_length_c
1870 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1871 u8Tdi = (u8Data >> 4) & 0x07;
1872 break;
1873 default:
1874 u8Tdi = 15;
1875 break;
1876 }
1877
1878 // u8Tdi+u8Mode*4
1879 // => 0~3: 2K
1880 // => 4~7: 4K
1881 // => 8~11:8K
1882 switch (u8Tdi+u8Mode*4)
1883 {
1884 case 0:
1885 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
1886 break;
1887 case 1:
1888 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
1889 break;
1890 case 2:
1891 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
1892 break;
1893 case 3:
1894 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
1895 break;
1896 case 4:
1897 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
1898 break;
1899 case 5:
1900 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
1901 break;
1902 case 6:
1903 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
1904 break;
1905 case 7:
1906 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
1907 break;
1908 case 8:
1909 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
1910 break;
1911 case 9:
1912 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
1913 break;
1914 case 10:
1915 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
1916 break;
1917 case 11:
1918 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
1919 break;
1920 default:
1921 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
1922 break;
1923 }
1924
1925 return bRet;
1926 }
1927
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)1928 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
1929 {
1930 MS_BOOL bRet = TRUE;
1931 MS_U8 u8Data = 0;
1932 MS_U8 u8Mode = 0;
1933
1934 // [5:4] reg_mcd_out_mode
1935 // output mode -> 00: 2k
1936 // 01: 4k
1937 // 10: 8k
1938 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1939
1940 u8Mode = (u8Data >> 4) & 0x03;
1941
1942 switch (u8Mode)
1943 {
1944 case 0:
1945 *peIsdbtFFT = E_ISDBT_FFT_2K;
1946 break;
1947 case 1:
1948 *peIsdbtFFT = E_ISDBT_FFT_4K;
1949 break;
1950 case 2:
1951 *peIsdbtFFT = E_ISDBT_FFT_8K;
1952 break;
1953 default:
1954 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
1955 break;
1956 }
1957
1958 return bRet;
1959 }
1960
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)1961 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
1962 {
1963 MS_BOOL bRet = TRUE;
1964 MS_U8 u8Data = 0;
1965 MS_U8 u8QAM = 0;
1966
1967 switch(eLayerIndex)
1968 {
1969 case E_ISDBT_Layer_A:
1970 // [6:4] reg_tmcc_cur_carrier_modulation_a
1971 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
1972 u8QAM = (u8Data >> 4) & 0x07;
1973 break;
1974 case E_ISDBT_Layer_B:
1975 // [6:4] reg_tmcc_cur_carrier_modulation_b
1976 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
1977 u8QAM = (u8Data >> 4) & 0x07;
1978 break;
1979 case E_ISDBT_Layer_C:
1980 // [6:4] reg_tmcc_cur_carrier_modulation_c
1981 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
1982 u8QAM = (u8Data >> 4) & 0x07;
1983 break;
1984 default:
1985 u8QAM = 15;
1986 break;
1987 }
1988
1989 switch(u8QAM)
1990 {
1991 case 0:
1992 *peIsdbtConstellation = E_ISDBT_DQPSK;
1993 break;
1994 case 1:
1995 *peIsdbtConstellation = E_ISDBT_QPSK;
1996 break;
1997 case 2:
1998 *peIsdbtConstellation = E_ISDBT_16QAM;
1999 break;
2000 case 3:
2001 *peIsdbtConstellation = E_ISDBT_64QAM;
2002 break;
2003 default:
2004 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
2005 break;
2006 }
2007
2008 return bRet;
2009 }
2010
_HAL_INTERN_ISDBT_ReadIFAGC(void)2011 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
2012 {
2013 MS_U8 data = 0;
2014
2015 _MBX_ReadReg(0x28FD, &data);
2016
2017 return data;
2018 }
2019
2020 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 * pFFT_Mode,MS_S32 * pTdCfoRegValue,MS_S32 * pFdCfoRegValue,MS_S16 * pIcfoRegValue)2021 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 *pFFT_Mode, MS_S32 *pTdCfoRegValue, MS_S32 *pFdCfoRegValue, MS_S16 *pIcfoRegValue)
2022 #else
2023 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
2024 #endif
2025 {
2026 MS_BOOL bRet = TRUE;
2027 MS_U8 u8Data = 0;
2028 MS_S32 s32TdCfoRegValue = 0;
2029 MS_S32 s32FdCfoRegValue = 0;
2030 MS_S16 s16IcfoRegValue = 0;
2031 #ifndef UTPA2
2032 float fTdCfoFreq = 0.0;
2033 float fICfoFreq = 0.0;
2034 float fFdCfoFreq = 0.0;
2035 #endif
2036
2037 //Get TD CFO
2038 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2039 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
2040
2041 //read td_freq_error
2042 //Read <29,38>
2043 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2044 s32TdCfoRegValue = u8Data;
2045 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
2046 s32TdCfoRegValue |= u8Data << 8;
2047 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
2048 s32TdCfoRegValue = u8Data << 16;
2049 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
2050 s32TdCfoRegValue |= u8Data << 24;
2051
2052 if (u8Data >= 0x10)
2053 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
2054
2055 s32TdCfoRegValue >>=4;
2056
2057 //TD_cfo_Hz = RegCfoTd * fb
2058 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2059 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
2060
2061 #ifndef UTPA2
2062 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
2063 fTdCfoFreq = fTdCfoFreq * 8126980.0;
2064 #endif
2065
2066 //Get FD CFO
2067 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2068 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2069 //load
2070 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2071 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2072
2073 //read CFO_KI
2074 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
2075 s32FdCfoRegValue = u8Data;
2076 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
2077 s32FdCfoRegValue |= u8Data << 8;
2078 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
2079 s32FdCfoRegValue |= u8Data << 16;
2080 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
2081 s32FdCfoRegValue |= u8Data << 24;
2082
2083 if(u8Data >= 0x01)
2084 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
2085
2086 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2087 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2088 //load
2089 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2090 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2091
2092 #ifndef UTPA2
2093 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
2094 fFdCfoFreq = fFdCfoFreq * 8126980.0;
2095 #endif
2096
2097 //Get ICFO
2098 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
2099 s16IcfoRegValue = u8Data;
2100 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
2101 s16IcfoRegValue |= u8Data << 8;
2102 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
2103
2104 if(s16IcfoRegValue >= 0x400)
2105 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
2106
2107 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
2108
2109 #ifdef UTPA2
2110 *pFFT_Mode = u8Data;
2111 *pTdCfoRegValue = s32TdCfoRegValue;
2112 *pFdCfoRegValue = s32TdCfoRegValue;
2113 *pIcfoRegValue = s16IcfoRegValue;
2114 #else
2115 if((u8Data & 0x30) == 0x0000) // 2k
2116 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
2117 else if((u8Data & 0x0030) == 0x0010) // 4k
2118 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
2119 else //if(u16data & 0x0030 == 0x0020) // 8k
2120 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
2121
2122 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
2123
2124 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
2125 #endif
2126
2127 return bRet;
2128 }
2129
2130 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2131 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2132 #else
2133 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2134 #endif
2135 {
2136 MS_BOOL bRet = TRUE;
2137 MS_U8 u8Data = 0;
2138 MS_U16 u16BerValue = 0;
2139 MS_U32 u32BerPeriod = 0;
2140
2141 // reg_rd_freezeber
2142 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2143 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
2144
2145 if (eLayerIndex == E_ISDBT_Layer_A)
2146 {
2147 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
2148 u16BerValue=u8Data;
2149 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
2150 u16BerValue |= (u8Data << 8);
2151 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
2152 u32BerPeriod = (u8Data&0x3F);
2153 u32BerPeriod <<= 16;
2154 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
2155 u32BerPeriod |= u8Data;
2156 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
2157 u32BerPeriod |= (u8Data << 8);
2158 }
2159 else if (eLayerIndex == E_ISDBT_Layer_B)
2160 {
2161 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
2162 u16BerValue=u8Data;
2163 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
2164 u16BerValue |= (u8Data << 8);
2165 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
2166 u32BerPeriod = (u8Data&0x3F);
2167 u32BerPeriod <<= 16;
2168 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
2169 u32BerPeriod |= u8Data;
2170 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
2171 u32BerPeriod |= (u8Data << 8);
2172 }
2173 else if (eLayerIndex == E_ISDBT_Layer_C)
2174 {
2175 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
2176 u16BerValue=u8Data;
2177 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
2178 u16BerValue |= (u8Data << 8);
2179 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
2180 u32BerPeriod = (u8Data&0x003F);
2181 u32BerPeriod <<= 16;
2182 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
2183 u32BerPeriod |= u8Data;
2184 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
2185 u32BerPeriod |= (u8Data << 8);
2186 }
2187 else
2188 {
2189 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2190 bRet = FALSE;
2191 }
2192
2193 // reg_rd_freezeber
2194 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2195 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
2196
2197 u32BerPeriod <<= 8; // *256
2198
2199 if(u32BerPeriod == 0) u32BerPeriod = 1;
2200
2201 #ifdef UTPA2
2202 *pBerPeriod = u32BerPeriod;
2203 *pBerValue = u16BerValue;
2204 #else
2205 *pfber = (float)u16BerValue/u32BerPeriod;
2206 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
2207 #endif
2208
2209 return bRet;
2210 }
2211
2212 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2213 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2214 #else
2215 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2216 #endif
2217 {
2218 MS_BOOL bRet = TRUE;
2219 MS_U8 u8Data = 0;
2220 MS_U8 u8FrzData = 0;
2221 MS_U32 u32BerValue = 0;
2222 MS_U16 u16BerPeriod = 0;
2223
2224 // reg_rd_freezeber
2225 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2226 u8Data = u8FrzData | 0x01;
2227 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2228
2229 if (eLayerIndex == E_ISDBT_Layer_A)
2230 {
2231 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
2232 u32BerValue = u8Data;
2233 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
2234 u32BerValue |= u8Data << 8;
2235 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
2236 u32BerValue |= u8Data << 16;
2237 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
2238 u32BerValue |= u8Data << 24;
2239
2240 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
2241 u16BerPeriod = u8Data;
2242 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
2243 u16BerPeriod |= u8Data << 8;
2244 }
2245 else if (eLayerIndex == E_ISDBT_Layer_B)
2246 {
2247 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
2248 u32BerValue = u8Data;
2249 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
2250 u32BerValue |= u8Data << 8;
2251 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
2252 u32BerValue |= u8Data << 16;
2253 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
2254 u32BerValue |= u8Data << 24;
2255
2256 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
2257 u16BerPeriod = u8Data;
2258 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
2259 u16BerPeriod |= u8Data << 8;
2260 }
2261 else if (eLayerIndex == E_ISDBT_Layer_C)
2262 {
2263 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
2264 u32BerValue = u8Data;
2265 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
2266 u32BerValue |= u8Data << 8;
2267 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2268 u32BerValue |= u8Data << 16;
2269 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
2270 u32BerValue |= u8Data << 24;
2271
2272 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
2273 u16BerPeriod = u8Data;
2274 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
2275 u16BerPeriod |= u8Data << 8;
2276 }
2277 else
2278 {
2279 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2280 bRet = FALSE;
2281 }
2282
2283 // reg_rd_freezeber
2284 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2285
2286 if(u16BerPeriod == 0) u16BerPeriod = 1;
2287
2288 #ifdef UTPA2
2289 *pBerPeriod = u16BerPeriod;
2290 *pBerValue = u32BerValue;
2291 #else
2292 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
2293 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
2294 #endif
2295 return bRet;
2296 }
2297
2298 #ifndef UTPA2
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)2299 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
2300 {
2301 float fber;
2302 MS_BOOL bRet = TRUE;
2303 EN_ISDBT_Layer eLayerIndex;
2304 MS_U16 u16SQI;
2305
2306 // Tmp solution
2307 eLayerIndex = E_ISDBT_Layer_A;
2308
2309 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2310 {
2311 //printf("Dan Demod unlock!!!\n");
2312 u16SQI = 0;
2313 }
2314 else
2315 {
2316 // Part 1: get ber value from demod.
2317 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2318
2319 u16SQI = _CALCULATE_SQI(fber);
2320 }
2321
2322 //printf("dan SQI = %d\n", SQI);
2323 return u16SQI;
2324 }
2325
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)2326 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
2327 {
2328 float fber;
2329 MS_BOOL bRet = TRUE;
2330 EN_ISDBT_Layer eLayerIndex;
2331 MS_U16 u16SQI;
2332
2333 // Tmp solution
2334 eLayerIndex = E_ISDBT_Layer_B;
2335
2336 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2337 {
2338 //printf("Dan Demod unlock!!!\n");
2339 u16SQI = 0;
2340 }
2341 else
2342 {
2343 // Part 1: get ber value from demod.
2344 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2345
2346 u16SQI = _CALCULATE_SQI(fber);
2347 }
2348
2349 //printf("dan SQI = %d\n", SQI);
2350 return u16SQI;
2351 }
2352
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)2353 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
2354 {
2355 float fber;
2356 MS_BOOL bRet = TRUE;
2357 EN_ISDBT_Layer eLayerIndex;
2358 MS_U16 u16SQI;
2359
2360 // Tmp solution
2361 eLayerIndex = E_ISDBT_Layer_C;
2362
2363 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2364 {
2365 //printf("Dan Demod unlock!!!\n");
2366 u16SQI = 0;
2367 }
2368 else
2369 {
2370 // Part 1: get ber value from demod.
2371 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2372
2373 u16SQI = _CALCULATE_SQI(fber);
2374 }
2375
2376 //printf("dan SQI = %d\n", SQI);
2377 return u16SQI;
2378 }
2379
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)2380 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
2381 {
2382 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
2383 MS_U16 u16SQI;
2384 EN_ISDBT_Layer eLayerIndex;
2385 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
2386
2387 //Get modulation of each layer
2388 eLayerIndex = E_ISDBT_Layer_A;
2389 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
2390 eLayerIndex = E_ISDBT_Layer_B;
2391 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
2392 eLayerIndex = E_ISDBT_Layer_C;
2393 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
2394
2395 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
2396 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
2397 else
2398 s8LayerAValue = -1;
2399
2400 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
2401 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
2402 else
2403 s8LayerBValue = -1;
2404
2405 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
2406 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
2407 else
2408 s8LayerCValue = -1;
2409
2410 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
2411 if (s8LayerAValue >= s8LayerBValue)
2412 {
2413 if (s8LayerCValue >= s8LayerAValue)
2414 {
2415 //Get Layer C u16SQI
2416 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2417 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
2418 }
2419 else //A>C
2420 {
2421 //Get Layer A u16SQI
2422 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2423 //printf("dan u16SQI Layer A: %d\n", u16SQI);
2424 }
2425 }
2426 else // B >= A
2427 {
2428 if (s8LayerCValue >= s8LayerBValue)
2429 {
2430 //Get Layer C u16SQI
2431 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2432 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
2433 }
2434 else //B>C
2435 {
2436 //Get Layer B u16SQI
2437 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2438 //printf("dan u16SQI Layer B: %d\n", u16SQI);
2439 }
2440 }
2441
2442 return u16SQI;
2443 }
2444 #endif
2445
2446 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetSNR(MS_U32 * pRegSNR,MS_U16 * pRegSnrObsNum)2447 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(MS_U32 *pRegSNR, MS_U16 *pRegSnrObsNum)
2448 #else
2449 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
2450 #endif
2451 {
2452 MS_BOOL bRet = TRUE;
2453 MS_U8 u8Data = 0;
2454 MS_U32 u32RegSNR = 0;
2455 MS_U16 u16RegSnrObsNum = 0;
2456 #ifndef UTPA2
2457 float fSNRAvg = 0.0;
2458 #endif
2459
2460 //set freeze
2461 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2462 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2463 //load
2464 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2465 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2466
2467 // ==============Average SNR===============//
2468 // [26:0] reg_snr_accu
2469 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
2470 u32RegSNR = u8Data&0x07;
2471 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
2472 u32RegSNR = (u32RegSNR<<8) | u8Data;
2473 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
2474 u32RegSNR = (u32RegSNR<<8) | u8Data;
2475 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
2476 u32RegSNR = (u32RegSNR<<8) | u8Data;
2477
2478 // [12:0] reg_snr_observe_sum_num
2479 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
2480 u16RegSnrObsNum = u8Data&0x1f;
2481 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
2482 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
2483
2484 //release freeze
2485 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2486 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2487 //load
2488 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2489 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2490
2491 if (u16RegSnrObsNum == 0)
2492 u16RegSnrObsNum = 1;
2493
2494
2495 #ifdef UTPA2
2496 *pRegSNR = u32RegSNR;
2497 *pRegSnrObsNum = u16RegSnrObsNum;
2498 #else
2499 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
2500 if (fSNRAvg == 0) //protect value 0
2501 fSNRAvg = 0.01;
2502
2503 #ifdef MSOS_TYPE_LINUX
2504 *pf_snr = 10.0f*(float)log10f((double)fSNRAvg/2);
2505 #else
2506 *pf_snr = 10.0f*(float)Log10Approx((double)fSNRAvg/2);
2507 #endif
2508 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
2509 #endif
2510
2511 return bRet;
2512 }
2513
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)2514 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
2515 {
2516 MS_U8 bRet = true;
2517 MS_U8 u8Data = 0;
2518 MS_U8 u8FrzData = 0;
2519 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
2520 #if DMD_ISDBT_TBVA_EN
2521 MS_U8 bTbvaBypass = 0;
2522 MS_U8 u8TbvaLayer = 0;
2523 #endif
2524 // Read packet errors of three layers
2525 // OUTER_FUNCTION_ENABLE
2526 // [8] reg_biterr_num_pcktprd_freeze
2527 // Freeze Packet error
2528 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2529 u8Data = u8FrzData | 0x01;
2530 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2531 #if DMD_ISDBT_TBVA_EN
2532 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x10*2, &u8Data);
2533 bTbvaBypass = u8Data & 0x01;
2534 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x11*2, &u8Data);
2535 u8TbvaLayer = u8Data & 0x03;
2536 switch(eLayerIndex)
2537 {
2538 case E_ISDBT_Layer_A:
2539 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2540 if (!bTbvaBypass && u8TbvaLayer == 0)
2541 {
2542 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2543 u16PacketErrA = u8Data << 8;
2544 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2545 u16PacketErrA = u16PacketErrA | u8Data;
2546 *pu16PacketErr = u16PacketErrA;
2547 }
2548 else
2549 {
2550 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2551 u16PacketErrA = u8Data << 8;
2552 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2553 u16PacketErrA = u16PacketErrA | u8Data;
2554 *pu16PacketErr = u16PacketErrA;
2555 }
2556 break;
2557 case E_ISDBT_Layer_B:
2558 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2559 if (!bTbvaBypass && u8TbvaLayer == 1)
2560 {
2561 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2562 u16PacketErrB = u8Data << 8;
2563 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2564 u16PacketErrB = u16PacketErrB | u8Data;
2565 *pu16PacketErr = u16PacketErrB;
2566 }
2567 else
2568 {
2569 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2570 u16PacketErrB = u8Data << 8;
2571 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2572 u16PacketErrB = u16PacketErrB | u8Data;
2573 *pu16PacketErr = u16PacketErrB;
2574 }
2575 break;
2576 case E_ISDBT_Layer_C:
2577 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2578 if (!bTbvaBypass && u8TbvaLayer == 2)
2579 {
2580 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2581 u16PacketErrC = u8Data << 8;
2582 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2583 u16PacketErrC = u16PacketErrC | u8Data;
2584 *pu16PacketErr = u16PacketErrC;
2585 }
2586 else
2587 {
2588 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2589 u16PacketErrC = u8Data << 8;
2590 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2591 u16PacketErrC = u16PacketErrC | u8Data;
2592 *pu16PacketErr = u16PacketErrC;
2593 }
2594 break;
2595 default:
2596 *pu16PacketErr = 0xFFFF;
2597 break;
2598 }
2599 #else
2600 switch(eLayerIndex)
2601 {
2602 case E_ISDBT_Layer_A:
2603 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2604 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2605 u16PacketErrA = u8Data << 8;
2606 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2607 u16PacketErrA = u16PacketErrA | u8Data;
2608 *pu16PacketErr = u16PacketErrA;
2609 break;
2610 case E_ISDBT_Layer_B:
2611 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2612 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2613 u16PacketErrB = u8Data << 8;
2614 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2615 u16PacketErrB = u16PacketErrB | u8Data;
2616 *pu16PacketErr = u16PacketErrB;
2617 break;
2618 case E_ISDBT_Layer_C:
2619 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2620 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2621 u16PacketErrC = u8Data << 8;
2622 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2623 u16PacketErrC = u16PacketErrC | u8Data;
2624 *pu16PacketErr = u16PacketErrC;
2625 break;
2626 default:
2627 *pu16PacketErr = 0xFFFF;
2628 break;
2629 }
2630 #endif
2631 // Unfreeze Packet error
2632 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2633
2634 return bRet;
2635 }
2636
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2637 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2638 {
2639 return _MBX_ReadReg(u16Addr, pu8Data);
2640 }
2641
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2642 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2643 {
2644 return _MBX_WriteReg(u16Addr, u8Data);
2645 }
2646
2647 //-------------------------------------------------------------------------------------------------
2648 // Global Functions
2649 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)2650 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
2651 {
2652 MS_BOOL bResult = TRUE;
2653
2654 switch(eCmd)
2655 {
2656 case DMD_ISDBT_HAL_CMD_Exit:
2657 bResult = _HAL_INTERN_ISDBT_Exit();
2658 break;
2659 case DMD_ISDBT_HAL_CMD_InitClk:
2660 _HAL_INTERN_ISDBT_InitClk();
2661 break;
2662 case DMD_ISDBT_HAL_CMD_Download:
2663 bResult = _HAL_INTERN_ISDBT_Download();
2664 break;
2665 case DMD_ISDBT_HAL_CMD_FWVERSION:
2666 _HAL_INTERN_ISDBT_FWVERSION();
2667 break;
2668 case DMD_ISDBT_HAL_CMD_SoftReset:
2669 bResult = _HAL_INTERN_ISDBT_SoftReset();
2670 break;
2671 case DMD_ISDBT_HAL_CMD_SetACICoef:
2672 bResult = _HAL_INTERN_ISDBT_SetACICoef();
2673 break;
2674 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
2675 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
2676 break;
2677 case DMD_ISDBT_HAL_CMD_SetModeClean:
2678 bResult = _HAL_INTERN_ISDBT_SetModeClean();
2679 break;
2680 case DMD_ISDBT_HAL_CMD_Active:
2681 break;
2682 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
2683 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
2684 break;
2685 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
2686 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
2687 break;
2688 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
2689 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
2690 break;
2691 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
2692 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
2693 break;
2694 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
2695 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
2696 break;
2697 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
2698 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
2699 break;
2700 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
2701 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
2702 break;
2703 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
2704 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
2705 break;
2706 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
2707 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
2708 break;
2709 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
2710 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
2711 break;
2712 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
2713 #ifdef UTPA2
2714 bResult = _HAL_INTERN_ISDBT_GetFreqOffset(&((*((DMD_ISDBT_CFO_DATA*)pArgs)).FFT_Mode), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).TdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).FdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).IcfoRegValue));
2715 #else
2716 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
2717 #endif
2718 break;
2719 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
2720 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
2721 #ifndef UTPA2
2722 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2723 #endif
2724 break;
2725 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
2726 #ifndef UTPA2
2727 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2728 #endif
2729 break;
2730 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
2731 #ifndef UTPA2
2732 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2733 #endif
2734 break;
2735 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
2736 #ifndef UTPA2
2737 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
2738 #endif
2739 break;
2740 case DMD_ISDBT_HAL_CMD_GetSNR:
2741 #ifdef UTPA2
2742 bResult = _HAL_INTERN_ISDBT_GetSNR(&((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSNR), &((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSnrObsNum));
2743 #else
2744 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
2745 #endif
2746 break;
2747 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
2748 #ifdef UTPA2
2749 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2750 #else
2751 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2752 #endif
2753 break;
2754 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
2755 #ifdef UTPA2
2756 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2757 #else
2758 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2759 #endif
2760 break;
2761 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
2762 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
2763 break;
2764 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
2765 break;
2766 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
2767 break;
2768 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
2769 break;
2770 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
2771 break;
2772 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
2773 break;
2774 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
2775 break;
2776 case DMD_ISDBT_HAL_CMD_GET_REG:
2777 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
2778 break;
2779 case DMD_ISDBT_HAL_CMD_SET_REG:
2780 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
2781 break;
2782 default:
2783 break;
2784 }
2785
2786 return bResult;
2787 }
2788
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)2789 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
2790 {
2791 return TRUE;
2792 }
2793
2794