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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _INTERN_DVBT_H_ 96 #define _INTERN_DVBT_H_ 97 98 #ifdef _INTERN_DVBT_C_ 99 #define EXTSEL 100 #else 101 #define EXTSEL extern 102 #endif 103 104 #define SUPPORT_ADAPTIVE_TS_CLK 105 //-------------------------------------------------------------------- 106 107 // #define DEMOD_DYNAMIC_SLAVE_ID_1 0x32 108 // #define DEMOD_DYNAMIC_SLAVE_ID_2 0x72 109 // #define DEMOD_DYNAMIC_SLAVE_ID_3 0xB2 110 // #define DEMOD_DYNAMIC_SLAVE_ID_4 0xF2 111 112 #define DEMOD_ADDR_H 0x00 113 #define DEMOD_ADDR_L 0x01 114 #define DEMOD_WRITE_REG 0x02 115 #define DEMOD_WRITE_REG_EX 0x03 116 #define DEMOD_READ_REG 0x04 117 #define DEMOD_RAM_CONTROL 0x05 118 119 #if 0//DTV_SCAN_AUTO_FINE_TUNE_ENABLE 120 //INTERN_DVBT_ Capture Range fix to 500K 121 #define DEMOD_CAPTURE_RANGE_500_K 500 122 #define DEMOD_CAPTURE_RANGE_SIZE DEMOD_CAPTURE_RANGE_500_K 123 #endif 124 125 #define MDrv_ReadByte(x) HAL_DMD_RIU_ReadByte(x) 126 #define MDrv_WriteByte(x,y) HAL_DMD_RIU_WriteByte(x,y) 127 128 #if 1 129 #define U8 MAPI_U8 130 #define U16 MAPI_U16 131 #define U32 MAPI_U32 132 #define BOOL MAPI_BOOL 133 #define BOOLEAN MAPI_BOOL 134 #if 0 135 #define BIT0 0x01 136 #define BIT1 0x02 137 #define BIT2 0x04 138 #define BIT3 0x08 139 #define BIT4 0x10 140 #define BIT5 0x20 141 #define BIT6 0x40 142 #define BIT7 0x80 143 #endif 144 #define BYTE MAPI_U8 145 146 #define WORD MAPI_WORD 147 #define E_RESULT_SUCCESS MAPI_TRUE 148 #define E_RESULT_FAILURE MAPI_FALSE 149 #define FUNCTION_RESULT MAPI_BOOL 150 151 152 153 154 #define INTERN_DVBT_TS_SERIAL_INVERSION 0 155 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1 156 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1 157 #define INTERN_DVBT_WEAK_SIGNAL_PICTURE_FREEZE_ENABLE 1 158 #endif 159 160 161 //-------------------------------------------------------------------- 162 typedef enum 163 { 164 E_SYS_UNKOWN = -1, 165 E_SYS_DVBT, 166 E_SYS_DVBC, 167 E_SYS_ATSC, 168 E_SYS_VIF, 169 170 E_SYS_NUM 171 }E_SYSTEM; 172 173 typedef enum 174 { 175 CMD_SYSTEM_INIT = 0, 176 CMD_DAC_CALI, 177 CMD_DVBT_CONFIG, 178 CMD_DVBC_CONFIG, 179 CMD_VIF_CTRL, 180 CMD_FSM_CTRL, 181 CMD_INDIR_RREG, 182 CMD_INDIR_WREG, 183 CMD_GET_INFO, 184 CMD_TS_CTRL, 185 CMD_TUNED_VALUE, 186 187 CMD_MAX_NUM 188 }E_CMD_CODE; 189 190 typedef enum 191 { 192 pc_op_code = 0, 193 pc_if_freq, 194 pc_sound_sys, 195 pc_vif_vga_maximum_l, 196 pc_vif_vga_maximum_h, 197 pc_scan_mode, 198 pc_vif_top, 199 pc_gain_distribution_thr_l, 200 pc_gain_distribution_thr_h, 201 202 VIF_PARAM_MAX_NUM 203 }E_VIF_PARAM; 204 205 typedef enum 206 { 207 pc_system = 0, 208 209 SYS_PARAM_MAX_NUM 210 }E_SYS_PARAM; 211 212 typedef enum 213 { 214 SET_IF_FREQ = 0, 215 SET_SOUND_SYS, 216 VIF_INIT, 217 SET_VIF_HANDLER, 218 VIF_TOP_ADJUST, 219 220 VIF_CMD_MAX_NUM 221 }E_VIF_CMD; 222 223 typedef enum 224 { 225 TS_PARALLEL = 0, 226 TS_SERIAL = 1, 227 228 TS_MODE_MAX_NUM 229 }E_TS_MODE; 230 231 typedef enum 232 { 233 dac_op_code = 0, 234 dac_idac_ch0, 235 dac_idac_ch1, 236 237 DAC_PARAM_MAX_NUM 238 } 239 E_DAC_PARAM; 240 241 typedef enum 242 { 243 DAC_RUN_CALI = 0, 244 DAC_IDAC_ASSIGN, 245 246 DAC_CMD_MAX_NUM 247 } 248 E_DAC_CMD; 249 250 typedef enum 251 { 252 agc_ref_small, 253 agc_ref_large, 254 agc_ref_aci, 255 ripple_switch_th_l, 256 ripple_switch_th_h, 257 258 TUNED_PARAM_MAX_NUM 259 }E_TUNED_PARAM; 260 261 //@@++ Arki 20100125 262 typedef enum 263 { 264 TS_MODUL_MODE, 265 TS_FFX_VALUE, 266 TS_GUARD_INTERVAL, 267 TS_CODE_RATE, 268 269 TS_PARAM_MAX_NUM 270 }E_SIGNAL_TYPE; 271 //@@-- Arki 20100125 272 273 typedef struct 274 { 275 MS_U8 cmd_code; 276 MS_U8 param[64]; 277 } S_CMDPKTREG; 278 279 #if 1 280 typedef enum 281 { 282 T_OPMODE_RFAGC_EN = 0x00, // 0X00 283 T_OPMODE_HUMDET_EN, // 0X01 284 T_OPMODE_DCR_EN, // 0X02 285 T_OPMODE_IIS_EN, // 0X03 286 T_OPMODE_CCI_EN, // 0X04 287 T_OPMODE_ACI_EN, // 0X05 288 T_OPMODE_IQB_EN, // 0X06 289 T_OPMODE_AUTO_IQ, // 0X07 290 T_OPMODE_AUTO_RFMAX, // 0X08 291 T_OPMODE_AUTO_ACI, // 0X09 292 T_OPMODE_FIX_MODE_CP, // 0x0A 293 T_OPMODE_FIX_TPS, // 0X0B 294 T_OPMODE_AUTO_SCAN, // 0X0C 295 T_OPMODE_RSV_0X0D, // 0X0D 296 T_OPMODE_RSV_0X0E, // 0X0E 297 T_OPMODE_RSV_0X0F, // 0X0F 298 T_CONFIG_RSSI, // 0x10 299 T_CONFIG_ZIF, // 0X11 300 T_CONFIG_FREQ, // 0X12 301 T_CONFIG_FC_L, // 0X13 302 T_CONFIG_FC_H, // 0x14 303 T_CONFIG_FS_L, // 0x15 304 T_CONFIG_FS_H, // 0x16 305 T_CONFIG_BW, // 0x17 306 T_CONFIG_MODE, // 0x18 307 T_CONFIG_CP, // 0x19 308 T_CONFIG_LP_SEL, // 0x1A 309 T_CONFIG_CSTL, // 0x1B 310 T_CONFIG_HIER, // 0x1C 311 T_CONFIG_HPCR, // 0x1D 312 T_CONFIG_LPCR, // 0x1E 313 T_CONFIG_IQ_SWAP, // 0x1F 314 T_CONFIG_RFMAX, // 0X20 315 T_CONFIG_CCI, // 0X21 316 T_CONFIG_ICFO_RANGE, // 0x22 317 T_CONFIG_RFAGC_REF, // 0X23 318 T_CONFIG_IFAGC_REF_2K, // 0X24 319 T_CONFIG_IFAGC_REF_8K, // 0X25 320 T_CONFIG_IFAGC_REF_ACI, // 0X26 321 T_CONFIG_IFAGC_REF_IIS, // 0X27 322 T_CONFIG_ACI_DET_TH_L, // 0X28 323 T_CONFIG_ACI_DET_TH_H, // 0X29 324 T_CONFIG_TS_SERIAL, // 0X2A 325 T_CONFIG_TS_CLK_RATE, // 0X2B 326 T_CONFIG_TS_OUT_INV, // 0X2C 327 T_CONFIG_TS_DATA_SWAP, // 0X2D 328 T_CONFIG_2K_SFO_H, // 0X2E 329 T_CONFIG_2K_SFO_L, // 0X2F 330 T_CONFIG_8K_SFO_H, // 0X30 331 T_CONFIG_8K_SFO_L, // 0X31 332 T_CONFIG_CHECK_CHANNEL, // 0X32 333 T_CONFIG_SLICER_SNR_POS, // 0X33 334 T_CONFIG_TDFE_CCI_KP, // 0X34 335 T_CONFIG_CCI_FSWEEP, // 0X35 336 T_CONFIG_TS_CLK_RATE_AUTO, // 0X36 337 T_CONFIG_IF_INV_PWM_OUT_EN, // 0x37 338 T_CONFIG_TUNER_LOWIF, // 0x38 339 T_CONFIG_FIF_L, // 0x39 340 T_CONFIG_FIF_H, // 0x3A 341 T_CONFIG_TUNER_SAWLESS, // 0x3B 342 T_CONFIG_IFAGC_REF_2K_H, // 0X3C 343 T_CONFIG_IFAGC_REF_8K_H, // 0X3D 344 T_CONFIG_IFAGC_REF_IIS_H, // 0x3E 345 T_CONFIG_IFAGC_REF_ACI_H, // 0x3F 346 T_DVBT_PARAM_LEN, 347 } DVBT_fake_Param; 348 #endif 349 350 /* 351 // Move to Tuner_SSI.h 352 typedef enum 353 { 354 _QPSK = 0x0, 355 _16QAM = 0x1, 356 _64QAM = 0x2, 357 }E_CONSTEL; 358 359 typedef enum 360 { 361 _CR1Y2 = 0x0, 362 _CR2Y3 = 0x1, 363 _CR3Y4 = 0x2, 364 _CR5Y6 = 0x3, 365 _CR7Y8 = 0x4, 366 }E_CODERATE; 367 368 369 typedef struct 370 { 371 U8 constel; 372 U8 code_rate; 373 float cn_ref; 374 }S_SQI_CN_NORDIGP1_INTERN_DVBT; 375 376 typedef struct 377 { 378 float power_db; 379 U8 sar3_val; 380 }S_INTERN_DVBT_RFAGC_SSI; 381 382 typedef struct 383 { 384 float power_db; 385 U8 agc_val; 386 }S_INTERN_DVBT_IFAGC_SSI; 387 388 typedef struct 389 { 390 U8 constel; 391 U8 code_rate; 392 float p_ref; 393 }S_INTERN_DVBT_SSI_PREF; 394 395 typedef struct 396 { 397 float attn_db; 398 U8 agc_err; 399 }S_INTERN_DVBT_IFAGC_ERR; 400 */ 401 //-------------------------------------------------------------------- 402 403 //-------------------------------------------------------------------- 404 MS_BOOL INTERN_DVBT_Reset ( void ); 405 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable); 406 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt); 407 MS_BOOL INTERN_DVBT_Exit ( void ); 408 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize); 409 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size); 410 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk); 411 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap); 412 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout); 413 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus); 414 //MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm); 415 //MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm); 416 MS_BOOL INTERN_DVBT_GetPostViterbiBer(MS_U16 *BitErrPeriod_reg, MS_U32 *BitErr_reg, MS_U16 *PktErr); 417 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber); 418 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr); 419 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id); 420 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW); 421 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType); 422 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter); 423 void INTERN_DVBT_GetSNR (MS_U32 *noise_power_reg); 424 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver); 425 MS_BOOL INTERN_DVBT_Show_Modulation_info(void); 426 MS_BOOL INTERN_DVBT_Show_Demod_Info(void); 427 MS_BOOL INTERN_DVBT_Show_Lock_Info(void); 428 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void); 429 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void); 430 MS_BOOL INTERN_DVBT_Show_BER_Info(void); 431 MS_BOOL INTERN_DVBT_Show_AGC_Info(void); 432 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value); 433 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value); 434 //arthur 435 MS_BOOL INTERN_DVBT_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err); 436 #ifdef SUPPORT_ADAPTIVE_TS_CLK 437 MS_BOOL INTERN_DVBT_Adaptive_TS_CLK(void); 438 MS_BOOL INTERN_DVBT_Locked_Task(void); 439 #endif 440 //-------------------------------------------------------------------- 441 442 #define INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY 443 444 #undef EXTSEL 445 #endif 446 447