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93 ////////////////////////////////////////////////////////////////////////////////
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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #include "ULog.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
133
134 #define TDE_REG_BASE 0x2400UL
135 #define DIV_REG_BASE 0x2500UL
136 #define TR_REG_BASE 0x2600UL
137 #define FTN_REG_BASE 0x2700UL
138 #define FTNEXT_REG_BASE 0x2800UL
139 #define MBX_REG_BASE 0x2F00UL
140
141
142 #if 0//ENABLE_SCAN_ONELINE_MSG
143 #define DBG_INTERN_DVBT_ONELINE(x) x
144 #else
145 #define DBG_INTERN_DVBT_ONELINE(x) // x
146 #endif
147
148 #ifdef MS_DEBUG
149 #define DBG_INTERN_DVBT(x) x
150 #define DBG_GET_SIGNAL(x) x
151 #define DBG_INTERN_DVBT_TIME(x) x
152 #define DBG_INTERN_DVBT_LOCK(x) x
153 #else
154 #define DBG_INTERN_DVBT(x) //x
155 #define DBG_GET_SIGNAL(x) //x
156 #define DBG_INTERN_DVBT_TIME(x) // x
157 #define DBG_INTERN_DVBT_LOCK(x) //x
158 #endif
159 #define DBG_DUMP_LOAD_DSP_TIME 0
160
161 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
162 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
163 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
164
165 /*bryan temp close*/
166 #define INTERN_DVBT_INTERNAL_DEBUG 0
167
168 #define SIGNAL_LEVEL_OFFSET 0.00
169 #define TAKEOVERPOINT -59.0
170 #define TAKEOVERRANGE 0.5
171 #define LOG10_OFFSET -0.21
172 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
173 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
174
175
176 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
177 #define TUNER_VPP 2
178 #define IF_AGC_VPP 2
179 #else
180 #define TUNER_VPP 1
181 #define IF_AGC_VPP 2
182 #endif
183
184 #if (TUNER_VPP == 1)
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
186 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
188 #endif
189
190 /*BEG INTERN_DVBT_DSPREG_TABLE*/
191 #define D_DMD_DVBT_PARAM_VERSION 0x01
192 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
193 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
194 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
195 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
196 #define D_DMD_DVBT_OP_DCR_EN 0x01
197 #define D_DMD_DVBT_OP_IIS_EN 0x01
198 #define D_DMD_DVBT_OP_IQB_EN 0x00
199 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
200 #define D_DMD_DVBT_OP_ACI_EN 0x01
201 #define D_DMD_DVBT_OP_CCI_EN 0x01
202 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
203 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
204 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
205 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
206 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
207 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
208 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
209 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
210 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
211 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
212 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
213 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
214 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
215 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
216 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
217 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
218 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
219 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
220 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
221 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
222 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
223 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
224
225 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
226 #define D_DMD_DVBT_CFG_FC_H 0x4E
227 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
228 #define D_DMD_DVBT_CFG_FS_H 0x5D
229 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
230
231 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
232 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
233 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
234 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
235 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
236 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
237 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
238 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
239 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
240 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
241 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
242 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
243
244 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
245 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
246 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
247 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
248 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
249 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
250 #else
251 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
252 #endif
253 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
254 //#define DMD_DVBT_CHECKSUM 0x00
255 /*END INTERN_DVBT_DSPREG_TABLE*/
256 #define DVBT_FS 45474 // 24000
257 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
258 #define FC_L 0x20 // 0323 jason
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ���� 10:22:29 0x9E
261 #define SET_ZIF 0x00
262 #define IQB_EN 0x00
263
264 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
265 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
266 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
267 #define CSTL 0x02 //0:QPSK 1:16 2: 64
268 #define HIER 0x00
269 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
270 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
271 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
272 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
273 #define LP_SEL 0x00 // LP select
274 #define IQ_SWAP 0x00 //0x01
275 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
276 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
277 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
278 #define TS_SER 0
279 #define TS_INV 0
280 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
281 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
282 #define IF_INV_PWM 0x00
283 #define T_LOWIF 1
284
285 MS_U8 INTERN_DVBT_DSPREG[] =
286 {
287 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
288 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
289 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
290 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
291 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
292 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
293 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
294 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
295 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
296 /*
297 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
298 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
299 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
300 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
301 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
302 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
303 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
304 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
305 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
306 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
307 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
308 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
309 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
310 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
311 */
312 };
313 /*END INTERN_DVBT_DSPREG_TABLE*/
314 //-----------------------------------------------------------------------
315 /****************************************************************
316 *Local Variables *
317 ****************************************************************/
318 static MS_BOOL bFECLock=0;
319 static MS_BOOL bTPSLock = 0;
320 static MS_U32 u32ChkScanTimeStart = 0;
321 static MS_U32 u32FecFirstLockTime=0;
322 static MS_U32 u32FecLastLockTime=0;
323 //bryan temp mark
324 #if(0)
325 static float fViterbiBerFiltered=-1;
326 #endif
327 //Global Variables
328 S_CMDPKTREG gsCmdPacket;
329 //U8 gCalIdacCh0, gCalIdacCh1;
330
331 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
332 MS_U8 INTERN_DVBT_table[] = {
333 #include "fwDMD_INTERN_DVBT.dat"
334 };
335
336 #endif
337
338 /*bryan temp mark*/
339 #if(0)
340 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
341 {
342 { _QPSK , _CR1Y2, -93},
343 { _QPSK , _CR2Y3, -91},
344 { _QPSK , _CR3Y4, -90},
345 { _QPSK , _CR5Y6, -89},
346 { _QPSK , _CR7Y8, -88},
347
348 { _16QAM , _CR1Y2, -87},
349 { _16QAM , _CR2Y3, -85},
350 { _16QAM , _CR3Y4, -84},
351 { _16QAM , _CR5Y6, -83},
352 { _16QAM , _CR7Y8, -82},
353
354 { _64QAM , _CR1Y2, -82},
355 { _64QAM , _CR2Y3, -80},
356 { _64QAM , _CR3Y4, -78},
357 { _64QAM , _CR5Y6, -77},
358 { _64QAM , _CR7Y8, -76},
359 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
360 };
361 #endif
362
363 /*bryan temp mark*/
364 #if(0)
365 static void INTERN_DVBT_SignalQualityReset(void);
366 #endif
367 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
368
369 #if(0)
INTERN_DVBT_SignalQualityReset(void)370 static void INTERN_DVBT_SignalQualityReset(void)
371 {
372 u32FecFirstLockTime=0;
373 fViterbiBerFiltered=-1;
374 }
375 #endif
376
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)377 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
378 {
379 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
380 MS_BOOL status = TRUE;
381 MS_U16 u16DspAddr = 0;
382
383 ULOGD("DEMOD","INTERN_DVBT_DSPReg_Init\n");
384
385 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
386 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
387
388 if (u8DVBT_DSPReg != NULL)
389 {
390 /*temp solution until new dsp table applied.*/
391 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
392 if (u8DVBT_DSPReg[0] >= 1)
393 {
394 u8DVBT_DSPReg+=2;
395 for (idx = 0; idx<u8Size; idx++)
396 {
397 u16DspAddr = *u8DVBT_DSPReg;
398 u8DVBT_DSPReg++;
399 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
400 u8DVBT_DSPReg++;
401 u8Mask = *u8DVBT_DSPReg;
402 u8DVBT_DSPReg++;
403 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
404 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
405 u8DVBT_DSPReg++;
406 ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
407 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
408 }
409 }
410 else
411 {
412 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
413 }
414 }
415
416 return status;
417 }
418
419 /***********************************************************************************
420 Subject: Command Packet Interface
421 Function: INTERN_DVBT_Cmd_Packet_Send
422 Parmeter:
423 Return: MS_BOOL
424 Remark:
425 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)426 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
427 {
428 MS_U8 status = true, indx;
429 MS_U8 reg_val=0, timeout = 0;
430 return TRUE;
431 //MsOS_ObtainMutex(_s32_Demod_DVBT_Mutex, MSOS_WAIT_FOREVER);
432 // ==== Command Phase ===================
433 ULOGD("DEMOD","--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
434 pCmdPacket->param[0],pCmdPacket->param[1],
435 pCmdPacket->param[2],pCmdPacket->param[3],
436 pCmdPacket->param[4],pCmdPacket->param[5] );
437
438 // wait _BIT_END clear
439 do
440 {
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
442 if((reg_val & _BIT_END) != _BIT_END)
443 {
444 break;
445 }
446 MsOS_DelayTask(5);
447 if (timeout++ > 200)
448 {
449 ULOGD("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
450 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
451 return false;
452 }
453 } while (1);
454
455 // set cmd_3:0 and _BIT_START
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
459
460
461
462 // wait _BIT_START clear
463 do
464 {
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
466 if((reg_val & _BIT_START) != _BIT_START)
467 {
468 break;
469 }
470 MsOS_DelayTask(5);
471 if (timeout++ > 200)
472 {
473 ULOGD("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
474 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
475 return false;
476 }
477 } while (1);
478
479 // ==== Data Phase ======================
480
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
482
483 for (indx = 0; indx < param_cnt; indx++)
484 {
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
486 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
487
488 // set param[indx] and _BIT_DRQ
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
492
493 // wait _BIT_DRQ clear
494 do
495 {
496 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
497 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
498 {
499 break;
500 }
501 MsOS_DelayTask(5);
502 if (timeout++ > 200)
503 {
504 ULOGD("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
505 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
506 return false;
507 }
508 } while (1);
509 }
510
511 // ==== End Phase =======================
512
513 // set _BIT_END to finish command
514 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
516 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
517 return status;
518 }
519
520
521 /***********************************************************************************
522 Subject: Command Packet Interface
523 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
524 Parmeter:
525 Return: MS_BOOL
526 Remark:
527 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)528 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
529 {
530 return TRUE;
531 }
532
533 /***********************************************************************************
534 Subject: SoftStop
535 Function: INTERN_DVBT_SoftStop
536 Parmeter:
537 Return: MS_BOOL
538 Remark:
539 ************************************************************************************/
540
INTERN_DVBT_SoftStop(void)541 MS_BOOL INTERN_DVBT_SoftStop ( void )
542 {
543 #if 1
544 MS_U16 u8WaitCnt=0;
545
546 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
547 {
548 ULOGD("DEMOD",">> MB Busy!\n");
549 return FALSE;
550 }
551
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
553
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
555 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
556
557 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
558 {
559 #if TEST_EMBEDED_DEMOD
560 MsOS_DelayTask(1); // << Ken 20090629
561 #endif
562 if (u8WaitCnt++ >= 0x7FFF)
563 {
564 ULOGD("DEMOD",">> DVBT SoftStop Fail!\n");
565 return FALSE;
566 }
567 }
568
569 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
571 #endif
572 return TRUE;
573 }
574
575
576 /***********************************************************************************
577 Subject: Reset
578 Function: INTERN_DVBT_Reset
579 Parmeter:
580 Return: MS_BOOL
581 Remark:
582 ************************************************************************************/
583 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)584 MS_BOOL INTERN_DVBT_Reset ( void )
585 {
586 ULOGD("DEMOD"," @INTERN_DVBT_reset\n");
587
588
589
590 // INTERN_DVBT_SoftStop();
591
592
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
594 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
595 MsOS_DelayTask(5);
596 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
597 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
598 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
599 MsOS_DelayTask(5);
600
601 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
602 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
603
604 bFECLock = FALSE;
605 bTPSLock = FALSE;
606 u32ChkScanTimeStart = MsOS_GetSystemTime();
607 return TRUE;
608 }
609
610 /***********************************************************************************
611 Subject: Exit
612 Function: INTERN_DVBT_Exit
613 Parmeter:
614 Return: MS_BOOL
615 Remark:
616 ************************************************************************************/
INTERN_DVBT_Exit(void)617 MS_BOOL INTERN_DVBT_Exit ( void )
618 {
619 return INTERN_DVBT_SoftStop();
620 }
621
622 /***********************************************************************************
623 Subject: Load DSP code to chip
624 Function: INTERN_DVBT_LoadDSPCode
625 Parmeter:
626 Return: MS_BOOL
627 Remark:
628 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)629 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
630 {
631 MS_U8 udata = 0x00;
632 MS_U16 i;
633 MS_U16 fail_cnt=0;
634
635 #if (DBG_DUMP_LOAD_DSP_TIME==1)
636 MS_U32 u32Time;
637 #endif
638
639
640 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
641 BININFO BinInfo;
642 MS_BOOL bResult;
643 MS_U32 u32GEAddr;
644 MS_U8 Data;
645 MS_S8 op;
646 MS_U32 srcaddr;
647 MS_U32 len;
648 MS_U32 SizeBy4K;
649 MS_U16 u16Counter=0;
650 MS_U8 *pU8Data;
651 #endif
652
653 #if 0
654 if(HAL_DMD_RIU_ReadByte(0x101E3E))
655 {
656 ULOGD("DEMOD","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
657 return FALSE;
658 }
659 #endif
660
661 // MDrv_Sys_DisableWatchDog();
662
663
664 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
665 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
666 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
667 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
668 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
669 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
670
671 //// Load code thru VDMCU_IF ////
672 ULOGD("DEMOD",">Load Code...\n");
673 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
674 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
675 {
676 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
677 }
678 #else
679 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
680 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
681 if ( bResult != PASS )
682 {
683 return FALSE;
684 }
685 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
686
687 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
688 InfoBlock_Flash_2_Checking_Start(&BinInfo);
689 #endif
690
691 #if OBA2
692 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
693 #else
694 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
695 #endif
696
697 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
698 InfoBlock_Flash_2_Checking_End(&BinInfo);
699 #endif
700
701 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
702
703 //bryan temp mark
704 //SizeBy4K=BinInfo.B_Len/0x1000;
705 SizeBy4K=BinInfo.B_Len>>12; //deivde to 4096
706
707 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
708
709 #if (DBG_DUMP_LOAD_DSP_TIME==1)
710 u32Time = msAPI_Timer_GetTime0();
711 #endif
712
713 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
714
715 for (i=0;i<=SizeBy4K;i++)
716 {
717 if(i==SizeBy4K)
718 len=BinInfo.B_Len%0x1000;
719 else
720 len=0x1000;
721
722 srcaddr = u32GEAddr+(0x1000*i);
723 //ULOGD("DEMOD","\t i = %08X\n", i);
724 //ULOGD("DEMOD","\t len = %08X\n", len);
725 op = 1;
726 u16Counter = 0 ;
727 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
728 while(len--)
729 {
730 u16Counter ++ ;
731 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
732 //pU8Data = (U8 *)(srcaddr|0x80000000);
733 #if OBA2
734 pU8Data = (U8 *)(srcaddr);
735 #else
736 pU8Data = (U8 *)(srcaddr|0x80000000);
737 #endif
738 Data = *pU8Data;
739
740 #if 0
741 if(u16Counter < 0x100)
742 ULOGD("DEMOD","0x%bx,", Data);
743 #endif
744 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
745
746 srcaddr += op;
747 }
748 // ULOGD("DEMOD","\n\n\n");
749 }
750
751 #if (DBG_DUMP_LOAD_DSP_TIME==1)
752 ULOGD("DEMOD","------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
753 #endif
754
755 #endif
756
757 //// Content verification ////
758 ULOGD("DEMOD",">Verify Code...\n");
759
760 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
761 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
762
763 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
764 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
765 {
766 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
767 if (udata != INTERN_DVBT_table[i])
768 {
769 ULOGD("DEMOD",">fail add = 0x%x\n", i);
770 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBT_table[i]);
771 ULOGD("DEMOD",">data = 0x%x\n", udata);
772
773 if (fail_cnt++ > 10)
774 {
775 ULOGD("DEMOD",">DVB-T DSP Loadcode fail!");
776 return false;
777 }
778 }
779 }
780 #else
781 for (i=0;i<=SizeBy4K;i++)
782 {
783 if(i==SizeBy4K)
784 len=BinInfo.B_Len%0x1000;
785 else
786 len=0x1000;
787
788 srcaddr = u32GEAddr+(0x1000*i);
789 //ULOGD("DEMOD","\t i = %08LX\n", i);
790 //ULOGD("DEMOD","\t len = %08LX\n", len);
791 op = 1;
792 u16Counter = 0 ;
793 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
794 while(len--)
795 {
796 u16Counter ++ ;
797 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
798 //pU8Data = (U8 *)(srcaddr|0x80000000);
799 #if OBA2
800 pU8Data = (U8 *)(srcaddr);
801 #else
802 pU8Data = (U8 *)(srcaddr|0x80000000);
803 #endif
804 Data = *pU8Data;
805
806 #if 0
807 if(u16Counter < 0x100)
808 ULOGD("DEMOD","0x%bx,", Data);
809 #endif
810 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
811 if (udata != Data)
812 {
813 ULOGD("DEMOD",">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
814 ULOGD("DEMOD",">code = 0x%x\n", Data);
815 ULOGD("DEMOD",">data = 0x%x\n", udata);
816
817 if (fail_cnt++ > 10)
818 {
819 ULOGD("DEMOD",">DVB-T DSP Loadcode fail!");
820 return false;
821 }
822 }
823
824 srcaddr += op;
825 }
826 // ULOGD("DEMOD","\n\n\n");
827 }
828 #endif
829
830 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
831 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
832 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
833 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
834
835 ULOGD("DEMOD",">DSP Loadcode done.");
836 //while(load_data_variable);
837
838
839 return TRUE;
840 }
841
842 /***********************************************************************************
843 Subject: DVB-T CLKGEN initialized function
844 Function: INTERN_DVBT_Power_On_Initialization
845 Parmeter:
846 Return: MS_BOOL
847 Remark:
848 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)849 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
850 {
851 HAL_DMD_RIU_WriteByte(0x103c0e,0x00);
852 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
853 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
854
855 // [Maxim] enable ADCI clock & ADCQ clock
856 // h0010 h0010 3 0 reg_ckg_dvbtc_adc_i 3 0 4 h1
857 // h0010 h0010 11 8 reg_ckg_dvbtc_adc_q 3 0 4 h1
858 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
859 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
860 //wriu 0x103321 0x00
861 //wriu 0x103320 0x00
862 HAL_DMD_RIU_WriteByte(0x103321,0x00);
863 HAL_DMD_RIU_WriteByte(0x103320,0x00);
864
865 // ----------------------------------------------
866 // start demod CLKGEN setting
867 // ----------------------------------------------
868 // *** Set register at CLKGEN1
869 // enable DMD MCU clock "bit[0] set 0"
870 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
871 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
872 // CLK_DMDMCU clock setting
873 // [0] disable clock
874 // [1] invert clock
875 // [4:2]
876 // 000:170 MHz(MPLL_DIV_BUf)
877 // 001:160MHz
878 // 010:144MHz
879 // 011:123MHz
880 // 100:108MHz
881 // 101:mem_clcok
882 // 110:mem_clock div 2
883 // 111:select XTAL
884 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
885 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
886
887 // set parallet ts clock
888 HAL_DMD_RIU_WriteByte(0x103301,0x05);
889 HAL_DMD_RIU_WriteByte(0x103300,0x14);
890
891 // enable atsc, DVBTC ts clock
892 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
893 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
894 HAL_DMD_RIU_WriteByte(0x103309,0x00);
895 HAL_DMD_RIU_WriteByte(0x103308,0x00);
896
897 // enable dvbc adc clock
898 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
899 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
900 HAL_DMD_RIU_WriteByte(0x103315,0x00);
901 HAL_DMD_RIU_WriteByte(0x103314,0x00);
902
903 // Reset TS divider
904 HAL_DMD_RIU_WriteByte(0x103302,0x01);
905 HAL_DMD_RIU_WriteByte(0x103302,0x00);
906
907
908 // enable clk_atsc_adcd_sync
909 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
910 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
911 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
912 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
913
914 // enable dvbt inner clock
915 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
916 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
917 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
918 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
919
920
921
922 // enable dvbt inner clock
923 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
924 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
925 HAL_DMD_RIU_WriteByte(0x111f21,0x44);
926 HAL_DMD_RIU_WriteByte(0x111f20,0x40);
927
928 // enable dvbc outer clock
929 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
930 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
931 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
932 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
933
934
935 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
936
937 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
938 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
939
940 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
941 HAL_DMD_RIU_WriteByte(0x111f2c,0x41);
942
943
944 HAL_DMD_RIU_WriteByte(0x111f2f,0x0c);
945 HAL_DMD_RIU_WriteByte(0x111f2e,0x04);
946
947
948 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
949 HAL_DMD_RIU_WriteByte(0x111f30,0x04);
950
951 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
952 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
953
954
955 HAL_DMD_RIU_WriteByte(0x111f35,0x10);
956 HAL_DMD_RIU_WriteByte(0x111f34,0x10);
957
958 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
959 HAL_DMD_RIU_WriteByte(0x111f36,0x11);
960
961 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
962 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
963
964 HAL_DMD_RIU_WriteByte(0x111f3d,0x0c);
965 HAL_DMD_RIU_WriteByte(0x111f3c,0x04);
966
967 HAL_DMD_RIU_WriteByte(0x111f45,0x04);
968 HAL_DMD_RIU_WriteByte(0x111f44,0x44);
969
970 HAL_DMD_RIU_WriteByte(0x111f69,0x00);
971 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
972
973 HAL_DMD_RIU_WriteByte(0x111f6b,0x00);
974 HAL_DMD_RIU_WriteByte(0x111f6a,0x00);
975
976 HAL_DMD_RIU_WriteByte(0x111f6d,0x00);
977 HAL_DMD_RIU_WriteByte(0x111f6c,0x10);
978
979 HAL_DMD_RIU_WriteByte(0x111f6f,0x0c);
980 HAL_DMD_RIU_WriteByte(0x111f6e,0x40);
981
982 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
983 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
984
985 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
986 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
987
988 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
989 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
990
991 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
992 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
993
994 HAL_DMD_RIU_WriteByte(0x111f79,0x40);
995 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
996
997 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
998 HAL_DMD_RIU_WriteByte(0x111f7a,0x04);
999
1000 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1001 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1002
1003 HAL_DMD_RIU_WriteByte(0x111f7f,0x40);
1004 HAL_DMD_RIU_WriteByte(0x111f7e,0x40);
1005
1006 HAL_DMD_RIU_WriteByte(0x111fe1,0x04);
1007 HAL_DMD_RIU_WriteByte(0x111fe0,0x04);
1008
1009 HAL_DMD_RIU_WriteByte(0x111ff0,0x04);
1010
1011 HAL_DMD_RIU_WriteByte(0x111fe3,0x04);
1012 HAL_DMD_RIU_WriteByte(0x111fe2,0x0c);
1013
1014 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1015 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1016
1017 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1018 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1019
1020 HAL_DMD_RIU_WriteByte(0x111fe9,0x04);
1021 HAL_DMD_RIU_WriteByte(0x111fe8,0x0c);
1022
1023 HAL_DMD_RIU_WriteByte(0x111feb,0x88);
1024 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1025
1026 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1027 HAL_DMD_RIU_WriteByte(0x111fec,0x08);
1028
1029 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1030 HAL_DMD_RIU_WriteByte(0x111fee,0x88);
1031
1032 HAL_DMD_RIU_WriteByte(0x15298f,0x00);
1033 HAL_DMD_RIU_WriteByte(0x15298e,0x00);
1034
1035 HAL_DMD_RIU_WriteByte(0x152991,0x00);
1036 HAL_DMD_RIU_WriteByte(0x152990,0x00);
1037 HAL_DMD_RIU_WriteByte(0x152992,0x00);
1038
1039 HAL_DMD_RIU_WriteByte(0x1529e5,0x00);
1040 HAL_DMD_RIU_WriteByte(0x1529e4,0x00);
1041
1042
1043 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1044 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1045
1046 HAL_DMD_RIU_WriteByte(0x111f43,0x40);
1047 HAL_DMD_RIU_WriteByte(0x111f42,0x04);
1048
1049 // 32+4K xdata sram
1050 //wriu 0x1117e0 0x23
1051 //wriu 0x1117e1 0x21
1052
1053 //wriu 0x1117e4 0x01
1054 //wriu 0x1117e6 0x11
1055 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
1056 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1057 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
1058 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1059
1060 // SRAM End Address
1061 HAL_DMD_RIU_WriteByte(0x111707,0xff);
1062 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1063
1064 // DRAM Disable
1065 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
1066
1067
1068
1069 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1070 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1071 }
1072
1073 /***********************************************************************************
1074 Subject: Power on initialized function
1075 Function: INTERN_DVBT_Power_On_Initialization
1076 Parmeter:
1077 Return: MS_BOOL
1078 Remark:
1079 ************************************************************************************/
1080
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)1081 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
1082 {
1083 MS_U16 status = true;
1084 MS_U8 cData = 0;
1085 //U8 cal_done;
1086 ULOGD("DEMOD","INTERN_DVBT_Power_On_Initialization\n");
1087
1088 #if defined(PWS_ENABLE)
1089 Mapi_PWS_Stop_VDMCU();
1090 #endif
1091
1092 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
1093 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1094 //// Firmware download //////////
1095 ULOGD("DEMOD","INTERN_DVBT Load DSP...\n");
1096 //MsOS_DelayTask(100);
1097
1098 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1099 {
1100 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1101 {
1102 ULOGD("DEMOD","DVB-T Load DSP Code Fail\n");
1103 return FALSE;
1104 }
1105 else
1106 {
1107 ULOGD("DEMOD","DVB-T Load DSP Code OK\n");
1108 }
1109 }
1110
1111
1112 //// MCU Reset //////////
1113 ULOGD("DEMOD","INTERN_DVBT Reset...\n");
1114 if (INTERN_DVBT_Reset() == FALSE)
1115 {
1116 ULOGD("DEMOD","Fail\n");
1117 return FALSE;
1118 }
1119 else
1120 {
1121 ULOGD("DEMOD","OK\n");
1122 }
1123
1124 // reset FDP
1125 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1126 // SRAM setting, DVB-T use it.
1127 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1128 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1129 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1130
1131 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1132 return status;
1133 }
1134
1135 /************************************************************************************************
1136 Subject: Driving control
1137 Function: INTERN_DVBT_Driving_Control
1138 Parmeter: bInversionEnable : TRUE For High
1139 Return: void
1140 Remark:
1141 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1142 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1143 {
1144 MS_U8 u8Temp;
1145
1146 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1147
1148 if (bEnable)
1149 {
1150 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1151 }
1152 else
1153 {
1154 u8Temp = u8Temp & (~0x01);
1155 }
1156
1157 ULOGD("DEMOD","---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp);
1158 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1159 }
1160 /************************************************************************************************
1161 Subject: Clk Inversion control
1162 Function: INTERN_DVBT_Clk_Inversion_Control
1163 Parmeter: bInversionEnable : TRUE For Inversion Action
1164 Return: void
1165 Remark:
1166 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1167 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1168 {
1169 MS_U8 u8Temp;
1170
1171 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1172
1173 if (bInversionEnable)
1174 {
1175 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1176 }
1177 else
1178 {
1179 u8Temp = u8Temp & (~0x02);
1180 }
1181
1182 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
1183 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1184 }
1185 /************************************************************************************************
1186 Subject: Transport stream serial/parallel control
1187 Function: INTERN_DVBT_Serial_Control
1188 Parmeter: bEnable : TRUE For serial
1189 Return: MS_BOOL :
1190 Remark:
1191 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1192 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1193 {
1194 MS_U8 status = true;
1195 MS_U8 temp_val;
1196 ULOGD("DEMOD"," @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk);
1197
1198 return status;
1199 if (u8TSClk == 0xFF) u8TSClk=0x13;
1200 if (bEnable) //Serial mode for TS pad
1201 {
1202 // serial
1203 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1204 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1205
1206 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1207 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1208 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1209
1210 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1211 temp_val|=0x04;
1212 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1213 #else
1214 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1215 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1216 temp_val|=0x07;
1217 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1218 #endif
1219 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1220 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1221
1222 //// INTERN_DVBT TS Control: Serial //////////
1223 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1224
1225 gsCmdPacket.param[0] = TS_SERIAL;
1226 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1227 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1228 #else
1229 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1230 #endif
1231 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1232 }
1233 else
1234 {
1235 //parallel
1236 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1237 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1238
1239 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1240 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1241 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1242 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1243 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1244 temp_val|=0x05;
1245 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1246 #else
1247 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1248 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1249 temp_val|=0x07;
1250 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1251 #endif
1252
1253 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1254 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1255
1256 //// INTERN_DVBT TS Control: Parallel //////////
1257 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1258
1259 gsCmdPacket.param[0] = TS_PARALLEL;
1260 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1261 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1262 #else
1263 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1264 #endif
1265 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1266 }
1267
1268 ULOGD("DEMOD","---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] );
1269
1270 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1271 return status;
1272 }
1273
1274 /************************************************************************************************
1275 Subject: TS1 output control
1276 Function: INTERN_DVBT_PAD_TS1_Enable
1277 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1278 Return: void
1279 Remark:
1280 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1281 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1282 {
1283 ULOGD("DEMOD"," @INTERN_DVBT_TS1_Enable... \n");
1284
1285 if(flag) // PAD_TS1 Enable TS CLK PAD
1286 {
1287 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1288 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1289 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1290 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1291 }
1292 else // PAD_TS1 Disable TS CLK PAD
1293 {
1294 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1295 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1296 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1297 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1298 }
1299 }
1300
1301 /************************************************************************************************
1302 Subject: channel change config
1303 Function: INTERN_DVBT_Config
1304 Parmeter: BW: bandwidth
1305 Return: MS_BOOL :
1306 Remark:
1307 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1308 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1309 {
1310 MS_U8 bandwidth;
1311 MS_U8 status = true;
1312
1313 ULOGD("DEMOD"," @INTERN_DVBT_config %d %d %d %d %d %d %d %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap);
1314
1315
1316 if (u8TSClk == 0xFF) u8TSClk=0x13;
1317 switch(BW)
1318 {
1319 case E_DMD_RF_CH_BAND_6MHz:
1320 bandwidth = 1;
1321 break;
1322 case E_DMD_RF_CH_BAND_7MHz:
1323 bandwidth = 2;
1324 break;
1325 case E_DMD_RF_CH_BAND_8MHz:
1326 default:
1327 bandwidth = 3;
1328 break;
1329 }
1330
1331 status &= INTERN_DVBT_Reset();
1332
1333 // BW mode
1334 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1335 // TS mode
1336 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1337 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1338 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1339 // Hierarchy mode
1340 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1341 // FC
1342 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1343 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1344 // FS
1345 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1346 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1347 // IQSwap
1348 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1349
1350 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1351 // Fif
1352 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1353 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1354
1355 return status;
1356 }
1357 /************************************************************************************************
1358 Subject: enable hw to lock channel
1359 Function: INTERN_DVBT_Active
1360 Parmeter: bEnable
1361 Return: MS_BOOL
1362 Remark:
1363 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1364 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1365 {
1366 MS_U8 status = true;
1367
1368 ULOGD("DEMOD"," @INTERN_DVBT_active\n");
1369
1370 //// INTERN_DVBT Finite State Machine on/off //////////
1371 #if 0
1372 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1373
1374 gsCmdPacket.param[0] = (MS_U8)bEnable;
1375 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1376 #else
1377 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1378 #endif
1379
1380 /*bryan temp mark*/
1381 #if(0)
1382 INTERN_DVBT_SignalQualityReset();
1383 #endif
1384
1385 return status;
1386 }
1387
1388
1389 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBT_Adaptive_TS_CLK(void)1390 MS_BOOL INTERN_DVBT_Adaptive_TS_CLK(void)
1391 {
1392 MS_U8 u8_ts_clk=0x00;
1393 MS_U8 TS_Clock_Temp;
1394 u8_ts_clk = HAL_DMD_RIU_ReadByte(MBRegBase+0x15);
1395 //printf("*************************************************************\n");
1396 //printf(" The TS clock: %x\n",u8_ts_clk);
1397
1398 //reg_atsc_dvb_div_reset =1
1399 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1400 TS_Clock_Temp=TS_Clock_Temp|0x01;
1401 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1402
1403 //set TS clock source div 5
1404 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01);
1405 TS_Clock_Temp=(TS_Clock_Temp&(~0x01));
1406 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp);
1407
1408 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
1409 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1410 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_ts_clk;
1411 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp);
1412
1413 //reg_atsc_dvb_div_reset =0
1414 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1415 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
1416 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1417
1418 // set ts FIFO
1419 // reg_RS_BACKEND
1420 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
1421 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ;
1422
1423 // enable ts
1424 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ;
1425 TS_Clock_Temp=TS_Clock_Temp|0x01;
1426 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ;
1427
1428 //debug: re-check ts clock
1429 //TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1430 //TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
1431 //printf("-------------------------------------------------------\n");
1432 //printf(" System report: %x\n",TS_Clock_Temp);
1433 //printf("*************************************************************\n");
1434
1435 return TRUE;
1436 }
1437
INTERN_DVBT_Locked_Task(void)1438 MS_BOOL INTERN_DVBT_Locked_Task(void)
1439 {
1440 INTERN_DVBT_Adaptive_TS_CLK();
1441
1442 //extension task
1443 {
1444 }
1445 return TRUE;
1446 }
1447 #endif
1448 /************************************************************************************************
1449 Subject: Return lock status
1450 Function: INTERN_DVBT_Lock
1451 Parmeter: eStatus :
1452 Return: MS_BOOL
1453 Remark:
1454 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1455 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1456 {
1457 /*bryan temp mark*/
1458 //float fBER=0.0f;
1459
1460
1461 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1462 {
1463 if (bFECLock == FALSE)
1464 {
1465 u32FecFirstLockTime = MsOS_GetSystemTime();
1466 ULOGD("DEMOD","++++++++[utopia]dvbt lock\n");
1467 }
1468 /*bryan temp mark*/
1469 /*
1470 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1471 {
1472 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1473 {
1474 if(fViterbiBerFiltered <= 0.0)
1475 fViterbiBerFiltered = fBER;
1476 else
1477 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1478 }
1479 DBG_INTERN_DVBT(ULOGD("DEMOD","[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1480 }
1481 */
1482 u32FecLastLockTime = MsOS_GetSystemTime();
1483 bFECLock = TRUE;
1484 return E_DMD_LOCK;
1485 }
1486 else
1487 {
1488 /*bryam temp mark*/
1489 #if(0)
1490 INTERN_DVBT_SignalQualityReset();
1491 #endif
1492
1493 if (bFECLock == TRUE)
1494 {
1495 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1496 {
1497 return E_DMD_LOCK;
1498 }
1499 }
1500 bFECLock = FALSE;
1501 }
1502
1503 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1504 {
1505 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1506 return E_DMD_UNLOCK;
1507 }
1508
1509 if(!bTPSLock)
1510 {
1511 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1512 {
1513 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- TPSLock \n");
1514 bTPSLock = TRUE;
1515 }
1516 }
1517 if(bTPSLock)
1518 {
1519 ULOGD("DEMOD","TPSLock %d\n",MsOS_GetSystemTime());
1520 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1521 {
1522 return E_DMD_CHECKING;
1523 }
1524 }
1525 else
1526 {
1527 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1528 {
1529 return E_DMD_CHECKING;
1530 }
1531 }
1532 return E_DMD_UNLOCK;
1533
1534 }
1535
1536
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1537 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1538 {
1539 MS_U16 u16Address = 0;
1540 MS_U8 cData = 0;
1541 MS_U8 cBitMask = 0;
1542 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1543 MS_U8 lock_to_unlock_flag=0;
1544 #endif
1545
1546 switch( eStatus )
1547 {
1548 case E_DMD_COFDM_FEC_LOCK:
1549 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1550
1551 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1552 MDrv_SYS_DMD_VD_MBX_ReadReg(MBX_REG_BASE+0x16, &lock_to_unlock_flag);
1553 if (((cData == 0x0B) && (bFECLock == FALSE)) ||((cData == 0x0B) && ((lock_to_unlock_flag & 0x01)==0x01)) )
1554 {
1555 // printf("Support adaptive TS CLK in polling mode! \n");
1556 INTERN_DVBT_Locked_Task();
1557 if((lock_to_unlock_flag & 0x01)==0x01)
1558 {
1559 MDrv_SYS_DMD_VD_MBX_WriteReg(MBX_REG_BASE+0x16,0x00);
1560 }
1561 }
1562
1563 #endif
1564
1565 if (cData == 0x0B)
1566 {
1567 return TRUE;
1568 }
1569 else
1570 {
1571 return FALSE; // continuously un-lock
1572 }
1573 break;
1574
1575 case E_DMD_COFDM_PSYNC_LOCK:
1576 u16Address = 0x232C; //FEC: P-sync Lock,
1577 cBitMask = BIT(1);
1578 break;
1579
1580 case E_DMD_COFDM_TPS_LOCK:
1581 u16Address = 0x2222; //TPS HW Lock,
1582 cBitMask = BIT(1);
1583 break;
1584
1585 case E_DMD_COFDM_DCR_LOCK:
1586 u16Address = 0x2737; //DCR Lock,
1587 cBitMask = BIT(0);
1588 break;
1589
1590 case E_DMD_COFDM_AGC_LOCK:
1591 u16Address = 0x271D; //AGC Lock,
1592 cBitMask = BIT(0);
1593 break;
1594
1595 case E_DMD_COFDM_MODE_DET:
1596 u16Address = 0x24CF; //Mode CP Detect,
1597 cBitMask = BIT(4);
1598 break;
1599
1600 case E_DMD_COFDM_TPS_EVER_LOCK:
1601 u16Address = 0x20C0; //TPS Ever Lock,
1602 cBitMask = BIT(3);
1603 break;
1604
1605 case E_DMD_COFDM_NO_CHANNEL:
1606 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1607 cBitMask = BIT(7);
1608 break;
1609
1610 default:
1611 return FALSE;
1612 }
1613
1614 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1615 return FALSE;
1616
1617 if ((cData & cBitMask) == cBitMask)
1618 {
1619 return TRUE;
1620 }
1621
1622 return FALSE;
1623
1624 }
1625
1626 /****************************************************************************
1627 Subject: To get the Post viterbi BER
1628 Function: INTERN_DVBT_GetPostViterbiBer
1629 Parmeter: Quility
1630 Return: E_RESULT_SUCCESS
1631 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1632 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1633 We will not read the Period, and have the "/256/8"
1634 *****************************************************************************/
1635 /*bryan temp mark*/
1636
INTERN_DVBT_GetPostViterbiBer(MS_U16 * BitErrPeriod_reg,MS_U32 * BitErr_reg,MS_U16 * PktErr_reg)1637 MS_BOOL INTERN_DVBT_GetPostViterbiBer(MS_U16 *BitErrPeriod_reg, MS_U32 *BitErr_reg, MS_U16 *PktErr_reg)
1638 {
1639 MS_BOOL status = true;
1640 MS_U8 reg=0, reg_frz=0;
1641 MS_U16 BitErrPeriod;
1642 MS_U32 BitErr;
1643 MS_U16 PktErr;
1644
1645 /////////// Post-Viterbi BER /////////////
1646 #if 0
1647 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1648 {
1649 *ber = (float)-1.0;
1650 return false;
1651 }
1652 #endif
1653 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1654 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1655 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1656
1657 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1658 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1660 BitErrPeriod = reg;
1661
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1663 BitErrPeriod = (BitErrPeriod << 8)|reg;
1664
1665 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1666 // 0x6b [15:8] reg_bit_err_num_15_8
1667 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1668 // 0x6d [15:8] reg_bit_err_num_31_24
1669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1670 BitErr = reg;
1671
1672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1673 BitErr = (BitErr << 8)|reg;
1674
1675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1676 BitErr = (BitErr << 8)|reg;
1677
1678 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1679 BitErr = (BitErr << 8)|reg;
1680
1681 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1682 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1683 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1684 PktErr = reg;
1685
1686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1687 PktErr = (PktErr << 8)|reg;
1688
1689 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1690 reg_frz=reg_frz&(~0x03);
1691 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1692
1693 if (BitErrPeriod == 0 ) //protect 0
1694 BitErrPeriod = 1;
1695
1696 *BitErrPeriod_reg = BitErrPeriod;
1697 *BitErr_reg = BitErr;
1698 *PktErr_reg = PktErr;
1699
1700 ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr);
1701
1702 return status;
1703 }
1704 #if(0)
1705 /****************************************************************************
1706 Subject: To get the Pre viterbi BER
1707 Function: INTERN_DVBT_GetPreViterbiBer
1708 Parmeter: ber
1709 Return: E_RESULT_SUCCESS
1710 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1711 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1712 We will not read the Period, and have the "/256/8"
1713 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1714 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1715 {
1716 MS_U8 status = true;
1717 MS_U8 reg=0, reg_frz=0;
1718 MS_U16 BitErrPeriod;
1719 MS_U32 BitErr;
1720 MS_BOOL BEROver;
1721
1722 // bank 7 0x10 [3] reg_rd_freezeber
1723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1724 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1725
1726 // bank 7 0x16 [7:0] reg_ber_timerl
1727 // [15:8] reg_ber_timerm
1728 // bank 7 0x18 [5:0] reg_ber_timerh
1729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1730 BitErrPeriod = reg&0x3f;
1731
1732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1733 BitErrPeriod = (BitErrPeriod << 8)|reg;
1734
1735 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1736 BitErrPeriod = (BitErrPeriod << 8)|reg;
1737
1738 // bank 7 0x1e [7:0] reg_ber_7_0
1739 // [15:8] reg_ber_15_8
1740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1741 BitErr = reg;
1742
1743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1744 BitErr = (BitErr << 8)|reg;
1745
1746 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1748 if (reg & 0x10)
1749 BEROver = true;
1750 else
1751 BEROver = false;
1752
1753 if (BitErrPeriod ==0 )//protect 0
1754 BitErrPeriod=1;
1755
1756 if (BEROver)
1757 {
1758 *ber = 1;
1759 ULOGD("DEMOD","BER is over\n");
1760 }
1761 else
1762 {
1763 if (BitErr <=0 )
1764 *ber=0.5 / (float)(BitErrPeriod * 256);
1765 else
1766 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1767 }
1768
1769 // bank 7 0x10 [3] reg_rd_freezeber
1770 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1771
1772 return status;
1773 }
1774 #endif
1775
1776 /****************************************************************************
1777 Subject: To get the Packet error
1778 Function: INTERN_DVBT_GetPacketErr
1779 Parmeter: pktErr
1780 Return: E_RESULT_SUCCESS
1781 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1782 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1783 We will not read the Period, and have the "/256/8"
1784 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1785 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1786 {
1787 MS_BOOL status = true;
1788 MS_U8 reg = 0, reg_frz = 0;
1789 MS_U16 PktErr;
1790
1791 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1792 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1793 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1794
1795 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1796 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1797 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1798 PktErr = reg;
1799
1800 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1801 PktErr = (PktErr << 8)|reg;
1802
1803 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1804 reg_frz=reg_frz&(~0x03);
1805 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1806
1807 ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr);
1808
1809 *u16PktErr = PktErr;
1810
1811 return status;
1812 }
1813
1814 /****************************************************************************
1815 Subject: To get the DVBT parameter
1816 Function: INTERN_DVBT_Get_TPS_Info
1817 Parmeter: point to return parameter
1818 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1819 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1820 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1821 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1822 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1823 FFT ( b14) : 0~1 => 2K, 8K
1824 Priority(bit 15) : 0~1=> HP,LP
1825 Return: TRUE
1826 FALSE
1827 Remark: The TPS parameters will be available after TPS lock
1828 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1829 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1830 {
1831 MS_U8 u8Temp;
1832
1833 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1834 return FALSE;
1835
1836 if ((u8Temp& 0x02) != 0x02)
1837 {
1838 return FALSE; //TPS unlock
1839 }
1840 else
1841 {
1842 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1843 return FALSE;
1844
1845 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1846 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1847
1848 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1849 return FALSE;
1850
1851 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1852 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1853
1854 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1855 return FALSE;
1856
1857 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1858 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1859
1860 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1861 return FALSE;
1862
1863 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
1864
1865 }
1866 return TRUE;
1867 }
1868
1869
1870 /****************************************************************************
1871 Subject: Read the signal to noise ratio (SNR)
1872 Function: INTERN_DVBT_GetSNR
1873 Parmeter: None
1874 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1875 Remark:
1876 *****************************************************************************/
1877
INTERN_DVBT_GetSNR(MS_U32 * noise_power_reg)1878 void INTERN_DVBT_GetSNR (MS_U32 *noise_power_reg)
1879 {
1880 MS_U8 status = true;
1881 MS_U8 reg=0, reg_frz=0;
1882 MS_U32 noise_power;
1883
1884
1885 // bank 6 0xfe [0] reg_fdp_freeze
1886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
1887 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
1888
1889 // bank 6 0xff [0] reg_fdp_load
1890 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1891
1892 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
1894 noise_power = reg & 0x07;
1895
1896 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
1897 noise_power = (noise_power << 8)|reg;
1898
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
1900 noise_power = (noise_power << 8)|reg;
1901
1902 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
1903 noise_power = (noise_power << 8)|reg;
1904
1905 // bank 6 0x26 [5:4] reg_transmission_mode
1906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
1907
1908 // bank 6 0xfe [0] reg_fdp_freeze
1909 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
1910
1911 // bank 6 0xff [0] reg_fdp_load
1912 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1913
1914 *noise_power_reg = noise_power;
1915 }
1916
1917 /****************************************************************************
1918 Subject: To check if Hierarchy on
1919 Function: INTERN_DVBT_Is_HierarchyOn
1920 Parmeter:
1921 Return: BOOLEAN
1922 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)1923 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
1924 {
1925 MS_U16 u16_tmp;
1926
1927 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
1928 return FALSE;
1929 //ULOGD("DEMOD","u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
1930 if(u16_tmp&0x38)
1931 {
1932 return TRUE;
1933 }
1934 return FALSE;
1935 }
1936
1937 // arthur
INTERN_DVBT_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1938 MS_BOOL INTERN_DVBT_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1939 {
1940 MS_BOOL status = true;
1941
1942 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1943
1944 return status;
1945 }
1946
1947 /*bryan temp mark*/
1948 #if(0)
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1949 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1950 {
1951 MS_U8 status = true;
1952 float ch_power_db = 0.0f;
1953 float ch_power_ref = 11.0f;
1954 float ch_power_rel = 0.0f;
1955 MS_U8 u8_index = 0;
1956 MS_U16 tps_info_qam,tps_info_cr;
1957
1958 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1959 {
1960 *strength = 0;
1961 return TRUE;
1962 }
1963 ULOGD("DEMOD","INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime());
1964
1965 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
1966 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
1967 /* Actually, it's more reasonable, that signal level depended on cable input power level
1968 * thougth the signal isn't dvb-t signal.
1969 */
1970
1971 // use pointer of IFAGC table to identify
1972 // case 1: RFAGC from SAR, IFAGC controlled by demod
1973 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1974 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1975 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
1976 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1977 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1978 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
1979 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
1980
1981
1982 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
1983 ULOGD("DEMOD","[dvbt]TPS qam parameter retrieve failure\n");
1984
1985 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
1986 ULOGD("DEMOD","[dvbt]TPS cr parameter retrieve failure\n");
1987
1988
1989 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
1990 {
1991 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
1992 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
1993 {
1994 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
1995 break;
1996 }
1997 else
1998 {
1999 u8_index++;
2000 }
2001 }
2002
2003 if (ch_power_ref > 10.0f)
2004 *strength = 0;
2005 else
2006 {
2007 ch_power_rel = ch_power_db - ch_power_ref;
2008
2009 if ( ch_power_rel < -15.0f )
2010 {
2011 *strength = 0;
2012 }
2013 else if ( ch_power_rel < 0.0f )
2014 {
2015 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2016 }
2017 else if ( ch_power_rel < 20 )
2018 {
2019 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2020 }
2021 else if ( ch_power_rel < 35.0f )
2022 {
2023 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2024 }
2025 else
2026 {
2027 *strength = 100;
2028 }
2029 }
2030
2031 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
2032 {
2033 *strength = 0;
2034 return TRUE;
2035 }
2036
2037 ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength);
2038 ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength);
2039
2040 return status;
2041 }
2042
2043
2044 /****************************************************************************
2045 Subject: To get the DVT Signal quility
2046 Function: INTERN_DVBT_GetSignalQuality
2047 Parmeter: Quility
2048 Return: E_RESULT_SUCCESS
2049 E_RESULT_FAILURE
2050 Remark: Here we have 4 level range
2051 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2052 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2053 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2054 <4>.4th Range => Quality <10
2055 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2056 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2057 {
2058 float ber_sqi;
2059 float fber;
2060 float cn_rec = 0;
2061 float cn_nordig_p1 = 0;
2062 float cn_rel = 0;
2063
2064 MS_U8 status = true;
2065 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
2066 MS_U16 u16_tmp;
2067
2068 ULOGD("DEMOD","INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime());
2069
2070 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
2071 {
2072
2073 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2074 {
2075 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2076 }
2077 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
2078 if(fViterbiBerFiltered<= 0.0)
2079 {
2080 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
2081 {
2082 ULOGD("DEMOD","GetPostViterbiBer Fail!\n");
2083 return FALSE;
2084 }
2085 fViterbiBerFiltered = fber;
2086 }
2087 else
2088 {
2089 fber = fViterbiBerFiltered;
2090 }
2091
2092 if (fber > 1.0E-3)
2093 ber_sqi = 0.0;
2094 else if (fber > 8.5E-7)
2095 #ifdef MSOS_TYPE_LINUX
2096 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2097 #else
2098 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2099 #endif
2100 else
2101 ber_sqi = 100.0;
2102
2103 cn_rec = INTERN_DVBT_GetSNR();
2104
2105 if (cn_rec == -1) //get SNR return fail
2106 status = false;
2107
2108 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2109 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2110 tps_cnstl = 0xff;
2111 tps_cr = 0xff;
2112 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
2113 tps_cnstl = (MS_U8)u16_tmp&0x07;
2114 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
2115 tps_cr = (MS_U8)u16_tmp&0x07;
2116
2117 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
2118 {
2119 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
2120 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
2121 {
2122 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
2123 break;
2124 }
2125 }
2126
2127 // 0,5, snr offset
2128 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
2129
2130 // patch....
2131 // Noridg SQI,
2132 // 64QAM, CR34, GI14, SNR 22dB.
2133 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
2134 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
2135 {
2136 cn_rel += 1.5f;
2137 }
2138
2139 if (cn_rel < -7.0f)
2140 {
2141 *quality = 0;
2142 }
2143 else if (cn_rel < 3.0)
2144 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
2145 else
2146 *quality = (MS_U16)ber_sqi;
2147 }
2148 else
2149 {
2150 *quality = 0;
2151 }
2152
2153 ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr);
2154 ULOGD("DEMOD","BER = %8.3e\n", fber);
2155 ULOGD("DEMOD","Signal Quility = %d\n", *quality);
2156 return status;
2157 }
2158 #endif
2159
2160 /****************************************************************************
2161 Subject: To get the Cell ID
2162 Function: INTERN_DVBT_Get_CELL_ID
2163 Parmeter: point to return parameter cell_id
2164
2165 Return: TRUE
2166 FALSE
2167 Remark:
2168 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2169 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2170 {
2171 MS_U8 status = true;
2172 MS_U8 value1=0;
2173 MS_U8 value2=0;
2174
2175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2176 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2177
2178 *cell_id = ((MS_U16)value1<<8)|value2;
2179 return status;
2180 }
2181 /*
2182 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2183 {
2184 #define SQI_LOOP_NUM 50
2185 U8 inn = 0;
2186 WORD sqi = 0;
2187 WORD ave_sqi = 0;
2188 WORD ave_num = 0;
2189 while(inn++<SQI_LOOP_NUM)
2190 {
2191 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2192 {
2193 ULOGD("DEMOD","[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2194 ave_sqi+=sqi;
2195 ave_num++;
2196 }
2197 MsOS_DelayTask(50);
2198 }
2199
2200 if(ave_num != 0 )
2201 *quality = ave_sqi/ave_num;
2202
2203 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2204 }
2205 */
2206 /****************************************************************************
2207 Subject: To get the DVBT Carrier Freq Offset
2208 Function: INTERN_DVBT_Get_FreqOffset
2209 Parmeter: Frequency offset (in KHz), bandwidth
2210 Return: E_RESULT_SUCCESS
2211 E_RESULT_FAILURE
2212 Remark:
2213 *****************************************************************************/
2214 /*bryan temp mark*/
2215 #if(0)
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2216 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2217 {
2218 float N, FreqB;
2219 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2220 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2221 MS_U8 reg_frz=0, reg=0;
2222 MS_U8 status;
2223
2224 FreqB = (float)u8BW * 8 / 7;
2225
2226 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2227
2228 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2229
2230 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2231 RegCfoTd = reg;
2232
2233 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2234 RegCfoTd = (RegCfoTd << 8)|reg;
2235
2236 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2237 RegCfoTd = (RegCfoTd << 8)|reg;
2238
2239 FreqCfoTd = (float)RegCfoTd;
2240
2241 if (RegCfoTd & 0x800000)
2242 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2243
2244 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2245
2246 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2247
2248 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2249 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2250
2251 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2252
2253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2254 RegCfoFd = reg;
2255
2256 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2257 RegCfoFd = (RegCfoFd << 8)|reg;
2258
2259 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2260 RegCfoFd = (RegCfoFd << 8)|reg;
2261
2262 FreqCfoFd = (float)RegCfoFd;
2263
2264 if (RegCfoFd & 0x800000)
2265 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2266
2267 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2268
2269 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2270 RegIcfo = reg & 0x07;
2271
2272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2273 RegIcfo = (RegIcfo << 8)|reg;
2274
2275 FreqIcfo = (float)RegIcfo;
2276
2277 if (RegIcfo & 0x400)
2278 FreqIcfo = FreqIcfo - (float)0x800;
2279
2280 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2281 reg = reg & 0x30;
2282
2283 switch (reg)
2284 {
2285 case 0x00: N = 2048; break;
2286 case 0x20: N = 4096; break;
2287 case 0x10:
2288 default: N = 8192; break;
2289 }
2290
2291 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2292 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2293 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2294 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2295 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2296 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2297 // DBG_GET_SIGNAL(ULOGD("DEMOD","FCFO = %f\n", FreqCfoFd));
2298 // DBG_GET_SIGNAL(ULOGD("DEMOD","TCFO = %f\n", FreqCfoTd));
2299 // DBG_GET_SIGNAL(ULOGD("DEMOD","ICFO = %f\n", FreqIcfo));
2300 ULOGD("DEMOD","CFOE = %f\n", *pFreqOff);
2301
2302 if (status == TRUE)
2303 return TRUE;
2304 else
2305 return FALSE;
2306 }
2307 #endif
2308
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2309 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2310 {
2311
2312 bPowerOn = bPowerOn;
2313 }
2314
INTERN_DVBT_Power_Save(void)2315 MS_BOOL INTERN_DVBT_Power_Save(void)
2316 {
2317
2318 return TRUE;
2319 }
2320
2321 /****************************************************************************
2322 Subject: To get the DVBT constellation parameter
2323 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2324 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2325 Return: TRUE
2326 FALSE
2327 Remark: The TPS parameters will be available after TPS lock
2328 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2329 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2330 {
2331 MS_U8 tps_param;
2332
2333 //@@++ Arki 20100125
2334 if (eSignalType == TS_MODUL_MODE)
2335 {
2336 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2337 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2338 }
2339
2340 if (eSignalType == TS_CODE_RATE)
2341 {
2342 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2343 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2344 }
2345
2346 if (eSignalType == TS_GUARD_INTERVAL)
2347 {
2348 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2349 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2350 }
2351
2352 if (eSignalType == TS_FFX_VALUE)
2353 {
2354 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2355 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2356 }
2357 //@@-- Arki 20100125
2358 return TRUE;
2359 }
2360
INTERN_DVBT_Version(MS_U16 * ver)2361 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2362 {
2363
2364 MS_U8 status = true;
2365 MS_U8 tmp = 0;
2366 MS_U16 u16_INTERN_DVBT_Version;
2367
2368 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2369 u16_INTERN_DVBT_Version = tmp;
2370 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2371 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2372 *ver = u16_INTERN_DVBT_Version;
2373
2374 return status;
2375 }
2376
INTERN_DVBT_Version_minor(MS_U8 * ver2)2377 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2378 {
2379
2380 MS_U8 status = true;
2381
2382 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2383
2384 return status;
2385 }
2386
2387
INTERN_DVBT_Show_Demod_Version(void)2388 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2389 {
2390
2391 MS_BOOL status = true;
2392 MS_U16 u16_INTERN_DVBT_Version;
2393 MS_U8 u8_minor_ver = 0;
2394
2395 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2396 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2397 ULOGD("DEMOD","[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2398
2399 return status;
2400 }
2401
2402 /*bryan temp mark*/
2403 #if(0)
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2404 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2405 {
2406 MS_U8 u8_index = 0;
2407 MS_BOOL bRet = false;
2408
2409 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2410 {
2411 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2412 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2413 {
2414 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2415 bRet = true;
2416 break;
2417 }
2418 else
2419 {
2420 u8_index++;
2421 }
2422 }
2423 return bRet;
2424 }
2425
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2426 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2427 {
2428 MS_U8 u8_index = 0;
2429 MS_BOOL bRet = false;
2430
2431 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2432 {
2433 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2434 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2435 {
2436 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2437 bRet = true;
2438 break;
2439 }
2440 else
2441 {
2442 u8_index++;
2443 }
2444 }
2445 return bRet;
2446 }
2447 #endif
2448
2449 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2450 void INTERN_DVBT_get_demod_state(MS_U8* state)
2451 {
2452 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2453 return;
2454 }
2455
INTERN_DVBT_Show_ChannelLength(void)2456 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2457 {
2458 MS_U8 status = true;
2459 MS_U8 tmp = 0;
2460 MS_U16 len = 0;
2461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2462 len = tmp;
2463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2464 len = (len<<8)|tmp;
2465 ULOGD("DEMOD","[dvbt]Hw_channel=%d\n",len);
2466 return status;
2467 }
2468
INTERN_DVBT_Show_SW_ChannelLength(void)2469 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2470 {
2471 MS_U8 status = true;
2472 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2473 MS_U16 sw_len = 0;
2474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2475 sw_len = tmp;
2476 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2477 sw_len = (sw_len<<8)|tmp;
2478 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2479 peak_num = tmp;
2480 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2481 insideGI = tmp&0x01;
2482 stoptracking = (tmp&0x02)>>1;
2483 flag_short_echo = (tmp&0x0C)>>2;
2484 fsa_mode = (tmp&0x30)>>4;
2485
2486 ULOGD("DEMOD","[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2487 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2488
2489 return status;
2490 }
2491
INTERN_DVBT_Show_ACI_CI(void)2492 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2493 {
2494
2495 #define BIT4 0x10
2496 MS_U8 status = true;
2497 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2498
2499 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2500 digACI = (tmp&BIT4)>>4;
2501
2502 // get flag_CI
2503 // 0: No interference
2504 // 1: CCI
2505 // 2: in-band ACI
2506 // 3: N+1 ACI
2507 // flag_ci = (tmp&0xc0)>>6;
2508 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2509 flag_CI = (tmp&0xC0)>>6;
2510 td_coef = (tmp&0x0C)>>2;
2511
2512 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2513
2514 ULOGD("DEMOD","[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2515
2516 return status;
2517 }
2518
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2519 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2520 {
2521 MS_U8 status = true;
2522 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2524 fd = tmp;
2525 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2526 ch_len = tmp;
2527 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2528 snr_sel = (tmp>>4)&0x03;
2529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2530 pertone_num = tmp;
2531
2532 ULOGD("DEMOD","[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2533
2534 return status;
2535 }
2536
INTERN_DVBT_Get_CFO(void)2537 MS_BOOL INTERN_DVBT_Get_CFO(void)
2538 {
2539
2540 float N = 0, FreqB = 0;
2541 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2542 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2543 MS_U8 reg_frz = 0, reg = 0;
2544 MS_U8 status = 0;
2545 MS_U8 u8BW = 8;
2546
2547 FreqB = (float)u8BW * 8 / 7;
2548
2549 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2550
2551 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2552
2553 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2554 RegCfoTd = reg;
2555
2556 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2557 RegCfoTd = (RegCfoTd << 8)|reg;
2558
2559 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2560 RegCfoTd = (RegCfoTd << 8)|reg;
2561
2562 FreqCfoTd = (float)RegCfoTd;
2563
2564 if (RegCfoTd & 0x800000)
2565 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2566
2567 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2568
2569 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2570
2571 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2572 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2573
2574 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2575
2576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2577 RegCfoFd = reg;
2578
2579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2580 RegCfoFd = (RegCfoFd << 8)|reg;
2581
2582 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2583 RegCfoFd = (RegCfoFd << 8)|reg;
2584
2585 FreqCfoFd = (float)RegCfoFd;
2586
2587 if (RegCfoFd & 0x800000)
2588 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2589
2590 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2591
2592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2593 RegIcfo = reg & 0x07;
2594
2595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2596 RegIcfo = (RegIcfo << 8)|reg;
2597
2598 FreqIcfo = (float)RegIcfo;
2599
2600 if (RegIcfo & 0x400)
2601 FreqIcfo = FreqIcfo - (float)0x800;
2602
2603 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2604 reg = reg & 0x30;
2605
2606 switch (reg)
2607 {
2608 case 0x00: N = 2048; break;
2609 case 0x20: N = 4096; break;
2610 case 0x10:
2611 default: N = 8192; break;
2612 }
2613
2614 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2615 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2616 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2617 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2618 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2619
2620 ULOGD("DEMOD","[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2621
2622 return status;
2623
2624 }
INTERN_DVBT_Get_SFO(void)2625 MS_BOOL INTERN_DVBT_Get_SFO(void)
2626 {
2627 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2628 MS_BOOL status = true;
2629 MS_U8 reg = 0;
2630 float FreqB = 9.143, FreqS = 45.473; //20.48
2631 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2632 float sfo_value = 0;
2633
2634 // get Reg_TDP_SFO,
2635 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2636 Reg_TDP_SFO = reg;
2637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2638 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2639 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2640 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2641
2642 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2643
2644 // get Reg_FDP_SFO,
2645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2646 Reg_FDP_SFO = reg;
2647 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2648 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2649 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2650 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2651
2652 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2653
2654 // get Reg_FSA_SFO,
2655 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2656 Reg_FSA_SFO = reg;
2657 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2658 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2660 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2661
2662 // get Reg_FSA_IN,
2663 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2664 Reg_FSA_IN = reg;
2665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2666 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2667 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2668
2669 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2670 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2671
2672 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2673 // ULOGD("DEMOD","\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2674 ULOGD("DEMOD","[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2675
2676
2677 return status;
2678 }
2679
INTERN_DVBT_Get_SYA_status(void)2680 void INTERN_DVBT_Get_SYA_status(void)
2681 {
2682 MS_U8 status = true;
2683 MS_U8 sya_k = 0,reg = 0;
2684 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2685
2686 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2687 sya_k = reg;
2688
2689 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2690 sya_th = reg;
2691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2692 sya_th = (sya_th<<8)|reg;
2693
2694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2695 sya_offset = reg;
2696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2697 sya_offset = (sya_offset<<8)|reg;
2698
2699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2700 len_m = reg;
2701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2702 len_m = (len_m<<8)|reg;
2703
2704 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2705 len_b = reg;
2706 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2707 len_b = (len_b<<8)|reg;
2708
2709
2710 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2711 len_a = reg;
2712 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2713 len_a = (len_a<<8)|reg;
2714
2715
2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2717 tracking_reg = reg;
2718
2719
2720 ULOGD("DEMOD","[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2721 ULOGD("DEMOD","[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2722
2723 return;
2724 }
2725
INTERN_DVBT_Get_cci_status(void)2726 void INTERN_DVBT_Get_cci_status(void)
2727 {
2728 MS_U8 status = true;
2729 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2730
2731 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2732 cci_fsweep = reg;
2733
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2735 cci_kp = reg;
2736
2737 ULOGD("DEMOD","[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2738
2739 return;
2740 }
2741
INTERN_DVBT_Show_PRESFO_Info(void)2742 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2743 {
2744 MS_U8 tmp = 0;
2745 MS_BOOL status = TRUE;
2746 ULOGD("DEMOD","\n[SFO]");
2747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2748 ULOGD("DEMOD","[%x]",tmp);
2749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2750 ULOGD("DEMOD","[%x]",tmp);
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2752 ULOGD("DEMOD","[%x]",tmp);
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2754 ULOGD("DEMOD","[%x]",tmp);
2755 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2756 ULOGD("DEMOD","[%x]",tmp);
2757 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2758 ULOGD("DEMOD","[%x]",tmp);
2759 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2760 ULOGD("DEMOD","[%x]",tmp);
2761 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2762 ULOGD("DEMOD","[%x][End]",tmp);
2763
2764 return status;
2765 }
2766
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2767 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2768 {
2769 MS_BOOL status = true;
2770
2771 *locktime = 0xffff;
2772 ULOGD("DEMOD","[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2773
2774 status = false;
2775 return status;
2776 }
2777
2778
INTERN_DVBT_Show_Lock_Time_Info(void)2779 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2780 {
2781 MS_U16 locktime = 0;
2782 MS_BOOL status = TRUE;
2783 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2784 ULOGD("DEMOD","[DVBT]lock_time = %d ms\n",locktime);
2785 return status;
2786 }
2787
INTERN_DVBT_Show_BER_Info(void)2788 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2789 {
2790 MS_U8 tmp = 0;
2791 MS_BOOL status = TRUE;
2792 ULOGD("DEMOD","\n[BER]");
2793 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2794 ULOGD("DEMOD","[%x,",tmp);
2795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2796 ULOGD("DEMOD","%x]",tmp);
2797 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2798 ULOGD("DEMOD","[%x,",tmp);
2799 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2800 ULOGD("DEMOD","%x]",tmp);
2801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2802 ULOGD("DEMOD","[%x,",tmp);
2803 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2804 ULOGD("DEMOD","%x][End]",tmp);
2805
2806 return status;
2807
2808 }
2809
2810
INTERN_DVBT_Show_AGC_Info(void)2811 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2812 {
2813 MS_U8 tmp = 0;
2814 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2815 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2816 MS_U16 if_agc_err = 0;
2817 MS_BOOL status = TRUE;
2818 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2819
2820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2821 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2823 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2824 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2826
2827
2828 // select IF gain to read
2829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2830 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2831
2832 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2833 if_agc_gain = tmp;
2834 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2835 if_agc_gain = (if_agc_gain<<8)|tmp;
2836
2837
2838 // select d1 gain to read.
2839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2840 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2841
2842 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2843 d1_gain = tmp;
2844 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2845 d1_gain = (d1_gain<<8)|tmp;
2846
2847 // select d2 gain to read.
2848 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2849 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2850
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2852 d2_gain = tmp;
2853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
2854 d2_gain = (d2_gain<<8)|tmp;
2855
2856 // select IF gain err to read
2857 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2858 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
2859
2860 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2861 if_agc_err = tmp;
2862 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2863 if_agc_err = (if_agc_err<<8)|tmp;
2864
2865 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
2866 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
2867 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
2868
2869
2870
2871 ULOGD("DEMOD","[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2872 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2873
2874 ULOGD("DEMOD","[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2875 ULOGD("DEMOD","[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
2876
2877 return status;
2878
2879 }
2880
INTERN_DVBT_Show_WIN_Info(void)2881 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
2882 {
2883 MS_U8 tmp = 0;
2884 MS_U8 trigger = 0;
2885 MS_U16 win_len = 0;
2886
2887 MS_BOOL status = TRUE;
2888
2889 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
2890 win_len = tmp;
2891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
2892 win_len = (win_len<<8)|tmp;
2893
2894 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
2895
2896 ULOGD("DEMOD","[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
2897
2898 return status;
2899 }
2900
INTERN_DVBT_Show_td_coeff(void)2901 void INTERN_DVBT_Show_td_coeff(void)
2902 {
2903 MS_U8 status = true;
2904 MS_U8 w1 = 0,w2 = 0,reg = 0;
2905
2906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
2907 w1 = reg;
2908
2909 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
2910 w2 = reg;
2911
2912 ULOGD("DEMOD","[td]w1=0x%x, w2=0x%x\n",w1,w2);
2913
2914 return;
2915 }
2916
2917 /********************************************************
2918 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
2919 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
2920 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2921 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2922 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
2923 * FFT ( b14) : 0~1 => 2K, 8K
2924 ********************************/
INTERN_DVBT_Show_Modulation_info(void)2925 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
2926 {
2927 MS_U16 tps_info;
2928
2929 // ULOGD("DEMOD","[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
2930
2931 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
2932 {
2933 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
2934 MS_U8 constel = tps_info&0x0007;
2935 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
2936 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
2937 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
2938 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
2939
2940 ULOGD("DEMOD","tps=0x%x ",tps_info);
2941
2942 switch(fft)
2943 {
2944 case 0:
2945 ULOGD("DEMOD","mode = 2K,");
2946 break;
2947 case 1:
2948 ULOGD("DEMOD","mode = 8K,");
2949 break;
2950 default:
2951 ULOGD("DEMOD","mode = unknow,");
2952 break;
2953 }
2954 switch(constel)
2955 {
2956 case 0:
2957 ULOGD("DEMOD"," QPSK, ");
2958 break;
2959 case 1:
2960 ULOGD("DEMOD","16QAM, ");
2961 break;
2962 case 2:
2963 ULOGD("DEMOD","64QAM, ");
2964 break;
2965 default:
2966 ULOGD("DEMOD","unknow QAM, ");
2967 break;
2968 }
2969 switch(gi)
2970 {
2971 case 0:
2972 ULOGD("DEMOD","GI=1/32, ");
2973 break;
2974 case 1:
2975 ULOGD("DEMOD","GI=1/16, ");
2976 break;
2977 case 2:
2978 ULOGD("DEMOD","GI= 1/8, ");
2979 break;
2980 case 3:
2981 ULOGD("DEMOD","GI= 1/4, ");
2982 break;
2983 default:
2984 ULOGD("DEMOD","unknow GI, ");
2985 break;
2986 }
2987
2988 switch(hp_cr)
2989 {
2990 case 0:
2991 ULOGD("DEMOD","HP_CR=1/2, ");
2992 break;
2993 case 1:
2994 ULOGD("DEMOD","HP_CR=2/3, ");
2995 break;
2996 case 2:
2997 ULOGD("DEMOD","HP_CR=3/4, ");
2998 break;
2999 case 3:
3000 ULOGD("DEMOD","HP_CR=5/6, ");
3001 break;
3002 case 4:
3003 ULOGD("DEMOD","HP_CR=7/8, ");
3004 break;
3005 default:
3006 ULOGD("DEMOD","unknow hp_cr, ");
3007 break;
3008 }
3009
3010 switch(lp_cr)
3011 {
3012 case 0:
3013 ULOGD("DEMOD","LP_CR=1/2, ");
3014 break;
3015 case 1:
3016 ULOGD("DEMOD","LP_CR=2/3, ");
3017 break;
3018 case 2:
3019 ULOGD("DEMOD","LP_CR=3/4, ");
3020 break;
3021 case 3:
3022 ULOGD("DEMOD","LP_CR=5/6, ");
3023 break;
3024 case 4:
3025 ULOGD("DEMOD","LP_CR=7/8, ");
3026 break;
3027 default:
3028 ULOGD("DEMOD","unknow lp_cr, ");
3029 break;
3030 }
3031
3032 ULOGD("DEMOD"," Hiearchy=0x%x\n",hiearchy);
3033
3034 // ULOGD("DEMOD","\n");
3035 return TRUE;
3036 }
3037 else
3038 {
3039 ULOGD("DEMOD","INVALID\n");
3040 return FALSE;
3041 }
3042 }
3043
3044
3045
3046
INTERN_DVBT_Show_BER_PacketErr(void)3047 void INTERN_DVBT_Show_BER_PacketErr(void)
3048 {
3049 float f_ber = 0;
3050 MS_U16 packetErr = 0;
3051 INTERN_DVBT_GetPostViterbiBer(&f_ber);
3052 INTERN_DVBT_GetPacketErr(&packetErr);
3053
3054 ULOGD("DEMOD","[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3055 return;
3056 }
3057
INTERN_DVBT_Show_Lock_Info(void)3058 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
3059 {
3060
3061 ULOGD("DEMOD","[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
3062 return false;
3063 }
3064
3065
INTERN_DVBT_Show_Demod_Info(void)3066 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
3067 {
3068 MS_U8 demod_state = 0;
3069 MS_BOOL status = true;
3070 static MS_U8 counter = 0;
3071
3072 INTERN_DVBT_get_demod_state(&demod_state);
3073
3074 ULOGD("DEMOD","==========[dvbt]state=%d\n",demod_state);
3075 if (demod_state < 5)
3076 {
3077 INTERN_DVBT_Show_Demod_Version();
3078 INTERN_DVBT_Show_AGC_Info();
3079 INTERN_DVBT_Show_ACI_CI();
3080 }
3081 else if(demod_state < 8)
3082 {
3083 INTERN_DVBT_Show_Demod_Version();
3084 INTERN_DVBT_Show_AGC_Info();
3085 INTERN_DVBT_Show_ACI_CI();
3086 INTERN_DVBT_Show_ChannelLength();
3087 INTERN_DVBT_Get_CFO();
3088 INTERN_DVBT_Get_SFO();
3089 INTERN_DVBT_Show_td_coeff();
3090 }
3091 else if(demod_state < 11)
3092 {
3093 INTERN_DVBT_Show_Demod_Version();
3094 INTERN_DVBT_Show_AGC_Info();
3095 INTERN_DVBT_Show_ACI_CI();
3096 INTERN_DVBT_Show_ChannelLength();
3097 INTERN_DVBT_Get_CFO();
3098 INTERN_DVBT_Get_SFO();
3099 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3100 INTERN_DVBT_Get_SYA_status();
3101 INTERN_DVBT_Show_td_coeff();
3102 }
3103 else if((demod_state == 11) && ((counter%4) == 0))
3104 {
3105 INTERN_DVBT_Show_Demod_Version();
3106 INTERN_DVBT_Show_AGC_Info();
3107 INTERN_DVBT_Show_ACI_CI();
3108 INTERN_DVBT_Show_ChannelLength();
3109 INTERN_DVBT_Get_CFO();
3110 INTERN_DVBT_Get_SFO();
3111 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3112 INTERN_DVBT_Get_SYA_status();
3113 INTERN_DVBT_Show_td_coeff();
3114 INTERN_DVBT_Show_Modulation_info();
3115 INTERN_DVBT_Show_BER_PacketErr();
3116 }
3117 else
3118 status = false;
3119
3120 ULOGD("DEMOD","===========================\n");
3121 counter++;
3122
3123 return status;
3124 }
3125 #endif
3126
3127