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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _INTERN_DVBC_H_ 96 #define _INTERN_DVBC_H_ 97 98 #ifdef _INTERN_DVBT_C_ 99 #define EXTSEL 100 #else 101 #define EXTSEL extern 102 #endif 103 104 #define NEW_TR_MODULE 105 //-------------------------------------------------------------------- 106 107 // #define DEMOD_DYNAMIC_SLAVE_ID_1 0x32 108 // #define DEMOD_DYNAMIC_SLAVE_ID_2 0x72 109 // #define DEMOD_DYNAMIC_SLAVE_ID_3 0xB2 110 // #define DEMOD_DYNAMIC_SLAVE_ID_4 0xF2 111 112 #define DEMOD_ADDR_H 0x00 113 #define DEMOD_ADDR_L 0x01 114 #define DEMOD_WRITE_REG 0x02 115 #define DEMOD_WRITE_REG_EX 0x03 116 #define DEMOD_READ_REG 0x04 117 #define DEMOD_RAM_CONTROL 0x05 118 119 #if 0//DTV_SCAN_AUTO_FINE_TUNE_ENABLE 120 //INTERN_DVBT_ Capture Range fix to 500K 121 #define DEMOD_CAPTURE_RANGE_500_K 500 122 #define DEMOD_CAPTURE_RANGE_SIZE DEMOD_CAPTURE_RANGE_500_K 123 #endif 124 125 #define MDrv_ReadByte(x) HAL_DMD_RIU_ReadByte(x) 126 #define MDrv_WriteByte(x,y) HAL_DMD_RIU_WriteByte(x,y) 127 128 #if 1 129 #define U8 MAPI_U8 130 #define U16 MAPI_U16 131 #define U32 MAPI_U32 132 #define BOOL MAPI_BOOL 133 #define BOOLEAN MAPI_BOOL 134 #if 0 135 #define BIT0 0x01 136 #define BIT1 0x02 137 #define BIT2 0x04 138 #define BIT3 0x08 139 #define BIT4 0x10 140 #define BIT5 0x20 141 #define BIT6 0x40 142 #define BIT7 0x80 143 #endif 144 #define BYTE MAPI_U8 145 146 #define WORD MAPI_WORD 147 #define E_RESULT_SUCCESS MAPI_TRUE 148 #define E_RESULT_FAILURE MAPI_FALSE 149 #define FUNCTION_RESULT MAPI_BOOL 150 151 152 153 154 #define INTERN_DVBC_TS_SERIAL_INVERSION 0 155 #define INTERN_DVBC_TS_PARALLEL_INVERSION 1 156 #define INTERN_DVBC_DTV_DRIVING_LEVEL 1 157 #define INTERN_DVBC_WEAK_SIGNAL_PICTURE_FREEZE_ENABLE 1 158 159 #define SUPPORT_ADAPTIVE_TS_CLK 160 #endif 161 162 typedef enum 163 { 164 E_RF_QAM_MODE_16QAM = 0x00, ///< 16QAM 165 E_RF_QAM_MODE_32QAM = 0x01, ///< 32QAM 166 E_RF_QAM_MODE_64QAM = 0x02, ///< 64QAM 167 E_RF_QAM_MODE_128QAM = 0x03, ///< 128QAM 168 E_RF_QAM_MODE_256QAM = 0x04, ///< 256QAM 169 E_RF_QAM_MODE_INVALID ///< Invalid 170 } RF_CHANNEL_QAM_MODE; 171 172 #if 0 173 typedef enum 174 { 175 COFDM_FEC_LOCK, 176 COFDM_PSYNC_LOCK, 177 COFDM_TPS_LOCK, 178 COFDM_DCR_LOCK, 179 COFDM_AGC_LOCK, 180 COFDM_MODE_DET, 181 182 } COFDM_LOCK_STATUS; 183 184 //-------------------------------------------------------------------- 185 typedef enum 186 { 187 E_SYS_UNKOWN = -1, 188 E_SYS_DVBT, 189 E_SYS_DVBC, 190 E_SYS_ATSC, 191 E_SYS_VIF, 192 193 E_SYS_NUM 194 }E_SYSTEM; 195 196 typedef enum 197 { 198 CMD_SYSTEM_INIT = 0, 199 CMD_DAC_CALI, 200 CMD_DVBT_CONFIG, 201 CMD_DVBC_CONFIG, 202 CMD_VIF_CTRL, 203 CMD_FSM_CTRL, 204 CMD_INDIR_RREG, 205 CMD_INDIR_WREG, 206 CMD_GET_INFO, 207 CMD_TS_CTRL, 208 CMD_TUNED_VALUE, 209 210 CMD_MAX_NUM 211 }E_CMD_CODE; 212 213 typedef enum 214 { 215 pc_op_code = 0, 216 pc_if_freq, 217 pc_sound_sys, 218 pc_vif_vga_maximum_l, 219 pc_vif_vga_maximum_h, 220 pc_scan_mode, 221 pc_vif_top, 222 pc_gain_distribution_thr_l, 223 pc_gain_distribution_thr_h, 224 225 VIF_PARAM_MAX_NUM 226 }E_VIF_PARAM; 227 228 typedef enum 229 { 230 pc_system = 0, 231 232 SYS_PARAM_MAX_NUM 233 }E_SYS_PARAM; 234 235 typedef enum 236 { 237 SET_IF_FREQ = 0, 238 SET_SOUND_SYS, 239 VIF_INIT, 240 SET_VIF_HANDLER, 241 VIF_TOP_ADJUST, 242 243 VIF_CMD_MAX_NUM 244 }E_VIF_CMD; 245 246 typedef enum 247 { 248 TS_PARALLEL = 0, 249 TS_SERIAL = 1, 250 251 TS_MODE_MAX_NUM 252 }E_TS_MODE; 253 254 typedef enum 255 { 256 dac_op_code = 0, 257 dac_idac_ch0, 258 dac_idac_ch1, 259 260 DAC_PARAM_MAX_NUM 261 } 262 E_DAC_PARAM; 263 264 typedef enum 265 { 266 DAC_RUN_CALI = 0, 267 DAC_IDAC_ASSIGN, 268 269 DAC_CMD_MAX_NUM 270 } 271 E_DAC_CMD; 272 273 typedef enum 274 { 275 agc_ref_small, 276 agc_ref_large, 277 agc_ref_aci, 278 ripple_switch_th_l, 279 ripple_switch_th_h, 280 281 TUNED_PARAM_MAX_NUM 282 }E_TUNED_PARAM; 283 284 //@@++ Arki 20100125 285 typedef enum 286 { 287 TS_MODUL_MODE, 288 TS_FFX_VALUE, 289 TS_GUARD_INTERVAL, 290 TS_CODE_RATE, 291 292 TS_PARAM_MAX_NUM 293 }E_SIGNAL_TYPE; 294 //@@-- Arki 20100125 295 296 typedef struct 297 { 298 MS_U8 cmd_code; 299 MS_U8 param[64]; 300 } S_CMDPKTREG; 301 302 typedef enum 303 { 304 E_RF_QAM_MODE_16QAM = 0x00, ///< 16QAM 305 E_RF_QAM_MODE_32QAM = 0x01, ///< 32QAM 306 E_RF_QAM_MODE_64QAM = 0x02, ///< 64QAM 307 E_RF_QAM_MODE_128QAM = 0x03, ///< 128QAM 308 E_RF_QAM_MODE_256QAM = 0x04, ///< 256QAM 309 E_RF_QAM_MODE_INVALID ///< Invalid 310 } RF_CHANNEL_QAM_MODE; 311 312 typedef enum 313 { 314 S0_entry_num, 315 S10_PSYNC_fail_num, 316 S10_TPS_invalid_num, 317 S8_TPS_invalid_num, 318 S6_TPS_unlock_num, 319 S4_Mode_CP_unlock_num, 320 CCI_Tracking_lock_num, 321 CCI_Tracking_lock_p1_num, 322 CCI_Tracking_lock_p2_num, 323 S11_PSYNC_FAIL_LOCKED_num, 324 S11_PSYNC_FAIL_SEARCH_num, 325 lock_time_l, 326 lock_time_h, 327 hw_channel_length_l, 328 hw_channel_length_h, 329 sw_channel_length_l, 330 sw_channel_length_h, 331 sw_offset_SA_l, 332 sw_offset_SA_h, 333 sw_oneshot_peak_num, 334 CI_Indicator, 335 ACI_Indicator, 336 FD_coeff, 337 TD_coeff, 338 SNR_Select, 339 FsaMode, 340 InGI, 341 Fsa_Stop_Track, 342 short_echo_Det, 343 344 DBG_LIST_NUM 345 }DBG_table_type; 346 #endif 347 348 /* 349 // Move to Tuner_SSI.h 350 typedef enum 351 { 352 _QPSK = 0x0, 353 _16QAM = 0x1, 354 _64QAM = 0x2, 355 }E_CONSTEL; 356 357 typedef enum 358 { 359 _CR1Y2 = 0x0, 360 _CR2Y3 = 0x1, 361 _CR3Y4 = 0x2, 362 _CR5Y6 = 0x3, 363 _CR7Y8 = 0x4, 364 }E_CODERATE; 365 366 367 typedef struct 368 { 369 U8 constel; 370 U8 code_rate; 371 float cn_ref; 372 }S_SQI_CN_NORDIGP1_INTERN_DVBT; 373 374 typedef struct 375 { 376 float power_db; 377 U8 sar3_val; 378 }S_INTERN_DVBT_RFAGC_SSI; 379 380 typedef struct 381 { 382 float power_db; 383 U8 agc_val; 384 }S_INTERN_DVBT_IFAGC_SSI; 385 386 typedef struct 387 { 388 U8 constel; 389 U8 code_rate; 390 float p_ref; 391 }S_INTERN_DVBT_SSI_PREF; 392 393 typedef struct 394 { 395 float attn_db; 396 U8 agc_err; 397 }S_INTERN_DVBT_IFAGC_ERR; 398 */ 399 //-------------------------------------------------------------------- 400 typedef struct 401 { 402 MS_U8 cmd_code; 403 MS_U8 param[64]; 404 } S_CMDPKTREG; 405 406 typedef enum 407 { 408 TS_MODUL_MODE, 409 TS_FFX_VALUE, 410 TS_GUARD_INTERVAL, 411 TS_CODE_RATE, 412 413 TS_PARAM_MAX_NUM 414 }E_SIGNAL_TYPE; 415 416 typedef enum 417 { 418 CMD_SYSTEM_INIT = 0, 419 CMD_DAC_CALI, 420 CMD_DVBT_CONFIG, 421 CMD_DVBC_CONFIG, 422 CMD_VIF_CTRL, 423 CMD_FSM_CTRL, 424 CMD_INDIR_RREG, 425 CMD_INDIR_WREG, 426 CMD_GET_INFO, 427 CMD_TS_CTRL, 428 CMD_TUNED_VALUE, 429 430 CMD_MAX_NUM 431 }E_CMD_CODE; 432 433 typedef enum 434 { 435 TS_PARALLEL = 0, 436 TS_SERIAL = 1, 437 438 TS_MODE_MAX_NUM 439 }E_TS_MODE; 440 441 typedef enum 442 { 443 E_SYS_UNKOWN = -1, 444 E_SYS_DVBT, 445 E_SYS_DVBC, 446 E_SYS_ATSC, 447 E_SYS_VIF, 448 449 E_SYS_NUM 450 }E_SYSTEM; 451 //-------------------------------------------------------------------- 452 MS_BOOL INTERN_DVBC_Reset ( void ); 453 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable); 454 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt); 455 MS_BOOL INTERN_DVBC_Exit ( void ); 456 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize); 457 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size); 458 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk); 459 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num); 460 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable); 461 462 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, MS_U32 u32TimeInterval); 463 //waiting add 464 MS_BOOL INTERN_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err); 465 //MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue); 466 //MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue); 467 MS_BOOL INTERN_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg); 468 469 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr); 470 471 MS_BOOL INTERN_DVBC_GetSNR(MS_U16 *snr_reg); 472 473 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id); 474 // MS_BOOL INTERN_DVBC_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType); 475 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver); 476 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate); 477 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW); 478 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode); 479 #ifdef SUPPORT_ADAPTIVE_TS_CLK 480 MS_BOOL INTERN_DVBC_Adaptive_TS_CLK(void); 481 MS_BOOL INTERN_DVBC_Locked_Task(void); 482 #endif 483 //-------------------------------------------------------------------- 484 485 #define INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY 486 487 #undef EXTSEL 488 #endif 489 490