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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "ULog.h"
108 #include "MsCommon.h"
109 #include "MsIRQ.h"
110 #include "MsOS.h"
111 //#include "apiPWS.h"
112
113 #include "MsTypes.h"
114 #include "drvBDMA.h"
115 //#include "drvIIC.h"
116 //#include "msAPI_Tuner.h"
117 //#include "msAPI_MIU.h"
118 //#include "BinInfo.h"
119 //#include "halVif.h"
120 #include "drvDMD_INTERN_DVBC.h"
121 #include "halDMD_INTERN_DVBC.h"
122 #include "halDMD_INTERN_common.h"
123 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
124 #include "InfoBlock.h"
125 #endif
126 #include "drvMMIO.h"
127 //#include "TDAG4D01A_SSI_DVBT.c"
128 #include "drvDMD_VD_MBX.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
133
134 #define TDE_REG_BASE 0x2400UL
135 #define INNC_REG_BASE 0x9b00UL // P2 = 1, 0x11b00 -> 0x1b00
136 #define EQE_REG_BASE 0x9a00UL // P2 = 1, 0x11a00 -> 0x1a00
137 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00
138 #define MBX_REG_BASE 0x2F00UL
139
140 #ifdef MS_DEBUG
141 #define DBG_INTERN_DVBC(x) x
142 #define DBG_GET_SIGNAL_DVBC(x) x
143 #define DBG_INTERN_DVBC_TIME(x) x
144 #define DBG_INTERN_DVBC_LOCK(x) x
145 #define INTERN_DVBC_INTERNAL_DEBUG 0
146 #else
147 #define DBG_INTERN_DVBC(x) //x
148 #define DBG_GET_SIGNAL_DVBC(x) //x
149 #define DBG_INTERN_DVBC_TIME(x) //x
150 #define DBG_INTERN_DVBC_LOCK(x) //x
151 #define INTERN_DVBC_INTERNAL_DEBUG 0
152 #endif
153 #define DBG_DUMP_LOAD_DSP_TIME 0
154
155
156 //#define SIGNAL_LEVEL_OFFSET 0.00f
157 //#define TAKEOVERPOINT -60.0f
158 //#define TAKEOVERRANGE 0.5f
159 //#define LOG10_OFFSET -0.21f
160 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
161 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
162
163 #define TUNER_IF 36167
164
165 #define TS_SER_C 0x00 //0: parallel 1:serial
166
167 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
168 #define TS_INV_C 0x01
169 #else
170 #define TS_INV_C 0x00
171 #endif
172
173 #define DVBC_FS 45474 //24000
174 #define CFG_ZIF 0x00 //For ZIF ,FC=0
175 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
176 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
177 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
178 #define FS_L_C (DVBC_FS&0xFF)
179 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
180 #define IQ_SWAP_C 0x00
181 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
182 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
183 // Symbol Rate: 6875 = 0x1ADB
184 // Symbol Rate: 6900 = 0x1AF4
185 // Symbol Rate: 7000 = 0x1B58
186 // Symbol Rate: 4000 = 0x0FA0
187 // Symbol Rate: 6125 = 0x17ED
188 #define SR0_H 0x1A
189 #define SR0_L 0xF4 //6900
190 #define SR1_H 0x1B
191 #define SR1_L 0x58 //7000
192 #define SR2_H 0x17
193 #define SR2_L 0xED //6125
194 #define SR3_H 0x0F
195 #define SR3_L 0xA0 //4000
196 #define SR4_H 0x1B
197 #define SR4_L 0x26 //6950
198 #define SR5_H 0x1A //0xDB
199 #define SR5_L 0xDB //0x1A //6875
200 #define SR6_H 0x1C
201 #define SR6_L 0x20 //7200
202 #define SR7_H 0x1C
203 #define SR7_L 0x52 //7250
204 #define SR8_H 0x0B
205 #define SR8_L 0xB8 //3000
206 #define SR9_H 0x03
207 #define SR9_L 0xE8 //1000
208 #define SR10_H 0x07
209 #define SR10_L 0xD0 //2000
210 #define SR11_H 0x00
211 #define SR11_L 0x00 //0000
212
213
214 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
215
216 // SAR dependent
217 #define NO_SIGNAL_TH_A 0xA3
218 // Tuner dependent
219 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
220 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
221 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
222 #define NO_SIGNAL_TH_C_H 0xff //0x00
223 #define DAGC1_REF 0x70
224 #define DAGC2_REF 0x30
225 #define AGC_REF_L 0x00
226 #define AGC_REF_H 0x06
227
228 #define INTERN_AUTO_SR_C 1
229 #define INTERN_AUTO_QAM_C 1
230
231 #define ATV_DET_EN 1
232
233 #if 0
234 MS_U8 INTERN_DVBC_DSPREG[] =
235 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
236 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
237 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
238 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
239 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
240 };
241 #else
242 MS_U8 INTERN_DVBC_DSPREG[] =
243 {
244 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
245 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
246 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
247 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
248 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
249 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
250 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
251 };
252 #endif
253 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
254
255 //-----------------------------------------------------------------------
256 /****************************************************************
257 *Local Variables *
258 ****************************************************************/
259
260 //static MS_BOOL TPSLock = 0;
261 static MS_U32 u32ChkScanTimeStartDVBC = 0;
262 static MS_U8 g_dvbc_lock = 0;
263
264 //Global Variables
265 S_CMDPKTREG gsCmdPacketDVBC;
266 //MS_U8 gCalIdacCh0, gCalIdacCh1;
267 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
268 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
269 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
270 MS_U8 INTERN_DVBC_table[] = {
271 #include "fwDMD_INTERN_DVBC.dat"
272 };
273
274 #endif
275
276 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
277 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
278 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
279 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
280 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW);
281 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
282 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
283 //MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
284
285 #if (INTERN_DVBC_INTERNAL_DEBUG)
286 void INTERN_DVBC_info(void);
287 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
288 #endif
289
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)290 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
291 {
292 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
293 MS_U8 status = TRUE;
294 MS_U16 u16DspAddr = 0;
295
296 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init\n");
297
298 #if 0//def MS_DEBUG
299 {
300 MS_U8 u8buffer[256];
301 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Reset\n");
302 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
303 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
304
305 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
306 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
307 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
308 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
309 ULOGD("DEMOD","%x ", u8buffer[idx]);
310 ULOGD("DEMOD","\n");
311
312 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Value\n");
313 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
314 ULOGD("DEMOD","%x ", INTERN_DVBC_DSPREG[idx]);
315 ULOGD("DEMOD","\n");
316 }
317 #endif
318
319 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
320 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
321
322 // readback to confirm.
323 #ifdef MS_DEBUG
324 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
325 {
326 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
327 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
328 {
329 ULOGD("DEMOD","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
330 }
331 }
332 #endif
333
334 if (u8DVBC_DSPReg != NULL)
335 {
336 if (1 == u8DVBC_DSPReg[0])
337 {
338 u8DVBC_DSPReg+=2;
339 for (idx = 0; idx<u8Size; idx++)
340 {
341 u16DspAddr = *u8DVBC_DSPReg;
342 u8DVBC_DSPReg++;
343 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
344 u8DVBC_DSPReg++;
345 u8Mask = *u8DVBC_DSPReg;
346 u8DVBC_DSPReg++;
347 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
348 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
349 u8DVBC_DSPReg++;
350 ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
351 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
352 }
353 }
354 else
355 {
356 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
357 }
358 }
359
360 #if 0//def MS_DEBUG
361 {
362 MS_U8 u8buffer[256];
363 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
364 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
365 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack\n");
366 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
367 ULOGD("DEMOD","%x ", u8buffer[idx]);
368 ULOGD("DEMOD","\n");
369 }
370 #endif
371
372 #if 0//def MS_DEBUG
373 {
374 MS_U8 u8buffer[256];
375 for (idx = 0; idx<128; idx++)
376 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
377 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
378 for (idx = 0; idx<128; idx++)
379 {
380 ULOGD("DEMOD","%x ", u8buffer[idx]);
381 if ((idx & 0xF) == 0xF) ULOGD("DEMOD","\n");
382 }
383 ULOGD("DEMOD","\n");
384 }
385 #endif
386 return status;
387 }
388
389 /***********************************************************************************
390 Subject: Command Packet Interface
391 Function: INTERN_DVBC_Cmd_Packet_Send
392 Parmeter:
393 Return: MS_BOOL
394 Remark:
395 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)396 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
397 {
398 MS_U8 status = true, indx;
399 MS_U8 reg_val, timeout = 0;
400 return TRUE;
401 // ==== Command Phase ===================
402 ULOGD("DEMOD","--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
403 pCmdPacket->param[0],pCmdPacket->param[1],
404 pCmdPacket->param[2],pCmdPacket->param[3],
405 pCmdPacket->param[4],pCmdPacket->param[5] );
406
407 // wait _BIT_END clear
408 do
409 {
410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
411 if((reg_val & _BIT_END) != _BIT_END)
412 {
413 break;
414 }
415 MsOS_DelayTask(5);
416 if (timeout > 200)
417 {
418 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
419 return false;
420 }
421 timeout++;
422 } while (1);
423
424 // set cmd_3:0 and _BIT_START
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
426 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
428
429
430 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
431 // wait _BIT_START clear
432 do
433 {
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
435 if((reg_val & _BIT_START) != _BIT_START)
436 {
437 break;
438 }
439 MsOS_DelayTask(10);
440 if (timeout > 200)
441 {
442 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
443 return false;
444 }
445 timeout++;
446 } while (1);
447
448 // ==== Data Phase ======================
449
450 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
451
452 for (indx = 0; indx < param_cnt; indx++)
453 {
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
455 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
456
457 // set param[indx] and _BIT_DRQ
458 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
460 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
461
462 // wait _BIT_DRQ clear
463 do
464 {
465 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
466 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
467 {
468 break;
469 }
470 MsOS_DelayTask(5);
471 if (timeout > 200)
472 {
473 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
474 return false;
475 }
476 timeout++;
477 } while (1);
478 }
479
480 // ==== End Phase =======================
481
482 // set _BIT_END to finish command
483 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
484 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
485 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
486 return status;
487 }
488
489
490 /***********************************************************************************
491 Subject: Command Packet Interface
492 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
493 Parmeter:
494 Return: MS_BOOL
495 Remark:
496 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)497 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
498 {
499 return TRUE;
500 }
501
502 /***********************************************************************************
503 Subject: SoftStop
504 Function: INTERN_DVBC_SoftStop
505 Parmeter:
506 Return: MS_BOOL
507 Remark:
508 ************************************************************************************/
509
INTERN_DVBC_SoftStop(void)510 MS_BOOL INTERN_DVBC_SoftStop ( void )
511 {
512 #if 1
513 MS_U16 u8WaitCnt=0;
514
515 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
516 {
517 ULOGD("DEMOD",">> MB Busy!\n");
518 return FALSE;
519 }
520
521 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
522
523 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
524 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
525
526 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
527 {
528 #if TEST_EMBEDED_DEMOD
529 MsOS_DelayTask(1); // << Ken 20090629
530 #endif
531 if (u8WaitCnt++ >= 0x7FFF)
532 {
533 ULOGD("DEMOD",">> DVBC SoftStop Fail!\n");
534 return FALSE;
535 }
536 }
537
538 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
539 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
540 #endif
541 return TRUE;
542 }
543
544
545 /***********************************************************************************
546 Subject: Reset
547 Function: INTERN_DVBC_Reset
548 Parmeter:
549 Return: MS_BOOL
550 Remark:
551 ************************************************************************************/
552 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)553 MS_BOOL INTERN_DVBC_Reset ( void )
554 {
555 ULOGD("DEMOD"," @INTERN_DVBC_reset\n");
556
557 //DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
558
559 // INTERN_DVBC_SoftStop();
560
561
562 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
563 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
564 MsOS_DelayTask(5);
565 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
566 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
567 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
568 MsOS_DelayTask(5);
569
570 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
571 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
572
573 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
574 g_dvbc_lock = 0;
575
576 return TRUE;
577 }
578
579 /***********************************************************************************
580 Subject: Exit
581 Function: INTERN_DVBC_Exit
582 Parmeter:
583 Return: MS_BOOL
584 Remark:
585 ************************************************************************************/
INTERN_DVBC_Exit(void)586 MS_BOOL INTERN_DVBC_Exit ( void )
587 {
588
589 return INTERN_DVBC_SoftStop();
590 }
591
592 /***********************************************************************************
593 Subject: Load DSP code to chip
594 Function: INTERN_DVBC_LoadDSPCode
595 Parmeter:
596 Return: MS_BOOL
597 Remark:
598 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)599 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
600 {
601 MS_U8 udata = 0x00;
602 MS_U16 i;
603 MS_U16 fail_cnt=0;
604
605 #if (DBG_DUMP_LOAD_DSP_TIME==1)
606 MS_U32 u32Time;
607 #endif
608
609
610 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
611 BININFO BinInfo;
612 MS_BOOL bResult;
613 MS_U32 u32GEAddr;
614 MS_U8 Data;
615 MS_S8 op;
616 MS_U32 srcaddr;
617 MS_U32 len;
618 MS_U32 SizeBy4K;
619 MS_U16 u16Counter=0;
620 MS_U8 *pU8Data;
621 #endif
622
623 #if 0
624 if(HAL_DMD_RIU_ReadByte(0x101E3E))
625 {
626 ULOGD("DEMOD","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
627 return FALSE;
628 }
629 #endif
630
631 // MDrv_Sys_DisableWatchDog();
632
633
634 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
635 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
636 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
637 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
638 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
639 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
640
641 //// Load code thru VDMCU_IF ////
642 ULOGD("DEMOD",">Load Code.....\n");
643 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
644 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
645 {
646 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
647 }
648 #else
649 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
650 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
651 if ( bResult != PASS )
652 {
653 return FALSE;
654 }
655 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
656
657 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
658 InfoBlock_Flash_2_Checking_Start(&BinInfo);
659 #endif
660
661 #if OBA2
662 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
663 #else
664 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
665 #endif
666
667 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
668 InfoBlock_Flash_2_Checking_End(&BinInfo);
669 #endif
670
671 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
672 SizeBy4K=BinInfo.B_Len/0x1000;
673 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
674
675 #if (DBG_DUMP_LOAD_DSP_TIME==1)
676 u32Time = msAPI_Timer_GetTime0();
677 #endif
678
679 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
680
681 for (i=0;i<=SizeBy4K;i++)
682 {
683 if(i==SizeBy4K)
684 len=BinInfo.B_Len%0x1000;
685 else
686 len=0x1000;
687
688 srcaddr = u32GEAddr+(0x1000*i);
689 //ULOGD("DEMOD","\t i = %08X\n", i);
690 //ULOGD("DEMOD","\t len = %08X\n", len);
691 op = 1;
692 u16Counter = 0 ;
693 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
694 while(len--)
695 {
696 u16Counter ++ ;
697 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
698 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
699 #if OBA2
700 pU8Data = (MS_U8 *)(srcaddr);
701 #else
702 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
703 #endif
704 Data = *pU8Data;
705
706 #if 0
707 if(u16Counter < 0x100)
708 ULOGD("DEMOD","0x%bx,", Data);
709 #endif
710 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
711
712 srcaddr += op;
713 }
714 // ULOGD("DEMOD","\n\n\n");
715 }
716
717 #if (DBG_DUMP_LOAD_DSP_TIME==1)
718 ULOGD("DEMOD","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
719 #endif
720
721 #endif
722
723 //// Content verification ////
724 ULOGD("DEMOD",">Verify Code...\n");
725
726 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
727 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
728
729 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
730 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
731 {
732 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
733 if (udata != INTERN_DVBC_table[i])
734 {
735 ULOGD("DEMOD",">fail add = 0x%x\n", i);
736 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBC_table[i]);
737 ULOGD("DEMOD",">data = 0x%x\n", udata);
738
739 if (fail_cnt > 10)
740 {
741 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
742 return false;
743 }
744 fail_cnt++;
745 }
746 }
747 #else
748 for (i=0;i<=SizeBy4K;i++)
749 {
750 if(i==SizeBy4K)
751 len=BinInfo.B_Len%0x1000;
752 else
753 len=0x1000;
754
755 srcaddr = u32GEAddr+(0x1000*i);
756 //ULOGD("DEMOD","\t i = %08LX\n", i);
757 //ULOGD("DEMOD","\t len = %08LX\n", len);
758 op = 1;
759 u16Counter = 0 ;
760 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
761 while(len--)
762 {
763 u16Counter ++ ;
764 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
765 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
766 #if OBA2
767 pU8Data = (MS_U8 *)(srcaddr);
768 #else
769 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
770 #endif
771 Data = *pU8Data;
772
773 #if 0
774 if(u16Counter < 0x100)
775 ULOGD("DEMOD","0x%bx,", Data);
776 #endif
777 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
778 if (udata != Data)
779 {
780 ULOGD("DEMOD",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
781 ULOGD("DEMOD",">code = 0x%x\n", Data);
782 ULOGD("DEMOD",">data = 0x%x\n", udata);
783
784 if (fail_cnt++ > 10)
785 {
786 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
787 return false;
788 }
789 }
790
791 srcaddr += op;
792 }
793 // ULOGD("DEMOD","\n\n\n");
794 }
795 #endif
796
797 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
798 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
799 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
800 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
801
802 ULOGD("DEMOD",">DSP Loadcode done.");
803 //while(load_data_variable);
804 #if 0
805 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
806 INTERN_DVBC_Active(ENABLE);
807 while(1);
808 #endif
809 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
810
811 return TRUE;
812 }
813
814 /***********************************************************************************
815 Subject: DVB-T CLKGEN initialized function
816 Function: INTERN_DVBC_Power_On_Initialization
817 Parmeter:
818 Return: MS_BOOL
819 Remark:
820 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)821 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
822 {
823 // MS_U8 temp_val;
824
825 HAL_DMD_RIU_WriteByte(0x103c0e, 0x00); //mux from DMD MCU to HK.
826 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
827 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
828
829 // CLK_DMDMCU clock setting
830 // [0] disable clock
831 // [1] invert clock
832 // [4:2]
833 // 000:170 MHz(MPLL_DIV_BUf)
834 // 001:160MHz
835 // 010:144MHz
836 // 011:123MHz
837 // 100:108MHz
838 // 101:mem_clcok
839 // 110:mem_clock div 2
840 // 111:select XTAL
841 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
842 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
843
844 // set parallet ts clock
845 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
846 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
847 // wriu 0x103301 0x06
848 // wriu 0x103300 0x19
849
850
851 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
852 HAL_DMD_RIU_WriteByte(0x103301,0x07);
853 HAL_DMD_RIU_WriteByte(0x103300,0x13);
854
855 // enable atsc, DVBTC ts clock
856 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
857 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
858 // wriu 0x103309 0x00
859 // wriu 0x103308 0x00
860
861 HAL_DMD_RIU_WriteByte(0x103309,0x00);
862 HAL_DMD_RIU_WriteByte(0x103308,0x00);
863
864 // enable dvbc adc clock
865 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
866 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
867 // wriu 0x103315 0x00
868 // wriu 0x103314 0x00
869
870 HAL_DMD_RIU_WriteByte(0x103315,0x00);
871 HAL_DMD_RIU_WriteByte(0x103314,0x00);
872
873 // Reset TS divider
874 HAL_DMD_RIU_WriteByte(0x103302,0x01);
875 HAL_DMD_RIU_WriteByte(0x103302,0x00);
876
877 // [Maxim] enable ADCI clock & ADCQ clock
878 // h0010 h0010 3 0 reg_ckg_dvbtc_adc_i 3 0 4 h1
879 // h0010 h0010 11 8 reg_ckg_dvbtc_adc_q 3 0 4 h1
880 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
881 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h10, 2'b11, 16'h0000); // enable dvbc adc clock
882 //wriu 0x103321 0x00
883 //wriu 0x103320 0x00
884 HAL_DMD_RIU_WriteByte(0x103321,0x00);
885 HAL_DMD_RIU_WriteByte(0x103320,0x00);
886
887
888 HAL_DMD_RIU_WriteByte(0x152929,0x00);
889 HAL_DMD_RIU_WriteByte(0x152928,0x04);
890
891 HAL_DMD_RIU_WriteByte(0x152903,0x04);
892 HAL_DMD_RIU_WriteByte(0x152902,0x04);
893
894 HAL_DMD_RIU_WriteByte(0x152905,0x00);
895 HAL_DMD_RIU_WriteByte(0x152904,0x00);
896
897 HAL_DMD_RIU_WriteByte(0x152907,0x04);
898 HAL_DMD_RIU_WriteByte(0x152906,0x00);
899
900 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
901 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
902
903
904 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
905 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
906
907 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
908 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
909
910 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
911 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
912
913 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
914 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
915
916 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
917 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
918
919 HAL_DMD_RIU_WriteByte(0x111f69,0x88);
920 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
921
922 HAL_DMD_RIU_WriteByte(0x111f4b,0x01);
923 HAL_DMD_RIU_WriteByte(0x111f4a,0x11);
924
925 HAL_DMD_RIU_WriteByte(0x152923,0x00);
926 HAL_DMD_RIU_WriteByte(0x152922,0x44);
927
928 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
929 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
930
931 HAL_DMD_RIU_WriteByte(0x15296d,0x00);
932 HAL_DMD_RIU_WriteByte(0x15296c,0x81);
933
934 HAL_DMD_RIU_WriteByte(0x152971,0x1c);
935 HAL_DMD_RIU_WriteByte(0x152970,0xc1);
936
937 HAL_DMD_RIU_WriteByte(0x152977,0x08);
938 HAL_DMD_RIU_WriteByte(0x152976,0x08);
939
940 HAL_DMD_RIU_WriteByte(0x152981,0x00);
941 HAL_DMD_RIU_WriteByte(0x152980,0x00);
942
943 HAL_DMD_RIU_WriteByte(0x152983,0x00);
944 HAL_DMD_RIU_WriteByte(0x152982,0x00);
945
946 HAL_DMD_RIU_WriteByte(0x152985,0x00);
947 HAL_DMD_RIU_WriteByte(0x152984,0x00);
948
949 HAL_DMD_RIU_WriteByte(0x152987,0x00);
950 HAL_DMD_RIU_WriteByte(0x152986,0x00);
951
952 HAL_DMD_RIU_WriteByte(0x111feb,0x18);
953 HAL_DMD_RIU_WriteByte(0x111fea,0x14);
954
955 HAL_DMD_RIU_WriteByte(0x111f74,0x10);
956
957 HAL_DMD_RIU_WriteByte(0x111f77,0x01);
958
959 HAL_DMD_RIU_WriteByte(0x111f79,0x41);
960 HAL_DMD_RIU_WriteByte(0x111f78,0x10);
961
962 HAL_DMD_RIU_WriteByte(0x111fe0,0x08);
963
964 HAL_DMD_RIU_WriteByte(0x111fe3,0x08);
965 HAL_DMD_RIU_WriteByte(0x111fe2,0x10);
966
967 HAL_DMD_RIU_WriteByte(0x111ff0,0x08);
968
969 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
970
971 // SRAM End Address
972 HAL_DMD_RIU_WriteByte(0x111707,0xff);
973 HAL_DMD_RIU_WriteByte(0x111706,0xff);
974
975 // DRAM Disable
976 HAL_DMD_RIU_WriteByte(0x111718,HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
977
978 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
979
980 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
981 }
982
983
984 /***********************************************************************************
985 Subject: Power on initialized function
986 Function: INTERN_DVBC_Power_On_Initialization
987 Parmeter:
988 Return: MS_BOOL
989 Remark:
990 ************************************************************************************/
991
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)992 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
993 {
994 MS_U8 status = true;
995 ULOGD("DEMOD","INTERN_DVBC_Power_On_Initialization\n");
996
997 #if defined(PWS_ENABLE)
998 Mapi_PWS_Stop_VDMCU();
999 #endif
1000
1001 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1002 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1003 //// Firmware download //////////
1004 ULOGD("DEMOD","INTERN_DVBC Load DSP...\n");
1005 //MsOS_DelayTask(100);
1006
1007 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
1008 {
1009 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1010 {
1011 ULOGD("DEMOD","DVB-C Load DSP Code Fail\n");
1012 return FALSE;
1013 }
1014 else
1015 {
1016 ULOGD("DEMOD","DVB-C Load DSP Code OK\n");
1017 }
1018 }
1019
1020 status &= INTERN_DVBC_Reset();
1021
1022 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1023
1024 return status;
1025 }
1026 /************************************************************************************************
1027 Subject: Driving control
1028 Function: INTERN_DVBC_Driving_Control
1029 Parmeter: bInversionEnable : TRUE For High
1030 Return: void
1031 Remark:
1032 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1033 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1034 {
1035 MS_U8 u8Temp;
1036
1037 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1038
1039 if (bEnable)
1040 {
1041 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1042 }
1043 else
1044 {
1045 u8Temp = u8Temp & (~0x01);
1046 }
1047
1048 ULOGD("DEMOD","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp);
1049 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1050 }
1051 /************************************************************************************************
1052 Subject: Clk Inversion control
1053 Function: INTERN_DVBC_Clk_Inversion_Control
1054 Parmeter: bInversionEnable : TRUE For Inversion Action
1055 Return: void
1056 Remark:
1057 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1058 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1059 {
1060 MS_U8 u8Temp;
1061
1062 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1063
1064 if (bInversionEnable)
1065 {
1066 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1067 }
1068 else
1069 {
1070 u8Temp = u8Temp & (~0x02);
1071 }
1072
1073 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
1074 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1075 }
1076 /************************************************************************************************
1077 Subject: Transport stream serial/parallel control
1078 Function: INTERN_DVBC_Serial_Control
1079 Parmeter: bEnable : TRUE For serial
1080 Return: MS_BOOL :
1081 Remark:
1082 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1083 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1084 {
1085 MS_U8 status = true;
1086 return status;
1087
1088
1089 }
1090
1091 /************************************************************************************************
1092 Subject: TS1 output control
1093 Function: INTERN_DVBC_PAD_TS1_Enable
1094 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1095 Return: void
1096 Remark:
1097 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1098 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1099 {
1100 ULOGD("DEMOD"," @INTERN_DVBC_TS1_Enable... \n");
1101
1102 if(flag) // PAD_TS1 Enable TS CLK PAD
1103 {
1104 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1105 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1106 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1107 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1108 }
1109 else // PAD_TS1 Disable TS CLK PAD
1110 {
1111 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1112 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1113 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1114 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1115 }
1116 }
1117
1118 /************************************************************************************************
1119 Subject: channel change config
1120 Function: INTERN_DVBC_Config
1121 Parmeter: BW: bandwidth
1122 Return: MS_BOOL :
1123 Remark:
1124 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1125 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1126 {
1127
1128 MS_U8 status = true;
1129 MS_U8 reg_symrate_l, reg_symrate_h;
1130 //MS_U16 u16Fc = 0;
1131 // force
1132 // u16SymbolRate = 0;
1133 // eQamMode = DMD_DVBC_QAMAUTO;
1134
1135 pu16_symbol_rate_list = pu16_symbol_rate_list;
1136 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1137
1138 //DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
1139 //DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
1140
1141 if (u8TSClk == 0xFF) u8TSClk=0x13;
1142
1143 /*
1144 switch(u32IFFreq)
1145 {
1146 case 36125:
1147 case 36167:
1148 case 36000:
1149 case 6000:
1150 case 4560:
1151 //u16Fc = DVBC_FS - u32IFFreq;
1152 DBG_INTERN_DVBC(ULOGD("DEMOD","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1153 break;
1154 case 44000:
1155 default:
1156 ULOGD("DEMOD","IF frequency not supported\n");
1157 status = false;
1158 break;
1159 }
1160 */
1161
1162 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1163 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1164
1165 status &= INTERN_DVBC_Reset();
1166
1167 if (eQamMode == DMD_DVBC_QAMAUTO)
1168 {
1169 ULOGD("DEMOD","DMD_DVBC_QAMAUTO\n");
1170 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1171 // give default value.
1172 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1173 }
1174 else
1175 {
1176 ULOGD("DEMOD","DMD_DVBC_QAM %d\n", eQamMode);
1177 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1178 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1179 }
1180 // auto symbol rate enable/disable
1181 if (u16SymbolRate == 0)
1182 {
1183 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1184 }
1185 else
1186 {
1187 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1188 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1189 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1190 }
1191 // TS mode
1192 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1193
1194 // IQ Swap
1195 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1196
1197 // Fc
1198 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1199 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1200 // Lif
1201 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1202 // Fif
1203 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1204 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1205
1206 //// INTERN_DVBC system init: DVB-C //////////
1207 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1208
1209 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1210 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1211
1212 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1213 INTERN_DVBC_Show_Demod_Version();
1214 #endif
1215
1216 return status;
1217 }
1218 /************************************************************************************************
1219 Subject: enable hw to lock channel
1220 Function: INTERN_DVBC_Active
1221 Parmeter: bEnable
1222 Return: MS_BOOL
1223 Remark:
1224 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1225 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1226 {
1227 MS_U8 status = true;
1228
1229 ULOGD("DEMOD"," @INTERN_DVBC_active\n");
1230
1231 //// INTERN_DVBC Finite State Machine on/off //////////
1232 #if 0
1233 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1234
1235 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1236 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1237 #else
1238 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1239 #endif
1240
1241 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1242 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1243 return status;
1244 }
1245
1246 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBC_Adaptive_TS_CLK(void)1247 MS_BOOL INTERN_DVBC_Adaptive_TS_CLK(void)
1248 {
1249 MS_U8 u8_ts_clk=0x00;
1250 MS_U8 TS_Clock_Temp;
1251 MS_U8 CLK_source=0;
1252
1253 u8_ts_clk = HAL_DMD_RIU_ReadByte(MBRegBase+0x15);
1254
1255 CLK_source=(u8_ts_clk>>6);
1256 u8_ts_clk=u8_ts_clk&0x1F;
1257
1258 //reg_atsc_dvb_div_reset =1 ; CLKGEN1
1259 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1260 TS_Clock_Temp=TS_Clock_Temp|0x01;
1261 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1262
1263 //set TS clock source div 5
1264 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01);
1265 if (CLK_source==0)
1266 TS_Clock_Temp &=(~0x01);
1267 else
1268 TS_Clock_Temp |= (0x01);
1269
1270 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp);
1271
1272 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
1273 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x00);
1274 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_ts_clk ;
1275 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x00,TS_Clock_Temp);
1276
1277 //reg_atsc_dvb_div_reset =0
1278 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1279 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
1280 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1281
1282 // set ts FIFO
1283 // reg_RS_BACKEND
1284 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
1285 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ;
1286
1287 // enable ts
1288 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ;
1289 TS_Clock_Temp=TS_Clock_Temp|0x01;
1290 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ;
1291
1292 //debug: re-check ts clock
1293 //TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1294 //TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
1295 //printf("===================================================================\n");
1296 //printf("Support adaptive TS CLK in polling mode! \n");
1297 //printf("===================================================================\n");
1298
1299 return TRUE;
1300 }
1301
INTERN_DVBC_Locked_Task(void)1302 MS_BOOL INTERN_DVBC_Locked_Task(void)
1303 {
1304 INTERN_DVBC_Adaptive_TS_CLK();
1305
1306 //extension task
1307 {
1308
1309 }
1310
1311 return TRUE;
1312 }
1313 #endif
1314
1315
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,MS_U32 u32CurrRFPowerDbm,MS_U32 u32NoChannelRFPowerDbm,MS_U32 u32TimeInterval)1316 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1317 {
1318 MS_U16 u16Address = 0;
1319 MS_U8 cData = 0;
1320 MS_U8 cBitMask = 0;
1321
1322 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1323 MS_U8 unlock_indicator=0;
1324 #endif
1325
1326 if (u32CurrRFPowerDbm < 1000)
1327 {
1328 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1329 {
1330 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1331 if (cData > 5)
1332 {
1333 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1334 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1335 }
1336 else
1337 {
1338 if ((u32CurrRFPowerDbm<u32NoChannelRFPowerDbm) && u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000)
1339 {
1340 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1341 }
1342 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1343 {
1344 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1345 #ifdef MS_DEBUG
1346 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1347 #endif
1348 return TRUE;
1349 }
1350 }
1351 #ifdef MS_DEBUG
1352 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%d Threshold:%d Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, u32CurrRFPowerDbm, u32NoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1353 #endif
1354 }
1355 }
1356
1357 {
1358 switch( eType )
1359 {
1360 case DMD_DVBC_GETLOCK_FEC_LOCK:
1361 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1362 #if (INTERN_DVBC_INTERNAL_DEBUG)
1363 INTERN_DVBC_info();
1364 #endif
1365 ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData);
1366 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1367 MDrv_SYS_DMD_VD_MBX_ReadReg(MBX_REG_BASE + 0x16, &unlock_indicator);
1368 #endif
1369 if (cData == 0x0C)
1370 {
1371 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1372 if(g_dvbc_lock == 0 || unlock_indicator==0x01)
1373 #else
1374 if(g_dvbc_lock == 0)
1375 #endif
1376 {
1377 g_dvbc_lock = 1;
1378 ULOGD("DEMOD","[T12][DVBC]lock++++\n");
1379
1380 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1381 INTERN_DVBC_Locked_Task();
1382 MDrv_SYS_DMD_VD_MBX_WriteReg(MBX_REG_BASE + 0x16, 0x00);
1383 #endif
1384 }
1385 return TRUE;
1386 }
1387 else
1388 {
1389 if(g_dvbc_lock == 1)
1390 {
1391 g_dvbc_lock = 0;
1392 ULOGD("DEMOD","[T12][DVBC]unlock----\n");
1393 }
1394 return FALSE;
1395 }
1396 break;
1397
1398 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1399 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1400 cBitMask = BIT(1);
1401 break;
1402
1403 case DMD_DVBC_GETLOCK_DCR_LOCK:
1404 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1405 cBitMask = BIT(0);
1406 break;
1407
1408 case DMD_DVBC_GETLOCK_AGC_LOCK:
1409 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1410 cBitMask = BIT(0);
1411 break;
1412
1413 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1414 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1415 cBitMask = BIT(2)|BIT(3)|BIT(4);
1416 #ifdef MS_DEBUG
1417 {
1418 MS_U8 reg_frz=0, FSM=0;
1419 MS_U16 u16Timer=0;
1420 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1421 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1422 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1423 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1424 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1425 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1426 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1427 u16Timer=(u16Timer<<8)+reg_frz;
1428 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1429 u16Timer=(u16Timer<<8)+reg_frz;
1430 ULOGD("DEMOD","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1431 }
1432 #endif
1433 break;
1434
1435 case DMD_DVBC_GETLOCK_ATV_DETECT:
1436 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1437 cBitMask = BIT(1); // check atv
1438 break;
1439
1440 case DMD_DVBC_GETLOCK_TR_LOCK:
1441 #if 0 // 20111108 temporarily solution
1442 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1443 cBitMask = BIT(4);
1444 break;
1445 #endif
1446 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1447 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1448 cBitMask = BIT(4);
1449 break;
1450
1451 default:
1452 return FALSE;
1453 }
1454
1455 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1456 return FALSE;
1457
1458 if ((cData & cBitMask) != 0)
1459 {
1460 return TRUE;
1461 }
1462
1463 return FALSE;
1464 }
1465
1466 return FALSE;
1467 }
1468
1469 /****************************************************************************
1470 Subject: To get the Post viterbi BER
1471 Function: INTERN_DVBC_GetPostViterbiBer
1472 Parmeter: Quility
1473 Return: E_RESULT_SUCCESS
1474 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1475 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1476 We will not read the Period, and have the "/256/8"
1477 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg)1478 MS_BOOL INTERN_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg)
1479 {
1480 MS_BOOL status = true;
1481 MS_U8 reg = 0, reg_frz = 0;
1482 //MS_U16 BitErrPeriod;
1483 //MS_U32 BitErr;
1484 //MS_U16 PktErr;
1485
1486 /////////// Post-Viterbi BER /////////////
1487
1488 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1489 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1490 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1491
1492 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1493 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1495 *BitErrPeriod_reg = reg;
1496
1497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1498 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8)|reg;
1499
1500 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1501 // 0x6b [15:8] reg_bit_err_num_15_8
1502 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1503 // 0x6d [15:8] reg_bit_err_num_31_24
1504 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1505 *BitErr_reg = reg;
1506
1507 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1508 *BitErr_reg = (*BitErr_reg << 8)|reg;
1509
1510 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1511 *BitErr_reg = (*BitErr_reg << 8)|reg;
1512
1513 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1514 *BitErr_reg = (*BitErr_reg << 8)|reg;
1515
1516
1517 //INTERN_DVBC_GetPacketErr(&PktErr);
1518
1519 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1520 reg_frz=reg_frz&(~0x03);
1521 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1522 /*
1523 if (BitErrPeriod == 0 ) //protect 0
1524 BitErrPeriod = 1;
1525
1526 if (BitErr <=0 )
1527 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1528 else
1529 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1530
1531 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1532 */
1533 return status;
1534 }
1535
1536 /****************************************************************************
1537 Subject: To get the Packet error
1538 Function: INTERN_DVBC_GetPacketErr
1539 Parmeter: pktErr
1540 Return: E_RESULT_SUCCESS
1541 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1542 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1543 We will not read the Period, and have the "/256/8"
1544 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1545 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1546 {
1547 MS_BOOL status = true;
1548 MS_U8 reg = 0, reg_frz = 0;
1549 MS_U16 PktErr;
1550
1551 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1552 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1553 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1554
1555 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1556 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1557 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1558 PktErr = reg;
1559
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1561 PktErr = (PktErr << 8)|reg;
1562
1563 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1564 reg_frz=reg_frz&(~0x03);
1565 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1566
1567 ULOGD("DEMOD","INTERN_DVBC PktErr = %d \n ", (int)PktErr);
1568
1569 *pktErr = PktErr;
1570
1571 return status;
1572 }
1573
1574
1575 /****************************************************************************
1576 Subject: Read the signal to noise ratio (SNR)
1577 Function: INTERN_DVBC_GetSNR
1578 Parmeter: None
1579 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1580 Remark:
1581 *****************************************************************************/
INTERN_DVBC_GetSNR(MS_U16 * snr_reg)1582 MS_BOOL INTERN_DVBC_GetSNR(MS_U16 *snr_reg)
1583 {
1584 MS_BOOL status = true;
1585 MS_U8 u8Data = 0, reg_frz = 0;
1586 // MS_U8 freeze = 0;
1587 //MS_U16 noisepower = 0;
1588
1589 //if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1590 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200*10, -200*10, 0) )
1591 {
1592 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1593 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1594 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1595
1596 // read vk
1597 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1598 //noisepower = u8Data;
1599 *snr_reg = u8Data;
1600 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1601 //noisepower = (noisepower<<8)|u8Data;
1602 *snr_reg = ((*snr_reg)<<8)|u8Data;
1603
1604 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1605 reg_frz=reg_frz&(~0x01);
1606 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1607
1608 //if(noisepower == 0x0000)
1609 // noisepower = 0x0001;
1610 if(*snr_reg == 0x0000)
1611 *snr_reg = 0x0001;
1612 /*
1613 #ifdef MSOS_TYPE_LINUX
1614 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1615 #else
1616 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1617 #endif
1618 */
1619 }
1620 else
1621 {
1622 *snr_reg = 0;
1623 }
1624 return status;
1625
1626
1627 }
1628
INTERN_DVBC_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1629 MS_BOOL INTERN_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1630 {
1631 MS_BOOL status = true;
1632
1633 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1634
1635 return status;
1636 }
1637
1638 //waiting mark
1639 #if(0)
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue)1640 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
1641 {
1642 MS_BOOL status = true;
1643 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1644 DMD_DVBC_MODULATION_TYPE Qam_mode;
1645
1646 ULOGD("DEMOD","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi));
1647
1648 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1649 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1650 /* Actually, it's more reasonable, that signal level depended on cable input power level
1651 * thougth the signal isn't dvb-t signal.
1652 */
1653 // use pointer of IFAGC table to identify
1654 // case 1: RFAGC from SAR, IFAGC controlled by demod
1655 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1656 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1657 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1658 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1659 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1660 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
1661 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
1662
1663 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1664
1665 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
1666 {
1667 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
1668 }
1669 else
1670 {
1671 ch_power_db_rel = -100.0f;
1672 }
1673
1674 if(ch_power_db_rel <= -85.0f)
1675 {*strength = 0;}
1676 else if (ch_power_db_rel <= -80.0f)
1677 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
1678 else if (ch_power_db_rel <= -75.0f)
1679 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
1680 else if (ch_power_db_rel <= -70.0f)
1681 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
1682 else if (ch_power_db_rel <= -65.0f)
1683 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
1684 else if (ch_power_db_rel <= -55.0f)
1685 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
1686 else if (ch_power_db_rel <= -45.0f)
1687 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
1688 else
1689 {*strength = 100;}
1690
1691 ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength);
1692 ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength);
1693
1694 return status;
1695 }
1696 #endif
1697
1698 /****************************************************************************
1699 Subject: To get the DVT Signal quility
1700 Function: INTERN_DVBC_GetSignalQuality
1701 Parmeter: Quility
1702 Return: E_RESULT_SUCCESS
1703 E_RESULT_FAILURE
1704 Remark: Here we have 4 level range
1705 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1706 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1707 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1708 <4>.4th Range => Quality <10
1709 *****************************************************************************/
1710 //waiting mark
1711 /*
1712 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
1713 {
1714
1715 float fber;
1716 float log_ber;
1717 MS_BOOL status = true;
1718 DMD_DVBC_MODULATION_TYPE Qam_mode;
1719 float f_snr;
1720
1721 fRFPowerDbm = fRFPowerDbm;
1722 status &= INTERN_DVBC_GetSNR(&f_snr);
1723 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
1724 {
1725 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
1726 {
1727 DBG_INTERN_DVBC(ULOGD("DEMOD","\nGetPostViterbiBer Fail!"));
1728 return FALSE;
1729 }
1730
1731 // log_ber = log10(fber)
1732 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
1733
1734 DBG_INTERN_DVBC(ULOGD("DEMOD","\nLog(BER) = %f",log_ber));
1735 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1736 if (Qam_mode == DMD_DVBC_QAM16)
1737 {
1738 if(log_ber <= (-5.5f))
1739 *quality = 100;
1740 else if(log_ber <= (-5.1f))
1741 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
1742 else if(log_ber <= (-4.9f))
1743 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1744 else if(log_ber <= (-4.5f))
1745 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
1746 else if(log_ber <= (-3.7f))
1747 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
1748 else if(log_ber <= (-3.2f))
1749 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1750 else if(log_ber <= (-2.9f))
1751 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1752 else if(log_ber <= (-2.5f))
1753 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
1754 else if(log_ber <= (-2.2f))
1755 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
1756 else if(log_ber <= (-2.0f))
1757 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1758 else
1759 *quality = 0;
1760 }
1761 else if (Qam_mode == DMD_DVBC_QAM32)
1762 {
1763 if(log_ber <= (-5.0f))
1764 *quality = 100;
1765 else if(log_ber <= (-4.7f))
1766 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
1767 else if(log_ber <= (-4.5f))
1768 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
1769 else if(log_ber <= (-3.8f))
1770 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
1771 else if(log_ber <= (-3.5f))
1772 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
1773 else if(log_ber <= (-3.0f))
1774 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
1775 else if(log_ber <= (-2.7f))
1776 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
1777 else if(log_ber <= (-2.4f))
1778 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1779 else if(log_ber <= (-2.2f))
1780 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1781 else if(log_ber <= (-2.0f))
1782 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1783 else
1784 *quality = 0;
1785 }
1786 else if (Qam_mode == DMD_DVBC_QAM64)
1787 {
1788 if(log_ber <= (-5.4f))
1789 *quality = 100;
1790 else if(log_ber <= (-5.1f))
1791 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
1792 else if(log_ber <= (-4.9f))
1793 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1794 else if(log_ber <= (-4.3f))
1795 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
1796 else if(log_ber <= (-3.7f))
1797 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
1798 else if(log_ber <= (-3.2f))
1799 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1800 else if(log_ber <= (-2.9f))
1801 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1802 else if(log_ber <= (-2.4f))
1803 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
1804 else if(log_ber <= (-2.2f))
1805 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1806 else if(log_ber <= (-2.05f))
1807 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
1808 else
1809 *quality = 0;
1810 }
1811 else if (Qam_mode == DMD_DVBC_QAM128)
1812 {
1813 if(log_ber <= (-5.1f))
1814 *quality = 100;
1815 else if(log_ber <= (-4.9f))
1816 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1817 else if(log_ber <= (-4.7f))
1818 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
1819 else if(log_ber <= (-4.1f))
1820 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
1821 else if(log_ber <= (-3.5f))
1822 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
1823 else if(log_ber <= (-3.1f))
1824 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1825 else if(log_ber <= (-2.7f))
1826 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1827 else if(log_ber <= (-2.5f))
1828 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
1829 else if(log_ber <= (-2.06f))
1830 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
1831 //else if(log_ber <= (-2.05))
1832 else
1833 {
1834 if (f_snr >= 27.2f)
1835 *quality = 20;
1836 else if (f_snr >= 25.1f)
1837 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
1838 else
1839 *quality = 0;
1840 }
1841 }
1842 else //256QAM
1843 {
1844 if(log_ber <= (-4.8f))
1845 *quality = 100;
1846 else if(log_ber <= (-4.6f))
1847 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
1848 else if(log_ber <= (-4.4f))
1849 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
1850 else if(log_ber <= (-4.0f))
1851 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
1852 else if(log_ber <= (-3.5f))
1853 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
1854 else if(log_ber <= (-3.1f))
1855 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1856 else if(log_ber <= (-2.7f))
1857 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1858 else if(log_ber <= (-2.4f))
1859 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1860 else if(log_ber <= (-2.06f))
1861 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
1862 //else if(log_ber <= (-2.05))
1863 else
1864 {
1865 if (f_snr >= 29.6f)
1866 *quality = 20;
1867 else if (f_snr >= 27.3f)
1868 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
1869 else
1870 *quality = 0;
1871 }
1872 }
1873 }
1874 else
1875 {
1876 *quality = 0;
1877 }
1878
1879 //DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
1880 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","BER = %8.3e\n", fber));
1881 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","Signal Quility = %d\n", *quality));
1882 return TRUE;
1883 }
1884 #endif
1885 */
1886
1887 /****************************************************************************
1888 Subject: To get the Cell ID
1889 Function: INTERN_DVBC_Get_CELL_ID
1890 Parmeter: point to return parameter cell_id
1891
1892 Return: TRUE
1893 FALSE
1894 Remark:
1895 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)1896 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
1897 {
1898 MS_BOOL status = true;
1899 MS_U8 value1 = 0;
1900 MS_U8 value2 = 0;
1901
1902 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
1903 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
1904
1905 *cell_id = ((MS_U16)value1<<8)|value2;
1906 return status;
1907 }
1908
1909 /****************************************************************************
1910 Subject: To get the DVBC Carrier Freq Offset
1911 Function: INTERN_DVBC_Get_FreqOffset
1912 Parmeter: Frequency offset (in KHz), bandwidth
1913 Return: E_RESULT_SUCCESS
1914 E_RESULT_FAILURE
1915 Remark:
1916 *****************************************************************************/
1917 #if(1)
INTERN_DVBC_Get_FreqOffset(MS_U32 * config_Fc_reg,MS_U32 * Fc_over_Fs_reg,MS_U16 * Cfo_offset_reg,MS_U8 u8BW)1918 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW)
1919 {
1920 MS_U8 reg_frz = 0, reg = 0;
1921 MS_BOOL status = TRUE;
1922
1923 // no use.
1924 u8BW = u8BW;
1925
1926 ULOGD("DEMOD","INTERN_DVBC_Get_FreqOffset\n");
1927
1928 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1929 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1930 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1931
1932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
1933 *config_Fc_reg = reg;
1934 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
1935 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
1936 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
1937 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
1938 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
1939 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
1940
1941 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1942 reg_frz=reg_frz&(~0x01);
1943 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1944
1945 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
1946 *Fc_over_Fs_reg = reg;
1947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
1948 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
1949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
1950 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
1951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
1952 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
1953
1954 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
1955 *Cfo_offset_reg = reg;
1956 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
1957 *Cfo_offset_reg = (*Cfo_offset_reg<<8)|reg;
1958
1959 //waiting mark
1960 /*
1961 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
1962
1963 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
1964
1965 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
1966
1967 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
1968
1969 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
1970 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
1971 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
1972
1973 *pFreqOff = FreqCfo_offset;
1974 */
1975 return status;
1976 }
1977 #endif
1978
1979
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)1980 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
1981 {
1982
1983 bPowerOn = bPowerOn;
1984 }
1985
INTERN_DVBC_Power_Save(void)1986 MS_BOOL INTERN_DVBC_Power_Save(void)
1987 {
1988
1989 return TRUE;
1990 }
1991
1992 /****************************************************************************
1993 Subject: To get the current modulation type at the DVB-C Demod
1994 Function: INTERN_DVBC_GetCurrentModulationType
1995 Parmeter: pointer for return QAM type
1996
1997 Return: TRUE
1998 FALSE
1999 Remark:
2000 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)2001 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
2002 {
2003 MS_U8 u8Data=0;
2004
2005 ULOGD("DEMOD","INTERN_DVBC_GetCurrentModulationType\n");
2006
2007
2008 MDrv_SYS_DMD_VD_MBX_ReadReg(0x9cc4, &u8Data);
2009
2010
2011
2012 //ULOGD("DEMOD","@@@@@@ 0x9cc4 pQAMMode = %d \n",u8Data&0x07);
2013
2014 switch(u8Data&0x07)
2015 {
2016 case 0:
2017 *pQAMMode = DMD_DVBC_QAM16;
2018 ULOGD("DEMOD","[dvbc]QAM=16\n");
2019 return TRUE;
2020 break;
2021 case 1:
2022 *pQAMMode = DMD_DVBC_QAM32;
2023 ULOGD("DEMOD","[dvbc]QAM=32\n");
2024 return TRUE;
2025 break;
2026 case 2:
2027 *pQAMMode = DMD_DVBC_QAM64;
2028 ULOGD("DEMOD","[dvbc]QAM=64\n");
2029 return TRUE;
2030 break;
2031 case 3:
2032 *pQAMMode = DMD_DVBC_QAM128;
2033 ULOGD("DEMOD","[dvbc]QAM=128\n");
2034 return TRUE;
2035 break;
2036 case 4:
2037 *pQAMMode = DMD_DVBC_QAM256;
2038 ULOGD("DEMOD","[dvbc]QAM=256\n");
2039 return TRUE;
2040 break;
2041 default:
2042 *pQAMMode = DMD_DVBC_QAMAUTO;
2043 ULOGD("DEMOD","[dvbc]QAM=invalid\n");
2044 return FALSE;
2045 }
2046 }
2047
2048 /****************************************************************************
2049 Subject: To get the current symbol rate at the DVB-C Demod
2050 Function: INTERN_DVBC_GetCurrentSymbolRate
2051 Parmeter: pointer pData for return Symbolrate
2052
2053 Return: TRUE
2054 FALSE
2055 Remark:
2056 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2057 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2058 {
2059 MS_U8 tmp = 0;
2060 MS_U16 u16SymbolRateTmp = 0;
2061
2062 ULOGD("DEMOD","INTERN_DVBC_GetCurrentSymbolRate\n");
2063
2064
2065 // intp
2066 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d2, &tmp);
2067 u16SymbolRateTmp = tmp;
2068 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d1, &tmp);
2069 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2070
2071 if (abs(u16SymbolRateTmp-6900)<2)
2072 {
2073 u16SymbolRateTmp=6900;
2074 }
2075
2076 if (abs(u16SymbolRateTmp-6875)<2)
2077 {
2078 u16SymbolRateTmp=6875;
2079 }
2080
2081 *u16SymbolRate = u16SymbolRateTmp;
2082
2083 ULOGD("DEMOD","[dvbc]SR=%d\n",*u16SymbolRate);
2084
2085
2086 return TRUE;
2087 }
2088
2089
2090 /****************************************************************************
2091 Subject: To get the current symbol rate offset at the DVB-C Demod
2092 Function: INTERN_DVBC_GetCurrentSymbolRate
2093 Parmeter: pointer pData for return Symbolrate offset
2094
2095 Return: TRUE
2096 FALSE
2097 Remark:
2098 *****************************************************************************/
2099 //waiting mark
2100 /*
2101 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2102 {
2103 MS_U8 u8Data = 0, reg_frz = 0;
2104 MS_U32 u32Data = 0;
2105 // MS_S32 s32Data = 0;
2106 MS_BOOL status = TRUE;
2107 MS_U16 u16SymbolRate = 0;
2108 float f_symb_offset = 0.0f;
2109
2110
2111
2112 // bank 26 0x03 [7] reg_bit_err_num_freeze
2113 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
2114 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
2115
2116 // sel, SFO debug output.
2117 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
2118 u32Data = u8Data;
2119 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
2120 u32Data = (u32Data<<8)|u8Data;
2121 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
2122 u32Data = (u32Data<<8)|u8Data;
2123 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
2124 u32Data = (u32Data<<8)|u8Data;
2125
2126 // bank 26 0x03 [7] reg_bit_err_num_freeze
2127 reg_frz=reg_frz&(~0x80);
2128 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
2129 // s32Data = (MS_S32)(u32Data<<8);
2130
2131 ULOGD("DEMOD","[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2132
2133 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2134
2135 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2136 // f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2137 f_symb_offset = (float)((MS_S32)u32Data) * (0.000007276f) * (float)u16SymbolRate/(float)DVBC_FS;
2138
2139 *pData = (MS_U16)(f_symb_offset + 0.5f);
2140
2141 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
2142
2143 return status;
2144 }
2145 #endif
2146 */
2147
INTERN_DVBC_Version(MS_U16 * ver)2148 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2149 {
2150
2151 MS_U8 status = true;
2152 MS_U8 tmp = 0;
2153 MS_U16 u16_INTERN_DVBC_Version;
2154
2155 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2156 u16_INTERN_DVBC_Version = tmp;
2157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2158 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2159 *ver = u16_INTERN_DVBC_Version;
2160
2161 return status;
2162 }
2163
2164
INTERN_DVBC_Show_Demod_Version(void)2165 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2166 {
2167
2168 MS_BOOL status = true;
2169 MS_U16 u16_INTERN_DVBC_Version;
2170
2171 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2172
2173 ULOGD("DEMOD","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2174
2175 return status;
2176 }
2177
2178
2179
2180 #if (INTERN_DVBC_INTERNAL_DEBUG)
2181
INTERN_DVBC_Show_AGC_Info(void)2182 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2183 {
2184 MS_U8 tmp = 0;
2185 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2186 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2187 MS_U16 if_agc_err = 0;
2188 MS_BOOL status = TRUE;
2189
2190 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2191 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2192 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2193 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2194 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2195 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2196
2197
2198 // select IF gain to read
2199 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2200 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2201
2202 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2203 if_agc_gain = tmp;
2204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2205 if_agc_gain = (if_agc_gain<<8)|tmp;
2206
2207
2208 // select d1 gain to read.
2209 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2210 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2211
2212 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2213 d1_gain = tmp;
2214 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2215 d1_gain = (d1_gain<<8)|tmp;
2216
2217 // select d2 gain to read.
2218 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2219 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2220
2221 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2222 d2_gain = tmp;
2223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2224 d2_gain = (d2_gain<<8)|tmp;
2225
2226 // select IF gain err to read
2227 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2228 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2229
2230 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2231 if_agc_err = tmp;
2232 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2233 if_agc_err = (if_agc_err<<8)|tmp;
2234
2235 ULOGD("DEMOD","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2236 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2237
2238 ULOGD("DEMOD","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2239
2240 return status;
2241 }
2242
INTERN_DVBC_info(void)2243 void INTERN_DVBC_info(void)
2244 {
2245 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2246 MS_U8 qam,tmp = 0;
2247 MS_U8 fft_u8 = 0;
2248 MS_U16 fft_u16bw = 0;
2249 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2250 //float f_snr = 0,f_freq = 0;
2251 //DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2252 MS_U16 f_start = 0,f_end = 0;
2253 MS_U8 s0_count = 0;
2254 MS_U8 sc4 = 0,sc3 = 0;
2255 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2256 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2257 MS_U16 count = 0;
2258 MS_U16 fb_i_1,fb_q_1;
2259 MS_U8 e0,e1,e2,e3;
2260 MS_S16 reg_freq;
2261 //float freq,mag;
2262
2263
2264
2265 INTERN_DVBC_Version(&version);
2266
2267 // fb_fs
2268 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2269 fb_fs = tmp;
2270 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2271 fb_fs = (fb_fs<<8)|tmp;
2272 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2273 fb_fs = (fb_fs<<8)|tmp;
2274 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2275 fb_fs = (fb_fs<<8)|tmp;
2276 // fc_fs
2277 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2278 fc_fs = tmp;
2279 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2280 fc_fs = (fc_fs<<8)|tmp;
2281 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2282 fc_fs = (fc_fs<<8)|tmp;
2283 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2284 fc_fs = (fc_fs<<8)|tmp;
2285 // crv
2286 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2287 crv = tmp;
2288 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2289 crv = (crv<<8)|tmp;
2290 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2291 crv = (crv<<8)|tmp;
2292 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2293 crv = (crv<<8)|tmp;
2294 // tr_error
2295 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2296 tr_error = tmp;
2297 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2298 tr_error = (tr_error<<8)|tmp;
2299 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2300 tr_error = (tr_error<<8)|tmp;
2301
2302 // intp
2303 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2304 intp = tmp;
2305 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2306 intp = (intp<<8)|tmp;
2307 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2308 intp = (intp<<8)|tmp;
2309 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2310 intp = (intp<<8)|tmp;
2311
2312 //waiting mark
2313 // fft info
2314 // intp
2315 /*
2316 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2317 fft_u16bw = tmp;
2318 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2319 fft_u16bw = (fft_u16bw<<8)|tmp;
2320 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2321 fft_u8 = tmp;
2322 */
2323
2324 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2325 qam = tmp;
2326
2327 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2328 f_start = tmp;
2329 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2330 f_start = (f_start<<8)|tmp;
2331 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2332 f_end = tmp;
2333 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2334 f_end = (f_end<<8)|tmp;
2335 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2336 s0_count = tmp;
2337
2338 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2339 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2340
2341 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2342 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2343 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2344 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2345 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2346 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2347 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2348
2349
2350 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2351
2352 count = 0x400;
2353 while(count--);
2354
2355 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2356 aci_e0 = tmp&0x0f;
2357 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2358 aci_e0 = aci_e0<<8|tmp;
2359
2360 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2361
2362 count = 0x400;
2363 while(count--);
2364
2365
2366 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2367 aci_e1 = tmp&0x0f;
2368 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2369 aci_e1 = aci_e1<<8|tmp;
2370
2371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2372
2373 count = 0x400;
2374 while(count--);
2375
2376 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2377 aci_e2 = tmp&0x0f;
2378 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2379 aci_e2 = aci_e2<<8|tmp;
2380
2381 // read aci coef
2382 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2383
2384 count = 0x400;
2385 while(count--);
2386
2387 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2388 aci_e3 = tmp&0x0f;
2389 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2390 aci_e3 = aci_e3<<8|tmp;
2391
2392 //waiting mark
2393 /*
2394 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2395 fb_i_1 = tmp;
2396 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2397 fb_i_1 = fb_i_1<<8|tmp;
2398
2399 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2400 fb_q_1 = tmp;
2401 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2402 fb_q_1 = fb_q_1<<8|tmp;
2403 */
2404
2405 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2406 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2407 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2408 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2409
2410 //reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2411 //freq = (float)reg_freq*45473.0/65536.0;
2412 //mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2413
2414
2415 INTERN_DVBC_GetPacketErr(&packetErr);
2416 //INTERN_DVBC_GetSNR(&f_snr);
2417 INTERN_DVBC_Show_AGC_Info();
2418 //INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2419 //INTERN_DVBC_Get_FreqOffset(&f_freq,8); //GetStatus
2420 //INTERN_DVBC_GetCurrentSymbolRate(&symb_rate); //GetStatus
2421 //INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2422 //INTERN_DVBC_GetCurrentModulationType(&QAMMode); //GetStatus
2423 /*
2424 ULOGD("DEMOD","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2425 //ULOGD("DEMOD","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2426 ULOGD("DEMOD","[MStar_2][2]0x%lx\n",intp);
2427 ULOGD("DEMOD","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2428 ULOGD("DEMOD","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2429 ULOGD("DEMOD","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2430 //ULOGD("DEMOD","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2431 ULOGD("DEMOD","[Mstar_6][3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2432 */
2433 return;
2434
2435 }
2436
2437
2438 #endif
2439
2440 /***********************************************************************************
2441 Subject: read register
2442 Function: MDrv_1210_IIC_Bypass_Mode
2443 Parmeter:
2444 Return:
2445 Remark:
2446 ************************************************************************************/
2447 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2448 //{
2449 // UNUSED(enable);
2450 // if (enable)
2451 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2452 // else
2453 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2454 //}
2455