1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_DTMB.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_DTMB_CHIP_NIKON 0x00
112 #define DMD_DTMB_CHIP_NASA 0x01
113 #define DMD_DTMB_CHIP_MADISON 0x02
114 #define DMD_DTMB_CHIP_MONACO 0x03
115 #define DMD_DTMB_CHIP_MUJI 0x04
116 #define DMD_DTMB_CHIP_MONET 0x05
117 #define DMD_DTMB_CHIP_MANHATTAN 0x06
118 #define DMD_DTMB_CHIP_MESSI 0x07
119 #define DMD_DTMB_CHIP_MASERATI 0x08
120 #define DMD_DTMB_CHIP_MACAN 0x09
121 #define DMD_DTMB_CHIP_MAXIM 0x0A
122
123 #if defined(CHIP_NIKON)
124 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
125 #elif defined(CHIP_NASA)
126 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
127 #elif defined(CHIP_MADISON)
128 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
129 #elif defined(CHIP_MONACO)
130 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
131 #elif defined(CHIP_MUJI)
132 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
133 #elif defined(CHIP_MONET)
134 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
135 #elif defined(CHIP_MANHATTAN)
136 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
137 #elif defined(CHIP_MESSI)
138 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
139 #elif defined(CHIP_MASERATI)
140 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MASERATI
141 #elif defined(CHIP_MACAN)
142 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MACAN
143 #elif defined(CHIP_MAXIM)
144 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MAXIM
145 #else
146 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
147 #endif
148
149 //-------------------------------------------------------------------------------------------------
150 // Local Defines
151 //-------------------------------------------------------------------------------------------------
152
153 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr) ) )
154 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr), val) )
155
156 #define HAL_INTERN_DTMB_DBINFO(y) //y
157
158 #define MBRegBase 0x112600
159 #define DMDMcuBase 0x103480
160
161 #define DTMB_REG_BASE 0x2600
162
163 #define DTMB_ACI_COEF_SIZE 112
164
165 #define DMD_DTMB_CHIP_ID_NASA 0x6E
166 #define DMD_DTMB_CHIP_ID_WALTZ 0x9C
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Variables
170 //-------------------------------------------------------------------------------------------------
171
172 const MS_U8 INTERN_DTMB_table[] = {
173 #include "DMD_INTERN_DTMB.dat"
174 };
175
176 const MS_U8 INTERN_DTMB_6M_table[] = {
177 #include "DMD_INTERN_DTMB_6M.dat"
178 };
179
180 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
181 const MS_U8 INTERN_DTMB_table_Waltz[] = {
182 #include "DMD_INTERN_DTMB_Waltz.dat"
183 };
184
185 const MS_U8 INTERN_DTMB_6M_table_Waltz[] = {
186 #include "DMD_INTERN_DTMB_6M_Waltz.dat"
187 };
188 #endif
189
190 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
191 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
192 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
193 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
194 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
195
196 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
197 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
198 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
199 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
200 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
201
202 //-------------------------------------------------------------------------------------------------
203 // Global Variables
204 //-------------------------------------------------------------------------------------------------
205
206 extern MS_U8 u8DMD_DTMB_DMD_ID;
207
208 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
209
210 //-------------------------------------------------------------------------------------------------
211 // Local Functions
212 //-------------------------------------------------------------------------------------------------
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)213 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
214 {
215 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
216 }
217
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)218 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
219 {
220 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
221 }
222
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)223 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
224 {
225 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
226 }
227
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)228 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
229 {
230 MS_U8 u8CheckCount;
231 MS_U8 u8CheckFlag;
232
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
234 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
235 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
236 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
237
238 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
239 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
240
241 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
242 {
243 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
244 if ((u8CheckFlag&0x01)==0)
245 break;
246 MsOS_DelayTask(1);
247 }
248
249 if (u8CheckFlag&0x01)
250 {
251 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
252 return FALSE;
253 }
254
255 return TRUE;
256 }
257
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)258 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
259 {
260 MS_U8 u8CheckCount;
261 MS_U8 u8CheckFlag;
262
263 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
264 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
265 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
266
267 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
268 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
269
270 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
271 {
272 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
273 if ((u8CheckFlag&0x02)==0)
274 {
275 *u8Data = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
276 break;
277 }
278 MsOS_DelayTask(1);
279 }
280
281 if (u8CheckFlag&0x02)
282 {
283 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
284 return FALSE;
285 }
286
287 return TRUE;
288 }
289
290 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)291 static void _HAL_INTERN_DTMB_InitClk(void)
292 {
293 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_NIKON--------------\n"));
294
295 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
296
297 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
298 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
299 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
300 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
301 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
302 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
303 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
304 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
305
306 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
307 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
308 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
309 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
310 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
311 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
312 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
313 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
314 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
315 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
316 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
317 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
318 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
319 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
320 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
321 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
322 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
323 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
324 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
325 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
326 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
327 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
328 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
329 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
330 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
331 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
332 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
333 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
334 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
335
336 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
337 }
338 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)339 static void _HAL_INTERN_DTMB_InitClk(void)
340 {
341 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
342
343 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
344 {
345 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_WALTZ--------------\n"));
346
347 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
348
349 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
350 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
351
352 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
353 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
354
355 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
356 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
357 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
358 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
359
360 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
361 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
362
363 _HAL_DMD_RIU_WriteByte(0x111f49, 0xcc);
364 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
365
366 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
367 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
368 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
369 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
370 _HAL_DMD_RIU_WriteByte(0x111f75, 0x00);
371 _HAL_DMD_RIU_WriteByte(0x111f74, 0x00);
372 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
373 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
374
375 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
376 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
377 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
378 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
379 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
380 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
381 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
382 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
383
384 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
385 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
386 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x00);
387 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x00);
388 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
389 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
390
391 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
392 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
393
394 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00);
395 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
396
397 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
398 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
399
400 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
401 }
402 else
403 {
404 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_NASA--------------\n"));
405
406 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
407
408 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
409 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
410 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
411 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
412 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
413 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
414 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
415 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
416
417 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
418 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
419 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
420 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
421 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
422 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
423 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
424 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
425 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
426 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
427 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
428 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
429 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
430 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
431 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
432 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
433 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
434 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
435 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
436 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
437 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
438 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
439 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
440 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
441 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
442 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
443 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
444 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
445 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
446
447 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
448 }
449 }
450 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)451 static void _HAL_INTERN_DTMB_InitClk(void)
452 {
453 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MADISON--------------\n"));
454
455 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
456
457 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
458 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
459 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
460 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
461 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
462 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
463 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
464 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
465
466 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
467 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
468
469 //carl
470 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
472 _HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
473 _HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
474
475 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
482 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
483
484 //carl
485 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
486 _HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
487
488 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
489 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
490 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
492 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
493 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
494 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
495 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
496 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
497 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
498 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
499 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
500 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
501 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
502 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
503 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
504 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
505 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
506 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
507
508 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
509 }
510 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)511 static void _HAL_INTERN_DTMB_InitClk(void)
512 {
513 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MONACO--------------\n"));
514
515 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
516
517 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
519
520 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
521 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
522
523 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
527
528 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
530
531 //carl
532 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
533 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
534
535 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
536 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
537 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
539 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
540 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
541 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
542 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
543 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
544 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
545
546 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
547 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
548 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
549 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
550
551 //carl
552 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
553 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
554 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
555 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
556
557 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
558 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
559
560 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
561
562 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
563 }
564 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)565 static void _HAL_INTERN_DTMB_InitClk(void)
566 {
567 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MUJI--------------\n"));
568
569 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
570
571 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
573
574 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
575 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
576
577 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
581 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
582 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
583
584 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
585 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
586
587 //carl
588 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
589 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
590
591 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
592 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
593 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
594 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
595 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
596 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
597 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
598 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
599 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
600 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
601
602 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
603 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
604 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
605 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
606
607 //carl
608 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
609 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
610 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
611 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
612
613 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
614 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
615
616 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
617
618 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
619 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
620
621 _HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
622 _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
623
624 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
625 }
626 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)627 static void _HAL_INTERN_DTMB_InitClk(void)
628 {
629 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MONET--------------\n"));
630
631 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
632
633 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
634 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
635
636 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
637 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
638
639 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
640 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
641 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
642 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
643 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
644 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
645
646 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
647 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
648
649 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
650 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
651
652 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
653 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
654 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
655 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
656
657 _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
658 _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
659
660 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
661 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
662 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
663 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
666
667 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
671
672 //carl
673 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
674 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
675
676 _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
677 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
678
679
680 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
682
683 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
684 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
685
686 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
687 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
688
689 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
690 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
691
692 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
693 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
694
695 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
696 }
697 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)698 static void _HAL_INTERN_DTMB_InitClk(void)
699 {
700 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n"));
701
702 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
703
704 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
705 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
706
707 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
708 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
709
710 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
711 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
712 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
713 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
715 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
716
717 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
719
720 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
721 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
722
723 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
724 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
725 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
727
728 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
729 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
730
731 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
732 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
733 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
735 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
736 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
737
738 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
739 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
740 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
741 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
742
743 //carl
744 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
745 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
746
747 // _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
748 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
749
750
751 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
752 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
753
754 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
755 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
756
757 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
758 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
759
760 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
761 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
762
763 _HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
764 _HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
765
766 _HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
767 _HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
768
769 _HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
770 _HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
771
772 _HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
773 _HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
774
775 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
776 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
777
778 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
779 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
780
781
782 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
783 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
784
785 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
786 }
787 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI)
_HAL_INTERN_DTMB_InitClk(void)788 static void _HAL_INTERN_DTMB_InitClk(void)
789 {
790 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MESSI--------------\n"));
791
792 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
793
794 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
795 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
796
797 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
798 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
799
800 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
803 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
804 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
805 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
806
807 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
809
810 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
811 //_HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
812 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
813
814 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
815 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
816 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
818
819 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
820 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
821
822 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
823 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
824 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
828
829 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
830 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
831 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
832 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
833
834 //carl
835 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
836 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
837
838 // _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
839 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
840
841
842 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
843 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
844
845 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
846 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
847
848 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
849 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
850
851 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
852 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
853
854 _HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
855 _HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
856
857 _HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
858 _HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
859
860 _HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
861 _HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
862
863 _HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
864 _HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
865
866 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
867 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
868
869 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
870 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
871
872
873 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
874 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
875
876 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
877 }
878
879 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM)
_HAL_INTERN_DTMB_InitClk(void)880 static void _HAL_INTERN_DTMB_InitClk(void)
881 {
882 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MAXIM--------------\n"));
883
884 _HAL_DMD_RIU_WriteByte(0x111707,0xff);// SRAM End Address
885 _HAL_DMD_RIU_WriteByte(0x111706,0xff);
886
887 _HAL_DMD_RIU_WriteByte(0x111718,_HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));// DRAM Disable
888
889 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
890
891
892 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01);//luffy for ADC Sync Flow
893 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01);//luffy for ADC Sync Flow
894
895 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
896 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
897
898 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
899 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
900
901 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
902 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
903
904 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00);//luffy for ADC Sync Flow
905 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00);//luffy for ADC Sync Flow
906
907 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
908 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
909
910 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
911 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
912
913 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
914 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
915
916 _HAL_DMD_RIU_WriteByte(0x103321, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
917 _HAL_DMD_RIU_WriteByte(0x103320, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
918
919 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00);//luffy for ADC Sync Flow
920
921 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
923
924 _HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
925 _HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
926
927 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
928 _HAL_DMD_RIU_WriteByte(0x152922, 0x14);
929
930 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
931 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
932
933 _HAL_DMD_RIU_WriteByte(0x152973, 0x00);
934 _HAL_DMD_RIU_WriteByte(0x152972, 0x00);
935
936 _HAL_DMD_RIU_WriteByte(0x152975, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x152974, 0x00);
938
939 _HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
940 _HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
941
942 _HAL_DMD_RIU_WriteByte(0x152961, 0x00);
943 _HAL_DMD_RIU_WriteByte(0x152960, 0x00);
944
945 _HAL_DMD_RIU_WriteByte(0x152963, 0x00);
946 _HAL_DMD_RIU_WriteByte(0x152962, 0x00);
947
948 _HAL_DMD_RIU_WriteByte(0x152965, 0x00);
949 _HAL_DMD_RIU_WriteByte(0x152964, 0x00);
950
951 _HAL_DMD_RIU_WriteByte(0x152969, 0x00);
952 _HAL_DMD_RIU_WriteByte(0x152968, 0x00);
953
954 _HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
955 _HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
956
957 _HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
958
959 _HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
960 _HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
961
962 _HAL_DMD_RIU_WriteByte(0x152971, 0x00);
963 _HAL_DMD_RIU_WriteByte(0x152970, 0x04);
964
965 _HAL_DMD_RIU_WriteByte(0x152979, 0x00);
966 _HAL_DMD_RIU_WriteByte(0x152978, 0x00);
967
968 _HAL_DMD_RIU_WriteByte(0x152951, 0x04);
969 _HAL_DMD_RIU_WriteByte(0x152950, 0x00);
970
971 _HAL_DMD_RIU_WriteByte(0x152981, 0x88);
972 _HAL_DMD_RIU_WriteByte(0x152980, 0x88);
973
974 _HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
975 _HAL_DMD_RIU_WriteByte(0x152982, 0x88);
976
977 _HAL_DMD_RIU_WriteByte(0x152985, 0x88);
978 _HAL_DMD_RIU_WriteByte(0x152984, 0x88);
979
980 _HAL_DMD_RIU_WriteByte(0x152987, 0x08);
981 _HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
982
983 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
984 _HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
985
986 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
987 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
988
989 _HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
990 _HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
991
992 _HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
993 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
994
995 _HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
996 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
997
998 _HAL_DMD_RIU_WriteByte(0x152993, 0x11);
999 _HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1000
1001 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1002 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1003
1004 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1005 _HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1006
1007 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1008 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1009
1010 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1011 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1012
1013 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1014 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1015
1016 _HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1017
1018 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1019 }
1020
1021 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
_HAL_INTERN_DTMB_InitClk(void)1022 static void _HAL_INTERN_DTMB_InitClk(void)
1023 {
1024 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MASERATI_MACAN--------------\n"));
1025
1026 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1027
1028 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1029
1030 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1031 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1032
1033 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
1034 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1035
1036 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1037 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1038
1039 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1040 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1041
1042 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1043 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1044
1045 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1046 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1047
1048 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1049 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1050
1051 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1052
1053 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1055
1056 _HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
1057 _HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
1058
1059 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
1060 _HAL_DMD_RIU_WriteByte(0x152922, 0x14);
1061
1062 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1063 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
1064
1065 _HAL_DMD_RIU_WriteByte(0x152973, 0x00);
1066 _HAL_DMD_RIU_WriteByte(0x152972, 0x00);
1067
1068 _HAL_DMD_RIU_WriteByte(0x152975, 0x00);
1069 _HAL_DMD_RIU_WriteByte(0x152974, 0x00);
1070
1071 _HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
1072 _HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
1073
1074 _HAL_DMD_RIU_WriteByte(0x152961, 0x00);
1075 _HAL_DMD_RIU_WriteByte(0x152960, 0x00);
1076
1077 _HAL_DMD_RIU_WriteByte(0x152963, 0x00);
1078 _HAL_DMD_RIU_WriteByte(0x152962, 0x00);
1079
1080 _HAL_DMD_RIU_WriteByte(0x152965, 0x00);
1081 _HAL_DMD_RIU_WriteByte(0x152964, 0x00);
1082
1083 _HAL_DMD_RIU_WriteByte(0x152969, 0x00);
1084 _HAL_DMD_RIU_WriteByte(0x152968, 0x00);
1085
1086 _HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
1087 _HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
1088
1089 _HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
1090
1091 _HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
1092 _HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
1093
1094 _HAL_DMD_RIU_WriteByte(0x152971, 0x00);
1095 _HAL_DMD_RIU_WriteByte(0x152970, 0x04);
1096
1097 _HAL_DMD_RIU_WriteByte(0x152979, 0x00);
1098 _HAL_DMD_RIU_WriteByte(0x152978, 0x00);
1099
1100 _HAL_DMD_RIU_WriteByte(0x152951, 0x04);
1101 _HAL_DMD_RIU_WriteByte(0x152950, 0x00);
1102
1103 _HAL_DMD_RIU_WriteByte(0x152981, 0x88);
1104 _HAL_DMD_RIU_WriteByte(0x152980, 0x88);
1105
1106 _HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
1107 _HAL_DMD_RIU_WriteByte(0x152982, 0x88);
1108
1109 _HAL_DMD_RIU_WriteByte(0x152985, 0x88);
1110 _HAL_DMD_RIU_WriteByte(0x152984, 0x88);
1111
1112 _HAL_DMD_RIU_WriteByte(0x152987, 0x08);
1113 _HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
1114
1115 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
1116 _HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
1117
1118 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
1119 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
1120
1121 _HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
1122 _HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
1123
1124 _HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
1125 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
1126
1127 _HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
1128 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
1129
1130 _HAL_DMD_RIU_WriteByte(0x152993, 0x11);
1131 _HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1132
1133 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1134 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1135
1136 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1137 _HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1138
1139 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1140 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1141
1142 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1143 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1144
1145 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1146 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1147
1148 _HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1149
1150 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1151 }
1152 #else
_HAL_INTERN_DTMB_InitClk(void)1153 static void _HAL_INTERN_DTMB_InitClk(void)
1154 {
1155 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
1156 }
1157 #endif
1158
_HAL_INTERN_DTMB_Ready(void)1159 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
1160 {
1161 MS_U8 udata = 0x00;
1162
1163 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1164
1165 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1166 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1167
1168 MsOS_DelayTask(1);
1169
1170 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1171
1172 if (udata) return FALSE;
1173
1174 return TRUE;
1175 }
1176
_HAL_INTERN_DTMB_Download(void)1177 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
1178 {
1179 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1180
1181 MS_U8 udata = 0x00;
1182 MS_U16 i = 0;
1183 MS_U16 fail_cnt = 0;
1184 MS_U8 u8TmpData;
1185 MS_U16 u16AddressOffset;
1186 const MS_U8 *DTMB_table;
1187 MS_U16 u16Lib_size;
1188
1189 if (pRes->sDMD_DTMB_PriData.bDownloaded)
1190 {
1191 if (_HAL_INTERN_DTMB_Ready())
1192 {
1193 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1194 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1195 MsOS_DelayTask(20);
1196 return TRUE;
1197 }
1198 }
1199
1200 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1201 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1202 {
1203 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1204 {
1205 DTMB_table = &INTERN_DTMB_6M_table_Waltz[0];
1206 u16Lib_size = sizeof(INTERN_DTMB_6M_table_Waltz);
1207 }
1208 else
1209 {
1210 DTMB_table = &INTERN_DTMB_table_Waltz[0];
1211 u16Lib_size = sizeof(INTERN_DTMB_table_Waltz);
1212 }
1213 }
1214 else
1215 {
1216 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1217 {
1218 DTMB_table = &INTERN_DTMB_6M_table[0];
1219 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1220 }
1221 else
1222 {
1223 DTMB_table = &INTERN_DTMB_table[0];
1224 u16Lib_size = sizeof(INTERN_DTMB_table);
1225 }
1226 }
1227 #else
1228 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1229 {
1230 DTMB_table = &INTERN_DTMB_6M_table[0];
1231 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1232 }
1233 else
1234 {
1235 DTMB_table = &INTERN_DTMB_table[0];
1236 u16Lib_size = sizeof(INTERN_DTMB_table);
1237 }
1238 #endif
1239
1240 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1241 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1242
1243 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1244
1245 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1246 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1247 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1248 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1249
1250 //// Load code thru VDMCU_IF ////
1251 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
1252
1253 for (i = 0; i < u16Lib_size; i++)
1254 {
1255 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
1256 }
1257
1258 //// Content verification ////
1259 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
1260
1261 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1262 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1263
1264 for (i = 0; i < u16Lib_size; i++)
1265 {
1266 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1267
1268 if (udata != DTMB_table[i])
1269 {
1270 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
1271 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
1272 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
1273
1274 if (fail_cnt++ > 10)
1275 {
1276 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
1277 return FALSE;
1278 }
1279 }
1280 }
1281
1282 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
1283
1284 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1285 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1286
1287 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
1288 HAL_INTERN_DTMB_DBINFO(printf("u16IF_KHZ=%d\n",pRes->sDMD_DTMB_InitData.u16IF_KHZ));
1289 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1290 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
1291 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1292 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
1293 HAL_INTERN_DTMB_DBINFO(printf("bIQSwap=%d\n",pRes->sDMD_DTMB_InitData.bIQSwap));
1294 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1295 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
1296 HAL_INTERN_DTMB_DBINFO(printf("u16AGC_REFERENCE=%X\n",pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE));
1297 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1298 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
1299 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1300 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
1301 HAL_INTERN_DTMB_DBINFO(printf("u32TdiStartAddr=%X\n",pRes->sDMD_DTMB_InitData.u32TdiStartAddr));
1302 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1303 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
1304 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1305 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
1306 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1307 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
1308 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1309 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
1310 HAL_INTERN_DTMB_DBINFO(printf("eLastType=%d\n",pRes->sDMD_DTMB_PriData.eLastType));
1311 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1312
1313 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1314 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1315
1316 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1317
1318 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1319 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1320
1321 pRes->sDMD_DTMB_PriData.bDownloaded = true;
1322
1323 MsOS_DelayTask(20);
1324
1325 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
1326
1327 return TRUE;
1328 }
1329
_HAL_INTERN_DTMB_FWVERSION(void)1330 static void _HAL_INTERN_DTMB_FWVERSION(void)
1331 {
1332 MS_U8 data1 = 0;
1333 MS_U8 data2 = 0;
1334 MS_U8 data3 = 0;
1335
1336 _MBX_ReadReg(0x20C4, &data1);
1337 _MBX_ReadReg(0x20C5, &data2);
1338 _MBX_ReadReg(0x20C6, &data3);
1339
1340 printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1341 }
1342
_HAL_INTERN_DTMB_Exit(void)1343 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
1344 {
1345 MS_U8 u8CheckCount = 0;
1346
1347 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1348
1349 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1350 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1351
1352 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1353 {
1354 MsOS_DelayTaskUs(10);
1355
1356 if (u8CheckCount++ == 0xFF)
1357 {
1358 printf(">> DTMB Exit Fail!\n");
1359 return FALSE;
1360 }
1361 }
1362
1363 printf(">> DTMB Exit Ok!\n");
1364
1365 return TRUE;
1366 }
1367
_HAL_INTERN_DTMB_SoftReset(void)1368 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
1369 {
1370 MS_U8 u8Data = 0;
1371
1372 //Reset FSM
1373 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1374
1375 while (u8Data!=0x02)
1376 {
1377 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1378 }
1379
1380 return TRUE;
1381 }
1382
_HAL_INTERN_DTMB_SetACICoef(void)1383 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1384 {
1385 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1386
1387 MS_U8 *ACI_table;
1388 MS_U8 i;
1389 MS_U16 u16AddressOffset;
1390
1391 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1392 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1393 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1394 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1395 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1396 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1397 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1398 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1399 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1400
1401 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1402 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1403
1404 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1405
1406 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1407 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1408 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1409 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1410
1411 //SET SR value
1412 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1413 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1414 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1415 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1416
1417 //set ACI coefficient
1418 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1419 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1420 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1421 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1422 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1423 {
1424 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1425 }
1426
1427 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1428 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1429
1430 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1431
1432 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1433 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1434
1435 MsOS_DelayTask(20);
1436
1437 return TRUE;
1438 }
1439
_HAL_INTERN_DTMB_SetDtmbMode(void)1440 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1441 {
1442 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1443 return _MBX_WriteReg(0x20C0, 0x04);
1444 }
1445
_HAL_INTERN_DTMB_SetModeClean(void)1446 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1447 {
1448 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1449 return _MBX_WriteReg(0x20C0, 0x00);
1450 }
1451
_HAL_INTERN_DTMB_Set_QAM_SR(void)1452 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1453 {
1454 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1455 return _MBX_WriteReg(0x20C0, 0x04);
1456 }
1457
_HAL_INTERN_DTMB_AGCLock(void)1458 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1459 {
1460 MS_U8 data = 0;
1461
1462 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1463 _MBX_ReadReg(0x2829, &data);//AGC_LOCK
1464 #else
1465 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1466 #endif
1467 if (data&0x01)
1468 {
1469 return TRUE;
1470 }
1471 else
1472 {
1473 return FALSE;
1474 }
1475 }
1476
_HAL_INTERN_DTMB_PNP_Lock(void)1477 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1478 {
1479 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1480 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1481 #endif
1482
1483 MS_U8 data = 0;
1484 MS_U8 data1 = 0;
1485
1486 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1487 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1488 {
1489 _MBX_ReadReg(0x3BBA, &data);
1490 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1491 }
1492 else
1493 {
1494 _MBX_ReadReg(0x22BA, &data);
1495 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1496 }
1497 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1498 _MBX_ReadReg(0x37BA, &data);
1499 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1500 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1501 _MBX_ReadReg(0x11BA, &data);
1502 _MBX_ReadReg(0x1249, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1503 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1504 _MBX_ReadReg(0x3BBA, &data);
1505 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1506 #else
1507 _MBX_ReadReg(0x22BA, &data);
1508 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1509 #endif
1510
1511 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1512 {
1513 return TRUE;
1514 }
1515 else
1516 {
1517 return FALSE;
1518 }
1519 }
1520
_HAL_INTERN_DTMB_FEC_Lock(void)1521 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1522 {
1523 MS_U8 u8state=0;
1524
1525
1526 _MBX_ReadReg(0x20C1, &u8state);
1527
1528 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1529 {
1530 return TRUE;
1531 }
1532 else
1533 {
1534 return FALSE;
1535 }
1536 }
1537
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1538 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1539 {
1540 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1541
1542 MS_U8 CM, QAM, IL, CR, SiNR;
1543 MS_U8 data_L = 0;
1544 MS_U8 data_H = 0;
1545
1546 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1547 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1548 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1549 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1550 {
1551 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1552 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1553 {
1554 _MBX_ReadReg(0x3B90, &data_L);
1555 _MBX_ReadReg(0x3B91, &data_H);
1556 }
1557 else
1558 {
1559 _MBX_ReadReg(0x2290, &data_L);
1560 _MBX_ReadReg(0x2291, &data_H);
1561 }
1562 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1563 _MBX_ReadReg(0x3790, &data_L);
1564 _MBX_ReadReg(0x3791, &data_H);
1565 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1566 _MBX_ReadReg(0x1190, &data_L);
1567 _MBX_ReadReg(0x1191, &data_H);
1568 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1569 _MBX_ReadReg(0x3B90, &data_L);
1570 _MBX_ReadReg(0x3B91, &data_H);
1571 #else
1572 _MBX_ReadReg(0x2290, &data_L);
1573 _MBX_ReadReg(0x2291, &data_H);
1574 #endif
1575
1576 if (data_L & 0x1)
1577 {
1578 CR = (data_L >> 6) & 0x03;
1579 IL = (data_L >> 3) & 0x01;
1580 QAM = (data_L >> 4) & 0x03;
1581 SiNR = (data_L >> 2) & 0x01;
1582 CM = (data_L >> 1) & 0x01;
1583 }
1584 else
1585 {
1586 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1587 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1588 {
1589 _MBX_ReadReg(0x3B9E, &data_L);
1590 _MBX_ReadReg(0x3B9F, &data_H);
1591 }
1592 else
1593 {
1594 _MBX_ReadReg(0x229E, &data_L);
1595 _MBX_ReadReg(0x229F, &data_H);
1596 }
1597 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1598 _MBX_ReadReg(0x379E, &data_L);
1599 _MBX_ReadReg(0x379F, &data_H);
1600 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1601 _MBX_ReadReg(0x119E, &data_L);
1602 _MBX_ReadReg(0x119F, &data_H);
1603 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1604 _MBX_ReadReg(0x3B9E, &data_L);
1605 _MBX_ReadReg(0x3B9F, &data_H);
1606 #else
1607 _MBX_ReadReg(0x229E, &data_L);
1608 _MBX_ReadReg(0x229F, &data_H);
1609 #endif
1610
1611 CR = (data_H >> 4) & 0x03;
1612 IL = (data_H >> 6) & 0x01;
1613 QAM = (data_H >> 2) & 0x03;
1614 SiNR = (data_H >> 1) & 0x01;
1615 CM = (data_H) & 0x01;
1616 }
1617
1618 #ifdef UTPA2
1619 if (CR == 0)
1620 psDtmbGetModulation->fSiCodeRate = 4;
1621 else if (CR == 1)
1622 psDtmbGetModulation->fSiCodeRate = 6;
1623 else if (CR == 2)
1624 psDtmbGetModulation->fSiCodeRate = 8;
1625 #else
1626 if (CR == 0)
1627 psDtmbGetModulation->fSiCodeRate = 0.4;
1628 else if (CR == 1)
1629 psDtmbGetModulation->fSiCodeRate = 0.6;
1630 else if (CR == 2)
1631 psDtmbGetModulation->fSiCodeRate = 0.8;
1632 #endif
1633
1634 if (IL == 0)
1635 psDtmbGetModulation->u8SiInterLeaver = 240;
1636 else
1637 psDtmbGetModulation->u8SiInterLeaver = 720;
1638
1639 if (QAM == 0)
1640 psDtmbGetModulation->u8SiQamMode = 4;
1641 else if (QAM == 1)
1642 psDtmbGetModulation->u8SiQamMode = 16;
1643 else if (QAM == 2)
1644 psDtmbGetModulation->u8SiQamMode = 32;
1645 else if (QAM == 3)
1646 psDtmbGetModulation->u8SiQamMode = 64;
1647
1648 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1649 psDtmbGetModulation->u8SiNR = SiNR;
1650 }
1651 else
1652 {
1653 }
1654
1655 return TRUE;
1656 }
1657
_HAL_INTERN_DTMB_ReadIFAGC(void)1658 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1659 {
1660 MS_U8 data = 0;
1661
1662 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1663 _MBX_ReadReg(0x280F, &data);
1664 #else
1665 _MBX_ReadReg(0x28FD, &data);
1666 #endif
1667
1668 return data;
1669 }
1670
1671 #ifdef UTPA2
_HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 * pFftfirstCfo,MS_S8 * pFftSecondCfo,MS_S16 * pSr)1672 static MS_BOOL _HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 *pFftfirstCfo, MS_S8 *pFftSecondCfo, MS_S16 *pSr)
1673 #else
1674 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1675 #endif
1676 {
1677 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1678
1679 MS_U8 u8Data = 0;
1680 MS_S16 fftfirstCfo = 0;
1681 MS_S8 fftSecondCfo = 0;
1682 MS_S16 sr = 0;
1683
1684 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1685 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1686 {
1687 _MBX_ReadReg(0x3C4D, &u8Data);
1688 fftfirstCfo = u8Data;
1689 _MBX_ReadReg(0x3C4C, &u8Data);
1690 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1691
1692 _MBX_ReadReg(0x3C50, &u8Data);
1693 fftSecondCfo = u8Data;
1694 }
1695 else
1696 {
1697 _MBX_ReadReg(0x234D, &u8Data);
1698 fftfirstCfo = u8Data;
1699 _MBX_ReadReg(0x234C, &u8Data);
1700 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1701
1702 _MBX_ReadReg(0x2350, &u8Data);
1703 fftSecondCfo = u8Data;
1704 }
1705 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1706 _MBX_ReadReg(0x384D, &u8Data);
1707 fftfirstCfo = u8Data;
1708 _MBX_ReadReg(0x384C, &u8Data);
1709 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1710
1711 _MBX_ReadReg(0x3850, &u8Data);
1712 fftSecondCfo = u8Data;
1713 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1714 _MBX_ReadReg(0x124D, &u8Data);
1715 fftfirstCfo = u8Data;
1716 _MBX_ReadReg(0x124C, &u8Data);
1717 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1718 _MBX_ReadReg(0x1250, &u8Data);
1719 fftSecondCfo = u8Data;
1720 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1721 _MBX_ReadReg(0x3C4D, &u8Data);
1722 fftfirstCfo = u8Data;
1723 _MBX_ReadReg(0x3C4C, &u8Data);
1724 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1725
1726 _MBX_ReadReg(0x3C50, &u8Data);
1727 fftSecondCfo = u8Data;
1728 #else
1729 _MBX_ReadReg(0x234D, &u8Data);
1730 fftfirstCfo = u8Data;
1731 _MBX_ReadReg(0x234C, &u8Data);
1732 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1733
1734 _MBX_ReadReg(0x2350, &u8Data);
1735 fftSecondCfo = u8Data;
1736 #endif
1737
1738 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1739 sr = 5670;
1740 else sr = 7560;
1741
1742 #ifdef UTPA2
1743 *pFftfirstCfo = fftfirstCfo;
1744 *pFftSecondCfo = fftSecondCfo;
1745 *pSr = sr;
1746
1747 return TRUE;
1748 #else
1749 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1750 #endif
1751 }
1752
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1753 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1754 {
1755 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1756
1757 MS_U8 data = 0;
1758 MS_U8 level = 0;
1759 MS_U32 snr = 0;
1760
1761 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1762 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1763 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1764 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1765 {
1766 if (!_HAL_INTERN_DTMB_FEC_Lock())
1767 level = 0;
1768 else
1769 {
1770 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1771 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1772 {
1773 _MBX_ReadReg(0x3BDA, &data);
1774 snr = data&0x3F;
1775 _MBX_ReadReg(0x3BD9, &data);
1776 snr = (snr<<8)|data;
1777 _MBX_ReadReg(0x3BD8, &data);
1778 snr = (snr<<8)|data;
1779 }
1780 else
1781 {
1782 _MBX_ReadReg(0x22DA, &data);
1783 snr = data&0x3F;
1784 _MBX_ReadReg(0x22D9, &data);
1785 snr = (snr<<8)|data;
1786 _MBX_ReadReg(0x22D8, &data);
1787 snr = (snr<<8)|data;
1788 }
1789 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1790 _MBX_ReadReg(0x37DA, &data);
1791 snr = data&0x3F;
1792 _MBX_ReadReg(0x37D9, &data);
1793 snr = (snr<<8)|data;
1794 _MBX_ReadReg(0x37D8, &data);
1795 snr = (snr<<8)|data;
1796 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1797 _MBX_ReadReg(0x11DA, &data);
1798 snr = data&0x3F;
1799 _MBX_ReadReg(0x11D9, &data);
1800 snr = (snr<<8)|data;
1801 _MBX_ReadReg(0x11D8, &data);
1802 snr = (snr<<8)|data;
1803 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1804 _MBX_ReadReg(0x3BDA, &data);
1805 snr = data&0x3F;
1806 _MBX_ReadReg(0x3BD9, &data);
1807 snr = (snr<<8)|data;
1808 _MBX_ReadReg(0x3BD8, &data);
1809 snr = (snr<<8)|data;
1810 #else
1811 _MBX_ReadReg(0x22DA, &data);
1812 snr = data&0x3F;
1813 _MBX_ReadReg(0x22D9, &data);
1814 snr = (snr<<8)|data;
1815 _MBX_ReadReg(0x22D8, &data);
1816 snr = (snr<<8)|data;
1817 #endif
1818
1819 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1820 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1821 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1822 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1823 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1824 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1825 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1826 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1827 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1828 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1829 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1830 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1831 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1832 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1833 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1834 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1835 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1836 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1837 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1838 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1839 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1840 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1841 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1842 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1843 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1844 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1845 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1846 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1847 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1848 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1849 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1850 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1851 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1852 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1853 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1854 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1855 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1856 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1857 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1858 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1859 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1860 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1861 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1862 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1863 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1864 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1865 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1866 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1867 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1868 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1869 }
1870 }
1871 else
1872 {
1873 level = 0;
1874 }
1875
1876 return level*2;
1877 }
1878
1879 #ifdef UTPA2
_HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 * pBitErr,MS_U16 * pError_window)1880 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 *pBitErr, MS_U16 *pError_window)
1881 #else
1882 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1883 #endif
1884 {
1885 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1886 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1887 #endif
1888
1889 MS_U8 u8Data=0;
1890 MS_U32 BitErr;
1891 MS_U16 error_window;
1892
1893 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1894 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1895 {
1896 _MBX_ReadReg(0x3F3B, &u8Data);
1897 BitErr = u8Data;
1898 _MBX_ReadReg(0x3F3A, &u8Data);
1899 BitErr = (BitErr << 8)|u8Data;
1900 _MBX_ReadReg(0x3F39, &u8Data);
1901 BitErr = (BitErr << 8)|u8Data;
1902 _MBX_ReadReg(0x3F38, &u8Data);
1903 BitErr = (BitErr << 8)|u8Data;
1904 }
1905 else
1906 {
1907 _MBX_ReadReg(0x263B, &u8Data);
1908 BitErr = u8Data;
1909 _MBX_ReadReg(0x263A, &u8Data);
1910 BitErr = (BitErr << 8)|u8Data;
1911 _MBX_ReadReg(0x2639, &u8Data);
1912 BitErr = (BitErr << 8)|u8Data;
1913 _MBX_ReadReg(0x2638, &u8Data);
1914 BitErr = (BitErr << 8)|u8Data;
1915 }
1916 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1917 _MBX_ReadReg(0x2D3B, &u8Data);
1918 BitErr = u8Data;
1919 _MBX_ReadReg(0x2D3A, &u8Data);
1920 BitErr = (BitErr << 8)|u8Data;
1921 _MBX_ReadReg(0x2D39, &u8Data);
1922 BitErr = (BitErr << 8)|u8Data;
1923 _MBX_ReadReg(0x2D38, &u8Data);
1924 BitErr = (BitErr << 8)|u8Data;
1925 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1926 _MBX_ReadReg(0x163B, &u8Data);
1927 BitErr = u8Data;
1928 _MBX_ReadReg(0x163A, &u8Data);
1929 BitErr = (BitErr << 8)|u8Data;
1930 _MBX_ReadReg(0x1639, &u8Data);
1931 BitErr = (BitErr << 8)|u8Data;
1932 _MBX_ReadReg(0x1638, &u8Data);
1933 BitErr = (BitErr << 8)|u8Data;
1934 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1935 _MBX_ReadReg(0x3F3B, &u8Data);
1936 BitErr = u8Data;
1937 _MBX_ReadReg(0x3F3A, &u8Data);
1938 BitErr = (BitErr << 8)|u8Data;
1939 _MBX_ReadReg(0x3F39, &u8Data);
1940 BitErr = (BitErr << 8)|u8Data;
1941 _MBX_ReadReg(0x3F38, &u8Data);
1942 BitErr = (BitErr << 8)|u8Data;
1943 #else
1944 _MBX_ReadReg(0x263B, &u8Data);
1945 BitErr = u8Data;
1946 _MBX_ReadReg(0x263A, &u8Data);
1947 BitErr = (BitErr << 8)|u8Data;
1948 _MBX_ReadReg(0x2639, &u8Data);
1949 BitErr = (BitErr << 8)|u8Data;
1950 _MBX_ReadReg(0x2638, &u8Data);
1951 BitErr = (BitErr << 8)|u8Data;
1952 #endif
1953
1954 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1955 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1956 {
1957 _MBX_ReadReg(0x3F2F, &u8Data);
1958 error_window = u8Data;
1959 _MBX_ReadReg(0x3F2E, &u8Data);
1960 error_window = (error_window << 8)|u8Data;
1961 }
1962 else
1963 {
1964 _MBX_ReadReg(0x262F, &u8Data);
1965 error_window = u8Data;
1966 _MBX_ReadReg(0x262E, &u8Data);
1967 error_window = (error_window << 8)|u8Data;
1968 }
1969 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1970 _MBX_ReadReg(0x2D2F, &u8Data);
1971 error_window = u8Data;
1972 _MBX_ReadReg(0x2D2E, &u8Data);
1973 error_window = (error_window << 8)|u8Data;
1974 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1975 _MBX_ReadReg(0x162F, &u8Data);
1976 error_window = u8Data;
1977 _MBX_ReadReg(0x162E, &u8Data);
1978 error_window = (error_window << 8)|u8Data;
1979 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1980 _MBX_ReadReg(0x3F2F, &u8Data);
1981 error_window = u8Data;
1982 _MBX_ReadReg(0x3F2E, &u8Data);
1983 error_window = (error_window << 8)|u8Data;
1984 #else
1985 _MBX_ReadReg(0x262F, &u8Data);
1986 error_window = u8Data;
1987 _MBX_ReadReg(0x262E, &u8Data);
1988 error_window = (error_window << 8)|u8Data;
1989 #endif
1990
1991 #ifdef UTPA2
1992 *pBitErr = BitErr;
1993 *pError_window = error_window;
1994 #else
1995 *pber=(float)BitErr/7488.0/(float)error_window;
1996 #endif
1997
1998 return TRUE;
1999 }
2000
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2001 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2002 {
2003 return _MBX_ReadReg(u16Addr, pu8Data);
2004 }
2005
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2006 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2007 {
2008 return _MBX_WriteReg(u16Addr, u8Data);
2009 }
2010
2011 //-------------------------------------------------------------------------------------------------
2012 // Global Functions
2013 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)2014 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
2015 {
2016 MS_BOOL bResult = TRUE;
2017
2018 switch(eCmd)
2019 {
2020 case DMD_DTMB_HAL_CMD_Exit:
2021 bResult = _HAL_INTERN_DTMB_Exit();
2022 break;
2023 case DMD_DTMB_HAL_CMD_InitClk:
2024 _HAL_INTERN_DTMB_InitClk();
2025 break;
2026 case DMD_DTMB_HAL_CMD_Download:
2027 bResult = _HAL_INTERN_DTMB_Download();
2028 break;
2029 case DMD_DTMB_HAL_CMD_FWVERSION:
2030 _HAL_INTERN_DTMB_FWVERSION();
2031 break;
2032 case DMD_DTMB_HAL_CMD_SoftReset:
2033 bResult = _HAL_INTERN_DTMB_SoftReset();
2034 break;
2035 case DMD_DTMB_HAL_CMD_SetACICoef:
2036 bResult = _HAL_INTERN_DTMB_SetACICoef();
2037 break;
2038 case DMD_DTMB_HAL_CMD_SetDTMBMode:
2039 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
2040 break;
2041 case DMD_DTMB_HAL_CMD_SetModeClean:
2042 bResult = _HAL_INTERN_DTMB_SetModeClean();
2043 break;
2044 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
2045 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
2046 break;
2047 case DMD_DTMB_HAL_CMD_Active:
2048 break;
2049 case DMD_DTMB_HAL_CMD_AGCLock:
2050 bResult = _HAL_INTERN_DTMB_AGCLock();
2051 break;
2052 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
2053 bResult = _HAL_INTERN_DTMB_PNP_Lock();
2054 break;
2055 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
2056 bResult = _HAL_INTERN_DTMB_FEC_Lock();
2057 break;
2058 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
2059 break;
2060 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
2061 break;
2062 case DMD_DTMB_HAL_CMD_GetModulation:
2063 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
2064 break;
2065 case DMD_DTMB_HAL_CMD_ReadIFAGC:
2066 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
2067 break;
2068 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
2069 #ifdef UTPA2
2070 bResult = _HAL_INTERN_DTMB_ReadFrequencyOffset(&((*((DMD_DTMB_CFO_DATA *)pArgs)).fftfirstCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).fftSecondCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).sr));
2071 #else
2072 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
2073 #endif
2074 break;
2075 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
2076 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
2077 break;
2078 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
2079 #ifdef UTPA2
2080 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer(&((*((DMD_DTMB_BER_DATA *)pArgs)).BitErr), &((*((DMD_DTMB_BER_DATA *)pArgs)).Error_window));
2081 #else
2082 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
2083 #endif
2084 break;
2085 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
2086 break;
2087 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
2088 break;
2089 case DMD_DTMB_HAL_CMD_GetSNR:
2090 break;
2091 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
2092 break;
2093 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
2094 break;
2095 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
2096 break;
2097 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
2098 break;
2099 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
2100 break;
2101 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
2102 break;
2103 case DMD_DTMB_HAL_CMD_DoIQSwap:
2104 break;
2105 case DMD_DTMB_HAL_CMD_GET_REG:
2106 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
2107 break;
2108 case DMD_DTMB_HAL_CMD_SET_REG:
2109 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
2110 break;
2111 default:
2112 break;
2113 }
2114
2115 return bResult;
2116 }
2117
MDrv_DMD_DTMB_Initial_Hal_Interface(void)2118 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
2119 {
2120 return TRUE;
2121 }
2122
2123