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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 #include "MsCommon.h"
103 #include "MsIRQ.h"
104 #include "MsOS.h"
105 #include "MsTypes.h"
106 #include "drvMMIO.h"
107 #include "drvDMD_common.h"
108 #include "drvDMD_VD_MBX.h"
109 #include "halDMD_INTERN_common.h"
110 #include "ULog.h"
111
112 #if defined (__aeon__) // Non-OS
113 #define BASEADDR_RIU 0xA0000000UL
114 //#elif ( OS_TYPE == linux ) // Linux
115 // #define RIU_BASE u32RegOSBase // MDrv_MIOMap_GetBASE(u32RegOSBase, puSize, MAP_NONPM_BANK)
116 #else // ecos
117 #define BASEADDR_RIU 0xBF800000UL
118 #endif
119
120 #define RIU_MACRO_START do {
121 #define RIU_MACRO_END } while (0)
122
123 // Address bus of RIU is 16 bits.
124 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_DMD.virtDMDBaseAddr + (addr) ) )
125 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_DMD.virtDMDBaseAddr + (addr) ) )
126 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_DMD.virtDMDBaseAddr + (addr), val) }
127 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_DMD.virtDMDBaseAddr + (addr), val) }
128
129 //=============================================================
130 // Standard Form
131
132 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
133
134 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
135
136 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
137
138 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
139 RIU_MACRO_START \
140 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
141 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
142 RIU_MACRO_END
143
144 #define RIU_WriteByte( u32Reg, u8Val ) \
145 RIU_MACRO_START \
146 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
147 RIU_MACRO_END
148
149 #define RIU_Write2Byte( u32Reg, u16Val ) \
150 RIU_MACRO_START \
151 if ( ((u32Reg) & 0x01) ) \
152 { \
153 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
154 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
155 } \
156 else \
157 { \
158 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
159 } \
160 RIU_MACRO_END
161
162 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
163 RIU_MACRO_START \
164 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
165 RIU_MACRO_END
166
167
168 typedef struct
169 {
170 MS_VIRT virtDMDBaseAddr;
171 MS_BOOL bBaseAddrInitialized;
172 } hal_DMD_t;
173
174 static hal_DMD_t _hal_DMD = // TODO: review, it would be init in Config()
175 {
176 .virtDMDBaseAddr = BASEADDR_RIU,
177 .bBaseAddrInitialized = 0,
178 };
179
180 extern s_I2C_Interface_func sI2cInterfaceFunc;
181
HAL_DMD_RegInit(void)182 MS_BOOL HAL_DMD_RegInit (void)
183 {
184 MS_VIRT virtNonPMBank;
185 MS_PHY phyNonPMBankSize;
186
187
188 ULOGD("DEMOD","bryan check DMD init!!\n");
189 if (!MDrv_MMIO_GetBASE( &virtNonPMBank, &phyNonPMBankSize, MS_MODULE_PM))
190 {
191 #ifdef MS_DEBUG
192 ULOGD("DEMOD","HAL_DMD_RegInit failure to get MS_MODULE_PM\n");
193 #endif
194 _hal_DMD.virtDMDBaseAddr = BASEADDR_RIU; // TODO what to do if failed??
195 _hal_DMD.bBaseAddrInitialized = 0;
196 return FALSE;
197 }
198
199 //HAL_ParFlash_Config(u32NonPMBank);
200 _hal_DMD.virtDMDBaseAddr=virtNonPMBank;
201 _hal_DMD.bBaseAddrInitialized = 1;
202 return TRUE;
203 }
204
HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)205 MS_U8 HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
206 {
207 if (_hal_DMD.bBaseAddrInitialized)
208 {
209 return RIU_ReadByte(u32Addr);
210 }
211 else
212 {
213 #ifdef MS_DEBUG
214 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
215 #endif
216 }
217 return 0;
218 }
219
HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr,MS_U8 u8Mask)220 MS_U8 HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr, MS_U8 u8Mask)
221 {
222 if (_hal_DMD.bBaseAddrInitialized)
223 {
224 return RIU_ReadRegBit(u32Addr, u8Mask);
225 }
226 else
227 {
228 #ifdef MS_DEBUG
229 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
230 #endif
231 }
232 return 0;
233 }
HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * pu8Data)234 MS_U8 HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *pu8Data)
235 {
236
237 MS_BOOL bRet=TRUE;
238 MS_U8 u8MsbData[6] = {0};
239
240 u8MsbData[0] = 0x10;
241 u8MsbData[1] = 0x00;
242 u8MsbData[2] = 0x00;
243 u8MsbData[3] = (u32Addr >> 8) &0xff;
244 u8MsbData[4] = u32Addr &0xff;
245
246 u8MsbData[0] = 0x35;
247 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
248
249 u8MsbData[0] = 0x10;
250 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 5, u8MsbData);
251 bRet &= sI2cInterfaceFunc.I2C_ReadBytes(u16SlaveAddr, 0, 0, 1, pu8Data);
252
253 u8MsbData[0] = 0x34;
254 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
255
256 return bRet;
257 }
HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)258 MS_U16 HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)
259 {
260 if (_hal_DMD.bBaseAddrInitialized)
261 {
262 return RIU_Read2Byte(u32Addr);
263 }
264 else
265 {
266 #ifdef MS_DEBUG
267 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
268 #endif
269 }
270 return 0;
271 }
272
HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 u8Data)273 MS_U8 HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 u8Data)
274 {
275 MS_BOOL bRet=TRUE;
276 MS_U8 u8MsbData[6] = {0};
277
278 u8MsbData[0] = 0x10;
279 u8MsbData[1] = 0x00;
280 u8MsbData[2] = 0x00;
281 u8MsbData[3] = (u32Addr >> 8) &0xff;
282 u8MsbData[4] = u32Addr &0xff;
283 u8MsbData[5] = u8Data;
284
285 u8MsbData[0] = 0x35;
286 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
287 u8MsbData[0] = 0x10;
288 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 6, u8MsbData);
289 u8MsbData[0] = 0x34;
290 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
291
292 return bRet;
293 }
HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * u8Data,MS_U8 u8Len)294 MS_U8 HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *u8Data, MS_U8 u8Len)
295 {
296 MS_BOOL bRet=TRUE;
297 MS_U16 index;
298 MS_U8 Data[0x80+5];
299
300 Data[0] = 0x10;
301 Data[1] = 0x00;
302 Data[2] = 0x00;
303 Data[3] = (u32Addr >> 8) &0xff;
304 Data[4] = u32Addr &0xff;
305
306 for(index = 0; index < u8Len ; index++)
307 {
308 Data[5+index] = u8Data[index];
309 }
310
311 Data[0] = 0x35;
312 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
313 Data[0] = 0x10;
314 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
315 sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, (5 + u8Len), Data);
316 Data[0] = 0x34;
317 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
318
319 return bRet;
320 }
321
HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr,MS_U8 ch_num)322 MS_BOOL HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr, MS_U8 ch_num)
323 {
324 MS_BOOL bRet=TRUE;
325 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
326 //Exit
327 Data[0] = 0x34;
328 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
329 Data[0]=(ch_num & 0x01)? 0x36 : 0x45;
330 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
331 //Init
332 Data[0] = 0x53;
333 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 5, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 5);
334 Data[0]=(ch_num & 0x04)? 0x80 : 0x81;
335 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
336 if ((ch_num==4)||(ch_num==5)||(ch_num==1))
337 Data[0]=0x82;
338 else
339 Data[0] = 0x83;
340 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
341
342 if ((ch_num==4)||(ch_num==5))
343 Data[0]=0x85;
344 else
345 Data[0] = 0x84;
346
347 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
348 Data[0]=(ch_num & 0x01)? 0x51 : 0x53;
349 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
350 Data[0]=(ch_num & 0x01)? 0x37 : 0x7F;
351 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
352 Data[0] = 0x35;
353 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
354 Data[0] = 0x71;
355 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
356 // MsOS_ReleaseMutex(_s32MutexId);
357 return bRet;
358 }
359
HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr,MS_U8 ch_num)360 MS_BOOL HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr, MS_U8 ch_num)
361 {
362 MS_BOOL bRet=TRUE;
363 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
364 Data[0] = (ch_num & 0x01)? 0x81 : 0x80;
365 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
366 Data[0] = (ch_num & 0x02)? 0x83 : 0x82;
367 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
368 Data[0] = (ch_num & 0x04)? 0x85 : 0x84;
369 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
370
371 return bRet;
372 }
HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)373 void HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
374 {
375 if (_hal_DMD.bBaseAddrInitialized)
376 {
377 RIU_WriteByte(u32Addr, u8Value);
378 }
379 else
380 {
381 #ifdef MS_DEBUG
382 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
383 #endif
384 }
385 }
386
HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr,MS_BOOL bEnable,MS_U8 u8Mask)387 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask)
388 {
389 if (_hal_DMD.bBaseAddrInitialized)
390 {
391 RIU_WriteRegBit(u32Addr, bEnable, u8Mask);
392 }
393 else
394 {
395 #ifdef MS_DEBUG
396 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
397 #endif
398 }
399 }
400
HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)401 void HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
402 {
403 if (_hal_DMD.bBaseAddrInitialized)
404 {
405 RIU_WriteByteMask(u32Addr, u8Value, u8Mask);
406 }
407 else
408 {
409 #ifdef MS_DEBUG
410 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
411 #endif
412 }
413 }
414
HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr,MS_U16 u16Value)415 void HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr, MS_U16 u16Value)
416 {
417 if (_hal_DMD.bBaseAddrInitialized)
418 {
419 RIU_Write2Byte(u32Addr, u16Value);
420 }
421 else
422 {
423 #ifdef MS_DEBUG
424 ULOGD("DEMOD","%s base address un-initialized\n", __FUNCTION__);
425 #endif
426 }
427 }
428
429 //waiting add
HAL_DMD_IFAGC_RegRead(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)430 MS_BOOL HAL_DMD_IFAGC_RegRead(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
431 {
432 MS_U8 status = true;
433 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0;
434 // bank 5 0x24 [15:0] reg_agc_gain2_out
435 // use only high byte value
436
437 // select IF gain to read
438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03);
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, ®_frz);
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80);
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, ®_tmp);
442 *ifagc_reg = reg_tmp;
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, ®_tmp);
444 *ifagc_reg_lsb = reg_tmp;
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz);
446
447 #ifdef MS_DEBUG
448 ULOGD("DEMOD","SSI_IFAGC_H = 0x%x 0x%x\n", *ifagc_reg,*ifagc_reg_lsb);
449 #endif
450
451 *ifagc_err = 0;
452 if(*ifagc_reg == 0xff)
453 {
454 // bank 5 0x04 [15] reg_tdp_lat
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00);
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, ®_frz);
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80);
458
459 // bank 5 0x2c [9:0] reg_agc_error
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, ®_tmp);
461 // if_agc_err = reg_tmp & 0x03;
462 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, ®_tmp2);
463 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
464
465 if(reg_tmp&0x2)
466 {
467 *ifagc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
468 }
469 else
470 {
471 *ifagc_err = reg_tmp<<8|reg_tmp2;
472 }
473
474 // release latch
475 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz);
476 }
477
478
479 return status;
480 }
481
482 //waiting mark
483 #if(0)
HAL_DMD_GetRFLevel(float * fRFPowerDbmResult,float fRFPowerDbm,MS_U8 u8SarValue,DMD_RFAGC_SSI * pRfagcSsi,MS_U16 u16RfagcSsi_Size,DMD_IFAGC_SSI * pIfagcSsi_HiRef,MS_U16 u16IfagcSsi_HiRef_Size,DMD_IFAGC_SSI * pIfagcSsi_LoRef,MS_U16 u16IfagcSsi_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_LoRef,MS_U16 u16IfagcErr_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_HiRef,MS_U16 u16IfagcErr_HiRef_Size)484 MS_BOOL HAL_DMD_GetRFLevel(float *fRFPowerDbmResult, float fRFPowerDbm, MS_U8 u8SarValue,
485 DMD_RFAGC_SSI *pRfagcSsi, MS_U16 u16RfagcSsi_Size,
486 DMD_IFAGC_SSI *pIfagcSsi_HiRef, MS_U16 u16IfagcSsi_HiRef_Size,
487 DMD_IFAGC_SSI *pIfagcSsi_LoRef, MS_U16 u16IfagcSsi_LoRef_Size,
488 DMD_IFAGC_ERR *pIfagcErr_LoRef, MS_U16 u16IfagcErr_LoRef_Size,
489 DMD_IFAGC_ERR *pIfagcErr_HiRef, MS_U16 u16IfagcErr_HiRef_Size)
490 {
491 DMD_IFAGC_SSI *ifagc_ssi;
492 DMD_IFAGC_ERR *ifagc_err;
493 float ch_power_db=0.0f;
494 float ch_power_rf=0.0f;
495 float ch_power_if=0.0f, ch_power_ifa = 0.0f, ch_power_ifb =0.0f;
496 float ch_power_takeover=0.0f;
497 MS_U16 if_agc_err = 0;
498 MS_U8 status = true;
499 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0,rf_agc_val =0,if_agc_val =0, if_agc_vala =0, if_agc_valb =0, if_agc_val_lsb =0, i;
500 MS_U8 ssi_tbl_len = 0, err_tbl_len = 0;
501
502 if ((pIfagcSsi_HiRef != NULL) && (pIfagcSsi_LoRef !=NULL))
503 {
504 // get RFAGC level
505 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
506 {
507 rf_agc_val = u8SarValue;
508
509 ch_power_rf=pRfagcSsi[u16RfagcSsi_Size-1].power_db;
510 if (rf_agc_val >=pRfagcSsi[0].sar3_val)
511 {
512 float ch_power_rfa = 0, ch_power_rfb =0;
513 MS_U8 rf_agc_vala =0, rf_agc_valb =0;
514 for(i = 1; i < u16RfagcSsi_Size; i++)
515 {
516 if (rf_agc_val < pRfagcSsi[i].sar3_val)
517 {
518 rf_agc_valb = pRfagcSsi[i].sar3_val;
519 ch_power_rfb = pRfagcSsi[i].power_db;
520
521 i--;
522 rf_agc_vala = pRfagcSsi[i].sar3_val;
523 ch_power_rfa=pRfagcSsi[i].power_db;
524 while ((i>1) && (rf_agc_vala==pRfagcSsi[i-1].sar3_val))
525 {
526 ch_power_rfa=pRfagcSsi[i-1].power_db;
527 i--;
528 }
529 ch_power_rf = ch_power_rfa+(ch_power_rfb-ch_power_rfa)*(float)(rf_agc_val-rf_agc_vala)/(rf_agc_valb-rf_agc_vala);
530 break;
531 }
532 }
533 #ifdef MS_DEBUG
534 ULOGD("DEMOD","RF Level from SAR:%f\n", ch_power_rf);
535 ULOGD("DEMOD","SSI_RFAGC (SAR-4) = 0x%x\n", rf_agc_val);
536 ULOGD("DEMOD","rf prev %f %x\n", ch_power_rfa, rf_agc_vala);
537 ULOGD("DEMOD","rf next %f %x\n", ch_power_rfb, rf_agc_valb);
538 #endif
539 }
540 }
541 else
542 {
543 #ifdef MS_DEBUG
544 ULOGD("DEMOD","RF Level from tuner: %f\n",fRFPowerDbm);
545 #endif
546 ch_power_rf = fRFPowerDbm;
547 }
548
549 // get IFAGC status
550 {
551 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13, ®_tmp);
552
553 #ifdef MS_DEBUG
554 ULOGD("DEMOD","AGC_REF = %d\n", (MS_U16)reg_tmp);
555 #endif
556
557 if (reg_tmp > 200)
558 {
559 ifagc_ssi = pIfagcSsi_HiRef;
560 ssi_tbl_len = u16IfagcSsi_HiRef_Size;
561 ifagc_err = pIfagcErr_HiRef;
562 err_tbl_len = u16IfagcErr_HiRef_Size;
563 }
564 else
565 {
566 ifagc_ssi = pIfagcSsi_LoRef;
567 ssi_tbl_len = u16IfagcSsi_LoRef_Size;
568 ifagc_err = pIfagcErr_LoRef;
569 err_tbl_len = u16IfagcErr_LoRef_Size;
570 }
571
572 // bank 5 0x24 [15:0] reg_agc_gain2_out
573 // use only high byte value
574
575 // select IF gain to read
576 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
577 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
578 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
580 if_agc_val = reg_tmp;
581 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp);
582 if_agc_val_lsb = reg_tmp;
583 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
584 #ifdef MS_DEBUG
585 ULOGD("DEMOD","SSI_IFAGC_H = 0x%x 0x%x\n", if_agc_val,if_agc_val_lsb);
586 #endif
587
588 ch_power_if=ifagc_ssi[0].power_db;
589 if (if_agc_val >=ifagc_ssi[0].agc_val)
590 {
591 for(i = 1; i < ssi_tbl_len; i++)
592 {
593 if (if_agc_val < ifagc_ssi[i].agc_val)
594 {
595 if_agc_valb = ifagc_ssi[i].agc_val;
596 ch_power_ifb = ifagc_ssi[i].power_db;
597
598 i--;
599 if_agc_vala = ifagc_ssi[i].agc_val;
600 ch_power_ifa=ifagc_ssi[i].power_db;
601 while ((i>1) && (if_agc_vala==ifagc_ssi[i-1].agc_val))
602 {
603 ch_power_ifa=ifagc_ssi[i-1].power_db;
604 i--;
605 }
606 ch_power_if = ch_power_ifa+(ch_power_ifb-ch_power_ifa)*(float)((if_agc_val-if_agc_vala)*256+if_agc_val_lsb)/((if_agc_valb-if_agc_vala)*256);
607 break;
608 }
609 }
610 }
611 #ifdef MS_DEBUG
612 ULOGD("DEMOD","if prev %f %x\n", ch_power_ifa, if_agc_vala);
613 ULOGD("DEMOD","if next %f %x\n", ch_power_ifb, if_agc_valb);
614 #endif
615
616 for(i = 0; i < ssi_tbl_len; i++)
617 {
618 if (ifagc_ssi[i].agc_val <= ifagc_ssi[i+1].agc_val)
619 {
620 ch_power_takeover = ifagc_ssi[i+1].power_db;
621 break;
622 }
623 }
624
625 #ifdef MS_DEBUG
626 ULOGD("DEMOD","ch_power_rf = %f\n", ch_power_rf);
627 ULOGD("DEMOD","ch_power_if = %f\n", ch_power_if);
628 ULOGD("DEMOD","ch_power_takeover = %f\n", ch_power_takeover);
629 #endif
630
631 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_rf : ch_power_if;
632
633 if(ch_power_rf > (ch_power_takeover + 0.5))
634 {
635 ch_power_db = ch_power_rf;
636 }
637 else if(ch_power_if < (ch_power_takeover - 0.5))
638 {
639 ch_power_db = ch_power_if;
640 }
641 else
642 {
643 ch_power_db = (ch_power_if + ch_power_rf)/2;
644 }
645
646 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_if : ch_power_rf;
647
648 ///////// IF-AGC Error for Add. Attnuation /////////////
649 if(if_agc_val == 0xff)
650 {
651 #if 0
652 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, ®_tmp);
654 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (reg_tmp&0xf0));
655 #endif
656 #endif
657 // bank 5 0x04 [15] reg_tdp_lat
658 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00);
659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
660 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
661 #if 0
662 //#if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
663 // bank 5 0x2c [9:0] reg_agc_error
664 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, ®_tmp);
665 // if_agc_err = reg_tmp & 0x03;
666 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, ®_tmp2);
667 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
668 //#else
669 #endif
670 // bank 5 0x2c [9:0] reg_agc_error
671 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
672 // if_agc_err = reg_tmp & 0x03;
673 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp2);
674 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
675 //#endif
676
677 if(reg_tmp&0x2)
678 {
679 if_agc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
680 }
681 else
682 {
683 if_agc_err = reg_tmp<<8|reg_tmp2;
684 }
685
686 // release latch
687 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
688
689 for(i = 0; i < err_tbl_len; i++)
690 {
691 if ( if_agc_err <= ifagc_err[i].agc_err ) // signed char comparison
692 {
693 ch_power_db += ifagc_err[i].attn_db;
694 break;
695 }
696 }
697 #ifdef MS_DEBUG
698 ULOGD("DEMOD","if_agc_err = 0x%x\n", if_agc_err);
699 #endif
700 }
701
702 // BY 20110812 temporaily remove ch_power_db += SIGNAL_LEVEL_OFFSET;
703 }
704 }
705 else
706 {
707 #ifdef MS_DEBUG
708 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
709 {
710 ULOGD("DEMOD","Error!! please add AGC table\n");
711 }
712 #endif
713 ch_power_db = fRFPowerDbm;
714 }
715 *fRFPowerDbmResult=ch_power_db;
716 return status;
717 }
718 #endif
719
720 //waiting mark
721 #if(0)
HAL_DMD_GetNordigSSI(float fPrel,MS_U16 * strength)722 void HAL_DMD_GetNordigSSI(float fPrel, MS_U16 *strength)
723 {
724 if (fPrel<-15.0f)
725 {
726 *strength = 0;
727 }
728 else if (fPrel<0.0f)
729 {
730 *strength = (MS_U16)((2.0f/3.0f)*(fPrel+15.0f));
731 }
732 else if (fPrel<20.0f)
733 {
734 *strength = (MS_U16)(4.0f*fPrel+10.0f);
735 }
736 else if (fPrel<35.0f)
737 {
738 *strength = (MS_U16)((2.0f/3.0f)*(fPrel-20.0f)+90.0f);
739 }
740 else
741 {
742 *strength = 100;
743 }
744
745 }
746 #endif
747 /*
748 from Steven.Hung
749 2. �n��T12 TS1 TS bus tristate
750 Set Bank CHIPTOP, 0x57[13:11]=3��h0; (reg_ts1config[2:0]=0)
751 3. �n��T12 IFAGC tristate
752 Set Bank CHIPTOP, 0x2[12]=1��h1; (reg_if_agc_pad_oen=1)
753 */
HAL_DMD_TS1_Tristate(MS_BOOL bEnable)754 void HAL_DMD_TS1_Tristate(MS_BOOL bEnable)
755 {
756 #ifdef MS_DEBUG
757 ULOGD("DEMOD","HAL_DMD_TS1_Tristate %d\n",bEnable);
758 #endif
759 if (bEnable)
760 {
761 HAL_DMD_RIU_WriteByteMask(0x101EAF, 0, BMASK(5:3));
762 }
763 else
764 {
765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3));
766 }
767 }
768
HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)769 void HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)
770 {
771 MS_U8 u8RegMuxBackup = 0;
772
773 #ifdef MS_DEBUG
774 ULOGD("DEMOD","HAL_DMD_RFAGC_Tristate %d\n",bEnable);
775 #endif
776 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
777 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
778 if (bEnable)
779 {
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0)));
781
782 }
783 else
784 {
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0)));
786 }
787 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
788 }
789
HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)790 void HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)
791 {
792 MS_U8 u8RegMuxBackup = 0;
793
794 #ifdef MS_DEBUG
795 ULOGD("DEMOD","HAL_DMD_IFAGC_Tristate %d\n",bEnable);
796 #endif
797 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
798 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
799 if (bEnable)
800 {
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4)));
802 }
803 else
804 {
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4)));
806 }
807 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
808 }
809
HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)810 void HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)
811 {
812 #ifdef MS_DEBUG
813 ULOGD("DEMOD","HAL_DMD_IFAGC_TS_Tristate %d\n",bEnable);
814 #endif
815 HAL_DMD_TS1_Tristate(bEnable);
816 HAL_DMD_IFAGC_Tristate(bEnable);
817 }
818
819 #if(0)
HAL_DMD_TS_GetClockRate(float * fTS_CLK)820 MS_BOOL HAL_DMD_TS_GetClockRate(float *fTS_CLK)
821 {
822 // from Raymond
823 *fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x103300)&BMASK(4:0))+1));
824 return TRUE;
825 }
826 #endif
HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)827 static void HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
828 {
829 if (u8PadSel==0)
830 {
831 HAL_DMD_RIU_WriteByteMask(0x112802, 4<<4, BMASK(6:4));
832 }
833 else
834 {
835 if (bPGAEnable)
836 {
837 HAL_DMD_RIU_WriteByteMask(0x112802, 1<<4, BMASK(6:4));
838 }
839 else
840 {
841 HAL_DMD_RIU_WriteByteMask(0x112802, 2<<4, BMASK(6:4));
842 }
843 }
844 }
845
HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)846 static void HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
847 {
848 if (u8PadSel==0)
849 {
850 HAL_DMD_RIU_WriteByteMask(0x112803, 4, BMASK(2:0));
851 }
852 else
853 {
854 if (bPGAEnable)
855 {
856 HAL_DMD_RIU_WriteByteMask(0x112803, 1, BMASK(2:0));
857 }
858 else
859 {
860 HAL_DMD_RIU_WriteByteMask(0x112803, 2, BMASK(2:0));
861 }
862 }
863 }
864
865
HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)866 static void HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)
867 {
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping
870 }
871
HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)872 static void HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)
873 {
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping
876 }
877
878 /************************************************************************************************
879 Subject: ADC I/Q Switch (After Init CLKGen)
880 Function: HAL_DMD_ADC_IQ_Switch
881 Parmeter: u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
882 Parmeter: u8PadSel : 0=Normal, 1=analog pad
883 Parmeter: bPGAEnable : 0=disable, 1=enable
884 Parmeter: u8PGAGain : default 5
885 Return: MS_BOOL :
886 Remark:
887 *************************************************************************************************/
HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain)888 MS_BOOL HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain)
889 {
890 MS_U8 u8RegMuxBackup = 0;
891 u8PGAGain=u8PGAGain;
892 #ifdef MS_DEBUG
893 ULOGD("DEMOD","HAL_DMD_ADC_IQ_Switch %d %d %d %d\n",u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
894 #endif
895
896 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
897 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
898 #ifdef MS_DEBUG
899 ULOGD("DEMOD","before 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
900 #endif
901 switch(u8ADCIQMode)
902 {
903 case 0://Normal case, I path
904 default:
905 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC
906 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC
907 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
908 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q
909 HAL_DMD_ADC_IMUX_Sel(u8PadSel, bPGAEnable);
910 HAL_DMD_SIF_PGA_Ctl(bPGAEnable);
911 HAL_DMD_VIF_PGA_Ctl(FALSE);
912 break;
913 case 1://VIF, Q path, for internal signal saw
914 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC
915 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(1)); // power on Q ADC
916 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
917 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(5)); // ADC clock out select 0:I, 1:Q
918 HAL_DMD_ADC_QMUX_Sel(u8PadSel, bPGAEnable);
919 HAL_DMD_SIF_PGA_Ctl(FALSE);
920 HAL_DMD_VIF_PGA_Ctl(bPGAEnable);
921 break;
922 case 2://both IQ, for ZIF tuner
923 break;
924 }
925 #ifdef MS_DEBUG
926 ULOGD("DEMOD","after 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
927 #endif
928 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
929 return TRUE;
930 }
931
932 /************************************************************************************************
933 Subject: HAL_DMD_TSO_Clk_Control
934 Function: ts output clock frequency and phase configure
935 Parmeter: u8cmd_array, clock div, 0x01, div (0x00~0x1f),
936 clock phase inv, 0x02, inv_en (0,1),
937 clock phase tuning, 0x03, phase_tuning_en (0,1), tuning_num (0x00~0x1f)
938 Return: MS_BOOL
939 Remark:
940 *************************************************************************************************/
HAL_DMD_TSO_Clk_Control(MS_U8 * u8cmd_array)941 MS_BOOL HAL_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array)
942 {
943 MS_U8 u8Temp;
944
945 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
946
947 if ( (u8Temp&0x01) == 0x00)
948 {
949 ULOGD("DEMOD","[utopia][halDMD]Error!!!, we shall select clk_dmplldiv3\n");
950 return false;
951 }
952 switch (u8cmd_array[0])
953 {
954 case 0x01: // clock frequency,div
955 {
956 MS_U8 u8data = 0;
957 u8data = HAL_DMD_RIU_ReadByte(0x103300);
958 u8data &= (0xff-0x1f);
959 u8data |= (u8cmd_array[1]&0x1f);
960 HAL_DMD_RIU_WriteByte(0x103300, u8data);
961 }
962 break;
963 case 0x02: // clock phase inv or not.
964 {
965 MS_U8 u8data = 0;
966 u8data = HAL_DMD_RIU_ReadByte(0x103301);
967 u8data &= (0xff-0x02);
968 u8data |= ((u8cmd_array[1]&0x01)<<1);
969 HAL_DMD_RIU_WriteByte(0x103301, u8data);
970 }
971 break;
972 case 0x03:
973 {
974 MS_U8 u8data = 0;
975
976 u8data = HAL_DMD_RIU_ReadByte(0x103301);
977 u8data &= (0xff-0x10);
978 u8data |= ((u8cmd_array[1]&0x01)<<4);
979 HAL_DMD_RIU_WriteByte(0x103301, u8data);
980
981 u8data = HAL_DMD_RIU_ReadByte(0x103300+(0x05<<1)+1);
982 u8data &= (0xff-0x1f);
983 u8data |= (u8cmd_array[2]&0x1f);
984 HAL_DMD_RIU_WriteByte(0x103300+(0x05<<1)+1, u8data);
985 }
986 break;
987 default:
988 ULOGD("DEMOD","[utopia][halDMD]Error!!!, cmd invalid\n");
989 break;
990
991 }
992 #ifdef MS_DEBUG
993 ULOGD("DEMOD","0x103300: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103300));
994 ULOGD("DEMOD","0x103301: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103301));
995 ULOGD("DEMOD","0x10330B: 0x%x\n",HAL_DMD_RIU_ReadByte(0x10330B));
996 #endif
997 return true;
998 }
999
1000 /****************************************************************************
1001 Subject: Function providing approx. result of Log10(X)
1002 Function: Log10Approx
1003 Parmeter: Operand X in float
1004 Return: Approx. value of Log10(X) in float
1005 Remark: Ouput range from 0.0, 0.3 to 9.6 (input 1 to 2^32)
1006 *****************************************************************************/
1007 /*
1008 #if(0)
1009 #if 1
1010 const float _LogApproxTableX[80] =
1011 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
1012 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
1013 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
1014 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
1015 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
1016 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
1017 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
1018 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
1019 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
1020 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
1021 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
1022 456767058.24, 593797175.72, 771936328.43, 1003517226.96
1023 };
1024
1025 const float _LogApproxTableY[80] =
1026 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
1027 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
1028 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
1029 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
1030 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
1031 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
1032 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
1033 };
1034
1035 float Log10Approx(float flt_x)
1036 {
1037 MS_U8 indx = 0;
1038
1039 do {
1040 if (flt_x < _LogApproxTableX[indx])
1041 break;
1042 indx++;
1043 }while (indx < 79); //stop at indx = 80
1044
1045 return _LogApproxTableY[indx];
1046 }
1047 #else
1048 float Log10Approx(float flt_x)
1049 {
1050 MS_U32 u32_temp = 1;
1051 MS_U8 indx = 0;
1052
1053 do {
1054 u32_temp = u32_temp << 1;
1055 if (flt_x < (float)u32_temp)
1056 break;
1057 }while (++indx < 32);
1058
1059 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
1060 return (float)0.3 * indx;
1061 }
1062 #endif
1063 #endif
1064 */