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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef _HAL_DMD_COMMON_H_ 95 #define _HAL_DMD_COMMON_H_ 96 97 #define MBRegBase 0x112600UL //Demod MailBox 98 #define VDMcuBase 0x103400UL //DmdMCU51 (40-4F) 99 #define DMDMcuBase 0x103480UL 100 #define XDMIU_REG_BASE 0x1d00 101 #define BACKEND_REG_BASE 0x1f00 102 #define TOP_REG_BASE 0x2000 103 #define TDP_REG_BASE 0x2100 104 #define FDP_REG_BASE 0x2200 105 #define ISDBT_FDPE_REG_BASE 0x3900 106 #define FEC_REG_BASE 0x2300 107 #define TDF_REG_BASE 0x2800 108 #define TDFE_REG_BASE 0x2900 109 #define TDFE2_REG_BASE 0x2a00 110 #define DTOP_REG_BASE 0x2e00 111 #define T2TDP_REG_BASE 0x3000 112 #define T2FDP_REG_BASE 0x3100 113 #define T2FEC_REG_BASE 0x3300 114 #define DVBTM_REG_BASE 0x3400 115 #define T2L1_REG_BASE 0x2b00 116 #define T2SNR_REG_BASE 0x2c00 117 #define T2DJB_REG_BASE 0x2d00 118 119 #define REG_CMD_CTRL MBRegBase + 0x1C 120 #define REG_DTA_CTRL MBRegBase + 0x1D 121 #define REG_CMD_ADDR MBRegBase + 0x1E 122 #define REG_CMD_DATA MBRegBase + 0x1F 123 124 #define _REG_START REG_CMD_CTRL 125 #define _REG_END REG_CMD_CTRL 126 #define _REG_DRQ REG_DTA_CTRL 127 #define _REG_FSM REG_CMD_CTRL 128 #define _REG_ERR REG_DTA_CTRL 129 130 #define _BIT_START ((BIT_(1))) 131 #define _BIT_END ((BIT_(0))) 132 #define _BIT_DRQ ((BIT_(0))) 133 #define _BIT_FSM ((BIT_(3))) 134 #define _BIT_ERR ((BIT_(7))) 135 136 typedef struct _s_MDRV_DMD_INTERFACE_FUNCTION 137 { 138 MS_BOOL (*MDrv_DMD_WriteReg)(MS_U32 u32Reg, MS_U8 u8Value); 139 MS_BOOL (*MDrv_DMD_ReadReg)(MS_U32 u32Reg, MS_U8 *u8Value); 140 MS_BOOL (*MDrv_DMD_WriteRegs)(MS_U32 u32Reg, MS_U8 *u8Value, MS_U8 u8Length); 141 MS_BOOL (*MDrv_DMD_I2C_Channel_Change)(MS_U8 ch_num); 142 MS_BOOL (*MDrv_DMD_I2C_Channel_Set)(MS_U8 ch_num); 143 float (*Log10Approx)(float flt_x); 144 }s_MDRV_DMD_INTERFACE_FUNCTION; 145 146 147 MS_BOOL HAL_DMD_RegInit (void); 148 MS_U8 HAL_DMD_RIU_ReadByte(MS_U32 u32Addr); 149 MS_U8 HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr, MS_U8 u8Mask); 150 MS_U16 HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr); 151 void HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value); 152 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask); 153 void HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask); 154 void HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr, MS_U16 u16Value); 155 156 //waiting add 157 MS_BOOL HAL_DMD_IFAGC_RegRead(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err); 158 /* 159 MS_BOOL HAL_DMD_GetRFLevel(float *fRFPowerDbmResult, float fRFPowerDbm, MS_U8 u8SarValue, 160 DMD_RFAGC_SSI *pRfagcSsi, MS_U16 u16RfagcSsi_Size, 161 DMD_IFAGC_SSI *pIfagcSsi_HiRef, MS_U16 u16IfagcSsi_HiRef_Size, 162 DMD_IFAGC_SSI *pIfagcSsi_LoRef, MS_U16 u16IfagcSsi_LoRef_Size, 163 DMD_IFAGC_ERR *pIfagcErr_LoRef, MS_U16 u16IfagcErr_LoRef_Size, 164 DMD_IFAGC_ERR *pIfagcErr_HiRef, MS_U16 u16IfagcErr_HiRef_Size); 165 */ 166 void HAL_DMD_GetNordigSSI(float fPrel, MS_U16 *strength); 167 void HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable); 168 void HAL_DMD_TS1_Tristate(MS_BOOL bEnable); 169 MS_BOOL HAL_DMD_TS_GetClockRate(float *fTS_CLK); 170 void HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable); 171 void HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable); 172 MS_BOOL HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain); 173 MS_BOOL HAL_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array); 174 //float Log10Approx(float flt_x); 175 MS_U8 HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *pu8Data); 176 MS_U8 HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 u8Data); 177 MS_U8 HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *u8Data, MS_U8 u8Len); 178 MS_BOOL HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr, MS_U8 ch_num); 179 MS_BOOL HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr, MS_U8 ch_num); 180 #endif 181 182