1 //<MStar Software>
2 //******************************************************************************
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ISDBT.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ISDBT_CHIP_EULER 0x00
112 #define DMD_ISDBT_CHIP_NUGGET 0x01
113 #define DMD_ISDBT_CHIP_KAPPA 0x02
114 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
115 #define DMD_ISDBT_CHIP_NAPOLI 0x04
116 #define DMD_ISDBT_CHIP_MONACO 0x05
117 #define DMD_ISDBT_CHIP_MIAMI 0x06
118 #define DMD_ISDBT_CHIP_MUJI 0x07
119 #define DMD_ISDBT_CHIP_MANHATTAN 0x08
120 #define DMD_ISDBT_CHIP_MULAN 0x09
121 #define DMD_ISDBT_CHIP_MESSI 0x0A
122 #define DMD_ISDBT_CHIP_MASERATI 0x0B
123 #define DMD_ISDBT_CHIP_KIWI 0x0C
124 #define DMD_ISDBT_CHIP_MACAN 0x0D
125 #if defined(CHIP_EULER)
126 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
127 #elif defined(CHIP_NUGGET)
128 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
129 #elif defined(CHIP_KAPPA)
130 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
131 #elif defined(CHIP_EINSTEIN)
132 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
133 #elif defined(CHIP_NAPOLI)
134 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
135 #elif defined(CHIP_MIAMI)
136 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
137 #elif defined(CHIP_MUJI)
138 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
139 #elif defined(CHIP_MANHATTAN)
140 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MANHATTAN
141 #elif defined(CHIP_MULAN)
142 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MULAN
143 #elif defined(CHIP_MESSI)
144 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MESSI
145 #elif defined(CHIP_MASERATI)
146 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MASERATI
147 #elif defined(CHIP_KIWI)
148 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KIWI
149 #elif defined(CHIP_MACAN)
150 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MACAN
151 #else
152 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
153 #endif
154
155 //-------------------------------------------------------------------------------------------------
156 // Local Defines
157 //-------------------------------------------------------------------------------------------------
158 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN)
159 #define DMD_ISDBT_TBVA_EN 1
160 #else
161 #define DMD_ISDBT_TBVA_EN 0
162 #endif
163 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr) ) )
164 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr), val) )
165
166 #define HAL_INTERN_ISDBT_DBINFO(y) //y
167 #ifndef MBRegBase
168 #define MBRegBase 0x112600UL
169 #endif
170 #ifndef MBRegBase_DMD1
171 #define MBRegBase_DMD1 0x112400UL
172 #endif
173 #ifndef DMDMcuBase
174 #define DMDMcuBase 0x103480UL
175 #endif
176
177 #define REG_ISDBT_LOCK_STATUS 0x36F5
178 #define ISDBT_TDP_REG_BASE 0x3700
179 #define ISDBT_FDP_REG_BASE 0x3800
180 #define ISDBT_FDPEXT_REG_BASE 0x3900
181 #define ISDBT_OUTER_REG_BASE 0x3A00
182
183
184 //-------------------------------------------------------------------------------------------------
185 // Local Variables
186 //-------------------------------------------------------------------------------------------------
187
188 const MS_U8 INTERN_ISDBT_table[] = {
189 #include "DMD_INTERN_ISDBT.dat"
190 };
191
192 #ifndef UTPA2
193 static const float _LogApproxTableX[80] =
194 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
195 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
196 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
197 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
198 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
199 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
200 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
201 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
202 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
203 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
204 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
205 456767058.24, 593797175.72, 771936328.43, 1003517226.96
206 };
207
208 static const float _LogApproxTableY[80] =
209 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
210 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
211 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
212 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
213 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
214 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
215 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
216 };
217 #endif
218
219 //-------------------------------------------------------------------------------------------------
220 // Global Variables
221 //-------------------------------------------------------------------------------------------------
222
223 extern MS_U8 u8DMD_ISDBT_DMD_ID;
224
225 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
226
227 //-------------------------------------------------------------------------------------------------
228 // Local Functions
229 //-------------------------------------------------------------------------------------------------
230 #ifndef UTPA2
231
232 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)233 static float Log10Approx(float flt_x)
234 {
235 MS_U8 indx = 0;
236
237 do {
238 if (flt_x < _LogApproxTableX[indx])
239 break;
240 indx++;
241 }while (indx < 79); //stop at indx = 80
242
243 return _LogApproxTableY[indx];
244 }
245 #endif
246
_CALCULATE_SQI(float fber)247 static MS_U16 _CALCULATE_SQI(float fber)
248 {
249 float flog_ber;
250 MS_U16 u16SQI;
251
252 #ifdef MSOS_TYPE_LINUX
253 flog_ber = (float)log10((double)fber);
254 #else
255 if (fber != 0.0)
256 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
257 else
258 flog_ber = -8.0;//when fber=0 means u16SQI=100
259 #endif
260
261 //printf("dan fber = %f\n", fber);
262 //printf("dan flog_ber = %f\n", flog_ber);
263 // Part 2: transfer ber value to u16SQI value.
264 if (flog_ber <= ( - 7.0))
265 {
266 u16SQI = 100; //*quality = 100;
267 }
268 else if (flog_ber < -6.0)
269 {
270 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
271 }
272 else if (flog_ber < -5.5)
273 {
274 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
275 }
276 else if (flog_ber < -5.0)
277 {
278 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
279 }
280 else if (flog_ber < -4.5)
281 {
282 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
283 }
284 else if (flog_ber < -4.0)
285 {
286 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
287 }
288 else if (flog_ber < -3.5)
289 {
290 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
291 }
292 else if (flog_ber < -3.0)
293 {
294 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
295 }
296 else if (flog_ber < -2.5)
297 {
298 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
299 }
300 else if (flog_ber < -2.0)
301 {
302 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
303 }
304 else
305 {
306 u16SQI = 0;
307 }
308
309 return u16SQI;
310 }
311 #endif
312
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)313 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
314 {
315 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
316 }
317
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)318 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
319 {
320 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
321 }
322
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)323 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
324 {
325 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
326 }
327
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)328 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
329 {
330 MS_U8 u8CheckCount;
331 MS_U8 u8CheckFlag = 0xFF;
332 MS_U32 u32MBRegBase = MBRegBase;
333
334 if (u8DMD_ISDBT_DMD_ID == 0)
335 u32MBRegBase = MBRegBase;
336 else if (u8DMD_ISDBT_DMD_ID == 1)
337 u32MBRegBase = MBRegBase_DMD1;
338
339 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
340 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
341 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
342 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
343
344 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
345 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
346
347 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
348 {
349 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
350 if ((u8CheckFlag&0x01)==0)
351 break;
352 MsOS_DelayTask(1);
353 }
354
355 if (u8CheckFlag&0x01)
356 {
357 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
358 return FALSE;
359 }
360
361 return TRUE;
362 }
363
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)364 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
365 {
366 MS_U8 u8CheckCount;
367 MS_U8 u8CheckFlag = 0xFF;
368 MS_U32 u32MBRegBase = MBRegBase;
369
370 if (u8DMD_ISDBT_DMD_ID == 0)
371 u32MBRegBase = MBRegBase;
372 else if (u8DMD_ISDBT_DMD_ID == 1)
373 u32MBRegBase = MBRegBase_DMD1;
374
375 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
376 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
377 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
378
379 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
380 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
381
382 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
383 {
384 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
385 if ((u8CheckFlag&0x02)==0)
386 {
387 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
388 break;
389 }
390 MsOS_DelayTask(1);
391 }
392
393 if (u8CheckFlag&0x02)
394 {
395 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
396 return FALSE;
397 }
398
399 return TRUE;
400 }
401
402
403
404 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)405 static void _HAL_INTERN_ISDBT_InitClk(void)
406 {
407 printf("--------------DMD_ISDBT_CHIP_EULER--------------\n");
408
409 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
410
411 // Init by HKMCU
412 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
413 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
414 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
415 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
416 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
417 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
418 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
419
420 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
421 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
422 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
423 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
424 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
425 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
426 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
427 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
428 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
429 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
430 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
431 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
432 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
433 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
434 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
435 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
436 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
437 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
438 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
439 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
440 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
441 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
442 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
443
444 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
445 }
446 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)447 static void _HAL_INTERN_ISDBT_InitClk(void)
448 {
449 MS_U8 u8Val = 0;
450
451 printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n");
452
453 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
454
455 // Init by HKMCU
456 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
457 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
458 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
459 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
460 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
461 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
462 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
463 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
464 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
465
466 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
467 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
468 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
469 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
470 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
472 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
473 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
475 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
483 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
484 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
485 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
489 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
490
491 u8Val = _HAL_DMD_RIU_ReadByte(0x1006F5);
492 _HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
493
494 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
495 }
496 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)497 static void _HAL_INTERN_ISDBT_InitClk(void)
498 {
499 printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n");
500
501 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
502
503 // Init by HKMCU
504 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
505 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
506 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
507 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
508 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
509 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
510 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
511
512 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
513 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
514 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
515 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
516 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
517 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
519 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
520 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
521 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
522 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
523 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
530 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
533 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
534 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
535
536 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
537 }
538 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)539 static void _HAL_INTERN_ISDBT_InitClk(void)
540 {
541 MS_U8 u8Val = 0;
542
543 printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n");
544
545 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
546
547 // Init by HKMCU
548 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
549 u8Val &= ~0x01;
550 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
551
552 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
553 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
554 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
555 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
556 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
557 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
558 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
559 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
560 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
561
562 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
563 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
564 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
565 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
566 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
567 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
568 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
569 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
570 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
571 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
573 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
574 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
575 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
576 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
579 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
581 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
582 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
583 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
584 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
585 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
586
587 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
588 }
589 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)590 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
591 {
592 MS_U8 u8Val = 0;
593
594 printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n");
595
596 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
597
598 // Init by HKMCU
599 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
600 u8Val &= ~0x01;
601 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
602
603 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
604 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
605 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
606 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
607 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
608 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
609 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
610 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
611 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
612
613 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
614 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
615 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
616 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
617 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
618 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
619 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
620 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
624 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
625 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
626 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
627 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
630 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
632 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
633 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
634 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
635 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
636 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
637
638 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
639 }
640 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)641 static void _HAL_INTERN_ISDBT_InitClk(void)
642 {
643 MS_U8 u8Val = 0;
644
645 printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n");
646
647 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
648
649 // Init by HKMCU
650 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
651 u8Val &= ~0x01;
652 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
653
654 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
655 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
656 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
657 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
658 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
659 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
660 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
661 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
662
663 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
666 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
667 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
671 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
673 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
674 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
675 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
676 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
677 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
678 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
679 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
680 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
682 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
683 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
684 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
685 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
686 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
687 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
688 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
689 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
690 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
691
692 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
693 }
694 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)695 static void _HAL_INTERN_ISDBT_InitClk(void)
696 {
697 printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n");
698
699 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
700
701 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
702 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
703 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
704 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
705 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
706 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
707 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
708 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
709
710 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
711 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
712 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
713 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
716 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
717 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
719 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
720 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
721 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
723 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
724 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
725 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
727 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
732 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
733 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
734 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
735 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
736 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
737 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
738
739 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
740 }
741 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)742 static void _HAL_INTERN_ISDBT_InitClk(void)
743 {
744 printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n");
745
746 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
747
748 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
749 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
750 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
751 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
752 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
753 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
754 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
755 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
756 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
757
758 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
759 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
760 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
761 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
762 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
763 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
764 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
765 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
768 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
769 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
771 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
772 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
773 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
774 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
775 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
776 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
777 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
779 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
780 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
781 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
782 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
783 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
784 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
785 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
786 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
787 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
788 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
789 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
790 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
791 _HAL_DMD_RIU_WriteByte(0x112091, 0x46);
792 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
793
794 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
795 }
796 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN)
_HAL_INTERN_ISDBT_InitClk(void)797 static void _HAL_INTERN_ISDBT_InitClk(void)
798 {
799 printf("--------------DMD_ISDBT_CHIP_MANHATTAN--------------\n");
800
801 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
802
803 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
804 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
805 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
806 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
807 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
809 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
810 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
811 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
812
813 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
814 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
815 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
816 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
818 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
819 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
822 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
823 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
824 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
828 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
829 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
830 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
831 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
832 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
833 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
834 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
835 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
836 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
837 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
838 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
839 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
840 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
841 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
842 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
843 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
844 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
845 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
846 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
847 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
848 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
849 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
850 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
851 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
852 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
853 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
854
855 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
856 }
857 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
_HAL_INTERN_ISDBT_InitClk(void)858 static void _HAL_INTERN_ISDBT_InitClk(void)
859 {
860 printf("--------------DMD_ISDBT_CHIP_MESSI--------------\n");
861
862 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
863
864 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
865 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
866 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
867 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
868 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
869 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
870 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
871 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
872 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
873
874 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
875 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
876 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
877 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
879 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
880 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
881 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
882 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
883 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
884 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
885 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
886 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
887 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
888 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
889 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
890 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
891 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
892 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
893 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
894 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
895 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
896 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
897 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
898 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
899 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
900 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
901 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
902 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
903 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
904 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
905 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x0C);
906 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
907 _HAL_DMD_RIU_WriteByte(0x111f51, 0x48);
908 _HAL_DMD_RIU_WriteByte(0x111f50, 0x44);
909 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
910 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
911 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
912 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
913 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
914 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
915 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
916 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
917 _HAL_DMD_RIU_WriteByte(0x111f89, 0x44);
918 _HAL_DMD_RIU_WriteByte(0x111f88, 0x44);
919 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
920 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x44);
921 _HAL_DMD_RIU_WriteByte(0x111f8d, 0x18);
922 _HAL_DMD_RIU_WriteByte(0x111f8c, 0x44);
923 _HAL_DMD_RIU_WriteByte(0x111f8f, 0x00);
924 _HAL_DMD_RIU_WriteByte(0x111f8e, 0x44);
925
926 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
927 }
928
929 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MASERATI)
_HAL_INTERN_ISDBT_InitClk(void)930 static void _HAL_INTERN_ISDBT_InitClk(void)
931 {
932 printf("--------------DMD_ISDBT_CHIP_MASERATI--------------\n");
933
934 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
935
936 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x10331e, 0x1c);
938 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
939 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
940 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
941 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
942 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
943 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
944 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
945 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
946
947 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
948 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
949 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
950 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
951 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
952 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
953 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
954 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
955 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
956 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
957 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
958 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
959 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
960 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
961 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
962 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
963 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
964 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
965 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
966 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
967 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
968 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
969 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
970 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
971 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
972 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
973 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
974 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
975 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
976 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
977 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
978 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
979 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
980 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
981 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
982 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
983 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
984 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
985 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x14);
986 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x14);
987 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
988 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
989 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
990 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
991 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
992 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
993 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
994 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
995 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
996 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
997 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
998 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
999 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1000 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1001 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1002 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1003 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1004 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1005 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1006 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1007
1008 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1009 }
1010 #else
_HAL_INTERN_ISDBT_InitClk(void)1011 static void _HAL_INTERN_ISDBT_InitClk(void)
1012 {
1013 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
1014 }
1015 #endif
1016
_HAL_INTERN_ISDBT_Ready(void)1017 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
1018 {
1019 MS_U8 udata = 0x00;
1020
1021 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1022
1023 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1024 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1025
1026 MsOS_DelayTask(1);
1027
1028 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1029
1030 if (udata) return FALSE;
1031
1032 return TRUE;
1033 }
1034
_HAL_INTERN_ISDBT_Download(void)1035 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
1036 {
1037 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
1038
1039 MS_U8 udata = 0x00;
1040 MS_U16 i = 0;
1041 MS_U16 fail_cnt = 0;
1042 MS_U8 u8TmpData;
1043 MS_U16 u16AddressOffset;
1044 const MS_U8 *ISDBT_table;
1045 MS_U16 u16Lib_size;
1046
1047 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
1048 {
1049 if (_HAL_INTERN_ISDBT_Ready())
1050 {
1051 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1052 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1053 MsOS_DelayTask(20);
1054 return TRUE;
1055 }
1056 }
1057
1058 ISDBT_table = &INTERN_ISDBT_table[0];
1059 u16Lib_size = sizeof(INTERN_ISDBT_table);
1060
1061 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1062 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1063
1064 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1065
1066 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1067 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1068 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1069 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1070
1071 //// Load code thru VDMCU_IF ////
1072 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
1073
1074 for (i = 0; i < u16Lib_size; i++)
1075 {
1076 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
1077 }
1078
1079 //// Content verification ////
1080 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
1081
1082 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1083 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1084
1085 for (i = 0; i < u16Lib_size; i++)
1086 {
1087 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1088
1089 if (udata != ISDBT_table[i])
1090 {
1091 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
1092 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
1093 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
1094
1095 if (fail_cnt++ > 10)
1096 {
1097 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
1098 return FALSE;
1099 }
1100 }
1101 }
1102
1103 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
1104
1105 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1106 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1107
1108 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
1109 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1110 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
1111 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1112 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
1113 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1114 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
1115 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1116 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
1117 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1118 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
1119 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1120 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
1121 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1122 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
1123 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1124 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
1125 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1126
1127 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1128 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1129
1130 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1131
1132 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1133 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1134
1135 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
1136
1137 MsOS_DelayTask(20);
1138
1139 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
1140
1141 return TRUE;
1142 }
1143
_HAL_INTERN_ISDBT_FWVERSION(void)1144 static void _HAL_INTERN_ISDBT_FWVERSION(void)
1145 {
1146 MS_U8 data1 = 0;
1147 MS_U8 data2 = 0;
1148 MS_U8 data3 = 0;
1149
1150 _MBX_ReadReg(0x20C4, &data1);
1151 _MBX_ReadReg(0x20C5, &data2);
1152 _MBX_ReadReg(0x20C6, &data3);
1153
1154 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1155 }
1156
_HAL_INTERN_ISDBT_Exit(void)1157 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
1158 {
1159 MS_U8 u8CheckCount = 0;
1160
1161 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1162
1163 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1164 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1165
1166 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1167 {
1168 MsOS_DelayTaskUs(10);
1169
1170 if (u8CheckCount++ == 0xFF)
1171 {
1172 printf(">> ISDBT Exit Fail!\n");
1173 return FALSE;
1174 }
1175 }
1176
1177 printf(">> ISDBT Exit Ok!\n");
1178
1179 return TRUE;
1180 }
1181
_HAL_INTERN_ISDBT_SoftReset(void)1182 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
1183 {
1184 MS_U8 u8Data = 0;
1185
1186 //Reset FSM
1187 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1188
1189 while (u8Data!=0x02)
1190 {
1191 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1192 }
1193
1194 return TRUE;
1195 }
1196
_HAL_INTERN_ISDBT_SetACICoef(void)1197 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
1198 {
1199 return TRUE;
1200 }
1201
_HAL_INTERN_ISDBT_SetIsdbtMode(void)1202 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
1203 {
1204 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
1205 return _MBX_WriteReg(0x20C0, 0x04);
1206 }
1207
_HAL_INTERN_ISDBT_SetModeClean(void)1208 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
1209 {
1210 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1211 return _MBX_WriteReg(0x20C0, 0x00);
1212 }
1213
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)1214 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
1215 {
1216 MS_BOOL bCheckPass = FALSE;
1217 MS_U8 u8Data = 0;
1218
1219 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1220
1221 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
1222 bCheckPass = TRUE;
1223
1224 return bCheckPass;
1225 }
1226
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)1227 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
1228 {
1229 MS_BOOL bCheckPass = FALSE;
1230 MS_U8 u8Data = 0;
1231
1232 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1233
1234 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
1235 bCheckPass = TRUE;
1236
1237 return bCheckPass;
1238 }
1239
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)1240 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
1241 {
1242 MS_BOOL bCheckPass = FALSE;
1243 MS_U8 u8Data = 0;
1244
1245 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1246
1247 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
1248 bCheckPass = TRUE;
1249
1250 return bCheckPass;
1251 }
1252
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)1253 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
1254 {
1255 MS_BOOL bCheckPass = FALSE;
1256 MS_U8 u8Data = 0;
1257
1258 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1259
1260 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
1261 bCheckPass = TRUE;
1262
1263 return bCheckPass;
1264 }
1265
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)1266 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
1267 {
1268 MS_BOOL bRet = TRUE;
1269 MS_U8 u8Data = 0;
1270 MS_U8 u8CodeRate = 0;
1271
1272 switch (eLayerIndex)
1273 {
1274 case E_ISDBT_Layer_A:
1275 // [10:8] reg_tmcc_cur_convolution_code_rate_a
1276 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1277 u8CodeRate = u8Data & 0x07;
1278 break;
1279 case E_ISDBT_Layer_B:
1280 // [10:8] reg_tmcc_cur_convolution_code_rate_b
1281 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1282 u8CodeRate = u8Data & 0x07;
1283 break;
1284 case E_ISDBT_Layer_C:
1285 // [10:8] reg_tmcc_cur_convolution_code_rate_c
1286 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1287 u8CodeRate = u8Data & 0x07;
1288 break;
1289 default:
1290 u8CodeRate = 15;
1291 break;
1292 }
1293
1294 switch (u8CodeRate)
1295 {
1296 case 0:
1297 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
1298 break;
1299 case 1:
1300 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
1301 break;
1302 case 2:
1303 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
1304 break;
1305 case 3:
1306 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
1307 break;
1308 case 4:
1309 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
1310 break;
1311 default:
1312 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
1313 break;
1314 }
1315
1316 return bRet;
1317 }
1318
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)1319 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
1320 {
1321 MS_BOOL bRet = TRUE;
1322 MS_U8 u8Data = 0;
1323 MS_U8 u8CP = 0;
1324
1325 // [7:6] reg_mcd_out_cp
1326 // output cp -> 00: 1/4
1327 // 01: 1/8
1328 // 10: 1/16
1329 // 11: 1/32
1330 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1331
1332 u8CP = (u8Data >> 6) & 0x03;
1333
1334 switch (u8CP)
1335 {
1336 case 0:
1337 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
1338 break;
1339 case 1:
1340 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
1341 break;
1342 case 2:
1343 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
1344 break;
1345 case 3:
1346 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
1347 break;
1348 }
1349
1350 return bRet;
1351 }
1352
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)1353 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
1354 {
1355 MS_BOOL bRet = TRUE;
1356 MS_U8 u8Data = 0;
1357 MS_U8 u8Mode = 0;
1358 MS_U8 u8Tdi = 0;
1359
1360 // [5:4] reg_mcd_out_mode
1361 // output mode -> 00: 2k
1362 // 01: 4k
1363 // 10: 8k
1364 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1365
1366 u8Mode = (u8Data >> 4) & 0x03;
1367
1368 switch (eLayerIndex)
1369 {
1370 case E_ISDBT_Layer_A:
1371 // [14:12] reg_tmcc_cur_interleaving_length_a
1372 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1373 u8Tdi = (u8Data >> 4) & 0x07;
1374 break;
1375 case E_ISDBT_Layer_B:
1376 // [14:12] reg_tmcc_cur_interleaving_length_b
1377 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1378 u8Tdi = (u8Data >> 4) & 0x07;
1379 break;
1380 case E_ISDBT_Layer_C:
1381 // [14:12] reg_tmcc_cur_interleaving_length_c
1382 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1383 u8Tdi = (u8Data >> 4) & 0x07;
1384 break;
1385 default:
1386 u8Tdi = 15;
1387 break;
1388 }
1389
1390 // u8Tdi+u8Mode*4
1391 // => 0~3: 2K
1392 // => 4~7: 4K
1393 // => 8~11:8K
1394 switch (u8Tdi+u8Mode*4)
1395 {
1396 case 0:
1397 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
1398 break;
1399 case 1:
1400 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
1401 break;
1402 case 2:
1403 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
1404 break;
1405 case 3:
1406 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
1407 break;
1408 case 4:
1409 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
1410 break;
1411 case 5:
1412 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
1413 break;
1414 case 6:
1415 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
1416 break;
1417 case 7:
1418 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
1419 break;
1420 case 8:
1421 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
1422 break;
1423 case 9:
1424 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
1425 break;
1426 case 10:
1427 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
1428 break;
1429 case 11:
1430 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
1431 break;
1432 default:
1433 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
1434 break;
1435 }
1436
1437 return bRet;
1438 }
1439
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)1440 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
1441 {
1442 MS_BOOL bRet = TRUE;
1443 MS_U8 u8Data = 0;
1444 MS_U8 u8Mode = 0;
1445
1446 // [5:4] reg_mcd_out_mode
1447 // output mode -> 00: 2k
1448 // 01: 4k
1449 // 10: 8k
1450 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1451
1452 u8Mode = (u8Data >> 4) & 0x03;
1453
1454 switch (u8Mode)
1455 {
1456 case 0:
1457 *peIsdbtFFT = E_ISDBT_FFT_2K;
1458 break;
1459 case 1:
1460 *peIsdbtFFT = E_ISDBT_FFT_4K;
1461 break;
1462 case 2:
1463 *peIsdbtFFT = E_ISDBT_FFT_8K;
1464 break;
1465 default:
1466 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
1467 break;
1468 }
1469
1470 return bRet;
1471 }
1472
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)1473 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
1474 {
1475 MS_BOOL bRet = TRUE;
1476 MS_U8 u8Data = 0;
1477 MS_U8 u8QAM = 0;
1478
1479 switch(eLayerIndex)
1480 {
1481 case E_ISDBT_Layer_A:
1482 // [6:4] reg_tmcc_cur_carrier_modulation_a
1483 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
1484 u8QAM = (u8Data >> 4) & 0x07;
1485 break;
1486 case E_ISDBT_Layer_B:
1487 // [6:4] reg_tmcc_cur_carrier_modulation_b
1488 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
1489 u8QAM = (u8Data >> 4) & 0x07;
1490 break;
1491 case E_ISDBT_Layer_C:
1492 // [6:4] reg_tmcc_cur_carrier_modulation_c
1493 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
1494 u8QAM = (u8Data >> 4) & 0x07;
1495 break;
1496 default:
1497 u8QAM = 15;
1498 break;
1499 }
1500
1501 switch(u8QAM)
1502 {
1503 case 0:
1504 *peIsdbtConstellation = E_ISDBT_DQPSK;
1505 break;
1506 case 1:
1507 *peIsdbtConstellation = E_ISDBT_QPSK;
1508 break;
1509 case 2:
1510 *peIsdbtConstellation = E_ISDBT_16QAM;
1511 break;
1512 case 3:
1513 *peIsdbtConstellation = E_ISDBT_64QAM;
1514 break;
1515 default:
1516 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
1517 break;
1518 }
1519
1520 return bRet;
1521 }
1522
_HAL_INTERN_ISDBT_ReadIFAGC(void)1523 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
1524 {
1525 MS_U8 data = 0;
1526
1527 _MBX_ReadReg(0x28FD, &data);
1528
1529 return data;
1530 }
1531
1532 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 * pFFT_Mode,MS_S32 * pTdCfoRegValue,MS_S32 * pFdCfoRegValue,MS_S16 * pIcfoRegValue)1533 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 *pFFT_Mode, MS_S32 *pTdCfoRegValue, MS_S32 *pFdCfoRegValue, MS_S16 *pIcfoRegValue)
1534 #else
1535 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
1536 #endif
1537 {
1538 MS_BOOL bRet = TRUE;
1539 MS_U8 u8Data = 0;
1540 MS_S32 s32TdCfoRegValue = 0;
1541 MS_S32 s32FdCfoRegValue = 0;
1542 MS_S16 s16IcfoRegValue = 0;
1543 #ifndef UTPA2
1544 float fTdCfoFreq = 0.0;
1545 float fICfoFreq = 0.0;
1546 float fFdCfoFreq = 0.0;
1547 #endif
1548
1549 //Get TD CFO
1550 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
1551 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
1552
1553 //read td_freq_error
1554 //Read <29,38>
1555 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
1556 s32TdCfoRegValue = u8Data;
1557 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
1558 s32TdCfoRegValue |= u8Data << 8;
1559 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
1560 s32TdCfoRegValue = u8Data << 16;
1561 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
1562 s32TdCfoRegValue |= u8Data << 24;
1563
1564 if (u8Data >= 0x10)
1565 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
1566
1567 s32TdCfoRegValue >>=4;
1568
1569 //TD_cfo_Hz = RegCfoTd * fb
1570 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
1571 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
1572
1573 #ifndef UTPA2
1574 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
1575 fTdCfoFreq = fTdCfoFreq * 8126980.0;
1576 #endif
1577
1578 //Get FD CFO
1579 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1580 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
1581 //load
1582 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1583 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1584
1585 //read CFO_KI
1586 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
1587 s32FdCfoRegValue = u8Data;
1588 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
1589 s32FdCfoRegValue |= u8Data << 8;
1590 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
1591 s32FdCfoRegValue |= u8Data << 16;
1592 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
1593 s32FdCfoRegValue |= u8Data << 24;
1594
1595 if(u8Data >= 0x01)
1596 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
1597
1598 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1599 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
1600 //load
1601 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1602 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1603
1604 #ifndef UTPA2
1605 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
1606 fFdCfoFreq = fFdCfoFreq * 8126980.0;
1607 #endif
1608
1609 //Get ICFO
1610 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
1611 s16IcfoRegValue = u8Data;
1612 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
1613 s16IcfoRegValue |= u8Data << 8;
1614 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
1615
1616 if(s16IcfoRegValue >= 0x400)
1617 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
1618
1619 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
1620
1621 #ifdef UTPA2
1622 *pFFT_Mode = u8Data;
1623 *pTdCfoRegValue = s32TdCfoRegValue;
1624 *pFdCfoRegValue = s32TdCfoRegValue;
1625 *pIcfoRegValue = s16IcfoRegValue;
1626 #else
1627 if((u8Data & 0x30) == 0x0000) // 2k
1628 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
1629 else if((u8Data & 0x0030) == 0x0010) // 4k
1630 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
1631 else //if(u16data & 0x0030 == 0x0020) // 8k
1632 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
1633
1634 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
1635
1636 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
1637 #endif
1638
1639 return bRet;
1640 }
1641
1642 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)1643 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
1644 #else
1645 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
1646 #endif
1647 {
1648 MS_BOOL bRet = TRUE;
1649 MS_U8 u8Data = 0;
1650 MS_U16 u16BerValue = 0;
1651 MS_U32 u32BerPeriod = 0;
1652
1653 // reg_rd_freezeber
1654 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
1655 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
1656
1657 if (eLayerIndex == E_ISDBT_Layer_A)
1658 {
1659 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
1660 u16BerValue=u8Data;
1661 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
1662 u16BerValue |= (u8Data << 8);
1663 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
1664 u32BerPeriod = (u8Data&0x3F);
1665 u32BerPeriod <<= 16;
1666 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
1667 u32BerPeriod |= u8Data;
1668 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
1669 u32BerPeriod |= (u8Data << 8);
1670 }
1671 else if (eLayerIndex == E_ISDBT_Layer_B)
1672 {
1673 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
1674 u16BerValue=u8Data;
1675 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
1676 u16BerValue |= (u8Data << 8);
1677 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
1678 u32BerPeriod = (u8Data&0x3F);
1679 u32BerPeriod <<= 16;
1680 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
1681 u32BerPeriod |= u8Data;
1682 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
1683 u32BerPeriod |= (u8Data << 8);
1684 }
1685 else if (eLayerIndex == E_ISDBT_Layer_C)
1686 {
1687 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
1688 u16BerValue=u8Data;
1689 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
1690 u16BerValue |= (u8Data << 8);
1691 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
1692 u32BerPeriod = (u8Data&0x003F);
1693 u32BerPeriod <<= 16;
1694 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
1695 u32BerPeriod |= u8Data;
1696 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
1697 u32BerPeriod |= (u8Data << 8);
1698 }
1699 else
1700 {
1701 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
1702 bRet = FALSE;
1703 }
1704
1705 // reg_rd_freezeber
1706 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
1707 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
1708
1709 u32BerPeriod <<= 8; // *256
1710
1711 if(u32BerPeriod == 0) u32BerPeriod = 1;
1712
1713 #ifdef UTPA2
1714 *pBerPeriod = u32BerPeriod;
1715 *pBerValue = u16BerValue;
1716 #else
1717 *pfber = (float)u16BerValue/u32BerPeriod;
1718 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
1719 #endif
1720
1721 return bRet;
1722 }
1723
1724 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)1725 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
1726 #else
1727 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
1728 #endif
1729 {
1730 MS_BOOL bRet = TRUE;
1731 MS_U8 u8Data = 0;
1732 MS_U8 u8FrzData = 0;
1733 MS_U32 u32BerValue = 0;
1734 MS_U16 u16BerPeriod = 0;
1735
1736 // reg_rd_freezeber
1737 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
1738 u8Data = u8FrzData | 0x01;
1739 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
1740
1741 if (eLayerIndex == E_ISDBT_Layer_A)
1742 {
1743 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
1744 u32BerValue = u8Data;
1745 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
1746 u32BerValue |= u8Data << 8;
1747 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
1748 u32BerValue |= u8Data << 16;
1749 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
1750 u32BerValue |= u8Data << 24;
1751
1752 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
1753 u16BerPeriod = u8Data;
1754 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
1755 u16BerPeriod |= u8Data << 8;
1756 }
1757 else if (eLayerIndex == E_ISDBT_Layer_B)
1758 {
1759 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
1760 u32BerValue = u8Data;
1761 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
1762 u32BerValue |= u8Data << 8;
1763 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
1764 u32BerValue |= u8Data << 16;
1765 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
1766 u32BerValue |= u8Data << 24;
1767
1768 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
1769 u16BerPeriod = u8Data;
1770 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
1771 u16BerPeriod |= u8Data << 8;
1772 }
1773 else if (eLayerIndex == E_ISDBT_Layer_C)
1774 {
1775 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
1776 u32BerValue = u8Data;
1777 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
1778 u32BerValue |= u8Data << 8;
1779 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
1780 u32BerValue |= u8Data << 16;
1781 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
1782 u32BerValue |= u8Data << 24;
1783
1784 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
1785 u16BerPeriod = u8Data;
1786 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
1787 u16BerPeriod |= u8Data << 8;
1788 }
1789 else
1790 {
1791 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
1792 bRet = FALSE;
1793 }
1794
1795 // reg_rd_freezeber
1796 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
1797
1798 if(u16BerPeriod == 0) u16BerPeriod = 1;
1799
1800 #ifdef UTPA2
1801 *pBerPeriod = u16BerPeriod;
1802 *pBerValue = u32BerValue;
1803 #else
1804 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
1805 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
1806 #endif
1807 return bRet;
1808 }
1809
1810 #ifndef UTPA2
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)1811 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
1812 {
1813 float fber;
1814 MS_BOOL bRet = TRUE;
1815 EN_ISDBT_Layer eLayerIndex;
1816 MS_U16 u16SQI;
1817
1818 // Tmp solution
1819 eLayerIndex = E_ISDBT_Layer_A;
1820
1821 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
1822 {
1823 //printf("Dan Demod unlock!!!\n");
1824 u16SQI = 0;
1825 }
1826 else
1827 {
1828 // Part 1: get ber value from demod.
1829 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
1830
1831 u16SQI = _CALCULATE_SQI(fber);
1832 }
1833
1834 //printf("dan SQI = %d\n", SQI);
1835 return u16SQI;
1836 }
1837
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)1838 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
1839 {
1840 float fber;
1841 MS_BOOL bRet = TRUE;
1842 EN_ISDBT_Layer eLayerIndex;
1843 MS_U16 u16SQI;
1844
1845 // Tmp solution
1846 eLayerIndex = E_ISDBT_Layer_B;
1847
1848 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
1849 {
1850 //printf("Dan Demod unlock!!!\n");
1851 u16SQI = 0;
1852 }
1853 else
1854 {
1855 // Part 1: get ber value from demod.
1856 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
1857
1858 u16SQI = _CALCULATE_SQI(fber);
1859 }
1860
1861 //printf("dan SQI = %d\n", SQI);
1862 return u16SQI;
1863 }
1864
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)1865 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
1866 {
1867 float fber;
1868 MS_BOOL bRet = TRUE;
1869 EN_ISDBT_Layer eLayerIndex;
1870 MS_U16 u16SQI;
1871
1872 // Tmp solution
1873 eLayerIndex = E_ISDBT_Layer_C;
1874
1875 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
1876 {
1877 //printf("Dan Demod unlock!!!\n");
1878 u16SQI = 0;
1879 }
1880 else
1881 {
1882 // Part 1: get ber value from demod.
1883 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
1884
1885 u16SQI = _CALCULATE_SQI(fber);
1886 }
1887
1888 //printf("dan SQI = %d\n", SQI);
1889 return u16SQI;
1890 }
1891
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)1892 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
1893 {
1894 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
1895 MS_U16 u16SQI;
1896 EN_ISDBT_Layer eLayerIndex;
1897 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
1898
1899 //Get modulation of each layer
1900 eLayerIndex = E_ISDBT_Layer_A;
1901 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
1902 eLayerIndex = E_ISDBT_Layer_B;
1903 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
1904 eLayerIndex = E_ISDBT_Layer_C;
1905 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
1906
1907 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
1908 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
1909 else
1910 s8LayerAValue = -1;
1911
1912 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
1913 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
1914 else
1915 s8LayerBValue = -1;
1916
1917 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
1918 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
1919 else
1920 s8LayerCValue = -1;
1921
1922 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
1923 if (s8LayerAValue >= s8LayerBValue)
1924 {
1925 if (s8LayerCValue >= s8LayerAValue)
1926 {
1927 //Get Layer C u16SQI
1928 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
1929 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
1930 }
1931 else //A>C
1932 {
1933 //Get Layer A u16SQI
1934 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
1935 //printf("dan u16SQI Layer A: %d\n", u16SQI);
1936 }
1937 }
1938 else // B >= A
1939 {
1940 if (s8LayerCValue >= s8LayerBValue)
1941 {
1942 //Get Layer C u16SQI
1943 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
1944 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
1945 }
1946 else //B>C
1947 {
1948 //Get Layer B u16SQI
1949 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
1950 //printf("dan u16SQI Layer B: %d\n", u16SQI);
1951 }
1952 }
1953
1954 return u16SQI;
1955 }
1956 #endif
1957
1958 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetSNR(MS_U32 * pRegSNR,MS_U16 * pRegSnrObsNum)1959 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(MS_U32 *pRegSNR, MS_U16 *pRegSnrObsNum)
1960 #else
1961 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
1962 #endif
1963 {
1964 MS_BOOL bRet = TRUE;
1965 MS_U8 u8Data = 0;
1966 MS_U32 u32RegSNR = 0;
1967 MS_U16 u16RegSnrObsNum = 0;
1968 #ifndef UTPA2
1969 float fSNRAvg = 0.0;
1970 #endif
1971
1972 //set freeze
1973 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1974 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
1975 //load
1976 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1977 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1978
1979 // ==============Average SNR===============//
1980 // [26:0] reg_snr_accu
1981 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
1982 u32RegSNR = u8Data&0x07;
1983 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
1984 u32RegSNR = (u32RegSNR<<8) | u8Data;
1985 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
1986 u32RegSNR = (u32RegSNR<<8) | u8Data;
1987 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
1988 u32RegSNR = (u32RegSNR<<8) | u8Data;
1989
1990 // [12:0] reg_snr_observe_sum_num
1991 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
1992 u16RegSnrObsNum = u8Data&0x1f;
1993 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
1994 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
1995
1996 //release freeze
1997 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1998 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
1999 //load
2000 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2001 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2002
2003 if (u16RegSnrObsNum == 0)
2004 u16RegSnrObsNum = 1;
2005
2006
2007 #ifdef UTPA2
2008 *pRegSNR = u32RegSNR;
2009 *pRegSnrObsNum = u16RegSnrObsNum;
2010 #else
2011 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
2012 if (fSNRAvg == 0) //protect value 0
2013 fSNRAvg = 0.01;
2014
2015 #ifdef MSOS_TYPE_LINUX
2016 *pf_snr = 10.0f*(float)log10f((double)fSNRAvg/2);
2017 #else
2018 *pf_snr = 10.0f*(float)Log10Approx((double)fSNRAvg/2);
2019 #endif
2020 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
2021 #endif
2022
2023 return bRet;
2024 }
2025
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)2026 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
2027 {
2028 MS_U8 bRet = true;
2029 MS_U8 u8Data = 0;
2030 MS_U8 u8FrzData = 0;
2031 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
2032 #if DMD_ISDBT_TBVA_EN
2033 MS_U8 bTbvaBypass = 0;
2034 MS_U8 u8TbvaLayer = 0;
2035 #endif
2036 // Read packet errors of three layers
2037 // OUTER_FUNCTION_ENABLE
2038 // [8] reg_biterr_num_pcktprd_freeze
2039 // Freeze Packet error
2040 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2041 u8Data = u8FrzData | 0x01;
2042 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2043 #if DMD_ISDBT_TBVA_EN
2044 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x10*2, &u8Data);
2045 bTbvaBypass = u8Data & 0x01;
2046 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x11*2, &u8Data);
2047 u8TbvaLayer = u8Data & 0x03;
2048 switch(eLayerIndex)
2049 {
2050 case E_ISDBT_Layer_A:
2051 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2052 if (!bTbvaBypass && u8TbvaLayer == 0)
2053 {
2054 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2055 u16PacketErrA = u8Data << 8;
2056 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2057 u16PacketErrA = u16PacketErrA | u8Data;
2058 *pu16PacketErr = u16PacketErrA;
2059 }
2060 else
2061 {
2062 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2063 u16PacketErrA = u8Data << 8;
2064 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2065 u16PacketErrA = u16PacketErrA | u8Data;
2066 *pu16PacketErr = u16PacketErrA;
2067 }
2068 break;
2069 case E_ISDBT_Layer_B:
2070 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2071 if (!bTbvaBypass && u8TbvaLayer == 1)
2072 {
2073 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2074 u16PacketErrB = u8Data << 8;
2075 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2076 u16PacketErrB = u16PacketErrB | u8Data;
2077 *pu16PacketErr = u16PacketErrB;
2078 }
2079 else
2080 {
2081 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2082 u16PacketErrB = u8Data << 8;
2083 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2084 u16PacketErrB = u16PacketErrB | u8Data;
2085 *pu16PacketErr = u16PacketErrB;
2086 }
2087 break;
2088 case E_ISDBT_Layer_C:
2089 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2090 if (!bTbvaBypass && u8TbvaLayer == 2)
2091 {
2092 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2093 u16PacketErrC = u8Data << 8;
2094 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2095 u16PacketErrC = u16PacketErrC | u8Data;
2096 *pu16PacketErr = u16PacketErrC;
2097 }
2098 else
2099 {
2100 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2101 u16PacketErrC = u8Data << 8;
2102 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2103 u16PacketErrC = u16PacketErrC | u8Data;
2104 *pu16PacketErr = u16PacketErrC;
2105 }
2106 break;
2107 default:
2108 *pu16PacketErr = 0xFFFF;
2109 break;
2110 }
2111 #else
2112 switch(eLayerIndex)
2113 {
2114 case E_ISDBT_Layer_A:
2115 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2116 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2117 u16PacketErrA = u8Data << 8;
2118 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2119 u16PacketErrA = u16PacketErrA | u8Data;
2120 *pu16PacketErr = u16PacketErrA;
2121 break;
2122 case E_ISDBT_Layer_B:
2123 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2124 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2125 u16PacketErrB = u8Data << 8;
2126 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2127 u16PacketErrB = u16PacketErrB | u8Data;
2128 *pu16PacketErr = u16PacketErrB;
2129 break;
2130 case E_ISDBT_Layer_C:
2131 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2132 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2133 u16PacketErrC = u8Data << 8;
2134 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2135 u16PacketErrC = u16PacketErrC | u8Data;
2136 *pu16PacketErr = u16PacketErrC;
2137 break;
2138 default:
2139 *pu16PacketErr = 0xFFFF;
2140 break;
2141 }
2142 #endif
2143 // Unfreeze Packet error
2144 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2145
2146 return bRet;
2147 }
2148
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2149 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2150 {
2151 return _MBX_ReadReg(u16Addr, pu8Data);
2152 }
2153
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2154 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2155 {
2156 return _MBX_WriteReg(u16Addr, u8Data);
2157 }
2158
2159 //-------------------------------------------------------------------------------------------------
2160 // Global Functions
2161 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)2162 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
2163 {
2164 MS_BOOL bResult = TRUE;
2165
2166 switch(eCmd)
2167 {
2168 case DMD_ISDBT_HAL_CMD_Exit:
2169 bResult = _HAL_INTERN_ISDBT_Exit();
2170 break;
2171 case DMD_ISDBT_HAL_CMD_InitClk:
2172 _HAL_INTERN_ISDBT_InitClk();
2173 break;
2174 case DMD_ISDBT_HAL_CMD_Download:
2175 bResult = _HAL_INTERN_ISDBT_Download();
2176 break;
2177 case DMD_ISDBT_HAL_CMD_FWVERSION:
2178 _HAL_INTERN_ISDBT_FWVERSION();
2179 break;
2180 case DMD_ISDBT_HAL_CMD_SoftReset:
2181 bResult = _HAL_INTERN_ISDBT_SoftReset();
2182 break;
2183 case DMD_ISDBT_HAL_CMD_SetACICoef:
2184 bResult = _HAL_INTERN_ISDBT_SetACICoef();
2185 break;
2186 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
2187 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
2188 break;
2189 case DMD_ISDBT_HAL_CMD_SetModeClean:
2190 bResult = _HAL_INTERN_ISDBT_SetModeClean();
2191 break;
2192 case DMD_ISDBT_HAL_CMD_Active:
2193 break;
2194 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
2195 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
2196 break;
2197 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
2198 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
2199 break;
2200 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
2201 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
2202 break;
2203 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
2204 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
2205 break;
2206 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
2207 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
2208 break;
2209 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
2210 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
2211 break;
2212 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
2213 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
2214 break;
2215 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
2216 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
2217 break;
2218 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
2219 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
2220 break;
2221 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
2222 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
2223 break;
2224 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
2225 #ifdef UTPA2
2226 bResult = _HAL_INTERN_ISDBT_GetFreqOffset(&((*((DMD_ISDBT_CFO_DATA*)pArgs)).FFT_Mode), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).TdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).FdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).IcfoRegValue));
2227 #else
2228 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
2229 #endif
2230 break;
2231 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
2232 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
2233 #ifndef UTPA2
2234 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2235 #endif
2236 break;
2237 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
2238 #ifndef UTPA2
2239 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2240 #endif
2241 break;
2242 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
2243 #ifndef UTPA2
2244 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2245 #endif
2246 break;
2247 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
2248 #ifndef UTPA2
2249 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
2250 #endif
2251 break;
2252 case DMD_ISDBT_HAL_CMD_GetSNR:
2253 #ifdef UTPA2
2254 bResult = _HAL_INTERN_ISDBT_GetSNR(&((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSNR), &((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSnrObsNum));
2255 #else
2256 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
2257 #endif
2258 break;
2259 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
2260 #ifdef UTPA2
2261 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2262 #else
2263 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2264 #endif
2265 break;
2266 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
2267 #ifdef UTPA2
2268 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2269 #else
2270 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2271 #endif
2272 break;
2273 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
2274 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
2275 break;
2276 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
2277 break;
2278 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
2279 break;
2280 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
2281 break;
2282 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
2283 break;
2284 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
2285 break;
2286 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
2287 break;
2288 case DMD_ISDBT_HAL_CMD_GET_REG:
2289 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
2290 break;
2291 case DMD_ISDBT_HAL_CMD_SET_REG:
2292 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
2293 break;
2294 default:
2295 break;
2296 }
2297
2298 return bResult;
2299 }
2300
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)2301 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
2302 {
2303 return TRUE;
2304 }
2305
2306