1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_DTMB.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_DTMB_CHIP_NIKON 0x00
112 #define DMD_DTMB_CHIP_NASA 0x01
113 #define DMD_DTMB_CHIP_MADISON 0x02
114 #define DMD_DTMB_CHIP_MONACO 0x03
115 #define DMD_DTMB_CHIP_MUJI 0x04
116 #define DMD_DTMB_CHIP_MONET 0x05
117 #define DMD_DTMB_CHIP_MANHATTAN 0x06
118 #define DMD_DTMB_CHIP_MESSI 0x07
119 #define DMD_DTMB_CHIP_MASERATI 0x08
120 #define DMD_DTMB_CHIP_MACAN 0x09
121 #define DMD_DTMB_CHIP_MAXIM 0x0A
122
123 #if defined(CHIP_NIKON)
124 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
125 #elif defined(CHIP_NASA)
126 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
127 #elif defined(CHIP_MADISON)
128 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
129 #elif defined(CHIP_MONACO)
130 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
131 #elif defined(CHIP_MUJI)
132 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
133 #elif defined(CHIP_MONET)
134 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
135 #elif defined(CHIP_MANHATTAN)
136 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
137 #elif defined(CHIP_MESSI)
138 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
139 #elif defined(CHIP_MASERATI)
140 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MASERATI
141 #elif defined(CHIP_MACAN)
142 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MACAN
143 #elif defined(CHIP_MAXIM)
144 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MAXIM
145 #else
146 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
147 #endif
148
149 //-------------------------------------------------------------------------------------------------
150 // Local Defines
151 //-------------------------------------------------------------------------------------------------
152
153 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr) ) )
154 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr), val) )
155
156 #define HAL_INTERN_DTMB_DBINFO(y) //y
157
158 #define MBRegBase 0x112600
159 #define DMDMcuBase 0x103480
160
161 #define DTMB_REG_BASE 0x2600
162
163 #define DTMB_ACI_COEF_SIZE 112
164
165 #define DMD_DTMB_CHIP_ID_NASA 0x6E
166 #define DMD_DTMB_CHIP_ID_WALTZ 0x9C
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Variables
170 //-------------------------------------------------------------------------------------------------
171
172 const MS_U8 INTERN_DTMB_table[] = {
173 #include "DMD_INTERN_DTMB.dat"
174 };
175
176 const MS_U8 INTERN_DTMB_6M_table[] = {
177 #include "DMD_INTERN_DTMB_6M.dat"
178 };
179
180 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
181 const MS_U8 INTERN_DTMB_table_Waltz[] = {
182 #include "DMD_INTERN_DTMB_Waltz.dat"
183 };
184
185 const MS_U8 INTERN_DTMB_6M_table_Waltz[] = {
186 #include "DMD_INTERN_DTMB_6M_Waltz.dat"
187 };
188 #endif
189
190 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
191 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
192 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
193 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
194 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
195
196 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
197 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
198 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
199 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
200 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
201
202 //-------------------------------------------------------------------------------------------------
203 // Global Variables
204 //-------------------------------------------------------------------------------------------------
205
206 extern MS_U8 u8DMD_DTMB_DMD_ID;
207
208 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
209
210 //-------------------------------------------------------------------------------------------------
211 // Local Functions
212 //-------------------------------------------------------------------------------------------------
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)213 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
214 {
215 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
216 }
217
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)218 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
219 {
220 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
221 }
222
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)223 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
224 {
225 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
226 }
227
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)228 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
229 {
230 MS_U8 u8CheckCount;
231 MS_U8 u8CheckFlag;
232
233 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
234 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
235 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
236 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
237
238 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
239 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
240
241 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
242 {
243 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
244 if ((u8CheckFlag&0x01)==0)
245 break;
246 MsOS_DelayTask(1);
247 }
248
249 if (u8CheckFlag&0x01)
250 {
251 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
252 return FALSE;
253 }
254
255 return TRUE;
256 }
257
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)258 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
259 {
260 MS_U8 u8CheckCount;
261 MS_U8 u8CheckFlag;
262
263 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
264 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
265 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
266
267 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
268 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
269
270 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
271 {
272 u8CheckFlag = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
273 if ((u8CheckFlag&0x02)==0)
274 {
275 *u8Data = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
276 break;
277 }
278 MsOS_DelayTask(1);
279 }
280
281 if (u8CheckFlag&0x02)
282 {
283 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
284 return FALSE;
285 }
286
287 return TRUE;
288 }
289
290 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)291 static void _HAL_INTERN_DTMB_InitClk(void)
292 {
293 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_NIKON--------------\n"));
294
295 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
296
297 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
298 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
299 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
300 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
301 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
302 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
303 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
304 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
305
306 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
307 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
308 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
309 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
310 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
311 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
312 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
313 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
314 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
315 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
316 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
317 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
318 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
319 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
320 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
321 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
322 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
323 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
324 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
325 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
326 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
327 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
328 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
329 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
330 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
331 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
332 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
333 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
334 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
335
336 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
337 }
338 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)339 static void _HAL_INTERN_DTMB_InitClk(void)
340 {
341 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
342
343 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
344 {
345 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_WALTZ--------------\n"));
346
347 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
348
349 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
350 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
351
352 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
353 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
354
355 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
356 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
357 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
358 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
359
360 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
361 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
362
363 _HAL_DMD_RIU_WriteByte(0x111f49, 0xcc);
364 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
365
366 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
367 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
368 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
369 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
370 _HAL_DMD_RIU_WriteByte(0x111f75, 0x00);
371 _HAL_DMD_RIU_WriteByte(0x111f74, 0x00);
372 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
373 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
374
375 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
376 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
377 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
378 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
379 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
380 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
381 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
382 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
383
384 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
385 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
386 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x00);
387 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x00);
388 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
389 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
390
391 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
392 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
393
394 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00);
395 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
396
397 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
398 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
399
400 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
401 }
402 else
403 {
404 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_NASA--------------\n"));
405
406 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
407
408 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
409 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
410 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
411 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
412 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
413 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
414 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
415 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
416
417 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
418 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
419 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
420 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
421 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
422 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
423 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
424 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
425 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
426 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
427 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
428 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
429 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
430 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
431 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
432 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
433 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
434 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
435 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
436 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
437 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
438 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
439 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
440 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
441 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
442 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
443 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
444 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
445 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
446
447 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
448 }
449 }
450 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)451 static void _HAL_INTERN_DTMB_InitClk(void)
452 {
453 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MADISON--------------\n"));
454
455 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
456
457 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
458 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
459 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
460 _HAL_DMD_RIU_WriteByte(0x103300, 0x14);
461 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
462 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
463 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
464 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
465
466 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
467 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
468
469 //carl
470 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
472 _HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
473 _HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
474
475 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
482 _HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
483
484 //carl
485 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
486 _HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
487
488 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
489 _HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
490 _HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
492 _HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
493 _HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
494 _HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
495 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
496 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
497 _HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
498 _HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
499 _HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
500 _HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
501 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
502 _HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
503 _HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
504 _HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
505 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
506 _HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
507
508 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
509 }
510 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)511 static void _HAL_INTERN_DTMB_InitClk(void)
512 {
513 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MONACO--------------\n"));
514
515 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
516
517 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
519
520 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
521 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
522
523 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
527
528 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
530
531 //carl
532 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
533 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
534
535 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
536 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
537 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
539 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
540 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
541 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
542 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
543 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
544 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
545
546 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
547 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
548 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
549 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
550
551 //carl
552 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
553 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
554 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
555 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
556
557 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
558 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
559
560 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
561
562 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
563 }
564 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)565 static void _HAL_INTERN_DTMB_InitClk(void)
566 {
567 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MUJI--------------\n"));
568
569 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
570
571 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
573
574 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
575 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
576
577 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
581 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
582 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
583
584 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
585 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
586
587 //carl
588 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
589 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
590
591 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
592 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
593 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
594 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
595 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
596 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
597 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
598 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
599 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
600 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
601
602 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
603 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
604 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
605 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
606
607 //carl
608 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
609 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
610 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
611 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
612
613 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
614 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
615
616 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
617
618 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
619 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
620
621 _HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
622 _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
623
624 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
625 }
626 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)627 static void _HAL_INTERN_DTMB_InitClk(void)
628 {
629 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MONET--------------\n"));
630
631 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
632
633 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
634 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
635
636 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
637 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
638
639 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
640 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
641 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
642 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
643 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
644 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
645
646 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
647 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
648
649 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
650 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
651
652 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
653 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
654 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
655 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
656
657 _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
658 _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
659
660 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
661 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
662 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
663 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
666
667 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
671
672 //carl
673 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
674 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
675
676 _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
677 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
678
679
680 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
682
683 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
684 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
685
686 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
687 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
688
689 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
690 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
691
692 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
693 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
694
695 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
696 }
697 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)698 static void _HAL_INTERN_DTMB_InitClk(void)
699 {
700 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n"));
701
702 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
703
704 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
705 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
706
707 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
708 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
709
710 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
711 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
712 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
713 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
715 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
716
717 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
719
720 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
721 _HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
722
723 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
724 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
725 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
727
728 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
729 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
730
731 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
732 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
733 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
735 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
736 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
737
738 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
739 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
740 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
741 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
742
743 //carl
744 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
745 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
746
747 // _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
748 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
749
750
751 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
752 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
753
754 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
755 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
756
757 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
758 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
759
760 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
761 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
762
763 _HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
764 _HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
765
766 _HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
767 _HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
768
769 _HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
770 _HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
771
772 _HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
773 _HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
774
775 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
776 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
777
778 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
779 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
780
781
782 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
783 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
784
785 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
786 }
787 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI)
_HAL_INTERN_DTMB_InitClk(void)788 static void _HAL_INTERN_DTMB_InitClk(void)
789 {
790 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MESSI--------------\n"));
791
792 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
793
794 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
795 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
796
797 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
798 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
799
800 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
803 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
804 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
805 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
806
807 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
809
810 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
811 //_HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
812 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
813
814 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
815 _HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
816 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
818
819 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
820 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
821
822 _HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
823 _HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
824 _HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
828
829 _HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
830 _HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
831 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
832 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
833
834 //carl
835 _HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
836 _HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
837
838 // _HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
839 _HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
840
841
842 _HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
843 _HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
844
845 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
846 _HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
847
848 _HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
849 _HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
850
851 _HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
852 _HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
853
854 _HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
855 _HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
856
857 _HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
858 _HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
859
860 _HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
861 _HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
862
863 _HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
864 _HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
865
866 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
867 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
868
869 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
870 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
871
872
873 // _HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
874 // _HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
875
876 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
877 }
878
879 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM)
_HAL_INTERN_DTMB_InitClk(void)880 static void _HAL_INTERN_DTMB_InitClk(void)
881 {
882 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MAXIM--------------\n"));
883
884 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
885
886
887 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01);//luffy for ADC Sync Flow
888 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01);//luffy for ADC Sync Flow
889
890 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
891 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
892
893 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
894 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
895
896 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
897 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
898
899 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00);//luffy for ADC Sync Flow
900 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00);//luffy for ADC Sync Flow
901
902 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
903 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
904
905 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
906 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
907
908 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
909 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
910
911 _HAL_DMD_RIU_WriteByte(0x103321, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
912 _HAL_DMD_RIU_WriteByte(0x103320, 0x00);//luffy for ADC Sync Flow//VT :maxim adds
913
914 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00);//luffy for ADC Sync Flow
915
916 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
917 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
918
919 _HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
920 _HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
921
922 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
923 _HAL_DMD_RIU_WriteByte(0x152922, 0x14);
924
925 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
926 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
927
928 _HAL_DMD_RIU_WriteByte(0x152973, 0x00);
929 _HAL_DMD_RIU_WriteByte(0x152972, 0x00);
930
931 _HAL_DMD_RIU_WriteByte(0x152975, 0x00);
932 _HAL_DMD_RIU_WriteByte(0x152974, 0x00);
933
934 _HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
935 _HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
936
937 _HAL_DMD_RIU_WriteByte(0x152961, 0x00);
938 _HAL_DMD_RIU_WriteByte(0x152960, 0x00);
939
940 _HAL_DMD_RIU_WriteByte(0x152963, 0x00);
941 _HAL_DMD_RIU_WriteByte(0x152962, 0x00);
942
943 _HAL_DMD_RIU_WriteByte(0x152965, 0x00);
944 _HAL_DMD_RIU_WriteByte(0x152964, 0x00);
945
946 _HAL_DMD_RIU_WriteByte(0x152969, 0x00);
947 _HAL_DMD_RIU_WriteByte(0x152968, 0x00);
948
949 _HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
950 _HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
951
952 _HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
953
954 _HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
955 _HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
956
957 _HAL_DMD_RIU_WriteByte(0x152971, 0x00);
958 _HAL_DMD_RIU_WriteByte(0x152970, 0x04);
959
960 _HAL_DMD_RIU_WriteByte(0x152979, 0x00);
961 _HAL_DMD_RIU_WriteByte(0x152978, 0x00);
962
963 _HAL_DMD_RIU_WriteByte(0x152951, 0x04);
964 _HAL_DMD_RIU_WriteByte(0x152950, 0x00);
965
966 _HAL_DMD_RIU_WriteByte(0x152981, 0x88);
967 _HAL_DMD_RIU_WriteByte(0x152980, 0x88);
968
969 _HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
970 _HAL_DMD_RIU_WriteByte(0x152982, 0x88);
971
972 _HAL_DMD_RIU_WriteByte(0x152985, 0x88);
973 _HAL_DMD_RIU_WriteByte(0x152984, 0x88);
974
975 _HAL_DMD_RIU_WriteByte(0x152987, 0x08);
976 _HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
977
978 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
979 _HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
980
981 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
982 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
983
984 _HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
985 _HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
986
987 _HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
988 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
989
990 _HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
991 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
992
993 _HAL_DMD_RIU_WriteByte(0x152993, 0x11);
994 _HAL_DMD_RIU_WriteByte(0x152992, 0x18);
995
996 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
997 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
998
999 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1000 _HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1001
1002 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1003 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1004
1005 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1006 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1007
1008 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1009 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1010
1011 _HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1012
1013 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1014 }
1015
1016 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
_HAL_INTERN_DTMB_InitClk(void)1017 static void _HAL_INTERN_DTMB_InitClk(void)
1018 {
1019 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MASERATI_MACAN--------------\n"));
1020
1021 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1022
1023 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1024
1025 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1026 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1027
1028 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
1029 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1030
1031 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1032 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1033
1034 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1035 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1036
1037 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1038 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1039
1040 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1041 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1042
1043 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1044 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1045
1046 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1047
1048 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1049 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1050
1051 _HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
1052 _HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
1053
1054 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
1055 _HAL_DMD_RIU_WriteByte(0x152922, 0x14);
1056
1057 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1058 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
1059
1060 _HAL_DMD_RIU_WriteByte(0x152973, 0x00);
1061 _HAL_DMD_RIU_WriteByte(0x152972, 0x00);
1062
1063 _HAL_DMD_RIU_WriteByte(0x152975, 0x00);
1064 _HAL_DMD_RIU_WriteByte(0x152974, 0x00);
1065
1066 _HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
1067 _HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
1068
1069 _HAL_DMD_RIU_WriteByte(0x152961, 0x00);
1070 _HAL_DMD_RIU_WriteByte(0x152960, 0x00);
1071
1072 _HAL_DMD_RIU_WriteByte(0x152963, 0x00);
1073 _HAL_DMD_RIU_WriteByte(0x152962, 0x00);
1074
1075 _HAL_DMD_RIU_WriteByte(0x152965, 0x00);
1076 _HAL_DMD_RIU_WriteByte(0x152964, 0x00);
1077
1078 _HAL_DMD_RIU_WriteByte(0x152969, 0x00);
1079 _HAL_DMD_RIU_WriteByte(0x152968, 0x00);
1080
1081 _HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
1082 _HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
1083
1084 _HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
1085
1086 _HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
1087 _HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
1088
1089 _HAL_DMD_RIU_WriteByte(0x152971, 0x00);
1090 _HAL_DMD_RIU_WriteByte(0x152970, 0x04);
1091
1092 _HAL_DMD_RIU_WriteByte(0x152979, 0x00);
1093 _HAL_DMD_RIU_WriteByte(0x152978, 0x00);
1094
1095 _HAL_DMD_RIU_WriteByte(0x152951, 0x04);
1096 _HAL_DMD_RIU_WriteByte(0x152950, 0x00);
1097
1098 _HAL_DMD_RIU_WriteByte(0x152981, 0x88);
1099 _HAL_DMD_RIU_WriteByte(0x152980, 0x88);
1100
1101 _HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
1102 _HAL_DMD_RIU_WriteByte(0x152982, 0x88);
1103
1104 _HAL_DMD_RIU_WriteByte(0x152985, 0x88);
1105 _HAL_DMD_RIU_WriteByte(0x152984, 0x88);
1106
1107 _HAL_DMD_RIU_WriteByte(0x152987, 0x08);
1108 _HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
1109
1110 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
1111 _HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
1112
1113 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
1114 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
1115
1116 _HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
1117 _HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
1118
1119 _HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
1120 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
1121
1122 _HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
1123 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
1124
1125 _HAL_DMD_RIU_WriteByte(0x152993, 0x11);
1126 _HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1127
1128 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1129 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1130
1131 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1132 _HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1133
1134 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1135 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1136
1137 _HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1138 _HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1139
1140 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1141 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1142
1143 _HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1144
1145 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1146 }
1147 #else
_HAL_INTERN_DTMB_InitClk(void)1148 static void _HAL_INTERN_DTMB_InitClk(void)
1149 {
1150 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
1151 }
1152 #endif
1153
_HAL_INTERN_DTMB_Ready(void)1154 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
1155 {
1156 MS_U8 udata = 0x00;
1157
1158 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1159
1160 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1161 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1162
1163 MsOS_DelayTask(1);
1164
1165 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1166
1167 if (udata) return FALSE;
1168
1169 return TRUE;
1170 }
1171
_HAL_INTERN_DTMB_Download(void)1172 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
1173 {
1174 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1175
1176 MS_U8 udata = 0x00;
1177 MS_U16 i = 0;
1178 MS_U16 fail_cnt = 0;
1179 MS_U8 u8TmpData;
1180 MS_U16 u16AddressOffset;
1181 const MS_U8 *DTMB_table;
1182 MS_U16 u16Lib_size;
1183
1184 if (pRes->sDMD_DTMB_PriData.bDownloaded)
1185 {
1186 if (_HAL_INTERN_DTMB_Ready())
1187 {
1188 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1189 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1190 MsOS_DelayTask(20);
1191 return TRUE;
1192 }
1193 }
1194
1195 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1196 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1197 {
1198 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1199 {
1200 DTMB_table = &INTERN_DTMB_6M_table_Waltz[0];
1201 u16Lib_size = sizeof(INTERN_DTMB_6M_table_Waltz);
1202 }
1203 else
1204 {
1205 DTMB_table = &INTERN_DTMB_table_Waltz[0];
1206 u16Lib_size = sizeof(INTERN_DTMB_table_Waltz);
1207 }
1208 }
1209 else
1210 {
1211 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1212 {
1213 DTMB_table = &INTERN_DTMB_6M_table[0];
1214 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1215 }
1216 else
1217 {
1218 DTMB_table = &INTERN_DTMB_table[0];
1219 u16Lib_size = sizeof(INTERN_DTMB_table);
1220 }
1221 }
1222 #else
1223 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1224 {
1225 DTMB_table = &INTERN_DTMB_6M_table[0];
1226 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1227 }
1228 else
1229 {
1230 DTMB_table = &INTERN_DTMB_table[0];
1231 u16Lib_size = sizeof(INTERN_DTMB_table);
1232 }
1233 #endif
1234
1235 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1236 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1237
1238 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1239
1240 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1241 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1242 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1243 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1244
1245 //// Load code thru VDMCU_IF ////
1246 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
1247
1248 for (i = 0; i < u16Lib_size; i++)
1249 {
1250 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
1251 }
1252
1253 //// Content verification ////
1254 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
1255
1256 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1257 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1258
1259 for (i = 0; i < u16Lib_size; i++)
1260 {
1261 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1262
1263 if (udata != DTMB_table[i])
1264 {
1265 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
1266 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
1267 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
1268
1269 if (fail_cnt++ > 10)
1270 {
1271 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
1272 return FALSE;
1273 }
1274 }
1275 }
1276
1277 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
1278
1279 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1280 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1281
1282 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
1283 HAL_INTERN_DTMB_DBINFO(printf("u16IF_KHZ=%d\n",pRes->sDMD_DTMB_InitData.u16IF_KHZ));
1284 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1285 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
1286 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1287 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
1288 HAL_INTERN_DTMB_DBINFO(printf("bIQSwap=%d\n",pRes->sDMD_DTMB_InitData.bIQSwap));
1289 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1290 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
1291 HAL_INTERN_DTMB_DBINFO(printf("u16AGC_REFERENCE=%X\n",pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE));
1292 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1293 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
1294 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1295 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
1296 HAL_INTERN_DTMB_DBINFO(printf("u32TdiStartAddr=%X\n",pRes->sDMD_DTMB_InitData.u32TdiStartAddr));
1297 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1298 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
1299 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1300 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
1301 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1302 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
1303 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1304 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
1305 HAL_INTERN_DTMB_DBINFO(printf("eLastType=%d\n",pRes->sDMD_DTMB_PriData.eLastType));
1306 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1307
1308 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1309 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1310
1311 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1312
1313 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1314 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1315
1316 pRes->sDMD_DTMB_PriData.bDownloaded = true;
1317
1318 MsOS_DelayTask(20);
1319
1320 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
1321
1322 return TRUE;
1323 }
1324
_HAL_INTERN_DTMB_FWVERSION(void)1325 static void _HAL_INTERN_DTMB_FWVERSION(void)
1326 {
1327 MS_U8 data1 = 0;
1328 MS_U8 data2 = 0;
1329 MS_U8 data3 = 0;
1330
1331 _MBX_ReadReg(0x20C4, &data1);
1332 _MBX_ReadReg(0x20C5, &data2);
1333 _MBX_ReadReg(0x20C6, &data3);
1334
1335 printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1336 }
1337
_HAL_INTERN_DTMB_Exit(void)1338 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
1339 {
1340 MS_U8 u8CheckCount = 0;
1341
1342 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1343
1344 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1345 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1346
1347 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1348 {
1349 MsOS_DelayTaskUs(10);
1350
1351 if (u8CheckCount++ == 0xFF)
1352 {
1353 printf(">> DTMB Exit Fail!\n");
1354 return FALSE;
1355 }
1356 }
1357
1358 printf(">> DTMB Exit Ok!\n");
1359
1360 return TRUE;
1361 }
1362
_HAL_INTERN_DTMB_SoftReset(void)1363 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
1364 {
1365 MS_U8 u8Data = 0;
1366
1367 //Reset FSM
1368 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1369
1370 while (u8Data!=0x02)
1371 {
1372 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1373 }
1374
1375 return TRUE;
1376 }
1377
_HAL_INTERN_DTMB_SetACICoef(void)1378 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1379 {
1380 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1381
1382 MS_U8 *ACI_table;
1383 MS_U8 i;
1384 MS_U16 u16AddressOffset;
1385
1386 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1387 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1388 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1389 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1390 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1391 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1392 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1393 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1394 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1395
1396 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1397 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1398
1399 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1400
1401 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1402 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1403 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1404 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1405
1406 //SET SR value
1407 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1408 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1409 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1410 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1411
1412 //set ACI coefficient
1413 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1414 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1415 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1416 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1417 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1418 {
1419 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1420 }
1421
1422 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1423 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1424
1425 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1426
1427 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1428 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1429
1430 MsOS_DelayTask(20);
1431
1432 return TRUE;
1433 }
1434
_HAL_INTERN_DTMB_SetDtmbMode(void)1435 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1436 {
1437 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1438 return _MBX_WriteReg(0x20C0, 0x04);
1439 }
1440
_HAL_INTERN_DTMB_SetModeClean(void)1441 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1442 {
1443 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1444 return _MBX_WriteReg(0x20C0, 0x00);
1445 }
1446
_HAL_INTERN_DTMB_Set_QAM_SR(void)1447 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1448 {
1449 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1450 return _MBX_WriteReg(0x20C0, 0x04);
1451 }
1452
_HAL_INTERN_DTMB_AGCLock(void)1453 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1454 {
1455 MS_U8 data = 0;
1456
1457 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1458 _MBX_ReadReg(0x2829, &data);//AGC_LOCK
1459 #else
1460 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1461 #endif
1462 if (data&0x01)
1463 {
1464 return TRUE;
1465 }
1466 else
1467 {
1468 return FALSE;
1469 }
1470 }
1471
_HAL_INTERN_DTMB_PNP_Lock(void)1472 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1473 {
1474 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1475 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1476 #endif
1477
1478 MS_U8 data = 0;
1479 MS_U8 data1 = 0;
1480
1481 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1482 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1483 {
1484 _MBX_ReadReg(0x3BBA, &data);
1485 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1486 }
1487 else
1488 {
1489 _MBX_ReadReg(0x22BA, &data);
1490 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1491 }
1492 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1493 _MBX_ReadReg(0x37BA, &data);
1494 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1495 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1496 _MBX_ReadReg(0x11BA, &data);
1497 _MBX_ReadReg(0x1249, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1498 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1499 _MBX_ReadReg(0x3BBA, &data);
1500 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1501 #else
1502 _MBX_ReadReg(0x22BA, &data);
1503 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1504 #endif
1505
1506 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1507 {
1508 return TRUE;
1509 }
1510 else
1511 {
1512 return FALSE;
1513 }
1514 }
1515
_HAL_INTERN_DTMB_FEC_Lock(void)1516 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1517 {
1518 MS_U8 u8state=0;
1519
1520
1521 _MBX_ReadReg(0x20C1, &u8state);
1522
1523 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1524 {
1525 return TRUE;
1526 }
1527 else
1528 {
1529 return FALSE;
1530 }
1531 }
1532
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1533 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1534 {
1535 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1536
1537 MS_U8 CM, QAM, IL, CR, SiNR;
1538 MS_U8 data_L = 0;
1539 MS_U8 data_H = 0;
1540
1541 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1542 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1543 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1544 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1545 {
1546 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1547 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1548 {
1549 _MBX_ReadReg(0x3B90, &data_L);
1550 _MBX_ReadReg(0x3B91, &data_H);
1551 }
1552 else
1553 {
1554 _MBX_ReadReg(0x2290, &data_L);
1555 _MBX_ReadReg(0x2291, &data_H);
1556 }
1557 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1558 _MBX_ReadReg(0x3790, &data_L);
1559 _MBX_ReadReg(0x3791, &data_H);
1560 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1561 _MBX_ReadReg(0x1190, &data_L);
1562 _MBX_ReadReg(0x1191, &data_H);
1563 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1564 _MBX_ReadReg(0x3B90, &data_L);
1565 _MBX_ReadReg(0x3B91, &data_H);
1566 #else
1567 _MBX_ReadReg(0x2290, &data_L);
1568 _MBX_ReadReg(0x2291, &data_H);
1569 #endif
1570
1571 if (data_L & 0x1)
1572 {
1573 CR = (data_L >> 6) & 0x03;
1574 IL = (data_L >> 3) & 0x01;
1575 QAM = (data_L >> 4) & 0x03;
1576 SiNR = (data_L >> 2) & 0x01;
1577 CM = (data_L >> 1) & 0x01;
1578 }
1579 else
1580 {
1581 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1582 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1583 {
1584 _MBX_ReadReg(0x3B9E, &data_L);
1585 _MBX_ReadReg(0x3B9F, &data_H);
1586 }
1587 else
1588 {
1589 _MBX_ReadReg(0x229E, &data_L);
1590 _MBX_ReadReg(0x229F, &data_H);
1591 }
1592 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1593 _MBX_ReadReg(0x379E, &data_L);
1594 _MBX_ReadReg(0x379F, &data_H);
1595 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1596 _MBX_ReadReg(0x119E, &data_L);
1597 _MBX_ReadReg(0x119F, &data_H);
1598 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1599 _MBX_ReadReg(0x3B9E, &data_L);
1600 _MBX_ReadReg(0x3B9F, &data_H);
1601 #else
1602 _MBX_ReadReg(0x229E, &data_L);
1603 _MBX_ReadReg(0x229F, &data_H);
1604 #endif
1605
1606 CR = (data_H >> 4) & 0x03;
1607 IL = (data_H >> 6) & 0x01;
1608 QAM = (data_H >> 2) & 0x03;
1609 SiNR = (data_H >> 1) & 0x01;
1610 CM = (data_H) & 0x01;
1611 }
1612
1613 #ifdef UTPA2
1614 if (CR == 0)
1615 psDtmbGetModulation->fSiCodeRate = 4;
1616 else if (CR == 1)
1617 psDtmbGetModulation->fSiCodeRate = 6;
1618 else if (CR == 2)
1619 psDtmbGetModulation->fSiCodeRate = 8;
1620 #else
1621 if (CR == 0)
1622 psDtmbGetModulation->fSiCodeRate = 0.4;
1623 else if (CR == 1)
1624 psDtmbGetModulation->fSiCodeRate = 0.6;
1625 else if (CR == 2)
1626 psDtmbGetModulation->fSiCodeRate = 0.8;
1627 #endif
1628
1629 if (IL == 0)
1630 psDtmbGetModulation->u8SiInterLeaver = 240;
1631 else
1632 psDtmbGetModulation->u8SiInterLeaver = 720;
1633
1634 if (QAM == 0)
1635 psDtmbGetModulation->u8SiQamMode = 4;
1636 else if (QAM == 1)
1637 psDtmbGetModulation->u8SiQamMode = 16;
1638 else if (QAM == 2)
1639 psDtmbGetModulation->u8SiQamMode = 32;
1640 else if (QAM == 3)
1641 psDtmbGetModulation->u8SiQamMode = 64;
1642
1643 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1644 psDtmbGetModulation->u8SiNR = SiNR;
1645 }
1646 else
1647 {
1648 }
1649
1650 return TRUE;
1651 }
1652
_HAL_INTERN_DTMB_ReadIFAGC(void)1653 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1654 {
1655 MS_U8 data = 0;
1656
1657 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1658 _MBX_ReadReg(0x280F, &data);
1659 #else
1660 _MBX_ReadReg(0x28FD, &data);
1661 #endif
1662
1663 return data;
1664 }
1665
1666 #ifdef UTPA2
_HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 * pFftfirstCfo,MS_S8 * pFftSecondCfo,MS_S16 * pSr)1667 static MS_BOOL _HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 *pFftfirstCfo, MS_S8 *pFftSecondCfo, MS_S16 *pSr)
1668 #else
1669 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1670 #endif
1671 {
1672 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1673
1674 MS_U8 u8Data = 0;
1675 MS_S16 fftfirstCfo = 0;
1676 MS_S8 fftSecondCfo = 0;
1677 MS_S16 sr = 0;
1678
1679 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1680 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1681 {
1682 _MBX_ReadReg(0x3C4D, &u8Data);
1683 fftfirstCfo = u8Data;
1684 _MBX_ReadReg(0x3C4C, &u8Data);
1685 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1686
1687 _MBX_ReadReg(0x3C50, &u8Data);
1688 fftSecondCfo = u8Data;
1689 }
1690 else
1691 {
1692 _MBX_ReadReg(0x234D, &u8Data);
1693 fftfirstCfo = u8Data;
1694 _MBX_ReadReg(0x234C, &u8Data);
1695 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1696
1697 _MBX_ReadReg(0x2350, &u8Data);
1698 fftSecondCfo = u8Data;
1699 }
1700 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1701 _MBX_ReadReg(0x384D, &u8Data);
1702 fftfirstCfo = u8Data;
1703 _MBX_ReadReg(0x384C, &u8Data);
1704 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1705
1706 _MBX_ReadReg(0x3850, &u8Data);
1707 fftSecondCfo = u8Data;
1708 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1709 _MBX_ReadReg(0x124D, &u8Data);
1710 fftfirstCfo = u8Data;
1711 _MBX_ReadReg(0x124C, &u8Data);
1712 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1713 _MBX_ReadReg(0x1250, &u8Data);
1714 fftSecondCfo = u8Data;
1715 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1716 _MBX_ReadReg(0x3C4D, &u8Data);
1717 fftfirstCfo = u8Data;
1718 _MBX_ReadReg(0x3C4C, &u8Data);
1719 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1720
1721 _MBX_ReadReg(0x3C50, &u8Data);
1722 fftSecondCfo = u8Data;
1723 #else
1724 _MBX_ReadReg(0x234D, &u8Data);
1725 fftfirstCfo = u8Data;
1726 _MBX_ReadReg(0x234C, &u8Data);
1727 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1728
1729 _MBX_ReadReg(0x2350, &u8Data);
1730 fftSecondCfo = u8Data;
1731 #endif
1732
1733 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1734 sr = 5670;
1735 else sr = 7560;
1736
1737 #ifdef UTPA2
1738 *pFftfirstCfo = fftfirstCfo;
1739 *pFftSecondCfo = fftSecondCfo;
1740 *pSr = sr;
1741
1742 return TRUE;
1743 #else
1744 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1745 #endif
1746 }
1747
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1748 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1749 {
1750 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1751
1752 MS_U8 data = 0;
1753 MS_U8 level = 0;
1754 MS_U32 snr = 0;
1755
1756 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1757 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1758 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1759 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1760 {
1761 if (!_HAL_INTERN_DTMB_FEC_Lock())
1762 level = 0;
1763 else
1764 {
1765 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1766 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1767 {
1768 _MBX_ReadReg(0x3BDA, &data);
1769 snr = data&0x3F;
1770 _MBX_ReadReg(0x3BD9, &data);
1771 snr = (snr<<8)|data;
1772 _MBX_ReadReg(0x3BD8, &data);
1773 snr = (snr<<8)|data;
1774 }
1775 else
1776 {
1777 _MBX_ReadReg(0x22DA, &data);
1778 snr = data&0x3F;
1779 _MBX_ReadReg(0x22D9, &data);
1780 snr = (snr<<8)|data;
1781 _MBX_ReadReg(0x22D8, &data);
1782 snr = (snr<<8)|data;
1783 }
1784 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1785 _MBX_ReadReg(0x37DA, &data);
1786 snr = data&0x3F;
1787 _MBX_ReadReg(0x37D9, &data);
1788 snr = (snr<<8)|data;
1789 _MBX_ReadReg(0x37D8, &data);
1790 snr = (snr<<8)|data;
1791 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1792 _MBX_ReadReg(0x11DA, &data);
1793 snr = data&0x3F;
1794 _MBX_ReadReg(0x11D9, &data);
1795 snr = (snr<<8)|data;
1796 _MBX_ReadReg(0x11D8, &data);
1797 snr = (snr<<8)|data;
1798 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1799 _MBX_ReadReg(0x3BDA, &data);
1800 snr = data&0x3F;
1801 _MBX_ReadReg(0x3BD9, &data);
1802 snr = (snr<<8)|data;
1803 _MBX_ReadReg(0x3BD8, &data);
1804 snr = (snr<<8)|data;
1805 #else
1806 _MBX_ReadReg(0x22DA, &data);
1807 snr = data&0x3F;
1808 _MBX_ReadReg(0x22D9, &data);
1809 snr = (snr<<8)|data;
1810 _MBX_ReadReg(0x22D8, &data);
1811 snr = (snr<<8)|data;
1812 #endif
1813
1814 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1815 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1816 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1817 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1818 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1819 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1820 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1821 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1822 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1823 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1824 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1825 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1826 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1827 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1828 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1829 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1830 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1831 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1832 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1833 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1834 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1835 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1836 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1837 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1838 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1839 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1840 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1841 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1842 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1843 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1844 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1845 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1846 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1847 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1848 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1849 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1850 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1851 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1852 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1853 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1854 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1855 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1856 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1857 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1858 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1859 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1860 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1861 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1862 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1863 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1864 }
1865 }
1866 else
1867 {
1868 level = 0;
1869 }
1870
1871 return level*2;
1872 }
1873
1874 #ifdef UTPA2
_HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 * pBitErr,MS_U16 * pError_window)1875 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 *pBitErr, MS_U16 *pError_window)
1876 #else
1877 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1878 #endif
1879 {
1880 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1881 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1882 #endif
1883
1884 MS_U8 u8Data=0;
1885 MS_U32 BitErr;
1886 MS_U16 error_window;
1887
1888 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1889 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1890 {
1891 _MBX_ReadReg(0x3F3B, &u8Data);
1892 BitErr = u8Data;
1893 _MBX_ReadReg(0x3F3A, &u8Data);
1894 BitErr = (BitErr << 8)|u8Data;
1895 _MBX_ReadReg(0x3F39, &u8Data);
1896 BitErr = (BitErr << 8)|u8Data;
1897 _MBX_ReadReg(0x3F38, &u8Data);
1898 BitErr = (BitErr << 8)|u8Data;
1899 }
1900 else
1901 {
1902 _MBX_ReadReg(0x263B, &u8Data);
1903 BitErr = u8Data;
1904 _MBX_ReadReg(0x263A, &u8Data);
1905 BitErr = (BitErr << 8)|u8Data;
1906 _MBX_ReadReg(0x2639, &u8Data);
1907 BitErr = (BitErr << 8)|u8Data;
1908 _MBX_ReadReg(0x2638, &u8Data);
1909 BitErr = (BitErr << 8)|u8Data;
1910 }
1911 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1912 _MBX_ReadReg(0x2D3B, &u8Data);
1913 BitErr = u8Data;
1914 _MBX_ReadReg(0x2D3A, &u8Data);
1915 BitErr = (BitErr << 8)|u8Data;
1916 _MBX_ReadReg(0x2D39, &u8Data);
1917 BitErr = (BitErr << 8)|u8Data;
1918 _MBX_ReadReg(0x2D38, &u8Data);
1919 BitErr = (BitErr << 8)|u8Data;
1920 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1921 _MBX_ReadReg(0x163B, &u8Data);
1922 BitErr = u8Data;
1923 _MBX_ReadReg(0x163A, &u8Data);
1924 BitErr = (BitErr << 8)|u8Data;
1925 _MBX_ReadReg(0x1639, &u8Data);
1926 BitErr = (BitErr << 8)|u8Data;
1927 _MBX_ReadReg(0x1638, &u8Data);
1928 BitErr = (BitErr << 8)|u8Data;
1929 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1930 _MBX_ReadReg(0x3F3B, &u8Data);
1931 BitErr = u8Data;
1932 _MBX_ReadReg(0x3F3A, &u8Data);
1933 BitErr = (BitErr << 8)|u8Data;
1934 _MBX_ReadReg(0x3F39, &u8Data);
1935 BitErr = (BitErr << 8)|u8Data;
1936 _MBX_ReadReg(0x3F38, &u8Data);
1937 BitErr = (BitErr << 8)|u8Data;
1938 #else
1939 _MBX_ReadReg(0x263B, &u8Data);
1940 BitErr = u8Data;
1941 _MBX_ReadReg(0x263A, &u8Data);
1942 BitErr = (BitErr << 8)|u8Data;
1943 _MBX_ReadReg(0x2639, &u8Data);
1944 BitErr = (BitErr << 8)|u8Data;
1945 _MBX_ReadReg(0x2638, &u8Data);
1946 BitErr = (BitErr << 8)|u8Data;
1947 #endif
1948
1949 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1950 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1951 {
1952 _MBX_ReadReg(0x3F2F, &u8Data);
1953 error_window = u8Data;
1954 _MBX_ReadReg(0x3F2E, &u8Data);
1955 error_window = (error_window << 8)|u8Data;
1956 }
1957 else
1958 {
1959 _MBX_ReadReg(0x262F, &u8Data);
1960 error_window = u8Data;
1961 _MBX_ReadReg(0x262E, &u8Data);
1962 error_window = (error_window << 8)|u8Data;
1963 }
1964 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1965 _MBX_ReadReg(0x2D2F, &u8Data);
1966 error_window = u8Data;
1967 _MBX_ReadReg(0x2D2E, &u8Data);
1968 error_window = (error_window << 8)|u8Data;
1969 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAXIM || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1970 _MBX_ReadReg(0x162F, &u8Data);
1971 error_window = u8Data;
1972 _MBX_ReadReg(0x162E, &u8Data);
1973 error_window = (error_window << 8)|u8Data;
1974 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1975 _MBX_ReadReg(0x3F2F, &u8Data);
1976 error_window = u8Data;
1977 _MBX_ReadReg(0x3F2E, &u8Data);
1978 error_window = (error_window << 8)|u8Data;
1979 #else
1980 _MBX_ReadReg(0x262F, &u8Data);
1981 error_window = u8Data;
1982 _MBX_ReadReg(0x262E, &u8Data);
1983 error_window = (error_window << 8)|u8Data;
1984 #endif
1985
1986 #ifdef UTPA2
1987 *pBitErr = BitErr;
1988 *pError_window = error_window;
1989 #else
1990 *pber=(float)BitErr/7488.0/(float)error_window;
1991 #endif
1992
1993 return TRUE;
1994 }
1995
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)1996 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
1997 {
1998 return _MBX_ReadReg(u16Addr, pu8Data);
1999 }
2000
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2001 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2002 {
2003 return _MBX_WriteReg(u16Addr, u8Data);
2004 }
2005
2006 //-------------------------------------------------------------------------------------------------
2007 // Global Functions
2008 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)2009 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
2010 {
2011 MS_BOOL bResult = TRUE;
2012
2013 switch(eCmd)
2014 {
2015 case DMD_DTMB_HAL_CMD_Exit:
2016 bResult = _HAL_INTERN_DTMB_Exit();
2017 break;
2018 case DMD_DTMB_HAL_CMD_InitClk:
2019 _HAL_INTERN_DTMB_InitClk();
2020 break;
2021 case DMD_DTMB_HAL_CMD_Download:
2022 bResult = _HAL_INTERN_DTMB_Download();
2023 break;
2024 case DMD_DTMB_HAL_CMD_FWVERSION:
2025 _HAL_INTERN_DTMB_FWVERSION();
2026 break;
2027 case DMD_DTMB_HAL_CMD_SoftReset:
2028 bResult = _HAL_INTERN_DTMB_SoftReset();
2029 break;
2030 case DMD_DTMB_HAL_CMD_SetACICoef:
2031 bResult = _HAL_INTERN_DTMB_SetACICoef();
2032 break;
2033 case DMD_DTMB_HAL_CMD_SetDTMBMode:
2034 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
2035 break;
2036 case DMD_DTMB_HAL_CMD_SetModeClean:
2037 bResult = _HAL_INTERN_DTMB_SetModeClean();
2038 break;
2039 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
2040 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
2041 break;
2042 case DMD_DTMB_HAL_CMD_Active:
2043 break;
2044 case DMD_DTMB_HAL_CMD_AGCLock:
2045 bResult = _HAL_INTERN_DTMB_AGCLock();
2046 break;
2047 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
2048 bResult = _HAL_INTERN_DTMB_PNP_Lock();
2049 break;
2050 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
2051 bResult = _HAL_INTERN_DTMB_FEC_Lock();
2052 break;
2053 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
2054 break;
2055 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
2056 break;
2057 case DMD_DTMB_HAL_CMD_GetModulation:
2058 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
2059 break;
2060 case DMD_DTMB_HAL_CMD_ReadIFAGC:
2061 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
2062 break;
2063 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
2064 #ifdef UTPA2
2065 bResult = _HAL_INTERN_DTMB_ReadFrequencyOffset(&((*((DMD_DTMB_CFO_DATA *)pArgs)).fftfirstCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).fftSecondCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).sr));
2066 #else
2067 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
2068 #endif
2069 break;
2070 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
2071 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
2072 break;
2073 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
2074 #ifdef UTPA2
2075 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer(&((*((DMD_DTMB_BER_DATA *)pArgs)).BitErr), &((*((DMD_DTMB_BER_DATA *)pArgs)).Error_window));
2076 #else
2077 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
2078 #endif
2079 break;
2080 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
2081 break;
2082 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
2083 break;
2084 case DMD_DTMB_HAL_CMD_GetSNR:
2085 break;
2086 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
2087 break;
2088 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
2089 break;
2090 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
2091 break;
2092 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
2093 break;
2094 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
2095 break;
2096 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
2097 break;
2098 case DMD_DTMB_HAL_CMD_DoIQSwap:
2099 break;
2100 case DMD_DTMB_HAL_CMD_GET_REG:
2101 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
2102 break;
2103 case DMD_DTMB_HAL_CMD_SET_REG:
2104 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
2105 break;
2106 default:
2107 break;
2108 }
2109
2110 return bResult;
2111 }
2112
MDrv_DMD_DTMB_Initial_Hal_Interface(void)2113 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
2114 {
2115 return TRUE;
2116 }
2117
2118