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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT2.c
98 /// @brief INTERN_DVBT2 DVBT2
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT2_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 //#include "BinInfo.h"
114 #include "drvDMD_VD_MBX.h"
115 #include "drvDMD_INTERN_DVBT2.h"
116 #include "halDMD_INTERN_DVBT2.h"
117 #include "halDMD_INTERN_common.h"
118
119 extern void *memcpy(void *destination, const void *source, size_t num);
120
121 #define TEST_EMBEDED_DEMOD 0
122 //U8 load_data_variable=1;
123 //-----------------------------------------------------------------------
124 #define BIN_ID_INTERN_DVBT2_DEMOD BIN_ID_INTERN_DVBT
125
126 #define TDE_REG_BASE 0x2400
127 #define DIV_REG_BASE 0x2500
128 #define TR_REG_BASE 0x2600
129 #define FTN_REG_BASE 0x2700
130 #define FTNEXT_REG_BASE 0x2800
131
132
133
134 #if 0//ENABLE_SCAN_ONELINE_MSG
135 #define DBG_INTERN_DVBT2_ONELINE(x) x
136 #else
137 #define DBG_INTERN_DVBT2_ONELINE(x) // x
138 #endif
139
140 #ifdef MS_DEBUG
141 #define DBG_INTERN_DVBT2(x) x
142 #define DBG_GET_SIGNAL(x) x
143 #define DBG_INTERN_DVBT2_TIME(x) x
144 #define DBG_INTERN_DVBT2_LOCK(x) x
145 #else
146 #define DBG_INTERN_DVBT2(x) //x
147 #define DBG_GET_SIGNAL(x) //x
148 #define DBG_INTERN_DVBT2_TIME(x) // x
149 #define DBG_INTERN_DVBT2_LOCK(x) //x
150 #endif
151 #define DBG_DUMP_LOAD_DSP_TIME 0
152
153 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0
154 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1
155 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1
156 #define INTERN_DVBT2_INTERNAL_DEBUG 1
157
158 #define SIGNAL_LEVEL_OFFSET 0.00
159 #define TAKEOVERPOINT -59.0
160 #define TAKEOVERRANGE 0.5
161 #define LOG10_OFFSET -0.21
162 #define INTERN_DVBT2_USE_SAR_3_ENABLE 0
163 #define INTERN_DVBT2_GET_TIME msAPI_Timer_GetTime0()
164
165
166 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
167 #define TUNER_VPP 2
168 #define IF_AGC_VPP 2
169 #else
170 #define TUNER_VPP 1
171 #define IF_AGC_VPP 2
172 #endif
173
174 #if (TUNER_VPP == 1)
175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
176 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
178 #endif
179
180 /*BEG INTERN_DVBT2_DSPREG_TABLE*/
181 #define DVBT2_FS 24000
182
183 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
184 #define T2_BW_VAL 0x04
185 // FC: FC = FS = 5000 = 0x1388 (5.0MHz IF)
186 #define T2_FC_L_VAL 0x88 // 5.0M
187 #define T2_FC_H_VAL 0x13
188 #define T2_TS_SERIAL_VAL 0x00
189 #define T2_TS_CLK_RATE_VAL 0x06
190 #define T2_TS_OUT_INV_VAL 0x00
191 #define T2_TS_DATA_SWAP_VAL 0x00
192 #define T2_IF_AGC_INV_PWM_EN_VAL 0x00
193 #define T2_LITE_VAL 0x00
194 #define T2_AGC_REF_VAL 0x40
195
196 /*END INTERN_DVBT2_DSPREG_TABLE*/
197 //-----------------------------------------------------------------------
198 /****************************************************************
199 *Local Variables *
200 ****************************************************************/
201 static MS_BOOL bFECLock=0;
202 static MS_BOOL bP1Lock = 0;
203 static MS_U32 u32ChkScanTimeStart = 0;
204 static MS_U32 u32FecFirstLockTime=0;
205 static MS_U32 u32FecLastLockTime=0;
206 static float fLDPCBerFiltered=-1;
207 //Global Variables
208 S_CMDPKTREG gsCmdPacket;
209 //U8 gCalIdacCh0, gCalIdacCh1;
210 extern MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
211 extern MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
212 extern MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
213 extern MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
214 extern MS_U32 u32DMD_DVBT2_FW_START_ADDR;
215
216 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
217 MS_U8 INTERN_DVBT2_table[] = {
218 #include "fwDMD_INTERN_DVBT2.dat"
219 };
220
221 #endif
222 /*
223 static DMD_T2_SSI_DBM_NORDIGP1 dvbt2_ssi_dbm_nordigp1[] =
224 {
225 {_T2_QPSK, _T2_CR1Y2, -95.7},
226 {_T2_QPSK, _T2_CR3Y5, -94.4},
227 {_T2_QPSK, _T2_CR2Y3, -93.6},
228 {_T2_QPSK, _T2_CR3Y4, -92.6},
229 {_T2_QPSK, _T2_CR4Y5, -92.0},
230 {_T2_QPSK, _T2_CR5Y6, -91.5},
231
232 {_T2_16QAM, _T2_CR1Y2, -90.8},
233 {_T2_16QAM, _T2_CR3Y5, -89.1},
234 {_T2_16QAM, _T2_CR2Y3, -87.9},
235 {_T2_16QAM, _T2_CR3Y4, -86.7},
236 {_T2_16QAM, _T2_CR4Y5, -85.8},
237 {_T2_16QAM, _T2_CR5Y6, -85.2},
238
239 {_T2_64QAM, _T2_CR1Y2, -86.9},
240 {_T2_64QAM, _T2_CR3Y5, -84.6},
241 {_T2_64QAM, _T2_CR2Y3, -83.2},
242 {_T2_64QAM, _T2_CR3Y4, -81.4},
243 {_T2_64QAM, _T2_CR4Y5, -80.3},
244 {_T2_64QAM, _T2_CR5Y6, -79.7},
245
246 {_T2_256QAM, _T2_CR1Y2, -83.5},
247 {_T2_256QAM, _T2_CR3Y5, -80.4},
248 {_T2_256QAM, _T2_CR2Y3, -78.6},
249 {_T2_256QAM, _T2_CR3Y4, -76.0},
250 {_T2_256QAM, _T2_CR4Y5, -74.4},
251 {_T2_256QAM, _T2_CR5Y6, -73.3},
252 {_T2_QAM_UNKNOWN, _T2_CR_UNKNOWN, 0.0}
253 };
254 */
255 static float dvbt2_ssi_dbm_nordigp1[][6] =
256 {
257 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
258 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
259 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
260 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
261 };
262
263 static void INTERN_DVBT2_SignalQualityReset(void);
264 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void);
265
INTERN_DVBT2_SignalQualityReset(void)266 static void INTERN_DVBT2_SignalQualityReset(void)
267 {
268 u32FecFirstLockTime=0;
269 fLDPCBerFiltered=-1;
270 }
271
INTERN_DVBT2_DSPReg_Init(const MS_U8 * u8DVBT2_DSPReg,MS_U8 u8Size)272 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT2_DSPReg, MS_U8 u8Size)
273 {
274 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
275 MS_BOOL status = TRUE;
276 MS_U16 u16DspAddr = 0;
277
278 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_DSPReg_Init\n"));
279
280 //for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
281 // status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
282 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_BW, T2_BW_VAL) != TRUE)
283 {
284 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
285 }
286 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_L, T2_FC_L_VAL) != TRUE)
287 {
288 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
289 }
290 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_H, T2_FC_H_VAL) != TRUE)
291 {
292 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
293 }
294 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_SERIAL, T2_TS_SERIAL_VAL) != TRUE)
295 {
296 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
297 }
298 //if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_CLK_RATE, T2_TS_CLK_RATE_VAL) != TRUE)
299 //{
300 // printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
301 //}
302 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_OUT_INV, T2_TS_OUT_INV_VAL) != TRUE)
303 {
304 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
305 }
306 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_SWAP, T2_TS_DATA_SWAP_VAL) != TRUE)
307 {
308 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
309 }
310 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_IF_AGC_INV_PWM_EN, T2_IF_AGC_INV_PWM_EN_VAL) != TRUE)
311 {
312 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
313 }
314 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_LITE, T2_LITE_VAL) != TRUE)
315 {
316 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
317 }
318
319 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_AGC_REF, T2_AGC_REF_VAL) != TRUE) //brown:0x40->agc_ref
320 {
321 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
322 }
323
324 if (u8DVBT2_DSPReg != NULL)
325 {
326 /*temp solution until new dsp table applied.*/
327 // if (INTERN_DVBT2_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
328 if (u8DVBT2_DSPReg[0] >= 1)
329 {
330 u8DVBT2_DSPReg+=2;
331 for (idx = 0; idx<u8Size; idx++)
332 {
333 u16DspAddr = *u8DVBT2_DSPReg;
334 u8DVBT2_DSPReg++;
335 u16DspAddr = (u16DspAddr) + ((*u8DVBT2_DSPReg)<<8);
336 u8DVBT2_DSPReg++;
337 u8Mask = *u8DVBT2_DSPReg;
338 u8DVBT2_DSPReg++;
339 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
340 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT2_DSPReg) & (u8Mask));
341 u8DVBT2_DSPReg++;
342 DBG_INTERN_DVBT2(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
343 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
344 }
345 }
346 else
347 {
348 printf("FATAL: parameter version incorrect\n");
349 }
350 }
351
352 return status;
353 }
354
355 /***********************************************************************************
356 Subject: SoftStop
357 Function: INTERN_DVBT2_SoftStop
358 Parmeter:
359 Return: MS_BOOL
360 Remark:
361 ************************************************************************************/
362
INTERN_DVBT2_SoftStop(void)363 MS_BOOL INTERN_DVBT2_SoftStop ( void )
364 {
365 MS_U16 u8WaitCnt=0;
366 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
367 {
368 printf(">> MB Busy!\n");
369 return FALSE;
370 }
371
372 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
373
374 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
375 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
376
377 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
378 {
379 if (u8WaitCnt++ >= 0xFFF)
380 {
381 printf(">> DVBT2 SoftStop Fail!\n");
382 return FALSE;
383 }
384 }
385
386 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
387 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
388 return TRUE;
389 }
390
INTERN_DVBT2_SoftReset(void)391 MS_BOOL INTERN_DVBT2_SoftReset ( void )
392 {
393 MS_BOOL bRet=TRUE;
394 //MS_U8 u8Data, fdp_fifo_done, djb_fifo_done, tdi_fifo_done;
395 MS_U8 u8Data = 0, fdp_fifo_done, tdi_fifo_done;
396 MS_U8 u8_timeout = 0;
397
398 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_SoftReset\n"));
399
400 //stop FSM_EN
401 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN
402
403 MsOS_DelayTask(5);
404
405 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
406 DBG_INTERN_DVBT2(printf("@@@TOP_RESET:0x%x\n", u8Data));
407 // MIU hold function
408 if((u8Data & 0x20) == 0x00)
409 {
410 // mask miu service with fdp, djb, tdi
411 //fdp 0x17 [12] reg_fdp_fifo_stop=1'b1
412 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
413 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10));
414 // [8] reg_fdp_load, fdp register dynamic change protection, 1->load register
415 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10);
416 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
417 //printf("@@@@@@ DVBT2 [reg_fdp_fifo_stop]=0x%x\n", u8Data);
418 //djb 0x65 [0] reg_stop_mu_request
419 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
420 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01));
421 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
422 //printf("@@@@@@ DVBT2 [reg_stop_mu_request]=0x%x\n", u8Data);
423 //snr 0x23 [8] reg_tdi_miu_off
424 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
425 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01));
426 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
427 //printf("@@@@@@ DVBT2 [reg_tdi_miu_off]=0x%x\n", u8Data);
428 // ---------------------------------------------
429 // Wait MIU mask or timeout!
430 // DVBT2_TIMER_INT[ 7:0] : indicator of the selected Timer's max count(15:8) (r)
431 // DVBT2_TIMER_INT[11:8] : timer3~timer0 interrupt (r)
432 // ---------------------------------------------
433 //fdp 0x18 [2] reg_fdp_fifo_req_done
434 //djb 0x65 [8] reg_miu_req_terminate_done
435 //tdi 0x23 [9] reg_tdi_miu_off_done
436 do
437 {
438 // Wait MIU mask done or timeout!
439 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data);
440 fdp_fifo_done = u8Data & 0x04;
441 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2)+1, &u8Data);
442 //djb_fifo_done = u8Data & 0x01;
443 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
444 tdi_fifo_done = u8Data & 0x02;
445
446 u8_timeout++;
447 }
448 //while(((fdp_fifo_done != 0x04)||(djb_fifo_done != 0x01)||(tdi_fifo_done != 0x02))
449 while(((fdp_fifo_done != 0x04)||(tdi_fifo_done != 0x02))
450 && u8_timeout != 0x7f);
451
452 //printf(">> DVBT2 fdp_fifo_done=%d, djb_fifo_done=%d, tdi_fifo_done=%d \n", fdp_fifo_done, djb_fifo_done, tdi_fifo_done);
453 printf(">> DVBT2 [fdp_fifo_done]=%d, [tdi_fifo_done]=%d \n", fdp_fifo_done, tdi_fifo_done);
454
455 MsOS_DelayTask(2);
456
457 if(u8_timeout == 0x7f)
458 {
459 printf(">> DVBT2 MIU hold function Fail!\n");
460 //return FALSE;
461 }
462 else
463 {
464 printf(">> DVBT2 MIU hold function done!!\n");
465 }
466 }
467 else
468 printf(">> No need DVBT2 MIU hold function!!\n");
469
470 // demod_top reset
471 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
472 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data|0x20));
473
474 MsOS_DelayTask(1);
475
476 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data&(~0x20)));
477
478 DBG_INTERN_DVBT2(printf("@INTERN_DVBT2_SoftReset done!!\n"));
479
480 return bRet;
481 }
482
483
484 /***********************************************************************************
485 Subject: Reset
486 Function: INTERN_DVBT2_Reset
487 Parmeter:
488 Return: MS_BOOL
489 Remark:
490 ************************************************************************************/
491 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT2_Reset(void)492 MS_BOOL INTERN_DVBT2_Reset ( void )
493 {
494 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_reset\n"));
495
496 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Reset, t = %ld\n",MsOS_GetSystemTime()));
497
498 INTERN_DVBT2_SoftStop();
499
500
501 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
502 MsOS_DelayTask(5);
503 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
504
505 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
506 MsOS_DelayTask(5);
507
508 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
509 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
510
511 bFECLock = FALSE;
512 bP1Lock = FALSE;
513 u32ChkScanTimeStart = MsOS_GetSystemTime();
514 return TRUE;
515 }
516
517 /***********************************************************************************
518 Subject: Exit
519 Function: INTERN_DVBT2_Exit
520 Parmeter:
521 Return: MS_BOOL
522 Remark:
523 ************************************************************************************/
INTERN_DVBT2_Exit(void)524 MS_BOOL INTERN_DVBT2_Exit ( void )
525 {
526 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_Exit\n"));
527
528 INTERN_DVBT2_SoftStop();
529
530
531 //diable clk gen
532 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
533 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
534 /*
535 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
536 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
537
538 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
539 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
540
541 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
542 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
543
544 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
545 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
546
547 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
548 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
549
550 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
551 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
552
553 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
554 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
555
556 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
557 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
558
559 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
560 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
561
562 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
563 */
564 return TRUE;
565 }
566 /*
567 MS_BOOL INTERN_DVBT2_Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length)
568 {
569
570 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Load2Sdram, len=0x%x, \n",data_length));
571 MS_U8 addrhi, addrlo;
572 int i, j, k, old_i=0;
573 int sdram_start_addr = 0;//1024 >> 2; //StrToInt(ed_sdram_start->Text)>>2; // 4KB alignment
574
575 //I2C_CH_Exit(); // exit CH4
576 //I2C_CH5_Reset(); // switch to CH5
577 //MDrv_DMD_I2C_Channel_Change(5);
578 //--------------------------------------------------------------------------
579 // Set xData map for DRAM
580 //--------------------------------------------------------------------------
581
582 //banknum = 0x1d; //dmdmcu51_xdmiu
583
584 //set xData map upper and low bound for 64k DRAM window
585 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x2020);
586 if(SLAVE_I2CWrite16(banknum,0x63,0x2020)==false)
587 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
588
589 //set xData map offset for 64k DRAM window
590 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x64, 0x0000);
591 if(SLAVE_I2CWrite16(banknum,0x64,0x0000)==false)
592 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
593
594 //set xData map upper and low bound for 4k DRAM window
595 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x65, 0x2420);
596 if(SLAVE_I2CWrite16(banknum,0x65,0x2420)==false)
597 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
598
599 //set xData map offset for 4k DRAM window
600 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, sdram_start_addr);
601 if(SLAVE_I2CWrite16(banknum,0x66,sdram_start_addr)==false)
602 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
603
604 //I2C_CH_Exit(); // exit CH5
605 //EnterDebugMode(1); // switch to CH1
606
607 //enable xData map for DRAM
608 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x0007);
609 if(SLAVE_I2CWrite16(banknum,0x62,0x0007)==false)
610 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
611
612
613 for ( i = 0, j = SDRAM_BASE, k = sdram_start_addr + 0x01; i < size;)
614 {
615 if (j == SDRAM_BASE + 0x1000)
616 {
617 //I2C_CH_Exit(); // exit CH1
618 //I2C_CH5_Reset(); // switch to CH5
619 //set xData map offset for 4k DRAM window
620 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, k++);
621 if(SLAVE_I2CWrite16(banknum,0x66,k++)==false)
622 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
623 j = SDRAM_BASE;
624
625 //I2C_CH_Exit(); // exit CH5
626 //EnterDebugMode(1); // switch to CH1
627
628 }
629
630 addrhi = (j >> 8) & 0xff;
631 addrlo = j & 0xff;
632
633 if (i+EZUSB_Write_Buffer<size)
634 {
635 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,EZUSB_Write_Buffer)==FALSE)
636 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
637
638 j=j+EZUSB_Write_Buffer;
639 i=i+EZUSB_Write_Buffer;
640 }
641 else
642 {
643 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,size-i)==FALSE)
644 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
645
646 i=size;
647 }
648
649 if ((i-old_i)>=2048)
650 {
651 ShowMCUDL_Progress(0,3*i,size);
652 old_i=i;
653 }
654 }//end for
655
656
657 FWDLRichEdit->Lines->Add(">SDRAM Down Load OK!");
658
659 I2C_CH_Exit(); // exit CH1
660 I2C_CH5_Reset(); // switch to CH5
661
662 //--------------------------------------------------------------------------
663 // Release xData map for SDRAM
664 //--------------------------------------------------------------------------
665
666 if(SLAVE_I2CWrite16(banknum,0x62,0x0000)==false)
667 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
668
669 }
670 */
671 /***********************************************************************************
672 Subject: Load DSP code to chip
673 Function: INTERN_DVBT2_LoadDSPCode
674 Parmeter:
675 Return: MS_BOOL
676 Remark:
677 ************************************************************************************/
INTERN_DVBT2_LoadDSPCode(void)678 static MS_BOOL INTERN_DVBT2_LoadDSPCode(void)
679 {
680 MS_U8 u8data = 0x00;
681 MS_U16 i;
682 MS_U16 fail_cnt=0;
683 //MS_U16 u16AddressOffset;
684 MS_U32 u32VA_DramCodeAddr;
685
686 #if (DBG_DUMP_LOAD_DSP_TIME==1)
687 MS_U32 u32Time;
688 #endif
689
690
691 #ifndef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
692 BININFO BinInfo;
693 MS_BOOL bResult;
694 MS_U32 u32GEAddr;
695 MS_U8 Data;
696 MS_S8 op;
697 MS_U32 srcaddr;
698 MS_U32 len;
699 MS_U32 SizeBy4K;
700 MS_U16 u16Counter=0;
701 MS_U8 *pU8Data;
702 #endif
703
704 #if 0
705 if(HAL_DMD_RIU_ReadByte(0x101E3E))
706 {
707 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
708 return FALSE;
709 }
710 #endif
711
712 // MDrv_Sys_DisableWatchDog();
713
714
715 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
716 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
717 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
718 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
719 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
720 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
721
722 //// Load code thru VDMCU_IF ////
723 DBG_INTERN_DVBT2(printf(">Load Code...\n"));
724 //#ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
725 //for ( i = 0; i < sizeof(INTERN_DVBT2_table); i++)
726 //{
727 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
728 //}
729 if (sizeof(INTERN_DVBT2_table) < 0x8000)
730 {
731 printf("----->Bin file Size is not match...\n");
732 }
733 else
734 {
735 // load half code to SRAM
736 for ( i = 0; i < 0x8000; i++)
737 {
738 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
739 }
740 DBG_INTERN_DVBT2(printf(">Load SRAM code done...\n"));
741
742
743 if((u32DMD_DVBT2_FW_START_ADDR & 0x8000) != 0x8000)
744 {
745 printf(">DVB-T2 DRAM Start address is not correct!!\n");
746 }
747 else
748 {
749 // load another half code to SDRAM
750 // VA = MsOS_PA2KSEG1(PA); //NonCache
751 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
752 u32VA_DramCodeAddr = MsOS_PA2KSEG1(u32DMD_DVBT2_FW_START_ADDR);
753 memcpy((void*)u32VA_DramCodeAddr, &INTERN_DVBT2_table[0x8000], sizeof(INTERN_DVBT2_table) - 0x8000);
754
755 DBG_INTERN_DVBT2(printf(">Load DRAM code done...\n"));
756 }
757 }
758
759 //#endif
760
761 //// Content verification ////
762 DBG_INTERN_DVBT2(printf(">Verify Code...\n"));
763
764 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
765 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
766
767 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
768 for ( i = 0; i < 0x8000; i++)
769 {
770 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
771 if (u8data != INTERN_DVBT2_table[i])
772 {
773 printf(">fail add = 0x%x\n", i);
774 printf(">code = 0x%x\n", INTERN_DVBT2_table[i]);
775 printf(">data = 0x%x\n", u8data);
776
777 if (fail_cnt++ > 10)
778 {
779 printf(">DVB-T2 DSP SRAM Loadcode fail!\n");
780 return false;
781 }
782 }
783 }
784 #else
785 for (i=0;i<=SizeBy4K;i++)
786 {
787 if(i==SizeBy4K)
788 len=BinInfo.B_Len%0x1000;
789 else
790 len=0x1000;
791
792 srcaddr = u32GEAddr+(0x1000*i);
793 //printf("\t i = %08LX\n", i);
794 //printf("\t len = %08LX\n", len);
795 op = 1;
796 u16Counter = 0 ;
797 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
798 while(len--)
799 {
800 u16Counter ++ ;
801 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
802 //pU8Data = (U8 *)(srcaddr|0x80000000);
803 #if OBA2
804 pU8Data = (U8 *)(srcaddr);
805 #else
806 pU8Data = (U8 *)(srcaddr|0x80000000);
807 #endif
808 Data = *pU8Data;
809
810 #if 0
811 if(u16Counter < 0x100)
812 printf("0x%bx,", Data);
813 #endif
814 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
815 if (u8data != Data)
816 {
817 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
818 printf(">code = 0x%x\n", Data);
819 printf(">data = 0x%x\n", u8data);
820
821 if (fail_cnt++ > 10)
822 {
823 printf(">DVB-T DSP Loadcode fail!");
824 return false;
825 }
826 }
827
828 srcaddr += op;
829 }
830 // printf("\n\n\n");
831 }
832 #endif
833
834 // add T2 DRAM bufer start address into fixed location
835 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
836 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
837
838 // write Start address to VD MCU 51 code sram
839 // //0x30~0x33
840 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR);
841 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 8));
842 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 16));
843 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 24));
844 //0x30~0x33
845 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_EQ_START_ADDR);
846 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 8));
847 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 16));
848 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 24));
849 //0x34~0x37
850 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_TDI_START_ADDR);
851 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 8));
852 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 16));
853 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 24));
854 //0x38~0x3b
855 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_DJB_START_ADDR);
856 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 8));
857 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 16));
858 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 24));
859 //0x3c~0x3f
860 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_FW_START_ADDR);
861 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 8));
862 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 16));
863 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 24));
864
865 DBG_INTERN_DVBT2(printf(">>> DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR));
866 DBG_INTERN_DVBT2(printf(">>> DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR));
867 DBG_INTERN_DVBT2(printf(">>> DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR));
868 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
869
870 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
871 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
872 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
873 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
874
875 DBG_INTERN_DVBT2(printf(">DSP Loadcode done."));
876 //while(load_data_variable);
877
878 return TRUE;
879 }
880
881 /***********************************************************************************
882 Subject: DVB-T CLKGEN initialized function
883 Function: INTERN_DVBT2_Power_On_Initialization
884 Parmeter:
885 Return: MS_BOOL
886 Remark:
887 ************************************************************************************/
INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)888 void INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)
889 {
890 MS_U8 temp_val;
891 MS_U16 u16_temp_val;
892
893 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_InitClkgen\n"));
894
895 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
896 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
897 // ----------------------------------------------
898 // start demod CLKGEN setting
899 // ----------------------------------------------
900 // *** Set register at CLKGEN1
901 // enable DMD MCU clock "bit[0] set 0"
902 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
903 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
904 // CLK_DMDMCU clock setting
905 // [0] disable clock
906 // [1] invert clock
907 // [4:2]
908 // 000:170 MHz(MPLL_DIV_BUf)
909 // 001:160MHz
910 // 010:144MHz
911 // 011:123MHz
912 // 100:108MHz
913 // 101:mem_clcok
914 // 110:mem_clock div 2
915 // 111:select XTAL
916 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
917 // HAL_DMD_RIU_WriteByte(0x10331e,0x1c); // 24MHz
918 HAL_DMD_RIU_WriteByte(0x10331e,0x10); // 108MHz
919
920 // set parallet ts clock
921 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
922 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
923 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0615
924 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
925 temp_val|=0x05;
926 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
927
928 HAL_DMD_RIU_WriteByte(0x103300,0x11);
929
930 // enable DVBTC ts clock
931 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
932 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
933 HAL_DMD_RIU_WriteByte(0x103309,0x00);
934 HAL_DMD_RIU_WriteByte(0x103308,0x00);
935
936 // enable dvbc adc clock
937 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
938 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
939 HAL_DMD_RIU_WriteByte(0x103315,0x00);
940 HAL_DMD_RIU_WriteByte(0x103314,0x00);
941
942 // ----------------------------------------------
943 // start demod_0 CLKGEN setting
944 // ----------------------------------------------
945
946 // enable clk_atsc_adcd_sync
947 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
948 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
949 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
950 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
951
952 //reg_ckg_dvbt_inner
953 HAL_DMD_RIU_WriteByte(0x111f21,0x11);
954 HAL_DMD_RIU_WriteByte(0x111f20,0x10);
955
956 //reg_ckg_dvbt_outer
957 HAL_DMD_RIU_WriteByte(0x111f23,0x01);
958 HAL_DMD_RIU_WriteByte(0x111f22,0x11);
959
960 //reg_ckg_acifir
961 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
962
963 //reg_ckg_dvbtm_sram_t1o2x_t22x
964 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
965 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
966
967 //reg_ckg_dvbtm_sram_adc_t22x
968 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
969 HAL_DMD_RIU_WriteByte(0x111f2c,0x01);
970
971 //reg_ckg_dvbtm_sram_t12x_t24x
972 HAL_DMD_RIU_WriteByte(0x111f2f,0x00);
973 HAL_DMD_RIU_WriteByte(0x111f2e,0x00);
974
975 //reg_ckg_dvbtm_ts_in
976 HAL_DMD_RIU_WriteByte(0x111f31,0x04);
977 HAL_DMD_RIU_WriteByte(0x111f30,0x00);
978
979 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
980 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
981
982 HAL_DMD_RIU_WriteByte(0x111f35,0x00);
983 HAL_DMD_RIU_WriteByte(0x111f34,0x00);
984
985 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
986 HAL_DMD_RIU_WriteByte(0x111f36,0x00);
987
988 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
989 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
990
991 HAL_DMD_RIU_WriteByte(0x111f3d,0x00);
992 HAL_DMD_RIU_WriteByte(0x111f3c,0x00);
993
994 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
995 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
996
997 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
998 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
999
1000 HAL_DMD_RIU_WriteByte(0x111fe1,0x00);
1001 HAL_DMD_RIU_WriteByte(0x111fe0,0x00);
1002
1003 HAL_DMD_RIU_WriteByte(0x111fe3,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111fe2,0x00);
1005
1006 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1007 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1008
1009 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1010 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1011
1012 HAL_DMD_RIU_WriteByte(0x111fe9,0x00);
1013 HAL_DMD_RIU_WriteByte(0x111fe8,0x00);
1014
1015 HAL_DMD_RIU_WriteByte(0x111feb,0xc8);
1016 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1017
1018 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1019 HAL_DMD_RIU_WriteByte(0x111fec,0x0c);
1020
1021 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1022 HAL_DMD_RIU_WriteByte(0x111fee,0x00);
1023
1024 // Mulan special
1025 // TEQ CLK for DVBT2
1026 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1027
1028 // SRAM share
1029 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
1030 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
1031
1032 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1033 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1034
1035 HAL_DMD_RIU_WriteByte(0x111f79,0x00);
1036 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
1037
1038 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
1039 HAL_DMD_RIU_WriteByte(0x111f7a,0x00);
1040
1041 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1042 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1043
1044 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
1045 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
1046
1047 // SRAM allocation
1048 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1049 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1050
1051 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1052 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1053
1054 HAL_DMD_RIU_WriteByte(0x111703,0x00);
1055 HAL_DMD_RIU_WriteByte(0x111702,0x00);
1056
1057 HAL_DMD_RIU_WriteByte(0x111707,0x7f);
1058 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1059
1060 // SDRAM address offset
1061 u16_temp_val = (MS_U16)(u32DMD_DVBT2_FW_START_ADDR>>16);
1062 HAL_DMD_RIU_WriteByte(0x11171b,(MS_U8)(u16_temp_val>>8));
1063 HAL_DMD_RIU_WriteByte(0x11171a,(MS_U8)u16_temp_val);
1064
1065 // DRAM allocation
1066 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1067 HAL_DMD_RIU_WriteByte(0x111708,0x00);
1068
1069 HAL_DMD_RIU_WriteByte(0x11170d,0x80);
1070 HAL_DMD_RIU_WriteByte(0x11170c,0x00);
1071
1072 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1073 HAL_DMD_RIU_WriteByte(0x11170a,0x00);
1074
1075 HAL_DMD_RIU_WriteByte(0x11170f,0xff);
1076 HAL_DMD_RIU_WriteByte(0x11170e,0xff);
1077
1078 // DRAM EN
1079 HAL_DMD_RIU_WriteByte(0x111718,0x04);
1080
1081 // [0]switch dram address mode:
1082 // 0: address from dmdmcu51 bank (old mode)
1083 // 1: address from dmdmcu51_top bank (new mode)
1084 HAL_DMD_RIU_WriteByte(0x11171c,0x01);
1085 // ----------------------------------------------
1086 // start demod CLKGEN setting
1087 // ----------------------------------------------
1088 // select DMD MCU
1089 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1090 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1091 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1092
1093 // stream2miu_en, activate rst_wadr
1094 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1095 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1096 // stream2miu_en, turn off rst_wadr
1097 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1098
1099 }
1100
1101 /***********************************************************************************
1102 Subject: Power on initialized function
1103 Function: INTERN_DVBT2_Power_On_Initialization
1104 Parmeter:
1105 Return: MS_BOOL
1106 Remark:
1107 ************************************************************************************/
1108
INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT2_DSPRegInitExt,MS_U8 u8DMD_DVBT2_DSPRegInitSize)1109 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT2_DSPRegInitExt, MS_U8 u8DMD_DVBT2_DSPRegInitSize)
1110 {
1111 MS_U16 status = true;
1112
1113 MS_U8 temp_val;
1114 //MS_U8 cData = 0;
1115 //U8 cal_done;
1116 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Power_On_Initialization\n"));
1117
1118 #if defined(PWS_ENABLE)
1119 Mapi_PWS_Stop_VDMCU();
1120 #endif
1121
1122 #if 1
1123 // Global demod reset. To fix DVBS -> DVBT2 or DVBS blind scan -> DVBT2 unlock issue.
1124 temp_val=HAL_DMD_RIU_ReadByte(0x101e3a);
1125 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val|0x02);
1126
1127 MsOS_DelayTask(1);
1128
1129 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val&(~0x02));
1130 #endif
1131
1132 INTERN_DVBT2_InitClkgen(bRFAGCTristateEnable);
1133 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1134 //// Firmware download //////////
1135 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Load DSP...\n"));
1136 //MsOS_DelayTask(100);
1137
1138 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1139 {
1140 if (INTERN_DVBT2_LoadDSPCode() == FALSE)
1141 {
1142 printf("DVB-T2 Load DSP Code Fail\n");
1143 return FALSE;
1144 }
1145 else
1146 {
1147 DBG_INTERN_DVBT2(printf("DVB-T2 Load DSP Code OK\n"));
1148 }
1149 }
1150
1151
1152 //// MCU Reset //////////
1153 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Reset...\n"));
1154 if (INTERN_DVBT2_Reset() == FALSE)
1155 {
1156 DBG_INTERN_DVBT2(printf("Fail\n"));
1157 return FALSE;
1158 }
1159 else
1160 {
1161 DBG_INTERN_DVBT2(printf("OK\n"));
1162 }
1163
1164 // SRAM setting, DVB-T use it.
1165 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1166 //MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1167 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1168
1169 status &= INTERN_DVBT2_DSPReg_Init(u8DMD_DVBT2_DSPRegInitExt, u8DMD_DVBT2_DSPRegInitSize);
1170 return status;
1171 }
1172
1173 /************************************************************************************************
1174 Subject: Driving control
1175 Function: INTERN_DVBT2_Driving_Control
1176 Parmeter: bInversionEnable : TRUE For High
1177 Return: void
1178 Remark:
1179 *************************************************************************************************/
INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)1180 void INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)
1181 {
1182 MS_U8 u8Temp;
1183
1184 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1185
1186 if (bEnable)
1187 {
1188 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1189 }
1190 else
1191 {
1192 u8Temp = u8Temp & (~0x01);
1193 }
1194
1195 DBG_INTERN_DVBT2(printf("---> INTERN_DVBT2_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1196 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1197 }
1198 /************************************************************************************************
1199 Subject: Clk Inversion control
1200 Function: INTERN_DVBT2_Clk_Inversion_Control
1201 Parmeter: bInversionEnable : TRUE For Inversion Action
1202 Return: void
1203 Remark:
1204 *************************************************************************************************/
INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)1205 void INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1206 {
1207 MS_U8 u8Temp;
1208
1209 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1210
1211 if (bInversionEnable)
1212 {
1213 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1214 }
1215 else
1216 {
1217 u8Temp = u8Temp & (~0x02);
1218 }
1219
1220 DBG_INTERN_DVBT2(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1221 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1222 }
1223 /************************************************************************************************
1224 Subject: Transport stream serial/parallel control
1225 Function: INTERN_DVBT2_Serial_Control
1226 Parmeter: bEnable : TRUE For serial
1227 Return: MS_BOOL :
1228 Remark:
1229 *************************************************************************************************/
INTERN_DVBT2_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1230 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1231 {
1232 MS_U8 status = true;
1233 MS_U8 temp_val;
1234 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_ts... u8TSClk=%d\n",u8TSClk));
1235
1236 if (u8TSClk == 0xFF) u8TSClk=0x13;
1237 if (bEnable) //Serial mode for TS pad
1238 {
1239 // serial
1240 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1241 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1242
1243 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1244 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1245 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1246
1247 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1248 temp_val|=0x04;
1249 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1250 #else
1251 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1252 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1253 temp_val|=0x07;
1254 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1255 #endif
1256 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1257 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1258 }
1259 else
1260 {
1261 //parallel
1262 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1263 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1264
1265 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1266 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1267 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1268 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1269 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1270 temp_val|=0x05;
1271 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1272 #else
1273 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1274 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1275 temp_val|=0x07;
1276 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1277 #endif
1278
1279 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1280 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1281 }
1282
1283 //DBG_INTERN_DVBT2(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1284
1285 INTERN_DVBT2_Driving_Control(INTERN_DVBT2_DTV_DRIVING_LEVEL);
1286 return status;
1287 }
1288
1289 /************************************************************************************************
1290 Subject: TS1 output control
1291 Function: INTERN_DVBT2_PAD_TS1_Enable
1292 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1293 Return: void
1294 Remark:
1295 *************************************************************************************************/
INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)1296 void INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)
1297 {
1298 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_TS1_Enable... \n"));
1299
1300 if(flag) // PAD_TS1 Enable TS CLK PAD
1301 {
1302 //printf("=== TS1_Enable ===\n");
1303 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1304 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1305 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1306 }
1307 else // PAD_TS1 Disable TS CLK PAD
1308 {
1309 //printf("=== TS1_Disable ===\n");
1310 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1311 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1312 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1313 }
1314 }
1315
1316 /************************************************************************************************
1317 Subject: channel change config
1318 Function: INTERN_DVBT2_Config
1319 Parmeter: BW: bandwidth
1320 Return: MS_BOOL :
1321 Remark:
1322 *************************************************************************************************/
INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U8 u8PlpID)1323 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID)
1324 {
1325 MS_U8 bandwidth;
1326 MS_U8 status = true;
1327 //MS_U8 temp_val;
1328 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_config %d %d %d %ld %d\n", BW, bSerialTS, u8TSClk, u32IFFreq, u8PlpID));
1329 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Config, t = %ld\n",MsOS_GetSystemTime()));
1330
1331 if (u8TSClk == 0xFF) u8TSClk=0x13;
1332 switch(BW)
1333 {
1334 case E_DMD_T2_RF_BAND_5MHz:
1335 bandwidth = 1;
1336 break;
1337 case E_DMD_T2_RF_BAND_6MHz:
1338 bandwidth = 2;
1339 break;
1340 case E_DMD_T2_RF_BAND_7MHz:
1341 bandwidth = 3;
1342 break;
1343 case E_DMD_T2_RF_BAND_10MHz:
1344 bandwidth = 5;
1345 break;
1346 case E_DMD_T2_RF_BAND_1p7MHz:
1347 bandwidth = 0;
1348 break;
1349 case E_DMD_T2_RF_BAND_8MHz:
1350 default:
1351 bandwidth = 4;
1352 break;
1353 }
1354
1355 status &= INTERN_DVBT2_Reset();
1356
1357 // BW mode
1358 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_BW, BW);
1359 // TS mode
1360 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_T2_TS_SERIAL, bSerialTS? 0x01:0x00);
1361 // FC
1362 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_L, u32IFFreq&0xff);
1363 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_H, (u32IFFreq>>8)&0xff);
1364 // PLP_ID
1365 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
1366
1367 /*
1368 if(bSerialTS)
1369 {
1370 // serial
1371 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1372 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1373
1374 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1375 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1376 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1377 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1378 temp_val|=0x04;
1379 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1380 #else
1381 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1382 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1383 temp_val|=0x07;
1384 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1385 #endif
1386 }
1387 else
1388 {
1389 //parallel
1390 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1391 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1392
1393 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1394 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1395 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1396 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1397 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1398 temp_val|=0x05;
1399 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1400 #else
1401 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1402 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1403 temp_val|=0x07;
1404 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1405 #endif
1406 }
1407 */
1408 return status;
1409 }
1410 /************************************************************************************************
1411 Subject: enable hw to lock channel
1412 Function: INTERN_DVBT2_Active
1413 Parmeter: bEnable
1414 Return: MS_BOOL
1415 Remark:
1416 *************************************************************************************************/
INTERN_DVBT2_Active(MS_BOOL bEnable)1417 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable)
1418 {
1419 MS_U8 status = true;
1420
1421 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_active\n"));
1422
1423 //// INTERN_DVBT2 Finite State Machine on/off //////////
1424 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1425
1426 INTERN_DVBT2_SignalQualityReset();
1427
1428 return status;
1429 }
1430 /************************************************************************************************
1431 Subject: Return lock status
1432 Function: INTERN_DVBT2_Lock
1433 Parmeter: eStatus :
1434 Return: MS_BOOL
1435 Remark:
1436 *************************************************************************************************/
INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout,MS_U16 u16DMD_DVBT2_FEC_Timeout)1437 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout)
1438 {
1439 float fBER=0.0f;
1440
1441 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK))
1442 {
1443 if (bFECLock == FALSE)
1444 {
1445 u32FecFirstLockTime = MsOS_GetSystemTime();
1446 DBG_INTERN_DVBT2(printf("++++++++[utopia]dvbt2 lock\n"));
1447 }
1448
1449 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1450 {
1451 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1452 {
1453 if(fLDPCBerFiltered <= 0.0)
1454 fLDPCBerFiltered = fBER;
1455 else
1456 fLDPCBerFiltered = 0.9f*fLDPCBerFiltered+0.1f*fBER;
1457 }
1458 DBG_INTERN_DVBT2(printf("[dvbt2]f_ber=%8.3e, g_ldpc_ber=%8.3e\n",fBER,fLDPCBerFiltered));
1459 }
1460 u32FecLastLockTime = MsOS_GetSystemTime();
1461 bFECLock = TRUE;
1462 return E_DMD_T2_LOCK;
1463 }
1464 else
1465 {
1466 INTERN_DVBT2_SignalQualityReset();
1467 if (bFECLock == TRUE)
1468 {
1469 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1470 {
1471 return E_DMD_T2_LOCK;
1472 }
1473 }
1474 bFECLock = FALSE;
1475 }
1476 /*
1477 #ifdef CHIP_KRITI
1478 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_NO_CHANNEL))
1479 {
1480 // DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- E_DMD_DVBT2_NO_CHANNEL \n"););
1481 return E_DMD_T2_UNLOCK;
1482 }
1483 #endif
1484 */
1485 if(!bP1Lock)
1486 {
1487 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_EVER_LOCK))
1488 {
1489 DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- P1Lock \n"));
1490 bP1Lock = TRUE;
1491 }
1492 }
1493 if(bP1Lock)
1494 {
1495 DBG_INTERN_DVBT2(printf("P1Lock %ld\n",MsOS_GetSystemTime()));
1496 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_FEC_Timeout)
1497 {
1498 return E_DMD_T2_CHECKING;
1499 }
1500 }
1501 else
1502 {
1503 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_P1_Timeout)
1504 {
1505 return E_DMD_T2_CHECKING;
1506 }
1507 }
1508 return E_DMD_T2_UNLOCK;
1509
1510 }
1511
1512
INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)1513 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)
1514 {
1515 MS_U16 u16Address = 0;
1516 MS_U8 cData = 0;
1517 MS_U8 cBitMask = 0;
1518 MS_U8 use_dsp_reg = 0;
1519
1520 switch( eStatus )
1521 {
1522 case E_DMD_DVBT2_FEC_LOCK:
1523 use_dsp_reg = 1;
1524 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //FEC lock,
1525 cBitMask = BIT(7);
1526 break;
1527
1528 case E_DMD_DVBT2_P1_LOCK:
1529 u16Address = 0x3082; //P1 HW Lock,
1530 cBitMask = BIT(3);
1531 break;
1532
1533 case E_DMD_DVBT2_DCR_LOCK:
1534 use_dsp_reg = 1;
1535 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //DCR Lock,
1536 cBitMask = BIT(2);
1537 break;
1538
1539 case E_DMD_DVBT2_AGC_LOCK:
1540 use_dsp_reg = 1;
1541 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //AGC Lock,
1542 cBitMask = BIT(0);
1543 break;
1544
1545 case E_DMD_DVBT2_MODE_DET:
1546 u16Address = 0x3082; //Mode CP Detect,
1547 cBitMask = BIT(1);
1548 break;
1549
1550 case E_DMD_DVBT2_P1_EVER_LOCK:
1551 use_dsp_reg = 1;
1552 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //P1 Ever Lock,
1553 cBitMask = BIT(5);
1554 break;
1555
1556 case E_DMD_DVBT2_L1_CRC_LOCK:
1557 u16Address = 0x2B41; //P1 Ever Lock,
1558 cBitMask = BIT(5)|BIT(6)|BIT(7);
1559 break;
1560
1561 case E_DMD_DVBT2_NO_CHANNEL:
1562 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1563 cBitMask = BIT(7);
1564 break;
1565
1566
1567 default:
1568 return FALSE;
1569 }
1570
1571 if (use_dsp_reg == 1)
1572 {
1573 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Address, &cData) == FALSE)
1574 {
1575 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1576 return FALSE;
1577 }
1578 }
1579 else
1580 {
1581 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1582 {
1583 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadReg fail \n"));
1584 return FALSE;
1585 }
1586 }
1587
1588 #ifdef MS_DEBUG
1589 MS_U8 u8tmp;
1590 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20c4, &u8tmp);
1591 DBG_INTERN_DVBT2(printf(">>>>>>>>>> DVBT2 State=%d \n", u8tmp));
1592 #endif
1593
1594 if ((cData & cBitMask) == cBitMask)
1595 {
1596 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is lock \n", eStatus));
1597 return TRUE;
1598 }
1599 else
1600 {
1601 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is unlock \n", eStatus));
1602 return FALSE;
1603 }
1604
1605 }
1606
1607 /****************************************************************************
1608 Subject: To get the Post LDPC BER
1609 Function: INTERN_DVBT2_GetPostLdpcBer
1610 Parmeter: Quility
1611 Return: E_RESULT_SUCCESS
1612 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1613 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1614 We will not read the Period, and have the "/256/8"
1615 *****************************************************************************/
INTERN_DVBT2_GetPostLdpcBer(float * ber)1616 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber)
1617 {
1618 MS_BOOL status = true;
1619 MS_U8 reg=0;
1620 MS_U16 BitErrPeriod;
1621 MS_U32 BitErr;
1622 MS_U16 FecType = 0;
1623
1624 /////////// Post-Viterbi BER /////////////
1625
1626 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1627 {
1628 *ber = (float)-1.0;
1629 return false;
1630 }
1631
1632 /////////// Data BER /////////////
1633 // bank 0x33 0x02 [0] freeze
1634 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1635
1636 // bank 0x33 0x12 Data BER Window[15:0]
1637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1638 BitErrPeriod = reg;
1639 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1640 BitErrPeriod = (BitErrPeriod << 8) | reg;
1641
1642 // bank 0x33 0x34 Data BER count[15:0]
1643 // bank 0x33 0x35 Data BER count[31:16]
1644 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1645 BitErr = reg;
1646 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1647 BitErr = (BitErr << 8) | reg;
1648 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1649 BitErr = (BitErr << 8) | reg;
1650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1651 BitErr = (BitErr << 8) | reg;
1652
1653 // bank 0x33 0x02 [0] freeze
1654 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1655
1656 if (BitErrPeriod == 0)
1657 //protect 0
1658 BitErrPeriod = 1;
1659
1660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1661 FecType = reg;
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1663 FecType = (FecType << 8) | reg;
1664
1665 if (FecType & 0x0180)
1666 {
1667 if (BitErr == 0)
1668 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1669 else
1670 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1671 }
1672 else
1673 {
1674 if (BitErr == 0)
1675 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1676 else
1677 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1678 }
1679
1680 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1681
1682 if (status == FALSE)
1683 {
1684 printf("INTERN_DVBT2_GetPostLdpcBer Fail!\n");
1685 return FALSE;
1686 }
1687
1688 return status;
1689 }
1690
1691 /****************************************************************************
1692 Subject: To get the Pre LDPC BER
1693 Function: INTERN_DVBT2_GetPreLdpcBer
1694 Parmeter: ber
1695 Return: E_RESULT_SUCCESS
1696 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1697 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1698 We will not read the Period, and have the "/256/8"
1699 *****************************************************************************/
INTERN_DVBT2_GetPreLdpcBer(float * ber)1700 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber)
1701 {
1702 MS_U8 status = true;
1703 MS_U8 reg=0;
1704 MS_U16 BitErrPeriod;
1705 MS_U32 BitErr;
1706 MS_U16 FecType = 0;
1707
1708 /////////// Data BER /////////////
1709 // bank 0x33 0x02 [0] freeze
1710 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1711
1712 // bank 0x33 0x12 Data BER Window[15:0]
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1714 BitErrPeriod = reg;
1715 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1716 BitErrPeriod = (BitErrPeriod << 8) | reg;
1717
1718 // bank 0x33 0x34 Data BER count[15:0]
1719 // bank 0x33 0x35 Data BER count[31:16]
1720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1721 BitErr = reg;
1722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1723 BitErr = (BitErr << 8) | reg;
1724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1725 BitErr = (BitErr << 8) | reg;
1726 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1727 BitErr = (BitErr << 8) | reg;
1728
1729 // bank 0x33 0x02 [0] freeze
1730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1731
1732 if (BitErrPeriod == 0)
1733 //protect 0
1734 BitErrPeriod = 1;
1735
1736 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1737 FecType = reg;
1738 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1739 FecType = (FecType << 8) | reg;
1740
1741 if (FecType & 0x0180)
1742 {
1743 if (BitErr == 0)
1744 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1745 else
1746 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1747 }
1748 else
1749 {
1750 if (BitErr == 0)
1751 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1752 else
1753 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1754 }
1755
1756 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1757
1758 if (status == FALSE)
1759 {
1760 printf("INTERN_DVBT2_GetPreLdpcBer Fail!\n");
1761 return FALSE;
1762 }
1763
1764 return status;
1765 }
1766
1767 /****************************************************************************
1768 Subject: To get the Packet error
1769 Function: INTERN_DVBT2_GetPacketErr
1770 Parmeter: pktErr
1771 Return: E_RESULT_SUCCESS
1772 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1773 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1774 We will not read the Period, and have the "/256/8"
1775 *****************************************************************************/
INTERN_DVBT2_GetPacketErr(MS_U16 * u16PktErr)1776 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr)
1777 {
1778 MS_BOOL status = true;
1779 MS_U8 reg = 0;
1780 MS_U16 PktErr;
1781
1782 //freeze
1783 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01);
1784 //read packet error
1785 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5B, ®);
1786 PktErr = reg;
1787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5A, ®);
1788 PktErr = (PktErr << 8) | reg;
1789
1790 *u16PktErr = PktErr;
1791 //release
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00);
1793
1794 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PktErr = %d \n ", (int)PktErr));
1795
1796 *u16PktErr = PktErr;
1797
1798 return status;
1799 }
1800
1801 /****************************************************************************
1802 Subject: To get the DVBT2 parameter
1803 Function: INTERN_DVBT2_Get_L1_Info
1804 Parmeter: point to return parameter
1805 Return: TRUE
1806 FALSE
1807 Remark: The TPS parameters will be available after TPS lock
1808 *****************************************************************************/
INTERN_DVBT2_Get_L1_Parameter(MS_U16 * pu16L1_parameter,DMD_DVBT2_SIGNAL_INFO eSignalType)1809 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType)
1810 {
1811 MS_U8 u8Data = 0;
1812 MS_U16 FecType = 0;
1813
1814 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
1815 {
1816 if (eSignalType == T2_MODUL_MODE)
1817 {
1818 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1819 return FALSE;
1820
1821 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(5) | BIT(4) | BIT(3))) >> 3;
1822 }
1823 else if (eSignalType == T2_CODE_RATE)
1824 {
1825 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1826 {
1827 return FALSE;
1828 }
1829 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1830 }
1831 else if (eSignalType == T2_PREAMBLE)
1832 {
1833 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1834 {
1835 return FALSE;
1836 }
1837 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(4))) >> 4;
1838 }
1839 else if (eSignalType == T2_S1_SIGNALLING)
1840 {
1841 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1842 {
1843 return FALSE;
1844 }
1845 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(3) | BIT(2) | BIT(1))) >> 1;
1846 }
1847 else if (eSignalType == T2_PILOT_PATTERN)
1848 {
1849 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE)
1850 {
1851 return FALSE;
1852 }
1853 *pu16L1_parameter = (((MS_U16) u8Data) & 0x0F);
1854 }
1855 else if (eSignalType == T2_BW_EXT)
1856 {
1857 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1858 {
1859 return FALSE;
1860 }
1861 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(0)));
1862 }
1863 else if (eSignalType == T2_PAPR_REDUCTION)
1864 {
1865 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2), &u8Data) == FALSE)
1866 {
1867 return FALSE;
1868 }
1869 *pu16L1_parameter = (((MS_U16) u8Data) & 0xF0) >> 4;
1870 }
1871 else if (eSignalType == T2_OFDM_SYMBOLS_PER_FRAME)
1872 {
1873 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2), &u8Data) == FALSE)
1874 {
1875 return FALSE;
1876 }
1877 *pu16L1_parameter = (MS_U16) u8Data;
1878 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2) + 1, &u8Data) == FALSE)
1879 {
1880 return FALSE;
1881 }
1882 *pu16L1_parameter |= (((MS_U16) u8Data) & 0x0F) << 8;
1883 }
1884 else if (eSignalType == T2_PLP_ROTATION)
1885 {
1886 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1887 {
1888 return FALSE;
1889 }
1890 *pu16L1_parameter = (((MS_U16) u8Data) & BIT(6)) >> 6;
1891 }
1892 else if (eSignalType == T2_PLP_FEC_TYPE)
1893 {
1894 //FEC Type[8:7]
1895 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8f, &u8Data) == FALSE) return FALSE;
1896 FecType = u8Data;
1897 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8e, &u8Data) == FALSE) return FALSE;
1898 FecType = (FecType << 8) | u8Data;
1899
1900 *pu16L1_parameter = (FecType & 0x0180) >> 7;
1901 }
1902 else if (eSignalType == T2_NUM_PLP)
1903 {
1904 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x42 * 2), &u8Data) == FALSE)
1905 {
1906 return FALSE;
1907 }
1908 *pu16L1_parameter = (MS_U16)u8Data;
1909 }
1910 else
1911 {
1912 return FALSE;
1913 }
1914
1915 return TRUE;
1916
1917 }
1918
1919 return FALSE;
1920 }
1921
1922
1923 /****************************************************************************
1924 Subject: Read the signal to noise ratio (SNR)
1925 Function: INTERN_DVBT2_GetSNR
1926 Parmeter: None
1927 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1928 Remark:
1929 *****************************************************************************/
INTERN_DVBT2_GetSNR(void)1930 float INTERN_DVBT2_GetSNR (void)
1931 {
1932 MS_U8 status = true;
1933 MS_U8 reg=0, reg_frz=0;
1934 MS_U16 u16_snr100 = 0;
1935 float f_snr;
1936 MS_U8 u8_win = 0;
1937 MS_U8 u8_gi = 0;
1938
1939 // freeze
1940 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
1941 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
1942
1943 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
1944 u16_snr100 = reg;
1945 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
1946 u16_snr100 = (u16_snr100<<8)|reg;
1947
1948 // unfreeze
1949 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
1950
1951 f_snr = (float)u16_snr100/100.0;
1952
1953 // snr cali
1954 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
1955 u8_win = (reg>>2)&0x01;
1956
1957 if (u8_win == 1)
1958 {
1959 float snr_offset = 0.0;
1960 float snr_cali = 0.0;
1961
1962 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
1963 u8_gi = (reg>>1)&0x07;
1964
1965 if (u8_gi == 0) snr_offset = 0.157;
1966 else if(u8_gi == 1) snr_offset = 0.317;
1967 else if(u8_gi == 2) snr_offset = 0.645;
1968 else if(u8_gi == 3) snr_offset = 1.335;
1969 else if(u8_gi == 4) snr_offset = 0.039;
1970 else if(u8_gi == 5) snr_offset = 0.771;
1971 else if(u8_gi == 6) snr_offset = 0.378;
1972
1973 snr_cali = f_snr - snr_offset;
1974 if (snr_cali > 0.0) f_snr = snr_cali;
1975 }
1976 //use Polynomial curve fitting to fix snr
1977 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
1978 //f_snr = f_snr + snr_poly;
1979
1980 if (status == true)
1981 return f_snr;
1982 else
1983 return -1;
1984
1985 }
1986
INTERN_DVBT2_GetSignalStrength(MS_U16 * strength,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1987 MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength,const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1988 {
1989 MS_U8 status = true;
1990 float ch_power_db = 0.0f;
1991 float ch_power_ref = 11.0f;
1992 float ch_power_rel = 0.0f;
1993 //MS_U8 u8_index = 0;
1994 MS_U16 L1_info_qam, L1_info_cr;
1995 MS_U8 demodState = 0;
1996
1997 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
1998 {
1999 *strength = 0;
2000 return TRUE;
2001 }
2002 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2003
2004 // if (INTERN_DVBT2_Lock(COFDM_TPS_LOCK))
2005 //if (INTERN_DVBT2_Lock(COFDM_AGC_LOCK))
2006 /* Actually, it's more reasonable, that signal level depended on cable input power level
2007 * thougth the signal isn't dvb-t signal.
2008 */
2009
2010 // use pointer of IFAGC table to identify
2011 // case 1: RFAGC from SAR, IFAGC controlled by demod
2012 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2013 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2014 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
2015 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2016 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2017 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
2018 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
2019
2020
2021 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2022 printf("[dvbt2] QAM parameter retrieve failure\n");
2023
2024 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2025 printf("[dvbt2]code rate parameter retrieve failure\n");
2026
2027 /*
2028 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2029 {
2030 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
2031 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
2032 {
2033 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2034 break;
2035 }
2036 else
2037 {
2038 u8_index++;
2039 }
2040 }
2041 */
2042 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
2043
2044 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBTM_REG_BASE + (0x78*2), &demodState);
2045
2046 if (ch_power_ref > 10.0f)
2047 *strength = 0;
2048 else
2049 {
2050 if (demodState != 0x09)
2051 {
2052 ch_power_rel = ch_power_db - (-50.0f);
2053 }
2054 else
2055 {
2056 ch_power_rel = ch_power_db - ch_power_ref;
2057 }
2058
2059 if ( ch_power_rel < -15.0f )
2060 {
2061 *strength = 0;
2062 }
2063 else if ( ch_power_rel < 0.0f )
2064 {
2065 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2066 }
2067 else if ( ch_power_rel < 20 )
2068 {
2069 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2070 }
2071 else if ( ch_power_rel < 35.0f )
2072 {
2073 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2074 }
2075 else
2076 {
2077 *strength = 100;
2078 }
2079 }
2080
2081 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2082 {
2083 *strength = 0;
2084 return TRUE;
2085 }
2086
2087 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2088 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2089
2090 return status;
2091 }
2092
2093 /****************************************************************************
2094 Subject: To get the DVT Signal quility
2095 Function: INTERN_DVBT2_GetSignalQuality
2096 Parmeter: Quility
2097 Return: E_RESULT_SUCCESS
2098 E_RESULT_FAILURE
2099 Remark: Here we have 4 level range
2100 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
2101 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
2102 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
2103 <4>.4th Range => Quality <10
2104 *****************************************************************************/
INTERN_DVBT2_GetSignalQuality(MS_U16 * quality,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2105 MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2106 {
2107 float ber_sqi, SQI;
2108 float fber;
2109 float cn_rec = 0;
2110 float cn_ref = 0;
2111 float cn_rel = 0;
2112
2113 MS_U8 status = true;
2114 MS_U16 L1_info_qam = 0, L1_info_cr = 0, i = 0;
2115
2116 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2117
2118 if (TRUE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_LOCK) )
2119 {
2120
2121 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2122 {
2123 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2124 }
2125 ///////// Get Pre-BCH (Post-LDPC) BER to determine BER_SQI //////////
2126 if(fLDPCBerFiltered<= 0.0)
2127 {
2128 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2129 {
2130 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2131 return FALSE;
2132 }
2133 fLDPCBerFiltered = fber;
2134 }
2135 else
2136 {
2137 fber = fLDPCBerFiltered;
2138 }
2139 /*
2140 if (fber > 1.0E-3)
2141 ber_sqi = 0.0;
2142 else if (fber > 8.5E-7)
2143 #ifdef MSOS_TYPE_LINUX
2144 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2145 #else
2146 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2147 #endif
2148 else
2149 ber_sqi = 100.0;
2150 */
2151 if (fber > 1E-4)
2152 ber_sqi = 0.0;
2153 else if (fber >= 1E-7)
2154 ber_sqi = 100.0 / 15;
2155 else
2156 ber_sqi = 100.0 / 6;
2157
2158 cn_rec = INTERN_DVBT2_GetSNR();
2159
2160 if (cn_rec == -1) //get SNR return fail
2161 status = false;
2162
2163 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2164 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2165 L1_info_qam = 0xff;
2166 L1_info_cr = 0xff;
2167
2168 cn_ref = (float)-1.0;
2169 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2170 printf("[dvbt2] QAM parameter retrieve failure\n");
2171
2172 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2173 printf("[dvbt2]code rate parameter retrieve failure\n");
2174
2175 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2176 {
2177 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2178 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2179 {
2180 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2181 break;
2182 }
2183 }
2184
2185 if (cn_ref == -1.0)
2186 SQI = (float)0.0;
2187 else
2188 {
2189 cn_rel = cn_rec - cn_ref;
2190 if (cn_rel > 3.0)
2191 SQI = 100;
2192 else if (cn_rel >= -3)
2193 {
2194 SQI = (cn_rel+3)*ber_sqi;
2195 if (SQI > 100.0) SQI = 100.0;
2196 else if (SQI < 0.0) SQI = 0.0;
2197 }
2198 else
2199 SQI = (float)0.0;
2200 }
2201
2202 // SQI patch, 256qam, R3/4 CN=20.8, SQI=0~13
2203 if ((L1_info_qam==_T2_256QAM) && (L1_info_cr==_T2_CR3Y4))
2204 {
2205 if ( (cn_rec > 20.6) && (cn_rec < 20.9))
2206 {
2207 if (SQI > 3) SQI -= 3;
2208 }
2209 else if ( (cn_rec >= 20.9) && (cn_rec < 21.2))
2210 {
2211 if (SQI > 9) SQI -= 9;
2212 }
2213 }
2214
2215 *quality = (MS_U16)SQI;
2216 }
2217 else
2218 {
2219 *quality = 0;
2220 }
2221
2222 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
2223 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2224 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2225 return status;
2226 }
2227
2228 /****************************************************************************
2229 Subject: To get the DVBT Carrier Freq Offset
2230 Function: INTERN_DVBT2_Get_FreqOffset
2231 Parmeter: Frequency offset (in KHz), bandwidth
2232 Return: E_RESULT_SUCCESS
2233 E_RESULT_FAILURE
2234 Remark:
2235 *****************************************************************************/
INTERN_DVBT2_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2236 MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2237 {
2238 float N, FreqB;
2239 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2240 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2241 MS_U8 reg_frz=0, reg=0;
2242 MS_U8 status;
2243
2244 FreqB = (float)u8BW * 8 / 7;
2245
2246 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2247
2248 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2249
2250 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2251 RegCfoTd = reg;
2252
2253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2254 RegCfoTd = (RegCfoTd << 8)|reg;
2255
2256 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2257 RegCfoTd = (RegCfoTd << 8)|reg;
2258
2259 FreqCfoTd = (float)RegCfoTd;
2260
2261 if (RegCfoTd & 0x800000)
2262 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2263
2264 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2265
2266 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2267
2268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2269 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2270
2271 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2272
2273 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2274 RegCfoFd = reg;
2275
2276 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2277 RegCfoFd = (RegCfoFd << 8)|reg;
2278
2279 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2280 RegCfoFd = (RegCfoFd << 8)|reg;
2281
2282 FreqCfoFd = (float)RegCfoFd;
2283
2284 if (RegCfoFd & 0x800000)
2285 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2286
2287 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2288
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2290 RegIcfo = reg & 0x07;
2291
2292 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2293 RegIcfo = (RegIcfo << 8)|reg;
2294
2295 FreqIcfo = (float)RegIcfo;
2296
2297 if (RegIcfo & 0x400)
2298 FreqIcfo = FreqIcfo - (float)0x800;
2299
2300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2301 reg = reg & 0x30;
2302
2303 switch (reg)
2304 {
2305 case 0x00: N = 2048; break;
2306 case 0x20: N = 4096; break;
2307 case 0x10:
2308 default: N = 8192; break;
2309 }
2310
2311 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2312 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2313 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2314 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2315 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2316 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2317 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2318 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2319 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2320 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2321
2322 if (status == TRUE)
2323 return TRUE;
2324 else
2325 return FALSE;
2326 }
2327
2328
INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)2329 void INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)
2330 {
2331
2332 bPowerOn = bPowerOn;
2333 }
2334
INTERN_DVBT2_Power_Save(void)2335 MS_BOOL INTERN_DVBT2_Power_Save(void)
2336 {
2337
2338 return TRUE;
2339 }
2340
INTERN_DVBT2_Version(MS_U16 * ver)2341 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver)
2342 {
2343
2344 MS_U8 status = true;
2345 MS_U8 tmp = 0;
2346 MS_U16 u16_INTERN_DVBT2_Version;
2347
2348 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2349 u16_INTERN_DVBT2_Version = tmp;
2350 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2351 u16_INTERN_DVBT2_Version = u16_INTERN_DVBT2_Version<<8|tmp;
2352 *ver = u16_INTERN_DVBT2_Version;
2353
2354 return status;
2355 }
2356
INTERN_DVBT2_Version_minor(MS_U8 * ver2)2357 MS_BOOL INTERN_DVBT2_Version_minor(MS_U8 *ver2)
2358 {
2359
2360 MS_U8 status = true;
2361
2362 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2363
2364 return status;
2365 }
2366
2367
INTERN_DVBT2_Show_Demod_Version(void)2368 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void)
2369 {
2370
2371 MS_BOOL status = true;
2372 MS_U16 u16_INTERN_DVBT2_Version = 0;
2373 MS_U8 u8_minor_ver = 0;
2374
2375 status &= INTERN_DVBT2_Version(&u16_INTERN_DVBT2_Version);
2376 status &= INTERN_DVBT2_Version_minor(&u8_minor_ver);
2377 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT2_Version,u8_minor_ver);
2378
2379 return status;
2380 }
2381
INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float write_value)2382 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
2383 {
2384 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
2385 return TRUE;
2386 /*
2387 MS_U8 u8_index = 0;
2388 MS_BOOL bRet = false;
2389
2390 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2391 {
2392 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2393 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2394 {
2395 dvbt2_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2396 bRet = true;
2397 break;
2398 }
2399 else
2400 {
2401 u8_index++;
2402 }
2403 }
2404 return bRet;
2405 */
2406 }
2407
INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float * read_value)2408 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
2409 {
2410 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
2411 return TRUE;
2412 /*
2413 MS_U8 u8_index = 0;
2414 MS_BOOL bRet = false;
2415
2416 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2417 {
2418 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2419 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2420 {
2421 *read_value = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2422 bRet = true;
2423 break;
2424 }
2425 else
2426 {
2427 u8_index++;
2428 }
2429 }
2430 return bRet;
2431 */
2432 }
2433
INTERN_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)2434 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
2435 {
2436 MS_BOOL status = TRUE;
2437 MS_U8 u8Data = 0;
2438 MS_U8 indx = 0;
2439
2440 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_GetPlpBitMap\n"));
2441
2442 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2443 if (u8Data != 0x30)
2444 return FALSE;
2445
2446 while (indx < 32)
2447 {
2448 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_PLP_ID_ARR + indx, &u8Data);
2449 u8PlpBitMap[indx] = u8Data;
2450 indx++;
2451 }
2452
2453 if (status)
2454 {
2455 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap data+++++++++++++++\n"));
2456 for (indx = 0; indx < 32; indx++)
2457 DBG_INTERN_DVBT2(printf("[%d] ", u8PlpBitMap[indx]));
2458 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap end+++++++++++++++\n"));
2459 }
2460 return status;
2461 }
2462
INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)2463 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
2464 {
2465 MS_BOOL status = TRUE;
2466 MS_U8 u8Data = 0;
2467 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2468 if (u8Data != 0x30)
2469 {
2470 printf(">>>dvbt2 L1 not ready yet\n");
2471 return FALSE;
2472 }
2473 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_DVBT2_LOCK_HIS, &u8Data);
2474
2475 if ((u8Data & BIT(7)) == 0x00)
2476 {
2477 printf(">>>dvbt2 is un-lock\n");
2478 return FALSE;
2479 }
2480 // assign PLP-ID value
2481 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x78) * 2, u8PlpID);
2482 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x01); // MEM_EN
2483 MsOS_DelayTask(1);
2484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x79) * 2, u8GroupID);
2485 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x00); // ~MEM_EN
2486
2487 return status;
2488 }
2489
INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID,MS_U8 u8GroupID)2490 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID)
2491 {
2492 MS_BOOL status = TRUE;
2493
2494 // assign Group-ID and PLP-ID value (must be written in order)
2495 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_GROUP_ID, u8GroupID);
2496 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
2497
2498 return status;
2499 }
2500
2501 #if (INTERN_DVBT2_INTERNAL_DEBUG == 1)
INTERN_DVBT2_get_demod_state(MS_U8 * state)2502 void INTERN_DVBT2_get_demod_state(MS_U8* state)
2503 {
2504 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2505 return;
2506 }
2507
INTERN_DVBT2_Show_ChannelLength(void)2508 MS_BOOL INTERN_DVBT2_Show_ChannelLength(void)
2509 {
2510 MS_U8 status = true;
2511 MS_U8 tmp = 0;
2512 MS_U16 len = 0;
2513 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2514 len = tmp;
2515 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2516 len = (len<<8)|tmp;
2517 printf("[dvbt]Hw_channel=%d\n",len);
2518 return status;
2519 }
2520
INTERN_DVBT2_Show_SW_ChannelLength(void)2521 MS_BOOL INTERN_DVBT2_Show_SW_ChannelLength(void)
2522 {
2523 MS_U8 status = true;
2524 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2525 MS_U16 sw_len = 0;
2526 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2527 sw_len = tmp;
2528 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2529 sw_len = (sw_len<<8)|tmp;
2530 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2531 peak_num = tmp;
2532 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2533 insideGI = tmp&0x01;
2534 stoptracking = (tmp&0x02)>>1;
2535 flag_short_echo = (tmp&0x0C)>>2;
2536 fsa_mode = (tmp&0x30)>>4;
2537
2538 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2539 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2540
2541 return status;
2542 }
2543
INTERN_DVBT2_Show_ACI_CI(void)2544 MS_BOOL INTERN_DVBT2_Show_ACI_CI(void)
2545 {
2546
2547 #define BIT4 0x10
2548 MS_U8 status = true;
2549 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2550
2551 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2552 digACI = (tmp&BIT4)>>4;
2553
2554 // get flag_CI
2555 // 0: No interference
2556 // 1: CCI
2557 // 2: in-band ACI
2558 // 3: N+1 ACI
2559 // flag_ci = (tmp&0xc0)>>6;
2560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2561 flag_CI = (tmp&0xC0)>>6;
2562 td_coef = (tmp&0x0C)>>2;
2563
2564 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2565
2566 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2567
2568 return status;
2569 }
2570
INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)2571 MS_BOOL INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)
2572 {
2573 MS_U8 status = true;
2574 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2575 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2576 fd = tmp;
2577 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2578 ch_len = tmp;
2579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2580 snr_sel = (tmp>>4)&0x03;
2581 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2582 pertone_num = tmp;
2583
2584 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2585
2586 return status;
2587 }
2588
INTERN_DVBT2_Get_CFO(void)2589 MS_BOOL INTERN_DVBT2_Get_CFO(void)
2590 {
2591
2592 float N = 0, FreqB = 0;
2593 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2594 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2595 MS_U8 reg_frz = 0, reg = 0;
2596 MS_U8 status = 0;
2597 MS_U8 u8BW = 8;
2598
2599 FreqB = (float)u8BW * 8 / 7;
2600
2601 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2602
2603 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2604
2605 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2606 RegCfoTd = reg;
2607
2608 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2609 RegCfoTd = (RegCfoTd << 8)|reg;
2610
2611 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2612 RegCfoTd = (RegCfoTd << 8)|reg;
2613
2614 FreqCfoTd = (float)RegCfoTd;
2615
2616 if (RegCfoTd & 0x800000)
2617 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2618
2619 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2620
2621 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2622
2623 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2624 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2625
2626 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2627
2628 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2629 RegCfoFd = reg;
2630
2631 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2632 RegCfoFd = (RegCfoFd << 8)|reg;
2633
2634 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2635 RegCfoFd = (RegCfoFd << 8)|reg;
2636
2637 FreqCfoFd = (float)RegCfoFd;
2638
2639 if (RegCfoFd & 0x800000)
2640 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2641
2642 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2643
2644 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2645 RegIcfo = reg & 0x07;
2646
2647 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2648 RegIcfo = (RegIcfo << 8)|reg;
2649
2650 FreqIcfo = (float)RegIcfo;
2651
2652 if (RegIcfo & 0x400)
2653 FreqIcfo = FreqIcfo - (float)0x800;
2654
2655 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2656 reg = reg & 0x30;
2657
2658 switch (reg)
2659 {
2660 case 0x00: N = 2048; break;
2661 case 0x20: N = 4096; break;
2662 case 0x10:
2663 default: N = 8192; break;
2664 }
2665
2666 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2667 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2668 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2669 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2670 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2671
2672 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2673
2674 return status;
2675
2676 }
INTERN_DVBT2_Get_SFO(void)2677 MS_BOOL INTERN_DVBT2_Get_SFO(void)
2678 {
2679 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2680 MS_BOOL status = true;
2681 MS_U8 reg = 0;
2682 float FreqB = 9.143, FreqS = 45.473; //20.48
2683 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2684 float sfo_value = 0;
2685
2686 // get Reg_TDP_SFO,
2687 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2688 Reg_TDP_SFO = reg;
2689 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2690 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2692 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2693
2694 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2695
2696 // get Reg_FDP_SFO,
2697 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2698 Reg_FDP_SFO = reg;
2699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2700 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2702 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2703
2704 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2705
2706 // get Reg_FSA_SFO,
2707 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2708 Reg_FSA_SFO = reg;
2709 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2710 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2712 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2713
2714 // get Reg_FSA_IN,
2715 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2716 Reg_FSA_IN = reg;
2717 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2718 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2719 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2720
2721 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2722 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2723
2724 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2725 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2726 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2727
2728
2729 return status;
2730 }
2731
INTERN_DVBT2_Get_SYA_status(void)2732 void INTERN_DVBT2_Get_SYA_status(void)
2733 {
2734 MS_U8 status = true;
2735 MS_U8 sya_k = 0,reg = 0;
2736 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2737
2738 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2739 sya_k = reg;
2740
2741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2742 sya_th = reg;
2743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2744 sya_th = (sya_th<<8)|reg;
2745
2746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2747 sya_offset = reg;
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2749 sya_offset = (sya_offset<<8)|reg;
2750
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2752 len_m = reg;
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2754 len_m = (len_m<<8)|reg;
2755
2756 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2757 len_b = reg;
2758 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2759 len_b = (len_b<<8)|reg;
2760
2761
2762 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2763 len_a = reg;
2764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2765 len_a = (len_a<<8)|reg;
2766
2767
2768 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2769 tracking_reg = reg;
2770
2771
2772 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2773 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2774
2775 return;
2776 }
2777
INTERN_DVBT2_Get_cci_status(void)2778 void INTERN_DVBT2_Get_cci_status(void)
2779 {
2780 MS_U8 status = true;
2781 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2782
2783 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2784 cci_fsweep = reg;
2785
2786 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2787 cci_kp = reg;
2788
2789 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2790
2791 return;
2792 }
2793
INTERN_DVBT2_Show_PRESFO_Info(void)2794 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void)
2795 {
2796 MS_U8 tmp = 0;
2797 MS_BOOL status = TRUE;
2798 printf("\n[SFO]");
2799 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2800 printf("[%x]",tmp);
2801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2802 printf("[%x]",tmp);
2803 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2804 printf("[%x]",tmp);
2805 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2806 printf("[%x]",tmp);
2807 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2808 printf("[%x]",tmp);
2809 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2810 printf("[%x]",tmp);
2811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2812 printf("[%x]",tmp);
2813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2814 printf("[%x][End]",tmp);
2815
2816 return status;
2817 }
2818
INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 * locktime)2819 MS_BOOL INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 *locktime)
2820 {
2821 MS_BOOL status = true;
2822
2823 *locktime = 0xffff;
2824 printf("[dvbt]INTERN_DVBT2_Get_Lock_Time_Info not implement\n");
2825
2826 status = false;
2827 return status;
2828 }
2829
2830
INTERN_DVBT2_Show_Lock_Time_Info(void)2831 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void)
2832 {
2833 MS_U16 locktime = 0;
2834 MS_BOOL status = TRUE;
2835 status &= INTERN_DVBT2_Get_Lock_Time_Info(&locktime);
2836 printf("[DVBT]lock_time = %d ms\n",locktime);
2837 return status;
2838 }
2839
INTERN_DVBT2_Show_BER_Info(void)2840 MS_BOOL INTERN_DVBT2_Show_BER_Info(void)
2841 {
2842 MS_U8 tmp = 0;
2843 MS_BOOL status = TRUE;
2844 printf("\n[BER]");
2845 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2846 printf("[%x,",tmp);
2847 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2848 printf("%x]",tmp);
2849 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2850 printf("[%x,",tmp);
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2852 printf("%x]",tmp);
2853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2854 printf("[%x,",tmp);
2855 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2856 printf("%x][End]",tmp);
2857
2858 return status;
2859
2860 }
2861
2862
INTERN_DVBT2_Show_AGC_Info(void)2863 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void)
2864 {
2865 MS_U8 tmp = 0;
2866 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2867 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2868 MS_U16 if_agc_err = 0;
2869 MS_BOOL status = TRUE;
2870 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2871
2872 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2873 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2874 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2876 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2878
2879
2880 // select IF gain to read
2881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2882 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2883
2884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2885 if_agc_gain = tmp;
2886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2887 if_agc_gain = (if_agc_gain<<8)|tmp;
2888
2889
2890 // select d1 gain to read.
2891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2892 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2893
2894 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2895 d1_gain = tmp;
2896 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2897 d1_gain = (d1_gain<<8)|tmp;
2898
2899 // select d2 gain to read.
2900 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2901 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2902
2903 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2904 d2_gain = tmp;
2905 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
2906 d2_gain = (d2_gain<<8)|tmp;
2907
2908 // select IF gain err to read
2909 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2910 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
2911
2912 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2913 if_agc_err = tmp;
2914 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2915 if_agc_err = (if_agc_err<<8)|tmp;
2916
2917 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
2918 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
2919 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
2920
2921
2922
2923 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2924 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2925
2926 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2927 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
2928
2929 return status;
2930
2931 }
2932
INTERN_DVBT2_Show_WIN_Info(void)2933 MS_BOOL INTERN_DVBT2_Show_WIN_Info(void)
2934 {
2935 MS_U8 tmp = 0;
2936 MS_U8 trigger = 0;
2937 MS_U16 win_len = 0;
2938
2939 MS_BOOL status = TRUE;
2940
2941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
2942 win_len = tmp;
2943 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
2944 win_len = (win_len<<8)|tmp;
2945
2946 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
2947
2948 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
2949
2950 return status;
2951 }
2952
INTERN_DVBT2_Show_td_coeff(void)2953 void INTERN_DVBT2_Show_td_coeff(void)
2954 {
2955 MS_U8 status = true;
2956 MS_U8 w1 = 0,w2 = 0,reg = 0;
2957
2958 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
2959 w1 = reg;
2960
2961 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
2962 w2 = reg;
2963
2964 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
2965
2966 return;
2967 }
2968
2969 /********************************************************
2970 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM
2971 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
2972 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256
2973 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE
2974 *Preamble(b12) : 0~1 => mixed, not_mixed
2975 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved
2976 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8
2977 *BW_Extend(b19) : 0~1 => normal, extension
2978 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved
2979 ********************************/
INTERN_DVBT2_Show_Modulation_info(void)2980 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void)
2981 {
2982 MS_BOOL bRet = TRUE;
2983 MS_U16 u16Data = 0;
2984
2985 char* cConStr[] = {"qpsk", "16qam", "64qam", "256qam"};
2986 char* cCRStr[] = {"1_2", "3_5", "2_3", "3_4", "4_5", "5_6"};
2987 char* cGIStr[] = {"1_32", "1_16", "1_8", "1_4", "1_128", "19_128", "19_256"};
2988 char* cFFTStr[] = {"2k", "8k", "4k", "1k", "16k", "32k", "8k", "32k"};
2989 char* cPreAStr[] = {"mixed", "not_mixed"};
2990 char* cS1SStr[] = {"t2_siso", "t2_miso", "non_t2", "reserved"};
2991 char* cPPSStr[] = {"PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", "PP8", "reserved"};
2992 char* cBWStr[] = {"normal", "extension"};
2993 char* cPAPRStr[] = {"none", "ace", "tr", "tr_and_ace", "reserved"};
2994
2995 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
2996 {
2997
2998 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_MODUL_MODE) == FALSE)
2999 {
3000 printf("T2_MODUL_MODE Error!\n");
3001 bRet = FALSE;
3002 }
3003 u16Data &= 0x07;
3004 //*L1_Info = (MS_U64)(u16Data);
3005 printf("T2 Constellation:%s\n", cConStr[u16Data]);
3006
3007 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_CODE_RATE) == FALSE)
3008 {
3009 printf(("T2_CODE_RATE Error!\n"));
3010 bRet = FALSE;
3011 }
3012 u16Data &= 0x07;
3013 //*L1_Info |= (MS_U64)(u16Data << 3);
3014 printf("T2 Code Rate:%s\n", cCRStr[u16Data]);
3015
3016 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_GUARD_INTERVAL) == FALSE)
3017 {
3018 printf("T2_GUARD_INTERVAL Error!\n");
3019 bRet = FALSE;
3020 }
3021 u16Data &= 0x07;
3022 //*L1_Info |= (MS_U64)(u16Data << 6);
3023 printf("T2 GI:%s\n", cGIStr[u16Data]);
3024
3025 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_FFT_VALUE) == FALSE)
3026 {
3027 printf("T2_FFT_VALUE Error!\n");
3028 bRet = FALSE;
3029 }
3030 u16Data &= 0x07;
3031 //*L1_Info |= (MS_U64)(u16Data << 9);
3032 printf("T2 FFT:%s\n", cFFTStr[u16Data]);
3033
3034 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PREAMBLE) == FALSE)
3035 {
3036 printf("T2_PREAMBLE Error!\n");
3037 bRet = FALSE;
3038 }
3039 u16Data &= 0x01;
3040 //*L1_Info |= (MS_U64)(u16Data << 12);
3041 printf("Preamble:%s\n", cPreAStr[u16Data]);
3042
3043 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_S1_SIGNALLING) == FALSE)
3044 {
3045 printf("T2_S1_SIGNALLING Error!\n");
3046 bRet = FALSE;
3047 }
3048 u16Data &= 0x03;
3049 if (u16Data > 2)
3050 u16Data = 3;
3051 //*L1_Info |= (MS_U64)(u16Data << 13);
3052 printf("S1 Signalling:%s\n", cS1SStr[u16Data]);
3053
3054 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PILOT_PATTERN) == FALSE)
3055 {
3056 printf("T2_PILOT_PATTERN Error!\n");
3057 bRet = FALSE;
3058 }
3059 u16Data &= 0x0F;
3060 if (u16Data > 7)
3061 u16Data = 8;
3062 //*L1_Info |= (MS_U64)(u16Data << 15);
3063 printf("PilotPattern:%s\n", cPPSStr[u16Data]);
3064
3065 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_BW_EXT) == FALSE)
3066 {
3067 printf("T2_BW_EXT Error!\n");
3068 bRet = FALSE;
3069 }
3070 u16Data &= 0x01;
3071 //*L1_Info |= (MS_U64)(u16Data << 19);
3072 printf("BW EXT:%s\n", cBWStr[u16Data]);
3073
3074 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PAPR_REDUCTION) == FALSE)
3075 {
3076 printf("T2_PAPR_REDUCTION Error!\n");
3077 bRet = FALSE;
3078 }
3079 u16Data &= 0x07;
3080 if (u16Data > 3)
3081 u16Data = 4;
3082 //*L1_Info |= (MS_U64)(u16Data << 20);
3083 printf("T2 PAPR:%s\n", cPAPRStr[u16Data]);
3084
3085 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_OFDM_SYMBOLS_PER_FRAME) == FALSE)
3086 {
3087 printf("T2_OFDM_SYMBOLS_PER_FRAME Error!\n");
3088 bRet = FALSE;
3089 }
3090 u16Data &= 0xFFF;
3091 //*L1_Info |= (MS_U64)(u16Data << 23);
3092 printf("T2 OFDM Symbols:%u\n", u16Data);
3093 }
3094 else
3095 {
3096 printf("INVALID\n");
3097 return FALSE;
3098 }
3099
3100 return bRet;
3101
3102 }
3103
3104
INTERN_DVBT2_Show_BER_PacketErr(void)3105 void INTERN_DVBT2_Show_BER_PacketErr(void)
3106 {
3107 float f_ber = 0;
3108 MS_U16 packetErr = 0;
3109 INTERN_DVBT2_GetPostLdpcBer(&f_ber);
3110 INTERN_DVBT2_GetPacketErr(&packetErr);
3111
3112 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3113 return;
3114 }
3115
INTERN_DVBT2_Show_Lock_Info(void)3116 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void)
3117 {
3118
3119 printf("[dvbt]INTERN_DVBT2_Show_Lock_Info not implement!!!\n");
3120 return false;
3121 }
3122
3123
INTERN_DVBT2_Show_Demod_Info(void)3124 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void)
3125 {
3126 MS_U8 demod_state = 0;
3127 MS_BOOL status = true;
3128 static MS_U8 counter = 0;
3129
3130 INTERN_DVBT2_get_demod_state(&demod_state);
3131
3132 printf("==========[dvbt]state=%d\n",demod_state);
3133 if (demod_state < 5)
3134 {
3135 INTERN_DVBT2_Show_Demod_Version();
3136 INTERN_DVBT2_Show_AGC_Info();
3137 INTERN_DVBT2_Show_ACI_CI();
3138 }
3139 else if(demod_state < 8)
3140 {
3141 INTERN_DVBT2_Show_Demod_Version();
3142 INTERN_DVBT2_Show_AGC_Info();
3143 INTERN_DVBT2_Show_ACI_CI();
3144 INTERN_DVBT2_Show_ChannelLength();
3145 INTERN_DVBT2_Get_CFO();
3146 INTERN_DVBT2_Get_SFO();
3147 INTERN_DVBT2_Show_td_coeff();
3148 }
3149 else if(demod_state < 11)
3150 {
3151 INTERN_DVBT2_Show_Demod_Version();
3152 INTERN_DVBT2_Show_AGC_Info();
3153 INTERN_DVBT2_Show_ACI_CI();
3154 INTERN_DVBT2_Show_ChannelLength();
3155 INTERN_DVBT2_Get_CFO();
3156 INTERN_DVBT2_Get_SFO();
3157 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3158 INTERN_DVBT2_Get_SYA_status();
3159 INTERN_DVBT2_Show_td_coeff();
3160 }
3161 else if((demod_state == 11) && ((counter%4) == 0))
3162 {
3163 INTERN_DVBT2_Show_Demod_Version();
3164 INTERN_DVBT2_Show_AGC_Info();
3165 INTERN_DVBT2_Show_ACI_CI();
3166 INTERN_DVBT2_Show_ChannelLength();
3167 INTERN_DVBT2_Get_CFO();
3168 INTERN_DVBT2_Get_SFO();
3169 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3170 INTERN_DVBT2_Get_SYA_status();
3171 INTERN_DVBT2_Show_td_coeff();
3172 INTERN_DVBT2_Show_Modulation_info();
3173 INTERN_DVBT2_Show_BER_PacketErr();
3174 }
3175 else
3176 status = false;
3177
3178 printf("===========================\n");
3179 counter++;
3180
3181 return status;
3182 }
3183 #endif
3184
3185