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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #include <math.h>
106 #include "MsCommon.h"
107 #include "MsIRQ.h"
108 #include "MsOS.h"
109 //#include "apiPWS.h"
110
111 #include "MsTypes.h"
112 #include "drvBDMA.h"
113 //#include "drvIIC.h"
114 //#include "msAPI_Tuner.h"
115 //#include "msAPI_MIU.h"
116 //#include "BinInfo.h"
117 //#include "halVif.h"
118 #include "drvDMD_INTERN_DVBS.h"
119 #include "halDMD_INTERN_DVBS.h"
120 #include "halDMD_INTERN_common.h"
121
122 #include "drvMMIO.h"
123 //#include "TDAG4D01A_SSI_DVBT.c"
124 #include "drvDMD_VD_MBX.h"
125 //-----------------------------------------------------------------------
126 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
127
128 //For DVBS
129 //#define DVBT2FEC_REG_BASE 0x3300
130 #define DVBS2OPPRO_REG_BASE 0x3E00
131 #define TOP_REG_BASE 0x2000 //DMDTOP
132 #define REG_BACKEND 0x1F00//_REG_BACKEND
133 #define DVBSFEC_REG_BASE 0x3F00
134 #define DVBS2FEC_REG_BASE 0x3300
135 #define DVBS2_REG_BASE 0x3A00
136 #define DVBS2_INNER_REG_BASE 0x3B00
137 #define DVBS2_INNER_EXT_REG_BASE 0x3C00
138 #define DVBS2_INNER_EXT2_REG_BASE 0x3D00
139 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
140 #define FRONTEND_REG_BASE 0x2800
141 #define FRONTENDEXT_REG_BASE 0x2900
142 #define FRONTENDEXT2_REG_BASE 0x2A00
143 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
144 #define DVBTM_REG_BASE 0x3400
145
146 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
147 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
148 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
149
150 //#define DVBS2_Function (1)
151 //#define MSB131X_ADCPLL_IQ_SWAP 0
152 //#define INTERN_DVBS_TS_DATA_SWAP 0
153
154 //#define MS_DEBUG //enable debug dump
155
156 #ifdef MS_DEBUG
157 #define DBG_INTERN_DVBS(x) x
158 #define DBG_GET_SIGNAL_DVBS(x) x
159 #define DBG_INTERN_DVBS_TIME(x) x
160 #define DBG_INTERN_DVBS_LOCK(x) x
161 #define INTERN_DVBS_INTERNAL_DEBUG 1
162 #else
163 #define DBG_INTERN_DVBS(x) //x
164 #define DBG_GET_SIGNAL_DVBS(x) //x
165 #define DBG_INTERN_DVBS_TIME(x) //x
166 #define DBG_INTERN_DVBS_LOCK(x) //x
167 #define INTERN_DVBS_INTERNAL_DEBUG 0
168 #endif
169 //----------------------------------------------------------
170 #define DBG_DUMP_LOAD_DSP_TIME 0
171
172
173 #define SIGNAL_LEVEL_OFFSET 0.00f
174 #define TAKEOVERPOINT -60.0f
175 #define TAKEOVERRANGE 0.5f
176 #define LOG10_OFFSET -0.21f
177 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
178 //extern MS_U32 msAPI_Timer_GetTime0(void);
179 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
180
181
182 //Debug Info
183 //Lock/Done Flag
184 #define AGC_LOCK 0x28170100
185 #define DAGC0_LOCK 0x283B0001
186 #define DAGC1_LOCK 0x285B0001
187 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
188 #define DAGC3_LOCK 0x286E0001
189 #define DCR_LOCK 0x28220100
190 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
191 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
192 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
193 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
194 #define TR_LOCK 0x3B0E0100 //TR 1 2
195 #define PR_LOCK 0x3B401000
196 #define FRAME_SYNC_ACQUIRE 0x3B300001
197 #define EQ_LOCK 0x3B5A1000
198 #define P_SYNC_LOCK 0x22160002
199 #define IN_SYNC_LOCK 0x3F0D8000
200
201 //AGC / DAGC
202 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
203 #define DEBUG_SEL_AGC_ERR 0x28260004
204 #define DEBUG_OUT_AGC 0x2828
205
206 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
207 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
208 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
209 #define DEBUG_OUT_DAGC0 0x2878
210
211 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
212 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
213 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
214 #define DEBUG_OUT_DAGC1 0x28B8
215
216 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
217 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
218 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
219 #define DEBUG_OUT_DAGC2 0x28C4
220
221 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
222 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
223 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
224 #define DEBUG_OUT_DAGC3 0x29DC
225
226 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
227 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
228 #define DEBUG_SEL_TR_INPUT 0x24080F00
229
230 #define FRONTEND_FREEZE_DUMP 0x27028000
231 #define INNER_FREEZE_DUMP 0x24080010
232
233 #define DCR_OFFSET 0x2740
234 #define INNER_DEBUG_SEL 0x2408
235 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
236 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
237 #define INNEREXT_FINEFE_KI_FF0 0x2556
238 #define INNEREXT_FINEFE_KI_FF2 0x2558
239 #define INNEREXT_FINEFE_KI_FF4 0x255A
240 #define INNER_PR_DEBUG_OUT0 0x2486
241 #define INNER_PR_DEBUG_OUT2 0x2488
242
243 #define IIS_COUNT0 0x2746
244 #define IIS_COUNT2 0x2748
245 #define IQB_PHASE 0x2766
246 #define IQB_GAIN 0x2768
247 #define TR_INDICATOR_FF0 0x2454
248 #define TR_INDICATOR_FF2 0x2456
249 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
250 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
251 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
252 //------------------------------------------------------------
253 //Init Mailbox parameter.
254 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
255 //For Parameter Init Setting
256 #define A_S2_ZIF_EN 0x01 //[0]
257 #define A_S2_RF_AGC_EN 0x00 //[0]
258 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
259 #define A_S2_IQB_EN 0x01 //[2]
260 #define A_S2_IIS_EN 0x00 //[0]
261 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
262 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
263 #define A_S2_IQ_SWAP 0x01 //[0]
264 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
265 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
266 #define A_S2_AGC_K 0x07 //[15:12]
267 #define A_S2_ADCI_GAIN 0x0F //[4:0]
268 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
269 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
270 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
271 //FRONTENDEXT_SRD_FRC_CFO
272 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
273 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
274 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
275 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
276 //CCI Parameter
277 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
278 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
279 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
280 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
281 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
282 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
283 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
284 //Inner TR Parameter
285 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
286 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
287 //Inner FineFE Parameter
288 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
289 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
290 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
291 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
292 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
293 //Inner PR KP Parameter
294 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
295 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
296 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
297 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
298 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
299 //Inner FS Parameter
300 #define A_S2_FS_GAMMA 0x10 //[7:0]
301 #define A_S2_FS_ALPHA0 0x10 //[7:0]
302 #define A_S2_FS_ALPHA1 0x10 //[7:0]
303 #define A_S2_FS_ALPHA2 0x10 //[7:0]
304 #define A_S2_FS_ALPHA3 0x10 //[7:0]
305
306 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
307 #define A_S2_FS_OBSWIN 0x08 //[12:8]
308 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
309 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
310 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
311 //Inner EQ Parameter
312 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
313 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
314 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
315 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
316 //Outer FEC Parameter
317 #define A_S2_FEC_ALFA 0x00 //[12:8]
318 #define A_S2_FEC_BETA 0x01 //[7:4]
319 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
320 //TS Parameter
321 #if INTERN_DVBS_TS_SERIAL_INVERSION
322 #define A_S2_TS_SERIAL 0x01 //[0]
323 #else
324 #define A_S2_TS_SERIAL 0x00 //[0]
325 #endif
326 #define A_S2_TS_CLK_RATE 0x00
327 #define A_S2_TS_OUT_INV 0x00 //[5]
328 #define A_S2_TS_DATA_SWAP 0x00 //[5]
329 //Rev Parameter
330
331 #define A_S2_FW_VERSION_L 0x00 //From FW
332 #define A_S2_FW_VERSION_H 0x00 //From FW
333 #define A_S2_CHIP_VERSION 0x01
334 #define A_S2_FS_L 0x00
335 #define A_S2_FS_H 0x00
336 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
337 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
338
339 MS_U8 INTERN_DVBS_DSPREG[] =
340 {
341 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
342 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
343 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
344 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
345 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
346 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
347 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
348 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
349 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
350 };
351
352 /****************************************************************
353 *Local Variables *
354 ****************************************************************/
355
356
357 static MS_U16 _u16SignalLevel[185][2]=
358 {//AV2028 SR=22M, 2/3 CN=5.9
359 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
360 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
361 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
362 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
363 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
364 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
365 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
366 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
367 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
368 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
369 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
370 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
371 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
372 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
373 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
374 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
375 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
376 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
377 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
378 };
379 MS_U8 u8DemodLockFlag;
380 MS_U8 modulation_order;
381 static MS_BOOL _bDemodType=FALSE;//DVBS:FALSE ; S2:TRUE
382 //static MS_BOOL TPSLock = 0;
383 static MS_U32 u32ChkScanTimeStartDVBS = 0;
384 static MS_U8 g_dvbs_lock = 0;
385 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
386 static MS_U8 _u8_DVBS2_CurrentCodeRate;
387 static float _fPostBer=0;
388 static float _f_DVBS_CurrentSNR=0;
389 static MS_U8 _u8ToneBurstFlag=0;
390 static MS_U16 _u16BlindScanStartFreq=0;
391 static MS_U16 _u16BlindScanEndFreq=0;
392 static MS_U16 _u16TunerCenterFreq=0;
393 static MS_U16 _u16ChannelInfoIndex=0;
394 //Debug Only+
395 static MS_U16 _u16NextCenterFreq=0;
396 static MS_U16 _u16LockedSymbolRate=0;
397 static MS_U16 _u16LockedCenterFreq=0;
398 static MS_U16 _u16PreLockedHB=0;
399 static MS_U16 _u16PreLockedLB=0;
400 static MS_U16 _u16CurrentSymbolRate=0;
401 static MS_S16 _s16CurrentCFO=0;
402 static MS_U16 _u16CurrentStepSize=0;
403 //Debug Only-
404 static MS_U16 _u16ChannelInfoArray[2][1000];
405 //static MS_U32 _u32CurrentSR=0;
406 static MS_BOOL _bSerialTS=FALSE;
407 static MS_BOOL _bTSDataSwap=FALSE;
408
409 //Global Variables
410 S_CMDPKTREG gsCmdPacketDVBS;
411 //MS_U8 gCalIdacCh0, gCalIdacCh1;
412 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
413 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
414 extern MS_U32 u32DMD_DVBS2_DJB_START_ADDR;
415 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
416 MS_U8 INTERN_DVBS_table[] =
417 {
418 #include "fwDMD_INTERN_DVBS.dat"
419 };
420
421 #endif
422
423 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
424 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
425 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
426 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
427 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
428 MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
429
430 #if (INTERN_DVBS_INTERNAL_DEBUG)
431 void INTERN_DVBS_info(void);
432 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
433 #endif
434
435 //------------------------------------------------------------------
436 // System Info Function
437 //------------------------------------------------------------------
438 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)439 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
440 {
441 #if 0
442 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
443 #endif
444 MS_U8 status = true;
445 #if 0
446 MS_U16 u16DspAddr = 0;
447 #endif
448 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
449
450 #if 0//def MS_DEBUG
451 {
452 MS_U8 u8buffer[256];
453 printf("INTERN_DVBS_DSPReg_Init Reset\n");
454 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
455 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
456
457 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
458 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
459 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
460 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
461 printf("%x ", u8buffer[idx]);
462 printf("\n");
463
464 printf("INTERN_DVBS_DSPReg_Init Value\n");
465 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
466 printf("%x ", INTERN_DVBS_DSPREG[idx]);
467 printf("\n");
468 }
469 #endif
470
471 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
472 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
473
474 // readback to confirm.
475 // ~read this to check mailbox initial values
476 #if 0
477 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
478 {
479 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
480 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
481 {
482 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
483 }
484 }
485 #endif
486 #if 0
487 if (u8DVBS_DSPReg != NULL)
488 {
489 if (1 == u8DVBS_DSPReg[0])
490 {
491 u8DVBS_DSPReg+=2;
492 for (idx = 0; idx<u8Size; idx++)
493 {
494 u16DspAddr = *u8DVBS_DSPReg;
495 u8DVBS_DSPReg++;
496 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
497 u8DVBS_DSPReg++;
498 u8Mask = *u8DVBS_DSPReg;
499 u8DVBS_DSPReg++;
500 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
501 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
502 u8DVBS_DSPReg++;
503 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
504 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
505 }
506 }
507 else
508 {
509 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
510 }
511 }
512 #endif
513 #if 0//def MS_DEBUG
514 {
515 MS_U8 u8buffer[256];
516 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
517 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
518 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
519 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
520 printf("%x ", u8buffer[idx]);
521 printf("\n");
522 }
523 #endif
524
525 #if 0//def MS_DEBUG
526 {
527 MS_U8 u8buffer[256];
528 for (idx = 0; idx<128; idx++)
529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
530 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
531 for (idx = 0; idx<128; idx++)
532 {
533 printf("%x ", u8buffer[idx]);
534 if ((idx & 0xF) == 0xF) printf("\n");
535 }
536 printf("\n");
537 }
538 #endif
539 return status;
540 }
541
542 /***********************************************************************************
543 Subject: Command Packet Interface
544 Function: INTERN_DVBS_Cmd_Packet_Send
545 Parmeter:
546 Return: MS_BOOL
547 Remark:
548 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)549 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
550 {
551 MS_U8 status = true, indx;
552 MS_U8 reg_val, timeout = 0;
553 return true;
554
555 // ==== Command Phase ===================
556 DBG_INTERN_DVBS(printf("--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
557 pCmdPacket->param[0],pCmdPacket->param[1],
558 pCmdPacket->param[2],pCmdPacket->param[3],
559 pCmdPacket->param[4],pCmdPacket->param[5] ));
560
561 // wait _BIT_END clear
562 do
563 {
564 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
565 if((reg_val & _BIT_END) != _BIT_END)
566 {
567 break;
568 }
569 MsOS_DelayTask(5);
570 if (timeout > 200)
571 {
572 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
573 return false;
574 }
575 timeout++;
576 } while (1);
577
578 // set cmd_3:0 and _BIT_START
579 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
580 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
581 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
582
583
584 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
585 // wait _BIT_START clear
586 do
587 {
588 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
589 if((reg_val & _BIT_START) != _BIT_START)
590 {
591 break;
592 }
593 MsOS_DelayTask(10);
594 if (timeout > 200)
595 {
596 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
597 return false;
598 }
599 timeout++;
600 } while (1);
601
602 // ==== Data Phase ======================
603
604 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
605
606 for (indx = 0; indx < param_cnt; indx++)
607 {
608 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
609 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
610
611 // set param[indx] and _BIT_DRQ
612 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
613 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
614 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
615
616 // wait _BIT_DRQ clear
617 do
618 {
619 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
620 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
621 {
622 break;
623 }
624 MsOS_DelayTask(5);
625 if (timeout > 200)
626 {
627 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
628 return false;
629 }
630 timeout++;
631 } while (1);
632 }
633
634 // ==== End Phase =======================
635
636 // set _BIT_END to finish command
637 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
638 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
639
640 return status;
641 }
642
643 /***********************************************************************************
644 Subject: Command Packet Interface
645 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
646 Parmeter:
647 Return: MS_BOOL
648 Remark:
649 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)650 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
651 {
652 return TRUE;
653 }
654
655 /***********************************************************************************
656 Subject: SoftStop
657 Function: INTERN_DVBS_SoftStop
658 Parmeter:
659 Return: MS_BOOL
660 Remark:
661 ************************************************************************************/
INTERN_DVBS_SoftStop(void)662 MS_BOOL INTERN_DVBS_SoftStop ( void )
663 {
664 #if 1
665 MS_U16 u16WaitCnt=0;
666
667 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
668 {
669 DBG_INTERN_DVBS(printf(">> MB Busy!\n"));
670 return FALSE;
671 }
672
673 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
674
675 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
676 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
677
678 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
679 {
680 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
681 {
682 DBG_INTERN_DVBS(printf(">> DVBT SoftStop Fail!\n"));
683 return FALSE;
684 }
685 }
686
687 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
688 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
689 #endif
690 return TRUE;
691 }
692
693 /***********************************************************************************
694 Subject: Reset
695 Function: INTERN_DVBC_Reset
696 Parmeter:
697 Return: MS_BOOL
698 Remark:
699 ************************************************************************************/
700 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
701
INTERN_DVBS_Reset(void)702 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
703 {
704 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_reset\n"));
705
706 DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_Reset, t = %d\n",MsOS_GetSystemTime()));
707
708 //INTERN_DVBS_SoftStop();
709
710
711 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
712
713 MsOS_DelayTask(1);
714 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
715
716 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
717 MsOS_DelayTask(5);
718
719 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
720 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
721
722 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
723 g_dvbs_lock = 0;
724
725 return TRUE;
726 }
727
728 /***********************************************************************************
729 Subject: Exit
730 Function: INTERN_DVBC_Exit
731 Parmeter:
732 Return: MS_BOOL
733 Remark:
734 ************************************************************************************/
INTERN_DVBS_Exit(void)735 MS_BOOL INTERN_DVBS_Exit ( void )
736 {
737 MS_U8 u8Data=0;
738 MS_U8 u8Data_temp=0;
739
740 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
741 HAL_DMD_RIU_WriteByte(0x101E39, 0);
742
743 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
744 u8Data&=~(0x02);
745 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
746
747 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
748 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_Exit\n"));
749 INTERN_DVBS_SoftStop();
750
751 return TRUE;
752 }
753
754 /***********************************************************************************
755 Subject: Load DSP code to chip
756 Function: INTERN_DVBS_LoadDSPCode
757 Parmeter:
758 Return: MS_BOOL
759 Remark:
760 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)761 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
762 {
763 MS_U8 udata = 0x00;
764 MS_U16 i;
765 MS_U16 fail_cnt=0;
766
767 #if (DBG_DUMP_LOAD_DSP_TIME==1)
768 MS_U32 u32Time;
769 #endif
770
771 //MDrv_Sys_DisableWatchDog();
772 /*
773 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
774 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
775 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
776 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
777 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
778 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
779 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
780 */
781 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
782 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
783 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
784 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
785 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
786 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
787
788 //// Load code thru VDMCU_IF ////
789 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
790 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
791 {
792 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
793 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
794 }
795
796 //// Content verification ////
797 DBG_INTERN_DVBS(printf(">Verify Code...\n"));
798
799 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
800 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
801
802 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
803 {
804 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
805 if (udata != INTERN_DVBS_table[i])
806 {
807 printf(">fail add = 0x%x\n", i);
808 printf(">code = 0x%x\n", INTERN_DVBS_table[i]);
809 printf(">data = 0x%x\n", udata);
810
811 if (fail_cnt > 10)
812 {
813 printf(">DVB-S DSP Loadcode fail!");
814 return false;
815 }
816 fail_cnt++;
817 }
818 }
819
820 #if 0 //use for Kris DJB with VCM
821 //====================================================================
822 // add S2 DRAM bufer start address into fixed location
823 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
824 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
825
826 //0x30~0x33
827 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBS2_DJB_START_ADDR);
828 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 8));
829 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 16));
830 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 24));
831
832 printf("@@@@@ share dram address = 0x %x \n ",u32DMD_DVBS2_DJB_START_ADDR);
833 //=====================================================================
834 #endif
835
836 /*
837 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
838 HAL_DMD_RIU_WriteByte(0x103483, 0x00);
839 HAL_DMD_RIU_WriteByte(0x103480, 0x01);
840 HAL_DMD_RIU_WriteByte(0x103481, 0x01);
841 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
842 */
843
844 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
845 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
846 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
847 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
848
849
850 DBG_INTERN_DVBS(printf(">DSP Loadcode done."));
851 #if 0
852 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
853 INTERN_DVBS_Active(ENABLE);
854 while(1);
855 #endif
856 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
857
858 return TRUE;
859 }
860
861 /***********************************************************************************
862 Subject: DVB-S CLKGEN initialized function
863 Function: INTERN_DVBS_Power_On_Initialization
864 Parmeter:
865 Return: MS_BOOL
866 Remark:
867 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)868 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
869 {
870 MS_U8 u8Temp=0;
871 // This file is translated by Steven Hung's riu2script.pl
872
873 // ==============================================================
874 // Start demod top initial setting by HK MCU ......
875 // ==============================================================
876 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
877 // 1'b0->reg_DMDTOP control by HK_MCU.
878 // 1'b1->reg_DMDTOP control by DMD_MCU.
879 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
880 // 1'b0->reg_DMDANA control by HK_MCU.
881 // 1'b1->reg_DMDANA control by DMD_MCU.
882 // select HK MCU ......
883 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
884 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
885 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
886
887
888 // ==============================================================
889 // Start TOP CLKGEN initial setting ......
890 // ==============================================================
891 // CLK_DMDMCU clock setting
892 // reg_ckg_dmdmcu@0x0f[4:0]
893 // [0] : disable clock
894 // [1] : invert clock
895 // [4:2]:
896 // 000:170 MHz(MPLL_DIV_BUF)
897 // 001:160MHz
898 // 010:144MHz
899 // 011:123MHz
900 // 100:108MHz (Kriti:DVBT2)
901 // 101:mem_clcok
902 // 110:mem_clock div 2
903 // 111:select XTAL
904 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
905 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
906 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
907 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
908
909
910 // set parallel ts clock
911 // [11] : reg_ckg_demod_test_in_en = 0
912 // 0: select internal ADC CLK
913 // 1: select external test-in clock
914 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
915 // 0: select gated clock
916 // 1: select free-run clock
917 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
918 // 0: normal phase to pad
919 // 1: invert phase to pad
920 // [8] : reg_ckg_atsc_dvb_div_sel = 1
921 // 0: select clk_dmplldiv5
922 // 1: select clk_dmplldiv3
923 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
924 // Demod TS output clock phase tuning number
925 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
926 // Demod TS output clock is equal Demod TS internal working clock.
927 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
928 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
929 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
930 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
931 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
932
933
934 // enable DVBTC ts clock
935 // [11:8]: reg_ckg_dvbtc_ts
936 // [8] : disable clock
937 // [9] : invert clock
938 // [11:10]: Select clock source
939 // 00:clk_atsc_dvb_div
940 // 01:62 MHz
941 // 10:54 MHz
942 // 11:reserved
943 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
944 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
945 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
946 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
947
948
949 // enable dvbc adc clock
950 // [3:0]: reg_ckg_dvbtc_adc
951 // [0] : disable clock
952 // [1] : invert clock
953 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
954 // 00: clk_dmdadc
955 // 01: clk_dmdadc_div2
956 // 10: clk_dmdadc_div4
957 // 11: DFT_CLK
958 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
959 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
960 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
961 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
962
963
964 // ==============================================================
965 // Start demod_0 CLKGEN setting ......
966 // ==============================================================
967 // enable atsc_adcd_sync clock
968 // [3:0] : reg_ckg_atsc_adcd_sync
969 // [0] : disable clock
970 // [1] : invert clock
971 // [3:2]: Select clock source
972 // 00: clk_dmdadc_sync
973 // 01: 1'b0
974 // 10: 1'b0
975 // 11: DFT_CLK
976 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
977 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
978 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
979 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
980
981 // DVBS2
982 // @0x350c
983 // [3:0] : reg_ckg_dvbs_outer1x
984 // [0] : disable clock
985 // [1] : invert clock
986 // [3:2]: Select clock source
987 // 00: adc_clk_buf
988 // 01: dvb_clk86_buf
989 // 10: dvb_clk43_buf
990 // 11: 1'b0
991 // [6:4] : reg_ckg_dvbs_outer2x
992 // [4] : disable clock
993 // [5] : invert clock
994 // [6] : Select clock source
995 // 00: adc_clk_buf
996 // 01: 1'b0
997 // 10: 1'b0
998 // 11: DFT_CLK
999 // [10:8]: reg_ckg_dvbs2_inner
1000 // [8] : disable clock
1001 // [9] : invert clock
1002 // [10]: Select clock source
1003 // 00: adc_clk_buf
1004 // 01: 1'b0
1005 // 10: 1'b0
1006 // 11: DFT_CLK
1007 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1008 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1009 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1010 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1011
1012
1013 // DVBS2
1014 // @0x350d
1015 // [11:8]: reg_ckg_dvbs2_oppro
1016 // [8] : disable clock
1017 // [9] : invert clock
1018 // [11:10]: Select clock source
1019 // 00: mpll_clk144_buf
1020 // 01: mpll_clk96_buf
1021 // 10: mpll_clk72_buf
1022 // 11: mpll_clk48_buf
1023 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1024 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1025 HAL_DMD_RIU_WriteByte(0x111f1b, 0x00);
1026 HAL_DMD_RIU_WriteByte(0x111f1a, 0x00);
1027
1028
1029 // @0x3510
1030 // [3:0] : reg_ckg_dvbtm_adc
1031 // N/A
1032 // [6:4] : reg_ckg_dvbt_inner1x
1033 // [4] : disable clock
1034 // [5] : invert clock
1035 // [6] : Select clock source
1036 // 00: dvb_clk24_buf
1037 // 01: dvb_clk21p5_buf
1038 // 10: 1'b0
1039 // 11: DFT_CLK
1040 // [10:8] reg_ckg_dvbt_inner2x
1041 // [8] : disable clock
1042 // [9] : invert clock
1043 // [10]: Select clock source
1044 // 00: dvb_clk48_buf
1045 // 01: dvb_clk43_buf
1046 // 10: 1'b0
1047 // 11: DFT_CLK
1048 // [14:12] reg_ckg_dvbt_inner4x
1049 // [12]: disable clock
1050 // [13]: invert clock
1051 // [14]: Select clock source
1052 // 00: dvb_clk96_buf
1053 // 01: dvb_clk86_buf
1054 // 10: 1'b0
1055 // 11: DFT_CLK
1056 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1057 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1058 HAL_DMD_RIU_WriteByte(0x111f21, 0x11);
1059 HAL_DMD_RIU_WriteByte(0x111f20, 0x10);
1060
1061 // @0x3511
1062 // [2:0] : reg_ckg_dvbt_outer1x
1063 // [0] : disable clock
1064 // [1] : invert clock
1065 // [2] : Select clock source
1066 // 00: dvb_clk48_buf
1067 // 01: dvb_clk43_buf
1068 // 10: 1'b0
1069 // 11: DFT_CLK
1070 // [6:4] : reg_ckg_dvbt_outer2x
1071 // [4] : disable clock
1072 // [5] : invert clock
1073 // [6] : Select clock source
1074 // 00: dvb_clk96_buf
1075 // 01: dvb_clk86_buf
1076 // 10: 1'b0
1077 // 11: DFT_CLK
1078 // [11:8]: reg_ckg_dvbtc_outer2x
1079 // [8] : disable clock
1080 // [9] : invert clock
1081 // [11:10]: Select clock source
1082 // 00: mpll_clk57p6_buf
1083 // 01: dvb_clk43_buf
1084 // 10: dvb_clk86_buf
1085 // 11: dvb_clk96_buf
1086 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1087 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1088 HAL_DMD_RIU_WriteByte(0x111f23, 0x0c);
1089 HAL_DMD_RIU_WriteByte(0x111f22, 0x11);
1090
1091
1092 // @0x3512
1093 // [11:8]: reg_ckg_acifir
1094 // [8] : disable clock
1095 // [9] : invert clock
1096 // [11:10]: Select clock source
1097 // 000: 1'b0
1098 // 001: clk_dmdadc
1099 // 010: clk_vif_ssc_mux
1100 // 011: 1'b0
1101 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1102 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1103 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1104
1105
1106 // @0x3514
1107 // [12:8]: reg_ckg_dvbtm_sram_t1o2x_t22x
1108 // [8] : disable clock
1109 // [9] : invert clock
1110 // [12:10]: Select clock source
1111 // 000: dvb_clk48_buf
1112 // 001: dvb_clk43_buf
1113 // 010: 1'b0
1114 // 011: 1'b0
1115 // 100: 1'b0
1116 // 101: 1'b0
1117 // 110: 1'b0
1118 // 111: 1'b0
1119 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1120 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1121 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1122 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1123
1124
1125 // @0x3516
1126 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x
1127 // [4] : disable clock
1128 // [5] : invert clock
1129 // [8:6]: Select clock source
1130 // 000: dvb_clk48_buf
1131 // 001: dvb_clk43_buf
1132 // 010: 1'b0
1133 // 011: 1'b0
1134 // 100: adc_clk_buf
1135 // 101: 1'b0
1136 // 110: 1'b0
1137 // 111: 1'b0
1138 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1139 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1140 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
1141 HAL_DMD_RIU_WriteByte(0x111f2c, 0x01);
1142
1143
1144 // @0x3517
1145 // [4:0] : reg_ckg_dvbtm_sram_t12x_t22x
1146 // [0] : disable clock
1147 // [1] : invert clock
1148 // [4:2]: Select clock source
1149 // 000: dvb_clk48_buf
1150 // 001: dvb_clk43_buf
1151 // 010: 1'b0
1152 // 011: 1'b0
1153 // 100: 1'b0
1154 // 101: 1'b0
1155 // 110: 1'b0
1156 // 111: 1'b0
1157 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1158 // [8] : disable clock
1159 // [9] : invert clock
1160 // [12:10]: Select clock source
1161 // 000: dvb_clk96_buf
1162 // 001: dvb_clk86_buf
1163 // 010: dvb_clk48_buf
1164 // 011: dvb_clk43_buf
1165 // 100: 1'b0
1166 // 101: 1'b0
1167 // 110: 1'b0
1168 // 111: 1'b0
1169 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1170 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1171 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
1172 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
1173
1174
1175 // @0x3518
1176 // [4:0] : reg_ckg_dvbtm_sram_t14x_t24x
1177 // [0] : disable clock
1178 // [1] : invert clock
1179 // [4:2]: Select clock source
1180 // 000: dvb_clk96_buf
1181 // 001: dvb_clk96_buf
1182 // 010: 1'b0
1183 // 011: 1'b0
1184 // 100: 1'b0
1185 // 101: 1'b0
1186 // 110: 1'b0
1187 // 111: 1'b0
1188 // [12:8]: reg_ckg_dvbtm_ts_in
1189 // [8] : disable clock
1190 // [9] : invert clock
1191 // [12:10]: Select clock source
1192 // 000: clk_dvbtc_rs_p
1193 // 001: dvb_clk48_buf
1194 // 010: dvb_clk43_buf
1195 // 011: clk_dvbs_outer1x_pre_mux4
1196 // 100: clk_dvbs2_oppro_pre_mux4
1197 // 101: 1'b0
1198 // 110: 1'b0
1199 // 111: 1'b0
1200 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1201 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1202 HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1203 HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1204
1205
1206 // @0x3519
1207 // [2:0] : reg_ckg_tdp_jl_inner1x
1208 // [0] : disable clock
1209 // [1] : invert clock
1210 // [2] : Select clock source
1211 // 00: dvb_clk24_buf
1212 // 01: dvb_clk21p5_buf
1213 // 10: 1'b0
1214 // 11: DFT_CLK
1215 // [6:4] : reg_ckg_tdp_jl_inner4x
1216 // [4] : disable clock
1217 // [5] : invert clock
1218 // [6] : Select clock source
1219 // 00: dvb_clk96_buf
1220 // 01: dvb_clk86_buf
1221 // 10: 1'b0
1222 // 11: DFT_CLK
1223 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1224 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1225 HAL_DMD_RIU_WriteByte(0x111f33, 0x3c);
1226 HAL_DMD_RIU_WriteByte(0x111f32, 0x00);
1227
1228
1229 // @0x351a
1230 // [6:4] : reg_ckg_dvbt2_inner1x
1231 // [4] : disable clock
1232 // [5] : invert clock
1233 // [6] : Select clock source
1234 // 00: dvb_clk96_buf
1235 // 01: dvb_clk86_buf
1236 // 10: 1'b0
1237 // 11: DFT_CLK
1238 // [10:8]: reg_ckg_dvbt2_inner2x
1239 // [8] : disable clock
1240 // [9] : invert clock
1241 // [10]: Select clock source
1242 // 00: dvb_clk48_buf
1243 // 01: dvb_clk43_buf
1244 // 10: 1'b0
1245 // 11: DFT_CLK
1246 // [14:12]:reg_ckg_dvbt2_inner4x
1247 // [12] : disable clock
1248 // [13] : invert clock
1249 // [14] : Select clock source
1250 // 00: dvb_clk96_buf
1251 // 01: dvb_clk86_buf
1252 // 10: 1'b0
1253 // 11: DFT_CLK
1254 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1255 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1256 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
1257 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
1258
1259
1260 // @0x351b
1261 // [1:0] : reg_ckg_dvbt2_ldpc
1262 // DVBT2 LDPC gated clock control register
1263 // [0] = 1:clock enable.
1264 // [1] = 1:manual mode.
1265 // [3:2] : reg_ckg_dvbt2_bch
1266 // DVBT2 BCH gated clock control register;
1267 // [0] = 1:clock enable
1268 // [1] = 1:manual mode.
1269 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1270 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1271 HAL_DMD_RIU_WriteByte(0x111f37, 0x00);
1272 HAL_DMD_RIU_WriteByte(0x111f36, 0x11);
1273
1274
1275 // @0x351d
1276 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1277 // [0] : disable clock
1278 // [1] : invert clock
1279 // [2] : Select clock source
1280 // 00: adc_clk_buf
1281 // 01: 1'b0
1282 // 10: 1'b0
1283 // 11: DFT_CLK
1284 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1285 // [4] : disable clock
1286 // [5] : invert clock
1287 // [6]: Select clock source
1288 // 00: clk_adc_div2_buf
1289 // 01: 1'b0
1290 // 10: 1'b0
1291 // 11: DFT_CLK
1292 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1293 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1294 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1295 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1296
1297
1298 // @0x351e
1299 // [4:0] : reg_ckg_dvbtm_sram_t11x_t22x
1300 // [0] : disable clock
1301 // [1] : invert clock
1302 // [4:2]: Select clock source
1303 // 000: dvb_clk48_buf
1304 // 001: dvb_clk43_buf
1305 // 010: dvb_clk24_buf
1306 // 011: dvb_clk21p5_buf
1307 // 100: 1'b0
1308 // 101: 1'b0
1309 // 110: 1'b0
1310 // 111: 1'b0
1311 // [12:8]: reg_ckg_dvbtm_sram_t11x_t24x
1312 // [8] : disable clock
1313 // [9] : invert clock
1314 // [:2]: Select clock source
1315 // 000: dvb_clk48_buf
1316 // 001: dvb_clk43_buf
1317 // 010: dvb_clk24_buf
1318 // 011: dvb_clk21p5_buf
1319 // 100: 1'b0
1320 // 101: 1'b0
1321 // 110: 1'b0
1322 // 111: 1'b0
1323 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0c04);
1324 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1325 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1326 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
1327 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
1328
1329
1330 // @0x3522
1331 // [3:0] : reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1332 // [0] : disable clock
1333 // [1] : invert clock
1334 // [2] : Select clock source
1335 // 00: dvb_clk12_buf
1336 // 01: dvb_clk10p75_buf
1337 // 10: 1'b0
1338 // 11: DFT_CLK
1339 // [7:4] : reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1340 // [4] : disable clock
1341 // [5] : invert clock
1342 // [6] : Select clock source
1343 // 00: dvb_clk48_buf
1344 // 01: dvb_clk43_buf
1345 // 10: 1'b0
1346 // 11: DFT_CLK
1347 // [11:8]: reg_ckg_dvbt_t2_inner1x
1348 // [8] : disable clock
1349 // [9] : invert clock
1350 // [11:10]: Select clock source
1351 // 00: dvb_clk24_buf
1352 // 01: dvb_clk21p5_buf
1353 // 10: 1'b0
1354 // 11: DFT_CLK
1355 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1356 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1357 HAL_DMD_RIU_WriteByte(0x111f45, 0x01);
1358 HAL_DMD_RIU_WriteByte(0x111f44, 0x11);
1359
1360 // @0x353a
1361 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner2x
1362 // [0] : disable clock
1363 // [1] : invert clock
1364 // [2] : Select clock source
1365 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1366 // 01: clk_isdbt_inner2x_p
1367 // 10: 1'b0
1368 // 11: DFT_CLK
1369 // [6:4] : reg_ckg_dvbtm_sram_t12x_t24x_isdbt_inner2x
1370 // [4] : disable clock
1371 // [5] : invert clock
1372 // [6] : Select clock source
1373 // 00: clk_dvbtm_sram_t12x_t24x_p
1374 // 01: clk_isdbt_inner2x_p
1375 // 10: 1'b0
1376 // 11: DFT_CLK
1377 // [10:8]: reg_ckg_dvbtm_sram_t24x_isdbt_inner2x
1378 // [8] : disable clock
1379 // [9] : invert clock
1380 // [10]: Select clock source
1381 // 00: clk_dvbtm_sram_t14x_t24x_p
1382 // 01: clk_isdbt_inner2x_p
1383 // 10: 1'b0
1384 // 11: DFT_CLK
1385 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner4x
1386 // [12] : disable clock
1387 // [13] : invert clock
1388 // [14] : Select clock source
1389 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1390 // 01: clk_isdbt_inner4x_p
1391 // 10: 1'b0
1392 // 11: DFT_CLK
1393 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1394 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1395 HAL_DMD_RIU_WriteByte(0x111f75, 0x01);
1396 HAL_DMD_RIU_WriteByte(0x111f74, 0x10);
1397
1398 // @0x353b
1399 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner2x
1400 // [0] : disable clock
1401 // [1] : invert clock
1402 // [2] : Select clock source
1403 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1404 // 01: clk_isdbt_inner2x_p
1405 // 10: 1'b0
1406 // 11: DFT_CLK
1407 // [6:4] : reg_ckg_dvbtm_sram_t22x_isdbt_inner2x
1408 // [4] : disable clock
1409 // [5] : invert clock
1410 // [6] : Select clock source
1411 // 00: clk_dvbtm_sram_t12x_t22x_p
1412 // 01: clk_isdbt_inner2x_p
1413 // 10: 1'b0
1414 // 11: DFT_CLK
1415 // [10:8]: reg_ckg_dvbtm_sram_t14x_t24x_s2inner_isdbt_inner2x
1416 // [8] : disable clock
1417 // [9] : invert clock
1418 // [10]: Select clock source
1419 // 00: clk_dvbtm_sram_t14x_t24x_s2inner_p
1420 // 01: clk_isdbt_inner2x_p
1421 // 10: 1'b0
1422 // 11: DFT_CLK
1423 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1424 // [12] : disable clock
1425 // [13] : invert clock
1426 // [14]: Select clock source
1427 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1428 // 01: clk_isdbt_inner4x_p
1429 // 10: 1'b0
1430 // 11: DFT_CLK
1431 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1432 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1433 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1434 HAL_DMD_RIU_WriteByte(0x111f76, 0x10);
1435
1436 // @0x353c
1437 // [2:0] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1438 // [0] : disable clock
1439 // [1] : invert clock
1440 // [2] : Select clock source
1441 // 00: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1442 // 01: clk_isdbt_inner4x_p
1443 // 10: 1'b0
1444 // 11: DFT_CLK
1445 // [6:4] : reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x
1446 // [4] : disable clock
1447 // [5] : invert clock
1448 // [6] : Select clock source
1449 // 00: clk_dvbtm_sram_t12x_t22x_p
1450 // 01: clk_isdbt_inner2x_p
1451 // 10: 1'b0
1452 // 11: DFT_CLK
1453 // [10:8]: reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x
1454 // [8] : disable clock
1455 // [9] : invert clock
1456 // [10]: Select clock source
1457 // 00: clk_dvbtm_sram_t11x_t22x_p
1458 // 01: clk_isdbt_inner2x_p
1459 // 10: 1'b0
1460 // 11: DFT_CLK
1461 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1462 // [12] : disable clock
1463 // [13] : invert clock
1464 // [14]: Select clock source
1465 // 00: clk_dvbtm_sram_t12x_t24x_p
1466 // 01: clk_isdbt_outer6x_dvbt_outer2x_c_mux
1467 // 10: 1'b0
1468 // 11: DFT_CLK
1469 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1470 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1471 HAL_DMD_RIU_WriteByte(0x111f79, 0x01);
1472 HAL_DMD_RIU_WriteByte(0x111f78, 0x10);
1473
1474 // @0x353e
1475 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_isdbt_outer6x
1476 // [0] : disable clock
1477 // [1] : invert clock
1478 // [2] : Select clock source
1479 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1480 // 01: clk_isdbt_outer6x_p
1481 // 10: 1'b0
1482 // 11: DFT_CLK
1483 // [6:4] : reg_ckg_dvbtm_sram_t22x_miu
1484 // [4] : disable clock
1485 // [5] : invert clock
1486 // [6] : Select clock source
1487 // 00: clk_dvbt2_inner2x_p
1488 // 01: clk_miu_p
1489 // 10: 1'b0
1490 // 11: DFT_CLK
1491 // [10:8]: reg_ckg_dvbtm_sram_adc_t22x_isdbt_inner2x
1492 // [8] : disable clock
1493 // [9] : invert clock
1494 // [10]: Select clock source
1495 // 00: clk_dvbtm_sram_adc_t22x_p
1496 // 01: clk_isdbt_inner2x_p
1497 // 10: 1'b0
1498 // 11: DFT_CLK
1499 // [14:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_miu
1500 // [12] : disable clock
1501 // [13] : invert clock
1502 // [14]: Select clock source
1503 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1504 // 01: clk_miu_p
1505 // 10: 1'b0
1506 // 11: DFT_CLK
1507 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1508 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1509 HAL_DMD_RIU_WriteByte(0x111f7d, 0x11);
1510 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1511
1512 // @0x353f
1513 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_isdbt_outer6x
1514 // [0] : disable clock
1515 // [1] : invert clock
1516 // [2] : Select clock source
1517 // 00: clk_dvbs_outer2x_dvbt_outer2x_miu_mux8
1518 // 01: clk_isdbt_outer6x_p
1519 // 10: 1'b0
1520 // 11: DFT_CLK
1521 // [6:4] : reg_ckg_dvbtm_sram_t22x_dvbtc_rs
1522 // [4] : disable clock
1523 // [5] : invert clock
1524 // [6] : Select clock source
1525 // 00: clk_dvbt2_inner2x_p
1526 // 01: clk_dvbtc_rs_p
1527 // 10: 1'b0
1528 // 11: DFT_CLK
1529 // [10:8]: reg_ckg_dvbtc_outer2x_isdbt_outer_rs
1530 // [8] : disable clock
1531 // [9] : invert clock
1532 // [10]: Select clock source
1533 // 00: clk_dvbtc_outer2x_p
1534 // 01: clk_isdbt_outer_rs_p
1535 // 10: 1'b0
1536 // 11: DFT_CLK
1537 // [14:12]: reg_ckg_dvbtm_sram_t22x_isdbt_outer6x_dvbt_outer2x
1538 // [12] : disable clock
1539 // [13] : invert clock
1540 // [14]: Select clock source
1541 // 00: clk_dvbtm_sram_t12x_t22x_p
1542 // 01: clk_isdbt_outer6x_dvbt_outer2x_mux
1543 // 10: 1'b0
1544 // 11: DFT_CLK
1545 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1546 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1547 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
1548 HAL_DMD_RIU_WriteByte(0x111f7e, 0x41);
1549
1550
1551 // @0x3570
1552 // [4:0] : reg_ckg_dvbt_inner2x_srd0p5x
1553 // [0] : disable clock
1554 // [1] : invert clock
1555 // [3:2]: Select clock source
1556 // 00: dvb_clk48_buf
1557 // 01: dvb_clk43_buf
1558 // 10: clk_adc_div2_buf
1559 // 11: 1'b0
1560 // 11: 1'b0
1561 // [13:8]: reg_ckg_dvbtm_sram_t1outer1x_t24x
1562 // [8] : disable clock
1563 // [9] : invert clock
1564 // [12:10]: Select clock source
1565 // 000: dvb_clk96_buf
1566 // 001: dvb_clk86_buf
1567 // 010: dvb_clk48_buf
1568 // 011: dvb_clk43_buf
1569 // 100: 1'b0
1570 // 101: 1'b0
1571 // 110: 1'b0
1572 // 111: 1'b0
1573 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1574 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1575 HAL_DMD_RIU_WriteByte(0x111fe1, 0x00);
1576 HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1577
1578
1579 // @0x3571
1580 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1581 // [0] : disable clock
1582 // [1] : invert clock
1583 // [3:2]: Select clock source
1584 // 000: dvb_clk96_buf
1585 // 001: dvb_clk86_buf
1586 // 010: dvb_clk48_buf
1587 // 011: dvb_clk43_buf
1588 // 100: adc_clk_buf
1589 // 101: 1'b0
1590 // 110: 1'b0
1591 // 111: 1'b0
1592 // [12:8]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1593 // [8] : disable clock
1594 // [9] : invert clock
1595 // [12:10]: Select clock source
1596 // 000: dvb_clk96_buf
1597 // 001: dvb_clk86_buf
1598 // 010: adc_clk_buf
1599 // 011: 1'b0
1600 // 100: 1'b0
1601 // 101: 1'b0
1602 // 110: 1'b0
1603 // 111: 1'b0
1604 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1605 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1606 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1607 HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1608
1609
1610 // @0x3572
1611 // [6:0] : reg_ckg_dvbt2_s2_bch_out
1612 // [0] : disable clock
1613 // [1] : invert clock
1614 // [2] : Select clock source
1615 // 00: dvb_clk48_buf
1616 // 01: dvb_clk43_buf
1617 // 10: 1'b0
1618 // 11: DFT_CLK
1619 // [12:8]: reg_ckg_dvbt2_outer2x
1620 // [8] : disable clock
1621 // [9] : invert clock
1622 // [12:10]: Select clock source
1623 // 000: mpll_clk144_buf
1624 // 001: mpll_clk108_buf
1625 // 010: mpll_clk96_buf
1626 // 011: mpll_clk72_buf
1627 // 100: mpll_clk54_buf
1628 // 101: mpll_clk48_buf
1629 // 110: mpll_clk36_buf
1630 // 111: mpll_clk24_buf
1631 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1632 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1633 HAL_DMD_RIU_WriteByte(0x111fe5, 0x00);
1634 HAL_DMD_RIU_WriteByte(0x111fe4, 0x08);
1635
1636
1637 // @0x3573
1638 // [3:0] : reg_ckg_dvbt2_inner4x_s2_inner
1639 // [0] : disable clock
1640 // [1] : invert clock
1641 // [2] : Select clock source
1642 // 00: dvb_clk96_buf
1643 // 01: dvb_clk86_buf
1644 // 10: 1'b0
1645 // 11: DFT_CLK
1646 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1647 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1648 HAL_DMD_RIU_WriteByte(0x111fe7, 0x00);
1649 HAL_DMD_RIU_WriteByte(0x111fe6, 0x08);
1650
1651
1652 // @0x3574
1653 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1654 // [0] : disable clock
1655 // [1] : invert clock
1656 // [4:2]:Select clock source
1657 // 000: dvb_clk96_buf
1658 // 001: dvb_clk86_buf
1659 // 010: dvb_clk48_buf
1660 // 011: dvb_clk43_buf
1661 // 100: adc_clk_buf
1662 // 101: 1'b0
1663 // 110: 1'b0
1664 // 111: 1'b0
1665 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1666 // [8] : disable clock
1667 // [9] : invert clock
1668 // [12:10]: Select clock source
1669 // 000: dvb_clk96_buf
1670 // 001: dvb_clk86_buf
1671 // 010: adc_clk_buf
1672 // 011: dvb_clk24_buf //JL SRAM Share (Windermere U02 ECO)
1673 // 100: dvb_clk21p5_buf //JL SRAM Share (Windermere U02 ECO)
1674 // 101: 1'b0
1675 // 110: 1'b0
1676 // 111: 1'b0
1677 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1678 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1679 HAL_DMD_RIU_WriteByte(0x111fe9, 0x08);
1680 HAL_DMD_RIU_WriteByte(0x111fe8, 0x10);
1681
1682
1683 // @0x3575
1684 // [4:0] : reg_ckg_dvbtc_rs
1685 // [0] : disable clock
1686 // [1] : invert clock
1687 // [4:2]:Select clock source
1688 // 000: mpll_clk216_buf
1689 // 001: mpll_clk172p8_buf
1690 // 010: mpll_clk144_buf
1691 // 011: mpll_clk288_buf
1692 // 100: dvb_clk96_buf
1693 // 101: dvb_clk86_buf
1694 // 110: mpll_clk57p6_buf
1695 // 111: dvb_clk43_buf
1696 // [11:8] : reg_ckg_dvbs_outer2x_dvbt_outer2x (N/A)
1697 // [15:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1698 // [12] : disable clock
1699 // [13] : invert clock
1700 // [15:14]:Select clock source
1701 // 000: 1'b0
1702 // 001: dvb_clk96_buf
1703 // 010: dvb_clk86_buf
1704 // 011: clk_miu
1705 // 100: 1'b0
1706 // 101: 1'b0
1707 // 110: 1'b0
1708 // 111: 1'b0
1709 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1710 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1711 HAL_DMD_RIU_WriteByte(0x111feb, 0x00);
1712 HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1713
1714
1715 // @0x3576
1716 // [4:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1717 // [0] : disable clock
1718 // [1] : invert clock
1719 // [4:2]:Select clock source
1720 // 000: 1'b0
1721 // 001: dvb_clk96_buf
1722 // 010: dvb_clk86_buf
1723 // 011: dvb_clk48_buf
1724 // 100: dvb_clk43_buf
1725 // 101: 1'b0
1726 // 110: 1'b0
1727 // 111: 1'b0
1728 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1729 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1730 HAL_DMD_RIU_WriteByte(0x111fed, 0x00);
1731 HAL_DMD_RIU_WriteByte(0x111fec, 0x00);
1732
1733
1734 // @0x3577
1735 // [3:0] : reg_ckg_dvbt2_inner4x_dvbtc_rs
1736 // [0] : disable clock
1737 // [1] : invert clock
1738 // [3:2]: Select clock source
1739 // 00: dvb_clk96_buf
1740 // 01: dvb_clk86_buf
1741 // 10: clk_dvbtc_rs_p
1742 // 11: 1'b0
1743 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1744 // [4] : disable clock
1745 // [5] : invert clock
1746 // [6] : Select clock source
1747 // 000: dvb_clk48_buf
1748 // 001: dvb_clk43_buf
1749 // 010: 1'b0
1750 // 011: adc_clk_buf
1751 // 100: 1'b0
1752 // 101: 1'b0
1753 // 110: 1'b0
1754 // 111: 1'b0
1755 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1756 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1757 HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1758 HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1759
1760
1761 // Maserati
1762 // @0x3578
1763 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1764 // [0] : disable clock
1765 // [1] : invert clock
1766 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1767 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1768 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1769
1770 // [3:0] : reg_ckg_sram_t22x_isdbt_inn2x_dtmb_inn2x
1771 // [0] : disable clock
1772 // [1] : invert clock
1773 // [3:2]:Select clock source
1774 // 000: clk_dvbtm_sram_t12x_t22x_p
1775 // 001: clk_isdbt_inner2x_p
1776 // 010: clk_share_dtmb_inner2x_isdbt_sram4_mux
1777 // 011:
1778 // [7:4] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_inn6x
1779 // [4] : disable clock
1780 // [5] : invert clock
1781 // [7:6]:Select clock source
1782 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1783 // 001: clk_isdbt_inner2x_p
1784 // 010: clk_share_dtmb_inner6x_isdbt_sram3_mux
1785 // 011:
1786 // [11:8] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1787 // [4] : disable clock
1788 // [5] : invert clock
1789 // [7:6]:Select clock source
1790 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1791 // 001: clk_isdbt_inner2x_p
1792 // 010: clk_share_dtmb_eq2x_isdbt_sram3_mux
1793 // 011:
1794 // [15:12]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1795 // [12] : disable clock
1796 // [13] : invert clock
1797 // [15:14]:Select clock source
1798 // 000: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1799 // 001: clk_isdbt_inner4x_p
1800 // 010: clk_dvbtc_sram2_p
1801 // 011: clk_dtmb_eq2x_inner2x_12x_mux
1802 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1803 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1804 HAL_DMD_RIU_WriteByte(0x152991, 0x00);
1805 HAL_DMD_RIU_WriteByte(0x152990, 0x01);
1806 // ==============================================================
1807 // End demod top initial setting by HK MCU ......
1808 // ==============================================================
1809 //wriu 0x101e39 0x03
1810 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
1811
1812 //==========================================================
1813 //diseqc_out : PAD_GPIO15_I
1814 //swich to Diseqc out pin from GPIO
1815 //==========================================================
1816 //Bank: Reg_CHIP_TOP(0x101e)
1817 //reg_test_out_mode : addr h��12, [6:4] = 3��h0
1818 //reg_ts4config : addr h��40, [11:10] = 2��h0
1819 //reg_ts5config : addr h��40, [13:12] = 2��h0
1820 //reg_i2smutemode : addr h��2, [15:14] = 2��h0
1821 //reg_fifthuartmode : h��4, [3:2] = 2��h0
1822 //reg_od5thuart : h��55, [5:4] = 2��h0
1823 //reg_diseqc_out_config : ��h45, [1] = 1��b1
1824 u8Temp = HAL_DMD_RIU_ReadByte(0x101E8A);
1825 u8Temp|=0x02;
1826 HAL_DMD_RIU_WriteByte(0x101E8A, u8Temp);
1827
1828 // SRAM allocation 64K avoid change souce from T2 failed.
1829 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1830 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1831
1832 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1833 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1834
1835 HAL_DMD_RIU_WriteByte(0x111703,0xff);
1836 HAL_DMD_RIU_WriteByte(0x111702,0xff);
1837
1838 HAL_DMD_RIU_WriteByte(0x111707,0xff);
1839 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1840
1841 //Diff from TV tool
1842 HAL_DMD_RIU_WriteByte(0x111708,0x01);
1843 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1844
1845 HAL_DMD_RIU_WriteByte(0x11170a,0x0f);
1846 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1847
1848 HAL_DMD_RIU_WriteByte(0x111718,0x02);
1849 HAL_DMD_RIU_WriteByte(0x111719,0x00);
1850
1851 HAL_DMD_RIU_WriteByte(0x11171a,0x00);
1852 HAL_DMD_RIU_WriteByte(0x11171b,0x00);
1853
1854 HAL_DMD_RIU_WriteByte(0x1117e0,0x14);
1855 HAL_DMD_RIU_WriteByte(0x1117e1,0x14);
1856
1857 HAL_DMD_RIU_WriteByte(0x1117e4,0x00);
1858 HAL_DMD_RIU_WriteByte(0x1117e5,0x00);
1859
1860 HAL_DMD_RIU_WriteByte(0x1117e6,0x00);
1861 HAL_DMD_RIU_WriteByte(0x1117e7,0x00);
1862
1863 DBG_INTERN_DVBS(printf("INTERN_DVBS_InitClkgen\n"));
1864 }
1865
1866 /***********************************************************************************
1867 Subject: Power on initialized function
1868 Function: INTERN_DVBS_Power_On_Initialization
1869 Parmeter:
1870 Return: MS_BOOL
1871 Remark:
1872 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)1873 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
1874 {
1875 MS_U8 status = true;
1876 //MS_U8 u8ChipVersion;
1877
1878 DBG_INTERN_DVBS(printf("INTERN_DVBS_Power_On_Initialization\n"));
1879
1880 #if defined(PWS_ENABLE)
1881 Mapi_PWS_Stop_VDMCU();
1882 #endif
1883 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
1884 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
1885
1886 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
1887 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
1888 DBG_INTERN_DVBS(printf("@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
1889
1890 //// Firmware download //////////
1891 DBG_INTERN_DVBS(printf("INTERN_DVBS Load DSP...\n"));
1892 //MsOS_DelayTask(100);
1893
1894 {
1895 if (INTERN_DVBS_LoadDSPCode() == FALSE)
1896 {
1897 DBG_INTERN_DVBS(printf("DVB-S Load DSP Code Fail\n"));
1898 return FALSE;
1899 }
1900 else
1901 {
1902 DBG_INTERN_DVBS(printf("DVB-S Load DSP Code OK\n"));
1903 }
1904 }
1905
1906 //// MCU Reset //////////
1907 if (INTERN_DVBS_Reset() == FALSE)
1908 {
1909 DBG_INTERN_DVBS(printf("INTERN_DVBS Reset...Fail\n"));
1910 return FALSE;
1911 }
1912 else
1913 {
1914 DBG_INTERN_DVBS(printf("INTERN_DVBS Reset...OK\n"));
1915 }
1916
1917
1918 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
1919 //status &= INTERN_DVBS_Active(ENABLE);//enable this
1920
1921 //Read Demod FW Version.
1922 INTERN_DVBS_Show_Demod_Version();
1923
1924 return status;
1925 }
1926 /************************************************************************************************
1927 Subject: Driving control
1928 Function: INTERN_DVBC_Driving_Control
1929 Parmeter: bInversionEnable : TRUE For High
1930 Return: void
1931 Remark:
1932 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)1933 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
1934 {
1935 MS_U8 u8Temp;
1936
1937 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1938
1939 if (bEnable)
1940 {
1941 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1942 }
1943 else
1944 {
1945 u8Temp = u8Temp & (~0x01);
1946 }
1947
1948 DBG_INTERN_DVBS(printf("---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1949 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1950 }
1951
1952 /************************************************************************************************
1953 Subject: Clk Inversion control
1954 Function: INTERN_DVBS_Clk_Inversion_Control
1955 Parmeter: bInversionEnable : TRUE For Inversion Action
1956 Return: void
1957 Remark:
1958 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)1959 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1960 {
1961 MS_U8 u8Temp;
1962
1963 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1964
1965 if (bInversionEnable)
1966 {
1967 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1968 }
1969 else
1970 {
1971 u8Temp = u8Temp & (~0x02);
1972 }
1973
1974 DBG_INTERN_DVBS(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1975 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1976 }
1977
1978 /************************************************************************************************
1979 Subject: Transport stream serial/parallel control
1980 Function: INTERN_DVBS_Serial_Control
1981 Parmeter: bEnable : TRUE For serial
1982 Return: MS_BOOL :
1983 Remark:
1984 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1985 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1986 {
1987 MS_U8 status = true;
1988 MS_U8 temp_val;
1989 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
1990
1991 if (u8TSClk == 0xFF) u8TSClk=0x13;
1992 if (bEnable) //Serial mode for TS pad
1993 {
1994 // serial
1995 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1996 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1997
1998 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1999 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2000 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2001 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2002 temp_val|=0x04;
2003 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2004 #else
2005 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2006 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2007 temp_val|=0x07;
2008 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2009 #endif
2010 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2011 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2012
2013 //// INTERN_DVBS TS Control: Serial //////////
2014
2015 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2016
2017 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2018 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2019 #else
2020 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2021 #endif
2022 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2023
2024 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2025 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2026 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2027 #else
2028 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2029 #endif
2030 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2031 }
2032 else
2033 {
2034 //parallel
2035 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2036 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2037
2038 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2039 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2040 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2041 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2042 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2043 temp_val|=0x05;
2044 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2045 #else
2046 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2047 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2048 temp_val|=0x07;
2049 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2050 #endif
2051
2052 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2053 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2054
2055 //// INTERN_DVBS TS Control: Parallel //////////
2056
2057 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2058
2059 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2060 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2061 #else
2062 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2063 #endif
2064 //// INTERN_DVBC TS Control: Parallel //////////
2065 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2066
2067 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2068 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2069 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2070 #else
2071 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2072 #endif
2073 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2074 }
2075
2076 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2077 DBG_INTERN_DVBS(printf("---> Inversion(Bit5) = %d \n",0 ));
2078 #else
2079 DBG_INTERN_DVBS(printf("---> Inversion(Bit5) = %d \n",1 ));
2080 #endif
2081
2082 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2083 return status;
2084 }
2085
2086 /************************************************************************************************
2087 Subject: TS1 output control
2088 Function: INTERN_DVBS_PAD_TS1_Enable
2089 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2090 Return: void
2091 Remark:
2092 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2093 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2094 {
2095 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_TS1_Enable... \n"));
2096
2097 if(flag) // PAD_TS1 Enable TS CLK PAD
2098 {
2099 //printf("=== TS1_Enable ===\n");
2100 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2101 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2102 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2103 }
2104 else // PAD_TS1 Disable TS CLK PAD
2105 {
2106 //printf("=== TS1_Disable ===\n");
2107 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2108 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2109 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2110 }
2111 }
2112
2113 /************************************************************************************************
2114 Subject: channel change config
2115 Function: INTERN_DVBC_Config
2116 Parmeter: BW: bandwidth
2117 Return: MS_BOOL :
2118 Remark:
2119 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2120 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2121 {
2122
2123 MS_BOOL status= true;
2124 MS_U16 u16CenterFreq;
2125 // MS_U16 u16Fc = 0;
2126 MS_U8 temp_val;
2127 MS_U8 u8Data =0;
2128 MS_U8 u8counter = 0;
2129 MS_U32 u32CurrentSR;
2130
2131 u32CurrentSR = u32SymbolRate/1000; //KHz
2132 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2133 u16CenterFreq =u32IFFreq;
2134 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2135 DBG_INTERN_DVBS(printf("INTERN_DVBS_Config, t = %d\n",MsOS_GetSystemTime()));
2136
2137 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2138 status &= INTERN_DVBS_Reset();
2139
2140 u8DemodLockFlag=0;
2141
2142 // Symbol Rate
2143 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2144 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2145 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2146 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2147
2148 #if 0
2149 //======== check SR is right or not ===========
2150 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2151 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2152 u32SR =u8Data;
2153 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2154 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2155 u32SR =((U32)u8Data<<8)|u32SR ;
2156 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2157 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2158 u32SR =((U32)u8Data<<16)|u32SR;
2159 //=================================================
2160 #endif
2161
2162 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2163 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2164 if(bSpecInv)
2165 {
2166 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2167 u8Data|=(0x02);
2168 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2169 }
2170
2171 // TS mode
2172 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2173 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2174 _bSerialTS = bSerialTS;
2175
2176 if (bSerialTS)
2177 {
2178 // serial
2179 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2180 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2181
2182 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2183 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2184 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2185 temp_val|=0x04;
2186 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2187 #else
2188 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2189 temp_val|=0x07;
2190 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2191 #endif
2192 }
2193 else
2194 {
2195 //parallel
2196 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2197 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2198
2199 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2200 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2201 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2202 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2203 temp_val|=0x05;
2204 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2205 #else
2206 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2207 temp_val|=0x07;
2208 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2209 #endif
2210 }
2211 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2212 INTERN_DVBS_Show_Demod_Version();
2213 #endif
2214
2215 //-----------------------------------------------------------
2216 //From INTERN_DVBS_Demod_Restart function.
2217
2218 //FW sw reset
2219 //[0]: 0: SW Reset, 1: Start state machine
2220 //[1]: 1: Blind scan enable, 0: manual scan
2221 //[2]: 1: Code flow track enable
2222 //[3]: 1: go to AGC state
2223 //[4]: 1: set DiSEqC
2224 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2225 u8Data = (u8Data&0xF0)|0x01;
2226 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2227 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2228 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2229 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2230
2231 u8counter = 20;
2232 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2233 {
2234 MsOS_DelayTask(1);
2235 printf("TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2236 u8Data|=0x01;
2237 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2238 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2239 DBG_INTERN_DVBS(printf(">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2240 u8counter--;
2241 }
2242
2243 if((u8Data & 0x01)==0x00)
2244 {
2245 status = FALSE;
2246 }
2247
2248 DBG_INTERN_DVBS(printf("INTERN_DVBS_config done\n"));
2249 return status;
2250 }
2251 /************************************************************************************************
2252 Subject: channel change config
2253 Function: INTERN_DVBS_Blind_Scan_Config
2254 Parmeter: BW: bandwidth
2255 Return: MS_BOOL :
2256 Remark:
2257 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2258 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2259 {
2260
2261 MS_BOOL status= true;
2262 MS_U16 u16CenterFreq;
2263 // MS_U16 u16Fc = 0;
2264 MS_U8 temp_val;
2265 MS_U8 u8Data=0;
2266 MS_U16 u16WaitCount = 0;
2267 MS_U32 u32CurrentSR;
2268
2269 u32CurrentSR = u32SymbolRate/1000; //KHz
2270 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2271 u16CenterFreq =u32IFFreq;
2272 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2273 DBG_INTERN_DVBS(printf("INTERN_DVBS_blindScan_Config, t = %d\n",MsOS_GetSystemTime()));
2274
2275 //status &= INTERN_DVBS_Reset();
2276 g_dvbs_lock = 0;
2277 u8DemodLockFlag=0;
2278
2279 // Symbol Rate
2280 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2281 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2282 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2283 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2284
2285 #if 0
2286 //======== check SR is right or not ===========
2287 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2288 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2289 u32SR =u8Data;
2290 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2291 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2292 u32SR =((U32)u8Data<<8)|u32SR ;
2293 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2294 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2295 u32SR =((U32)u8Data<<16)|u32SR;
2296 //=================================================
2297 #endif
2298
2299 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2300 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2301 if(bSpecInv)
2302 {
2303 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2304 u8Data|=(0x02);
2305 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2306 }
2307
2308 // TS mode
2309 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2310 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2311 _bSerialTS = bSerialTS;
2312 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2313
2314 if (bSerialTS)
2315 {
2316 // serial
2317 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2318 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2319
2320 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2321 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2322 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2323 temp_val|=0x04;
2324 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2325 #else
2326 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2327 temp_val|=0x07;
2328 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2329 #endif
2330 }
2331 else
2332 {
2333 //parallel
2334 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2335 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2336
2337 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2338 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2339 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2340 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2341 temp_val|=0x05;
2342 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2343 #else
2344 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2345 temp_val|=0x07;
2346 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2347 #endif
2348 }
2349 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2350 INTERN_DVBS_Show_Demod_Version();
2351 #endif
2352
2353 //-----------------------------------------------------------
2354 //From INTERN_DVBS_Demod_Restart function.
2355
2356 //enable send DiSEqC
2357 //[0]: 0: SW Reset, 1: Start state machine
2358 //[1]: 1: Blind scan enable, 0: manual scan
2359 //[2]: 1: Code flow track enable
2360 //[3]: 1: go to AGC state
2361 //[4]: 1: set DiSEqC
2362 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2363 u8Data |= 0x08;
2364 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2365
2366 u16WaitCount=0;
2367 do
2368 {
2369 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2370 u16WaitCount++;
2371 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2372 MsOS_DelayTask(1);
2373 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2374
2375 // disable blind scan
2376 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2377 u8Data&=~(0x02);
2378 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2379
2380 //disble send DiSEqC
2381 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2382 u8Data&=~(0x08);
2383 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2384
2385
2386 DBG_INTERN_DVBS(printf("INTERN_DVBS_blindScan_Config done\n"));
2387 return status;
2388 }
2389
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2390 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2391 {
2392 bPowerOn = bPowerOn;
2393 }
2394
INTERN_DVBS_Power_Save(void)2395 MS_BOOL INTERN_DVBS_Power_Save(void)
2396 {
2397 return TRUE;
2398 }
2399 //------------------------------------------------------------------
2400 // END System Info Function
2401 //------------------------------------------------------------------
2402
2403 //------------------------------------------------------------------
2404 // Get And Show Info Function
2405 //------------------------------------------------------------------
2406 /************************************************************************************************
2407 Subject: enable hw to lock channel
2408 Function: INTERN_DVBS_Active
2409 Parmeter: bEnable
2410 Return: MS_BOOL
2411 Remark:
2412 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2413 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2414 {
2415 MS_U8 status = TRUE;
2416 //MS_U8 u8Data;
2417
2418 DBG_INTERN_DVBS(printf(" @INTERN_DVBS_Active\n"));
2419
2420 //// INTERN_DVBS Finite State Machine on/off //////////
2421 #if 0
2422 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2423
2424 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2425 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2426 #else
2427
2428 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2429 #endif
2430
2431 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2432 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2433 return status;
2434 }
2435
INTERN_DVBS_GetTsDivNum(MS_FLOAT * fTSDivNum)2436 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_FLOAT* fTSDivNum)
2437 {
2438 MS_U8 u8Data = 0;
2439 MS_BOOL status = true;
2440 MS_U32 u32SymbolRate=0;
2441 //float fSymbolRate;
2442 //MS_U8 ISSY_EN = 0;
2443 MS_U8 code_rate_idx = 0;
2444 MS_U8 pilot_flag = 0;
2445 MS_U8 fec_type_idx = 0;
2446 MS_U8 mod_type_idx = 0;
2447 MS_U16 k_bch_array[2][11] ={
2448 {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2449 { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2450 MS_U16 n_ldpc_array[2] = {64800, 16200};
2451 MS_FLOAT pilot_term = 0;
2452 MS_FLOAT k_bch;
2453 MS_FLOAT n_ldpc;
2454 MS_FLOAT ts_div_num_offset = 2.0;
2455 //MS_U32 u32Time_start,u32Time_end;
2456 //MS_U32 u32temp;
2457 //MS_FLOAT pkt_interval;
2458 //MS_U8 time_counter=0;
2459
2460 INTERN_DVBS_GetCurrentSymbolRate(&u32SymbolRate);
2461 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2462 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", u32SymbolRate));
2463 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2464
2465 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2466 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2467
2468 if(!u8Data)//DVBS2
2469 {
2470 #if 0
2471 //Get DVBS2 Code Rate
2472 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2473 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2474 switch (u8Data)
2475 {
2476 case 0x03: //CR 1/2
2477 k_bch=32208.0;
2478 _u8_DVBS2_CurrentCodeRate = 5;
2479 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2480 break;
2481 case 0x01: //CR 1/3
2482 k_bch=21408.0; //8PSK???
2483 _u8_DVBS2_CurrentCodeRate = 6;
2484 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2485 break;
2486 case 0x05: //CR 2/3
2487 k_bch=43040.0;
2488 _u8_DVBS2_CurrentCodeRate = 7;
2489 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2490 break;
2491 case 0x00: //CR 1/4
2492 k_bch=16008.0; //8PSK???
2493 _u8_DVBS2_CurrentCodeRate = 8;
2494 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2495 break;
2496 case 0x06: //CR 3/4
2497 k_bch=48408.0;
2498 _u8_DVBS2_CurrentCodeRate = 9;
2499 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2500 break;
2501 case 0x02: //CR 2/5
2502 k_bch=25728.0; //8PSK???
2503 _u8_DVBS2_CurrentCodeRate = 10;
2504 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2505 break;
2506 case 0x04: //CR 3/5
2507 k_bch=38688.0;
2508 _u8_DVBS2_CurrentCodeRate = 11;
2509 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2510 break;
2511 case 0x07: //CR 4/5
2512 k_bch=51648.0;
2513 _u8_DVBS2_CurrentCodeRate = 12;
2514 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2515 break;
2516 case 0x08: //CR 5/6
2517 k_bch=53840.0;
2518 _u8_DVBS2_CurrentCodeRate = 13;
2519 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2520 break;
2521 case 0x09: //CR 8/9
2522 k_bch=57472.0;
2523 _u8_DVBS2_CurrentCodeRate = 14;
2524 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2525 break;
2526 case 0x0A: //CR 9/10
2527 k_bch=58192.0;
2528 _u8_DVBS2_CurrentCodeRate = 15;
2529 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2530 break;
2531 default:
2532 k_bch=58192.0;
2533 _u8_DVBS2_CurrentCodeRate = 15;
2534 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2535 break;
2536 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2537 #endif
2538 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2539 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2540
2541 // pilot_flag => 0 : off 1 : on
2542 // fec_type_idx => 0 : normal 1 : short
2543 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2544 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2545 //set TS clock rate
2546 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &code_rate_idx);
2547 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, &fec_type_idx);
2548 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2549 modulation_order = mod_type_idx;
2550 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &pilot_flag);
2551 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2552
2553 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, &ISSY_EN);
2554 //if(ISSY_EN==0)
2555 //{
2556 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2557 n_ldpc = n_ldpc_array[fec_type_idx];
2558 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2559 if(_bSerialTS)//serial mode
2560 {
2561 *fTSDivNum =288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate));
2562 *fTSDivNum = *fTSDivNum/2 -1;
2563 }
2564 else//parallel mode
2565 {
2566 *fTSDivNum = 288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8);
2567 *fTSDivNum = *fTSDivNum/2 -1;
2568 }
2569 *fTSDivNum-=ts_div_num_offset;
2570 //}
2571 #if 0
2572 else if(ISSY_EN==1)//ISSY = 1
2573 {
2574 //u32Time_start = msAPI_Timer_GetTime0();
2575 time_counter=0;
2576 do
2577 {
2578 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2579 u8Data &= 0x01;
2580 // u32Time_end =msAPI_Timer_GetTime0();
2581 MsOS_DelayTask(1);
2582 time_counter = time_counter +1;
2583 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2584
2585 //read pkt interval
2586 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2587 u32temp = u8Data;
2588 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2589 u32temp |= (MS_U32)u8Data<<8;
2590 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2591 u32temp |= (MS_U32)u8Data<<16;
2592 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2593 u32temp |= (MS_U32)u8Data<<24;
2594 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2595 if(_bSerialTS)//serial mode
2596 {
2597 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2598 *fTSDivNum = (*fTSDivNum-1)/2;
2599 }
2600 else
2601 {
2602 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2603 *fTSDivNum = (*fTSDivNum-1)/2;
2604 }
2605
2606 }
2607
2608 else
2609 {
2610 *fTSDivNum =0x0A;
2611 }
2612
2613 if(*fTSDivNum>255)
2614 *fTSDivNum=255;
2615 if(*fTSDivNum<1)
2616 *fTSDivNum=1;
2617
2618 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2619 /*if(u8Data) // Pilot ON
2620 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2621 else //Pilot off
2622 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2623 */
2624 if(_bSerialTS)
2625 {
2626 if(u8Data)//if pilot ON
2627 {
2628 if(modulation_order==2)
2629 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2630 else if(modulation_order==3)
2631 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2632 }
2633 else
2634 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2635 }
2636 else//Parallel mode
2637 {
2638 if(u8Data)
2639 {
2640 if(modulation_order==2)
2641 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2642 else if(modulation_order==3)
2643 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2644 }
2645 else
2646 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2647 }
2648 #endif
2649 }
2650 else //S
2651 {
2652 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2653 //u8_gCodeRate = (u8Data & 0x70)>>4;
2654 //DVBS Code Rate
2655 //switch (u8_gCodeRate)
2656 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2657 switch (u8Data)
2658 {
2659 case 0x00: //CR 1/2
2660 _u8_DVBS2_CurrentCodeRate = 0;
2661 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2662 if(_bSerialTS)
2663 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2));
2664 else
2665 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2666
2667 *fTSDivNum = *fTSDivNum/2-1-5;
2668 break;
2669 case 0x01: //CR 2/3
2670 _u8_DVBS2_CurrentCodeRate = 1;
2671 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2672 if(_bSerialTS)
2673 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2));
2674 else
2675 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2676
2677 *fTSDivNum = *fTSDivNum/2-1-5;
2678 break;
2679 case 0x02: //CR 3/4
2680 _u8_DVBS2_CurrentCodeRate = 2;
2681 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2682 if(_bSerialTS)
2683 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2));
2684 else
2685 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2686
2687 *fTSDivNum = *fTSDivNum/2-1-5;
2688 break;
2689 case 0x03: //CR 5/6
2690 _u8_DVBS2_CurrentCodeRate = 3;
2691 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2692 if(_bSerialTS)
2693 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2));
2694 else
2695 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2696
2697 *fTSDivNum = *fTSDivNum/2-1-5;
2698 break;
2699 case 0x04: //CR 7/8
2700 _u8_DVBS2_CurrentCodeRate = 4;
2701 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2702 if(_bSerialTS)
2703 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2));
2704 else
2705 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2706
2707 *fTSDivNum = *fTSDivNum/2-1-5;
2708 break;
2709 default:
2710 _u8_DVBS2_CurrentCodeRate = 4;
2711 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2712 if(_bSerialTS)
2713 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2));
2714 else
2715 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0));
2716
2717 *fTSDivNum = *fTSDivNum/2-1-5;
2718 break;
2719 }
2720 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2721 return status;
2722 }
2723
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2724 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2725 {
2726 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2727 MS_U8 bRet = TRUE;
2728 MS_FLOAT fTSDivNum=0;
2729
2730 switch( eType )
2731 {
2732 case DMD_DVBS_GETLOCK:
2733 #if (INTERN_DVBS_INTERNAL_DEBUG)
2734 INTERN_DVBS_info();
2735 #endif
2736 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2737 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2738 if ((u8Data&0x02)==0x00)//manual mode
2739 {
2740 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2741 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2742
2743 if((u8Data == 15) || (u8Data == 16))
2744 {
2745 if (u8Data==15)
2746 {
2747 _bDemodType=FALSE; //S
2748 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2749 }
2750 else if(u8Data==16)
2751 {
2752 _bDemodType=TRUE; //S2
2753 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2754 }
2755 if(g_dvbs_lock == 0)
2756 {
2757 g_dvbs_lock = 1;
2758 }
2759
2760 if(u8DemodLockFlag==0)
2761 {
2762 u8DemodLockFlag=1;
2763
2764 // caculate TS clock divider number
2765 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2766
2767 if (fTSDivNum > 0x1F)
2768 fTSDivNum = 0x1F;
2769 else if (fTSDivNum < 0x00)
2770 fTSDivNum=0x00;
2771
2772 u8Data = (MS_U8)fTSDivNum;
2773 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2774 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2775
2776 //Ts Output Enable
2777 HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
2778 }
2779 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod Lock+++\n"));
2780 bRet = TRUE;
2781 }
2782 else
2783 {
2784 if(g_dvbs_lock == 1)
2785 {
2786 g_dvbs_lock = 0;
2787 u8DemodLockFlag=0;
2788 }
2789 DBG_INTERN_DVBS(printf("@INTERN_DVBS_Demod UnLock---\n"));
2790 bRet = FALSE;
2791 }
2792
2793 if(_bSerialTS==1)
2794 {
2795 if (bRet==FALSE)
2796 {
2797 _bTSDataSwap=FALSE;
2798 }
2799 else
2800 {
2801 if (_bTSDataSwap==FALSE)
2802 {
2803 _bTSDataSwap=TRUE;
2804 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
2805 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
2806 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
2807 }
2808 }
2809 }
2810 }
2811 else
2812 {
2813 bRet = TRUE;
2814 }
2815 break;
2816
2817 default:
2818 bRet = FALSE;
2819 }
2820 return bRet;
2821 }
2822
INTERN_DVBS_GetTunrSignalLevel_PWR(void)2823 float INTERN_DVBS_GetTunrSignalLevel_PWR(void)// Need check debug out table
2824 {
2825 MS_BOOL status=TRUE;
2826 MS_U16 u16Data =0;
2827 MS_U8 u8Data =0;
2828 MS_U8 u8Index =0;
2829 float fCableLess = 0.0;
2830
2831 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
2832 {
2833 fCableLess = 0;
2834 }
2835
2836 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
2837 u8Data=(u8Data&0xF0)|0x03;
2838 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
2839
2840 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
2841 u8Data|=0x80;
2842 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
2843
2844 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
2845 u16Data=u8Data;
2846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
2847 u16Data=(u16Data<<8)|u8Data;
2848 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
2849 //MsOS_DelayTask(400);
2850
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
2852 u8Data&=~(0x80);
2853 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
2854
2855 if (status==FALSE)
2856 {
2857 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
2858 fCableLess = 0;
2859 }
2860
2861 //printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data);
2862 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
2863 {
2864 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
2865 {
2866 if (u8Index >=1)
2867 {
2868 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
2869 }
2870 else
2871 {
2872 fCableLess = _u16SignalLevel[u8Index][1];
2873 }
2874 }
2875 }
2876 //---------------------------------------------------
2877 if (fCableLess >= 350)
2878 fCableLess = fCableLess - 35;
2879 else if ((fCableLess < 350) && (fCableLess >= 250))
2880 fCableLess = fCableLess - 25;
2881 else
2882 fCableLess = fCableLess - 5;
2883
2884 if (fCableLess < 0)
2885 fCableLess = 0;
2886 if (fCableLess > 920)
2887 fCableLess = 920;
2888
2889 fCableLess = (-1.0)*(fCableLess/10.0);
2890
2891 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
2892
2893 return fCableLess;
2894 }
2895
2896 /****************************************************************************
2897 Subject: To get the Post viterbi BER
2898 Function: INTERN_DVBS_GetPostViterbiBer
2899 Parmeter: Quility
2900 Return: E_RESULT_SUCCESS
2901 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
2902 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
2903 We will not read the Period, and have the "/256/8"
2904 *****************************************************************************/
INTERN_DVBS_GetPostViterbiBer(float * postber)2905 MS_BOOL INTERN_DVBS_GetPostViterbiBer(float *postber)//POST BER //V
2906 {
2907 MS_BOOL status = true;
2908 MS_U8 reg = 0, reg_frz = 0;
2909 MS_U16 BitErrPeriod;
2910 MS_U32 BitErr;
2911
2912 /////////// Post-Viterbi BER /////////////After Viterbi
2913
2914 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
2915 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1*2+1, ®_frz);//h0001 h0001 8 8 reg_ber_en
2916 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz|0x01);
2917
2918 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
2919 // 0x47 [15:8] reg_bit_err_sblprd_15_8
2920 //KRIS register table
2921 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
2922 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
2923 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
2924 BitErrPeriod = reg;
2925
2926 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
2927 BitErrPeriod = (BitErrPeriod << 8)|reg;
2928
2929
2930 //h001d h001d 7 0 reg_bit_err_num_7_0
2931 //h001d h001d 15 8 reg_bit_err_num_15_8
2932 //h001e h001e 7 0 reg_bit_err_num_23_16
2933 //h001e h001e 15 8 reg_bit_err_num_31_24
2934
2935 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
2936 BitErr = reg;
2937 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
2938 BitErr = (BitErr << 8)|reg;
2939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
2940 BitErr = (BitErr << 8)|reg;
2941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
2942 BitErr = (BitErr << 8)|reg;
2943
2944 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2945 reg_frz=reg_frz&(~0x01);
2946 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz);
2947
2948 if (BitErrPeriod == 0 ) //PRD
2949 BitErrPeriod = 1;
2950
2951 if (BitErr <= 0 )
2952 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
2953 else
2954 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
2955
2956 if (*postber <= 0.0f)
2957 *postber = 1.0e-10f;
2958
2959 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
2960
2961 return status;
2962 }
2963
2964
INTERN_DVBS_GetPreViterbiBer(float * preber)2965 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
2966 {
2967 MS_BOOL status = true;
2968 //MS_U8 reg = 0, reg_frz = 0;
2969 //MS_U16 BitErrPeriod;
2970 //MS_U32 BitErr;
2971
2972 #if 0
2973 /////////// Pre-Viterbi BER /////////////Before Viterbi
2974
2975 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
2976 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
2977 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
2978
2979 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
2980 // 0x47 [15:8] reg_bit_err_sblprd_15_8
2981 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
2982 BitErrPeriod = reg;
2983
2984 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
2985 BitErrPeriod = (BitErrPeriod << 8)|reg;
2986
2987 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
2988 BitErrPeriod = (BitErrPeriod << 8)|reg;
2989
2990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
2991 BitErrPeriod = (BitErrPeriod << 8)|reg;
2992 BitErrPeriod = (BitErrPeriod & 0x3FFF);
2993
2994 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
2995 // 0x6b [15:8] reg_bit_err_num_15_8
2996 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
2997 // 0x6d [15:8] reg_bit_err_num_31_24
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
2999 BitErr = reg;
3000
3001 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3002 BitErr = (BitErr << 8)|reg;
3003
3004 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3005 reg_frz=reg_frz&(~0x08);
3006 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3007
3008 if (BitErrPeriod ==0 )//protect 0
3009 BitErrPeriod=1;
3010 if (BitErr <=0 )
3011 *perber=0.5f / (float)BitErrPeriod / 256;
3012 else
3013 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3014
3015 if (*perber <= 0.0f)
3016 *perber = 1.0e-10f;
3017
3018 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3019 #endif
3020
3021 return status;
3022 }
3023
3024 /****************************************************************************
3025 Subject: To get the Packet error
3026 Function: INTERN_DVBS_GetPacketErr
3027 Parmeter: pktErr
3028 Return: E_RESULT_SUCCESS
3029 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3030 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3031 We will not read the Period, and have the "/256/8"
3032 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3033 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3034 {
3035 MS_BOOL status = true;
3036 MS_U8 u8Data = 0;
3037 MS_U16 u16PktErr = 0;
3038
3039 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3040 if(!u8Data) //DVB-S2
3041 {
3042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3043 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3044
3045 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3046 u16PktErr = u8Data;
3047 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2, &u8Data);
3048 u16PktErr = (u16PktErr << 8)|u8Data;
3049
3050 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3051 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3052 }
3053 else
3054 { //DVB-S
3055 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3056 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3057
3058 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3059 u16PktErr = u8Data;
3060 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2, &u8Data);
3061 u16PktErr = (u16PktErr << 8)|u8Data;
3062
3063 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3064 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3065 }
3066 *pktErr = u16PktErr;
3067
3068 DBG_INTERN_DVBS(printf("INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3069
3070 return status;
3071 }
3072
3073 /****************************************************************************
3074 Subject: Read the signal to noise ratio (SNR)
3075 Function: INTERN_DVBS_GetSNR
3076 Parmeter: None
3077 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3078 Remark:
3079 *****************************************************************************/
INTERN_DVBS_GetSNR(float * f_snr)3080 MS_BOOL INTERN_DVBS_GetSNR(float *f_snr)//V
3081 {
3082 MS_BOOL status= TRUE;
3083 MS_U8 u8Data =0, reg_frz =0;
3084 //NDA SNR
3085 MS_U32 u32NDA_SNR_A =0;
3086 MS_U32 u32NDA_SNR_AB =0;
3087 //NDA SNR
3088 float NDA_SNR_A =0.0;
3089 float NDA_SNR_AB =0.0;
3090 float NDA_SNR =0.0;
3091 double NDA_SNR_LINEAR=0.0;
3092 //float snr_poly =0.0;
3093 //float Fixed_SNR =0.0;
3094
3095 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3096 {
3097 return 0;
3098 }
3099
3100 // freeze
3101 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3102 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3103
3104 //NDA SNR_A
3105 // read Linear_SNR
3106 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3107 u32NDA_SNR_A=(u8Data&0x03);
3108 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3109 u32NDA_SNR_A=(u32NDA_SNR_A<<8)|u8Data;
3110 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3111 u32NDA_SNR_A=(u32NDA_SNR_A<<8)|u8Data;
3112 //NDA SNR_AB
3113 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3114 u32NDA_SNR_AB=(u8Data&0x3F);
3115 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3116 u32NDA_SNR_AB = (u32NDA_SNR_AB<<8)|u8Data;
3117 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3118 u32NDA_SNR_AB=(u32NDA_SNR_AB<<8)|u8Data;
3119 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3120 u32NDA_SNR_AB=(u32NDA_SNR_AB<<8)|u8Data;
3121
3122 //UN_freeze
3123 reg_frz=reg_frz&(~0x10);
3124 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3125
3126 if (status== FALSE)
3127 {
3128 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetSNR Fail! \n"));
3129 return 0;
3130 }
3131 //NDA SNR
3132 NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3133 NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3134 //
3135 //since support 16,32APSK we need to add judgement
3136 if(modulation_order==4)
3137 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3138 else if(modulation_order==5)//(2-1.41333232789)
3139 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3140 else
3141 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3142
3143 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3144
3145 if(NDA_SNR_LINEAR<=0)
3146 NDA_SNR=1.0;
3147 else
3148 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3149
3150 //printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR);
3151 _f_DVBS_CurrentSNR = NDA_SNR;
3152 /*
3153 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3154 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3155 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3156 Fixed_SNR = NDA_SNR + snr_poly;
3157 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3158
3159 if (Fixed_SNR < 17.0)
3160 Fixed_SNR = Fixed_SNR;
3161 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3162 Fixed_SNR = Fixed_SNR - 0.8;
3163 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3164 Fixed_SNR = Fixed_SNR - 2.0;
3165 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3166 Fixed_SNR = Fixed_SNR - 3.0;
3167 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3168 Fixed_SNR = Fixed_SNR - 3.5;
3169 else if (Fixed_SNR >= 29.0)
3170 Fixed_SNR = Fixed_SNR - 3.0;
3171
3172 if (Fixed_SNR < 1.0)
3173 Fixed_SNR = 1.0;
3174 if (Fixed_SNR > 30.0)
3175 Fixed_SNR = 30.0;
3176 */
3177 *f_snr = NDA_SNR;
3178 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3179
3180 return status;
3181 }
3182
3183 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 * pu16SignalBar,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3184 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 *pu16SignalBar, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3185 {
3186 //-1.2~-92.2 dBm
3187 MS_BOOL status = true;
3188 MS_U8 u8Data =0;
3189 MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3190 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3191
3192 DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%d, RF level=%f, Table=%x\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3193
3194 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3195 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3196 // Actually, it's more reasonable, that signal level depended on cable input power level
3197 // thougth the signal isn't dvb-t signal.
3198 //
3199 // use pointer of IFAGC table to identify
3200 // case 1: RFAGC from SAR, IFAGC controlled by demod
3201 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3202 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3203 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3204 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3205 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3206 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3207 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3208 ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3209 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3210
3211 MS_U8 u8Data2 = 0;
3212 MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3213 DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3214
3215
3216 status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3217
3218 if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS)//S
3219 {
3220 float fDVBS_SSI_Pref[]=
3221 {
3222 //0, 1, 2, 3, 4
3223 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3224 };
3225 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3226 _u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x07);
3227 ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3228 }
3229 else
3230 {
3231 float fDVBS2_SSI_Pref[][11]=
3232 {
3233 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3234 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3235 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3236 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3237 };
3238
3239 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3240 _u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x3C)>>2;
3241
3242 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3243 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD6, &u8Data2);
3244
3245 if(((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x00))
3246 {
3247 _u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_QPSK;
3248 }
3249 else if (((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x80))
3250 {
3251 _u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_8PSK;//8PSK
3252 }
3253 ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3254 }
3255
3256 if(ch_power_db_rel <= -15.0f)
3257 {
3258 *pu16SignalBar = 0;
3259 }
3260 else if (ch_power_db_rel <= 0.0f)
3261 {
3262 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3263 }
3264 else if (ch_power_db_rel <= 20.0f)
3265 {
3266 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3267 }
3268 else if (ch_power_db_rel <= 35.0f)
3269 {
3270 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3271 }
3272 else
3273 {
3274 *pu16SignalBar = 100;
3275 }
3276
3277 DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3278
3279 return status;
3280 }
3281
3282 //SQI
3283 /****************************************************************************
3284 Subject: To get the DVT Signal quility
3285 Function: INTERN_DVBS_GetSignalQuality
3286 Parmeter: Quility
3287 Return: E_RESULT_SUCCESS
3288 E_RESULT_FAILURE
3289 Remark: Here we have 4 level range
3290 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3291 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3292 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3293 <4>.4th Range => Quality <10
3294 *****************************************************************************/
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3295 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3296 {
3297
3298 float fber = 0.0;
3299 //float log_ber;
3300 MS_BOOL status = TRUE;
3301 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3302 MS_U8 u8Data =0;
3303 MS_U16 u16Data =0;
3304 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3305 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3306 //fRFPowerDbm = fRFPowerDbm;
3307 float snr_poly =0.0;
3308 float Fixed_SNR =0.0;
3309 double eFlag_PER=0.0;
3310
3311 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3312 {
3313 if(_bDemodType) //S2
3314 {
3315
3316 //INTERN_DVBS_GetSNR(&f_snr);
3317 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
3318 u16Data=u8Data;
3319 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
3320 u16Data = (u16Data<<8)|u8Data;
3321 f_snr=(float)u16Data/256.0;
3322 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3323 Fixed_SNR = f_snr + snr_poly;
3324
3325 if (Fixed_SNR < 17.0)
3326 Fixed_SNR = Fixed_SNR;
3327 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3328 Fixed_SNR = Fixed_SNR - 0.8;
3329 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3330 Fixed_SNR = Fixed_SNR - 2.0;
3331 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3332 Fixed_SNR = Fixed_SNR - 3.0;
3333 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3334 Fixed_SNR = Fixed_SNR - 3.5;
3335 else if (Fixed_SNR >= 29.0)
3336 Fixed_SNR = Fixed_SNR - 3.0;
3337
3338
3339 if (Fixed_SNR < 1.0)
3340 Fixed_SNR = 1.0;
3341 if (Fixed_SNR > 30.0)
3342 Fixed_SNR = 30.0;
3343
3344 //BCH EFLAG2_Window, window size 0x2000
3345 BCH_Eflag2_Window=0x2000;
3346 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3347 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3348 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3349 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3350 if(eFlag_PER>0)
3351 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3352 else
3353 fber = 0;
3354
3355 #ifdef MSOS_TYPE_LINUX
3356 //log_ber = ( - 1) *log10f(1 / fber);
3357 if (fber > 1.0E-1)
3358 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3359 else if(fber > 8.5E-7)
3360 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3361 else
3362 ber_sqi = 100.0;
3363 #else
3364 //log_ber = ( - 1) *Log10Approx(1 / fber);
3365 if (fber > 1.0E-1)
3366 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3367 else if(fber > 8.5E-7)
3368 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3369 else
3370 ber_sqi = 100.0;
3371
3372 #endif
3373
3374 *quality = Fixed_SNR/30*ber_sqi;
3375 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3376 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3377 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3378 }
3379 else //S
3380 {
3381 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3382 {
3383 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3384 return FALSE;
3385 }
3386 _fPostBer=fber;
3387
3388
3389 if (status==FALSE)
3390 {
3391 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3392 return 0;
3393 }
3394 float fDVBS_SQI_CNref[]=
3395 { //0, 1, 2, 3, 4
3396 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3397 };
3398
3399 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3400 #if 0
3401 #ifdef MSOS_TYPE_LINUX
3402 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3403 #else
3404 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3405 #endif
3406 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3407 #endif
3408 if (fber > 2.5E-2)
3409 ber_sqi = 0.0;
3410 else if(fber > 8.5E-7)
3411 #ifdef MSOS_TYPE_LINUX
3412 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3413 #else
3414 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3415 #endif
3416 else
3417 ber_sqi = 100.0;
3418
3419 //status &= INTERN_DVBS_GetSNR(&f_snr);
3420 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
3421 u16Data=u8Data;
3422 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
3423 u16Data = (u16Data<<8)|u8Data;
3424 f_snr=(float)u16Data/256.0;
3425 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3426
3427 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3428
3429 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3430 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3431 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3432 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3433 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3434
3435 if (cn_rel < -7.0f)
3436 {
3437 *quality = 0;
3438 }
3439 else if (cn_rel < 3.0)
3440 {
3441 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3442 }
3443 else
3444 {
3445 *quality = (MS_U16)ber_sqi;
3446 }
3447
3448
3449 }
3450 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3451 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3452 return TRUE;
3453 }
3454 else
3455 {
3456 *quality = 0;
3457 }
3458
3459 return TRUE;
3460 }
3461
3462 /****************************************************************************
3463 Subject: To get the Cell ID
3464 Function: INTERN_DVBS_Get_CELL_ID
3465 Parmeter: point to return parameter cell_id
3466
3467 Return: TRUE
3468 FALSE
3469 Remark:
3470 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3471 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3472 {
3473 MS_BOOL status = true;
3474 MS_U8 value1 = 0;
3475 MS_U8 value2 = 0;
3476
3477 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3478 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3479
3480 *cell_id = ((MS_U16)value1<<8)|value2;
3481 return status;
3482 }
3483
3484 /****************************************************************************
3485 Subject: To get the DVBC Carrier Freq Offset
3486 Function: INTERN_DVBS_Get_FreqOffset
3487 Parmeter: Frequency offset (in KHz), bandwidth
3488 Return: E_RESULT_SUCCESS
3489 E_RESULT_FAILURE
3490 Remark:
3491 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)3492 MS_BOOL INTERN_DVBS_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
3493 {
3494 //MS_U8 u8Data;
3495 //MS_U16 u16Data;
3496 //MS_S16 s16CFO;
3497 //float FreqOffset;
3498 //MS_U32 u32FreqOffset = 0;
3499 //MS_U8 reg = 0;
3500 MS_BOOL status = TRUE;
3501 #if 0
3502 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3503 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3504 u16Data=u8Data;
3505 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3506 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3507 if (u16Data >= 0x8000)
3508 {
3509 u16Data=0x10000- u16Data;
3510 s16CFO=-1*u16Data;
3511 }
3512 else
3513 {
3514 s16CFO=u16Data;
3515 }
3516 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", s16CFO));
3517 if(abs(s16CFO)%1000 >= 500)
3518 {
3519 if(s16CFO < 0)
3520 *pFreqOff=(s16CFO/1000)-1.0;
3521 else
3522 *pFreqOff=(s16CFO/1000)+1.0;
3523 }
3524 else
3525 *pFreqOff = s16CFO/1000;
3526 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset *pFreqOff = %d[MHz] <<<\n", (MS_S16)*pFreqOff));
3527 // no use.
3528 u8BW = u8BW;
3529 /*
3530 printf("INTERN_DVBS_Get_FreqOffset\n");//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset\n"));
3531
3532 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x1C*2 + 1, 0x08);
3533
3534 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3535 reg|=0x80;
3536 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3537
3538 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x23*2, ®);
3539 u32FreqOffset=reg;
3540 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2 + 1, ®);
3541 u32FreqOffset=(u32FreqOffset<<8)|reg;
3542 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2, ®);
3543 u32FreqOffset=(u32FreqOffset<<8)|reg;
3544
3545 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3546 reg&=~(0x80);
3547 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3548
3549 FreqOffset=(float)u32FreqOffset;
3550 if (FreqOffset>=2048)
3551 {
3552 FreqOffset=FreqOffset-4096;
3553 }
3554 FreqOffset=(FreqOffset/4096)*SAMPLING_RATE_FS;
3555
3556 *pFreqOff = FreqOffset/1000; //KHz
3557 printf("INTERN_DVBS_Get_FreqOffset:%d[MHz]\n", (MS_S16)FreqOffset/1000);//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset:%f[MHz]\n", FreqOffset/1000));
3558 */
3559 #endif
3560 return status;
3561 }
3562
3563 /****************************************************************************
3564 Subject: To get the current modulation type at the DVB-S Demod
3565 Function: INTERN_DVBS_GetCurrentModulationType
3566 Parmeter: pointer for return QAM type
3567
3568 Return: TRUE
3569 FALSE
3570 Remark:
3571 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3572 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3573 {
3574 MS_U8 u8Data=0;
3575 MS_U16 u16tmp=0;
3576 MS_U8 MOD_type;
3577 MS_BOOL status = true;
3578 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3579
3580 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentModulationType\n"));
3581
3582 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3583
3584 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3585 // pilot_flag => 0 : off 1 : on
3586 // fec_type_idx => 0 : normal 1 : short
3587 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3588 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3589 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3590 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3591 if(u8Data)
3592 {
3593 *pQAMMode = DMD_DVBS_QPSK;
3594 modulation_order=2;
3595 printf("INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3596 //return TRUE;
3597 }
3598 else //S2
3599 {
3600 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3601 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3602 //if((u8Data & 0x0F)==0x02) //QPSK
3603 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3604 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3605 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3606
3607 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3608 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3609 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3610
3611 // INNER_DEBUG_SEL
3612 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x04*2+1, &u8Data);
3613 u8Data = u8Data & 0xc0;
3614 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3b00+0x04*2+1, u8Data);
3615
3616 // reg_plscdec_debug_out
3617 // PLSCDEC info
3618 //[0:4] PLSC MODCOD
3619 //[5] dummy frame
3620 //[6] reserve frame
3621 //[7:9] modulation type
3622 //[10:13] code rate type
3623 //[14] FEC type
3624 //[15] pilot type
3625 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2 , &u8Data);
3626 u16tmp = (MS_U16)u8Data;
3627 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2+1 , &u8Data);
3628 u16tmp |= (MS_U16)u8Data << 8;
3629 MOD_type = ((MS_U8)(u16tmp>>7)&0x07); // 2:QPSK, 3:8PSK, 4:16APSK, 5:32APSK
3630
3631 if(MOD_type==2)
3632 {
3633 *pQAMMode = DMD_DVBS_QPSK;
3634 modulation_order=2;
3635 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3636 //return TRUE;
3637 }
3638 else if(MOD_type==3)
3639 {
3640 *pQAMMode = DMD_DVBS_8PSK;
3641 modulation_order=3;
3642 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3643 //return TRUE;
3644 }
3645 else if(MOD_type==4)
3646 {
3647 *pQAMMode = DMD_DVBS_16APSK;
3648 modulation_order=4;
3649 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3650 }
3651 else
3652 {
3653 *pQAMMode = DMD_DVBS_QPSK;
3654 modulation_order=2;
3655 printf("INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
3656 return FALSE;
3657 }
3658
3659 }
3660
3661 return status;
3662 /*#else
3663 *pQAMMode = DMD_DVBS_QPSK;
3664 printf("[dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3665 //return true;
3666 #endif*/
3667 }
3668
3669 /****************************************************************************
3670 Subject: To get the current DemodType at the DVB-S Demod
3671 Function: INTERN_DVBS_GetCurrentDemodType
3672 Parmeter: pointer for return DVBS/DVBS2 type
3673
3674 Return: TRUE
3675 FALSE
3676 Remark:
3677 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)3678 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
3679 {
3680 MS_U8 u8Data=0;
3681 MS_BOOL status = true;
3682
3683 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentDemodType\n"));
3684
3685 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
3686 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
3687 //if ((u8Data & 0x01) == 0)
3688 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
3689 if(!u8Data) //S2
3690 {
3691 *pDemodType = DMD_SAT_DVBS2;
3692 DBG_INTERN_DVBS(printf("[dvbs]DemodType=DVBS2\n"));
3693 }
3694 else //S
3695 {
3696 *pDemodType = DMD_SAT_DVBS;
3697 DBG_INTERN_DVBS(printf("[dvbs]DemodType=DVBS\n"));
3698 }
3699 return status;
3700 }
3701 /****************************************************************************
3702 Subject: To get the current CodeRate at the DVB-S Demod
3703 Function: INTERN_DVBS_GetCurrentCodeRate
3704 Parmeter: pointer for return Code Rate type
3705
3706 Return: TRUE
3707 FALSE
3708 Remark:
3709 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)3710 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
3711 {
3712 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
3713 MS_BOOL status = true;
3714
3715 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate\n"));
3716 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3717 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3718 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3719 if(!u8Data)
3720 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
3721 {
3722 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3723 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3724 //u8_gCodeRate = (u8Data & 0x3C);
3725 //_u8_DVBS2_CurrentCodeRate = 0;
3726 switch (u8Data)
3727 //switch (u8_gCodeRate)
3728 {
3729 case 0x03:
3730 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3731 _u8_DVBS2_CurrentCodeRate = 5;//0;
3732 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
3733 break;
3734 case 0x01:
3735 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
3736 _u8_DVBS2_CurrentCodeRate = 6;//1;
3737 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
3738 break;
3739 case 0x05:
3740 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3741 _u8_DVBS2_CurrentCodeRate = 7;//2;
3742 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
3743 break;
3744 case 0x00:
3745 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
3746 _u8_DVBS2_CurrentCodeRate = 8;//3;
3747 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
3748 break;
3749 case 0x06:
3750 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3751 _u8_DVBS2_CurrentCodeRate = 9;//4;
3752 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
3753 break;
3754 case 0x02:
3755 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
3756 _u8_DVBS2_CurrentCodeRate = 10;//5;
3757 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
3758 break;
3759 case 0x04:
3760 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
3761 _u8_DVBS2_CurrentCodeRate = 11;//6;
3762 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
3763 break;
3764 case 0x07:
3765 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
3766 _u8_DVBS2_CurrentCodeRate = 12;//7;
3767 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
3768 break;
3769 case 0x08:
3770 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3771 _u8_DVBS2_CurrentCodeRate = 13;//8;
3772 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
3773 break;
3774 case 0x09:
3775 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
3776 _u8_DVBS2_CurrentCodeRate = 14;//9;
3777 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
3778 break;
3779 case 0x0a:
3780 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3781 _u8_DVBS2_CurrentCodeRate = 15;//10;
3782 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
3783 break;
3784 default:
3785 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3786 _u8_DVBS2_CurrentCodeRate = 15;//10;
3787 DBG_INTERN_DVBS(printf("INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
3788 }
3789 }
3790 else //S
3791 {
3792 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3793 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
3794 //u8_gCodeRate = (u8Data & 0x70)>>4;
3795 switch (u8Data)
3796 //switch (u8_gCodeRate)
3797 {
3798 case 0x00:
3799 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3800 _u8_DVBS2_CurrentCodeRate = 0;
3801 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
3802 break;
3803 case 0x01:
3804 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3805 _u8_DVBS2_CurrentCodeRate = 1;
3806 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
3807 break;
3808 case 0x02:
3809 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3810 _u8_DVBS2_CurrentCodeRate = 2;
3811 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
3812 break;
3813 case 0x03:
3814 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3815 _u8_DVBS2_CurrentCodeRate = 3;
3816 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
3817 break;
3818 case 0x04:
3819 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
3820 _u8_DVBS2_CurrentCodeRate = 4;
3821 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
3822 break;
3823 default:
3824 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
3825 _u8_DVBS2_CurrentCodeRate = 4;
3826 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
3827 }
3828 }
3829 return status;
3830 }
3831
3832 /****************************************************************************
3833 Subject: To get the current symbol rate at the DVB-S Demod
3834 Function: INTERN_DVBS_GetCurrentSymbolRate
3835 Parmeter: pointer pData for return Symbolrate
3836
3837 Return: TRUE
3838 FALSE
3839 Remark:
3840 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)3841 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
3842 {
3843 MS_U8 tmp = 0;
3844 MS_U16 u16SymbolRateTmp = 0;
3845
3846 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
3847 u16SymbolRateTmp = tmp;
3848 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
3849 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
3850
3851 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
3852 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
3853
3854 DBG_INTERN_DVBS_LOCK(printf("[dvbs]Symbol Rate=%d\n",*u32SymbolRate));
3855
3856 return TRUE;
3857 }
3858
INTERN_DVBS_Version(MS_U16 * ver)3859 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
3860 {
3861 MS_U8 status = true;
3862 MS_U8 tmp = 0;
3863 MS_U16 u16_INTERN_DVBS_Version;
3864
3865 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
3866 u16_INTERN_DVBS_Version = tmp;
3867 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
3868 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
3869 *ver = u16_INTERN_DVBS_Version;
3870
3871 return status;
3872 }
3873
INTERN_DVBS_Show_Demod_Version(void)3874 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
3875 {
3876 MS_BOOL status = true;
3877 MS_U16 u16_INTERN_DVBS_Version;
3878
3879 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
3880
3881 printf(">>> [Macan]Demod FW Version: R%d.%d <<<\n", ((u16_INTERN_DVBS_Version>>8)&0x00FF),(u16_INTERN_DVBS_Version&0x00FF));
3882
3883
3884 return status;
3885 }
3886
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)3887 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
3888 {
3889 MS_BOOL status=TRUE;
3890 MS_U8 u8Data=0;
3891
3892 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x1E, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
3893 if ((u8Data&0x03)==0x00)
3894 *pRollOff = 0; //Rolloff 0.35
3895 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
3896 *pRollOff = 1; //Rolloff 0.25
3897 else
3898 *pRollOff = 2; //Rolloff 0.20
3899 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
3900
3901 return status;
3902 }
3903
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)3904 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
3905 {
3906 MS_BOOL status=TRUE;
3907 MS_U16 u16_gSignalQualityValue;
3908 MS_U16 _u16_packetError;
3909
3910 status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
3911 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
3912
3913 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
3914 {
3915 *u8_gSQValue = 30;
3916 }
3917 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
3918 {
3919 *u8_gSQValue = 10;
3920 }
3921
3922 return status;
3923 }
3924
3925 /****************************************************************************
3926 ** Function: Read demod related information
3927 ** Polling after demod lock
3928 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
3929 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)3930 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
3931 {
3932 MS_BOOL status = TRUE;
3933
3934 //MS_U8 tmp = 0;
3935 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
3936 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
3937 //MS_U16 if_agc_err = 0;
3938 #if 0
3939 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
3940 agc_k = ((agc_k & 0xF0)>>4);
3941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
3942 agc_ref = tmp;
3943 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
3944 //agc_ref = (agc_ref<<8)|tmp;
3945 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
3946 d0_k = ((d0_k & 0xF0)>>4);
3947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
3948 d0_ref = (d0_ref & 0xFF);
3949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
3950 d1_k = (d1_k & 0xF0)>>4;
3951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
3952 d1_ref = (d1_ref & 0xFF);
3953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
3954 d2_k = ((d2_k & 0xF0)>>4);
3955 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
3956 d2_ref = (d2_ref & 0xFF);
3957 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
3958 d3_k = ((d3_k & 0xF0)>>4);
3959 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
3960 d3_ref = (d3_ref & 0xFF);
3961
3962
3963 // select IF gain to read
3964 //Debug Select
3965 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
3966 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
3967 //IF_AGC_GAIN
3968 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
3969 if_agc_gain = tmp;
3970 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
3971 if_agc_gain = (if_agc_gain<<8)|tmp;
3972
3973
3974 // select d0 gain to read.
3975 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
3976 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
3977 //DAGC0_GAIN
3978 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
3979 d0_gain = tmp;
3980 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
3981 d0_gain = (d0_gain<<8)|tmp;
3982 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
3983 d0_gain = (d0_gain<<4)|(tmp>>4);
3984
3985
3986 // select d1 gain to read.
3987 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
3988 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
3989 //DAGC1_GAIN
3990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
3991 d1_gain = tmp;
3992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
3993 d1_gain = (d1_gain<<8)|tmp;
3994
3995
3996 // select d2 gain to read.
3997 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
3998 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
3999 //DAGC2_GAIN
4000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4001 d2_gain = tmp;
4002 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4003 d2_gain = (d2_gain<<8)|tmp;
4004
4005
4006 // select d3 gain to read.
4007 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4008 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4009 //DAGC3_GAIN
4010 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4011 d3_gain = tmp;
4012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4013 d3_gain = (d3_gain<<8)|tmp;
4014 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4015 d3_gain = (d3_gain<<4)|(tmp>>4);
4016
4017
4018 // select IF gain err to read
4019 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4020 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4021
4022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4023 if_agc_err = tmp;
4024 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4025 if_agc_err = (if_agc_err<<8)|tmp;
4026
4027
4028 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4029 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4030
4031 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4032
4033 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4034 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4035
4036 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4037 #endif
4038 return status;
4039 }
4040
INTERN_DVBS_info(void)4041 void INTERN_DVBS_info(void)
4042 {
4043 //status &= INTERN_DVBS_Show_Demod_Version();
4044 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4045 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4046 }
4047
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4048 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4049 {
4050 MS_BOOL status = TRUE;
4051 //MS_U8 u8Data = 0;
4052 //MS_U16 u16Data = 0, u16Address = 0;
4053 //float psd_smooth_factor;
4054 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4055 //MS_U16 u32temp5;
4056 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4057
4058 #if 0
4059 //Lock Flag
4060 printf("========================================================================\n");
4061 printf("Debug Message Flag [Lock Flag]==========================================\n");
4062
4063 u16Address = (AGC_LOCK>>16)&0xffff;
4064 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4065 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4066 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4067 else
4068 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4069
4070 u16Address = (DAGC0_LOCK>>16)&0xffff;
4071 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4072 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4073 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4074 else
4075 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4076
4077 u16Address = (DAGC1_LOCK>>16)&0xffff;
4078 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4079 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4080 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4081 else
4082 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4083
4084 u16Address = (DAGC2_LOCK>>16)&0xffff;
4085 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4086 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4087 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4088 else
4089 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4090
4091 u16Address = (DAGC3_LOCK>>16)&0xffff;
4092 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4093 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4094 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4095 else
4096 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4097
4098 u16Address = (DCR_LOCK>>16)&0xffff;
4099 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4100 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4101 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4102 else
4103 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4104 //Mark Coarse SRD
4105 //Mark Fine SRD
4106 /*
4107 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4108 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4109 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4110 printf("[DVBS]: Close CFO =====================: Fail. \n");
4111 else
4112 printf("[DVBS]: Close CFO =====================: OK. \n");
4113 */
4114 u16Address = (TR_LOCK>>16)&0xffff;
4115 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4116 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4117 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4118 else
4119 printf("[DVBS]: TR LOCK =======================: OK. \n");
4120
4121 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4122 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4123 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4124 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4125 else
4126 printf("[DVBS]: FS Acquire ====================: OK. \n");
4127
4128 u16Address = (PR_LOCK>>16)&0xffff;
4129 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4130 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4131 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4132 else
4133 printf("[DVBS]: PR LOCK =======================: OK. \n");
4134
4135 u16Address = (EQ_LOCK>>16)&0xffff;
4136 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4137 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4138 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4139 else
4140 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4141
4142 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4143 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4144 if ((u16Data&0x0002)!=0x0002)
4145 printf("[DVBS]: P_sync ========================: Fail. \n");
4146 else
4147 printf("[DVBS]: P_sync ========================: OK. \n");
4148
4149 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4150 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4151 if ((u16Data&0x8000)!=0x8000)
4152 printf("[DVBS]: In_sync =======================: Fail. \n");
4153 else
4154 printf("[DVBS]: In_sync =======================: OK. \n");
4155 //---------------------------------------------------------
4156 //Lock Time
4157 printf("------------------------------------------------------------------------\n");
4158 printf("Debug Message [Lock Time]===============================================\n");
4159
4160 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4161 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4162 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4163 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4164 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4165 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4166 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4167 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4168 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4169 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4170 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4171 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4172 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4173 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4174 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4175
4176 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4177 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4178 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4179 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4180 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4181 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4182 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4183 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4184 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4185 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4186 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4187 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4188
4189 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4190 u16Data = u8Data;
4191 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4192 u16Data = (u16Data<<8)|u8Data;
4193 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4194 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4195 u16Data = u8Data;
4196 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4197 u16Data = (u16Data<<8)|u8Data;
4198 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4199 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4200 u16Data = u8Data;
4201 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4202 u16Data = (u16Data<<8)|u8Data;
4203 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4204 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4205 u16Data = u8Data;
4206 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4207 u16Data = (u16Data<<8)|u8Data;
4208 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4209 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4210 u16Data = u8Data;
4211 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4212 u16Data = (u16Data<<8)|u8Data;
4213 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
4214 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
4215 u16Data = u8Data;
4216 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
4217 u16Data = (u16Data<<8)|u8Data;
4218 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
4219 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
4220 u16Data = u8Data;
4221 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
4222 u16Data = (u16Data<<8)|u8Data;
4223 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
4224 //---------------------------------------------------------
4225 //FIQ Status
4226 printf("------------------------------------------------------------------------\n");
4227 printf("Debug Message [FIQ Status]==============================================\n");
4228 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4229 u16Data = u8Data;
4230 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4231 u16Data = (u16Data<<8)|u8Data;
4232
4233 if ((u16Data&0x0001)==0x0000)
4234 printf("[DVBS]: AGC Lock ======================: Fail. \n");
4235 else
4236 printf("[DVBS]: AGC Lock ======================: OK. \n");
4237
4238 if ((u16Data&0x0002)==0x0000)
4239 printf("[DVBS]: Hum Detect ====================: Fail. \n");
4240 else
4241 printf("[DVBS]: Hum Detect ====================: OK. \n");
4242
4243 if ((u16Data&0x0004)==0x0000)
4244 printf("[DVBS]: DCR Lock ======================: Fail. \n");
4245 else
4246 printf("[DVBS]: DCR Lock ======================: OK. \n");
4247
4248 if ((u16Data&0x0008)==0x0000)
4249 printf("[DVBS]: IIS Detect ====================: Fail. \n");
4250 else
4251 printf("[DVBS]: IIS Detect ====================: OK. \n");
4252
4253 if ((u16Data&0x0010)==0x0000)
4254 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
4255 else
4256 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
4257
4258 if ((u16Data&0x0020)==0x0000)
4259 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
4260 else
4261 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
4262
4263 if ((u16Data&0x0040)==0x0000)
4264 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
4265 else
4266 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
4267
4268 if ((u16Data&0x0080)==0x0000)
4269 printf("[DVBS]: CCI Detect ====================: Fail. \n");
4270 else
4271 printf("[DVBS]: CCI Detect ====================: OK. \n");
4272
4273 if ((u16Data&0x0100)==0x0000)
4274 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
4275 else
4276 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
4277
4278 if ((u16Data&0x0200)==0x0000)
4279 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
4280 else
4281 printf("[DVBS]: SRD Fine Done =================: OK. \n");
4282
4283 if ((u16Data&0x0400)==0x0000)
4284 printf("[DVBS]: EQ Lock =======================: Fail. \n");
4285 else
4286 printf("[DVBS]: EQ Lock =======================: OK. \n");
4287
4288 if ((u16Data&0x0800)==0x0000)
4289 printf("[DVBS]: FineFE Done ===================: Fail. \n");
4290 else
4291 printf("[DVBS]: FineFE Done ===================: OK. \n");
4292
4293 if ((u16Data&0x1000)==0x0000)
4294 printf("[DVBS]: PR Lock =======================: Fail. \n");
4295 else
4296 printf("[DVBS]: PR Lock =======================: OK. \n");
4297
4298 if ((u16Data&0x2000)==0x0000)
4299 printf("[DVBS]: Reserved Frame ================: Fail. \n");
4300 else
4301 printf("[DVBS]: Reserved Frame ================: OK. \n");
4302
4303 if ((u16Data&0x4000)==0x0000)
4304 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
4305 else
4306 printf("[DVBS]: Dummy Frame ===================: OK. \n");
4307
4308 if ((u16Data&0x8000)==0x0000)
4309 printf("[DVBS]: PLSC Done =====================: Fail. \n");
4310 else
4311 printf("[DVBS]: PLSC Done =====================: OK. \n");
4312
4313 printf("------------------------------------------------------------------------\n");
4314 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4315 u16Data = u8Data;
4316 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4317 u16Data = (u16Data<<8)|u8Data;
4318 if ((u16Data&0x0001)==0x0000)
4319 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
4320 else
4321 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
4322
4323 if ((u16Data&0x0002)==0x0000)
4324 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
4325 else
4326 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
4327
4328 if ((u16Data&0x0004)==0x0000)
4329 printf("[DVBS]: FS Acquisition ================: Fail. \n");
4330 else
4331 printf("[DVBS]: FS Acquisition ================: OK. \n");
4332
4333 if ((u16Data&0x0008)==0x0000)
4334 printf("[DVBS]: TR Lock =======================: Fail. \n");
4335 else
4336 printf("[DVBS]: TR Lock =======================: OK. \n");
4337
4338 if ((u16Data&0x0010)==0x0000)
4339 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
4340 else
4341 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
4342
4343 if ((u16Data&0x0020)==0x0000)
4344 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
4345 else
4346 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
4347
4348 if ((u16Data&0x0040)==0x0000)
4349 printf("[DVBS]: Fsync Found ===================: Fail. \n");
4350 else
4351 printf("[DVBS]: Fsync Found ===================: OK. \n");
4352
4353 if ((u16Data&0x0080)==0x0000)
4354 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
4355 else
4356 printf("[DVBS]: Fsync Lock ====================: OK. \n");
4357
4358 if ((u16Data&0x0100)==0x0000)
4359 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
4360 else
4361 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
4362
4363 if ((u16Data&0x0200)==0x0000)
4364 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
4365 else
4366 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
4367
4368 if ((u16Data&0x0400)==0x0000)
4369 printf("[DVBS]: False Alarm ===================: Fail. \n");
4370 else
4371 printf("[DVBS]: False Alarm ===================: OK. \n");
4372
4373 if ((u16Data&0x0800)==0x0000)
4374 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
4375 else
4376 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
4377
4378 if ((u16Data&0x1000)==0x0000)
4379 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
4380 else
4381 printf("[DVBS]: Uncrt Over ====================: OK. \n");
4382
4383 if ((u16Data&0x2000)==0x0000)
4384 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
4385 else
4386 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
4387
4388 //if ((u16Data&0x4000)==0x0000)
4389 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
4390 //else
4391 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
4392
4393 //if ((u16Data&0x8000)==0x0000)
4394 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
4395 //else
4396 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
4397
4398 /*
4399 printf("------------------------------------------------------------------------\n");
4400 u16Address = 0x0B64;
4401 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
4402 u16Data = u8Data;
4403 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
4404 u16Data = (u16Data<<8)|u8Data;
4405 if ((u16Data&0x0001)==0x0000)
4406 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
4407 else
4408 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
4409
4410 if ((u16Data&0x0002)==0x0000)
4411 printf("[DVBS]: BCH Busy ======================: Fail. \n");
4412 else
4413 printf("[DVBS]: BCH Busy ======================: OK. \n");
4414
4415 if ((u16Data&0x0004)==0x0000)
4416 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
4417 else
4418 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
4419
4420 if ((u16Data&0x0008)==0x0000)
4421 printf("[DVBS]: LDPC Win ======================: Fail. \n");
4422 else
4423 printf("[DVBS]: LDPC Win ======================: OK. \n");
4424
4425 if ((u16Data&0x0010)==0x0000)
4426 printf("[DVBS]: LDPC Error ====================: Fail. \n");
4427 else
4428 printf("[DVBS]: LDPC Error ====================: OK. \n");
4429
4430 if ((u16Data&0x0020)==0x0000)
4431 printf("[DVBS]: Out BCH Error =================: Fail. \n");
4432 else
4433 printf("[DVBS]: Out BCH Error =================: OK. \n");
4434
4435 if ((u16Data&0x0040)==0x0000)
4436 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
4437 else
4438 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
4439
4440 if ((u16Data&0x0080)==0x0000)
4441 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
4442 else
4443 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
4444
4445 if ((u16Data&0x0100)==0x0000)
4446 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
4447 else
4448 printf("[DVBS]: Packet Error Out ==============: OK. \n");
4449
4450 if ((u16Data&0x0200)==0x0000)
4451 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
4452 else
4453 printf("[DVBS]: BBH CRC Error =================: OK. \n");
4454
4455 if ((u16Data&0x0400)==0x0000)
4456 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
4457 else
4458 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
4459
4460 if ((u16Data&0x0800)==0x0000)
4461 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
4462 else
4463 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
4464
4465 if ((u16Data&0x1000)==0x0000)
4466 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
4467 else
4468 printf("[DVBS]: Syncd Check Error =============: OK. \n");
4469
4470 //if ((u16Data&0x2000)==0x0000)
4471 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
4472 //else
4473 // printf("[DVBS]: Syncd Check Error======: OK. \n");
4474
4475 if ((u16Data&0x4000)==0x0000)
4476 printf("[DVBS]: Demap Init ====================: Fail. \n");
4477 else
4478 printf("[DVBS]: Demap Init ====================: OK. \n");
4479 */
4480 //Spectrum Information
4481 printf("------------------------------------------------------------------------\n");
4482
4483 u16Address = 0x2836;
4484 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4485 psd_smooth_factor=(u16Data>>8)&0x7F;
4486
4487 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
4488 u16Data = u8Data;
4489 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
4490 u16Data = (u16Data<<8)|u8Data;
4491 u32temp5=u16Data;
4492 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
4493 u16Data = u8Data;
4494 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
4495 u16Data = (u16Data<<8)|u8Data;
4496 u32temp5|=(u16Data<<16);
4497 if (psd_smooth_factor!=0)
4498 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4499 else
4500 srd_left_top_value=0;
4501
4502 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4503 u16Data = u8Data;
4504 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4505 u16Data = (u16Data<<8)|u8Data;
4506 u32temp5=u16Data;
4507 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
4508 u16Data = u8Data;
4509 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
4510 u16Data = (u16Data<<8)|u8Data;
4511 u32temp5|=(u16Data<<16);
4512 if (psd_smooth_factor!=0)
4513 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4514 else
4515 srd_left_bottom_value=0;
4516
4517 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
4518 u16Data = u8Data;
4519 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
4520 u16Data = (u16Data<<8)|u8Data;
4521 u32temp5=u16Data;
4522 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
4523 u16Data = u8Data;
4524 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
4525 u16Data = (u16Data<<8)|u8Data;
4526 u32temp5|=(u16Data<<16);
4527 if (psd_smooth_factor!=0)
4528 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4529 else
4530 srd_right_top_value=0;
4531
4532 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
4533 u16Data = u8Data;
4534 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
4535 u16Data = (u16Data<<8)|u8Data;
4536 u32temp5=u16Data;
4537 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
4538 u16Data = u8Data;
4539 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
4540 u16Data = (u16Data<<8)|u8Data;
4541 u32temp5|=(u16Data<<16);
4542 if (psd_smooth_factor!=0)
4543 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4544 else
4545 srd_right_bottom_value=0;
4546
4547 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
4548 u16Data = u8Data;
4549 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
4550 u16Data = (u16Data<<8)|u8Data;
4551 srd_left=u16Data;
4552 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
4553 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
4554 u16Data = u8Data;
4555 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
4556 u16Data = (u16Data<<8)|u8Data;
4557 srd_right=u16Data;
4558 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
4559 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
4560 u16Data = u8Data;
4561 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
4562 u16Data = (u16Data<<8)|u8Data;
4563 srd_left_top=u16Data;
4564 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
4565 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
4566 u16Data = u8Data;
4567 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
4568 u16Data = (u16Data<<8)|u8Data;
4569 srd_left_bottom=u16Data;
4570 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
4571 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
4572 u16Data = u8Data;
4573 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
4574 u16Data = (u16Data<<8)|u8Data;
4575 srd_right_top=u16Data;
4576 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
4577 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
4578 u16Data = u8Data;
4579 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
4580 u16Data = (u16Data<<8)|u8Data;
4581 srd_right_bottom=u16Data;
4582 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
4583
4584 printf("-----------------------------------------\n");
4585 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
4586 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
4587 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
4588 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
4589
4590 if (psd_smooth_factor!=0)
4591 {
4592 if ((srd_left_top-srd_left_bottom)!=0)
4593 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
4594 else
4595 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
4596
4597 if((srd_right_bottom - srd_right_top)!=0)
4598 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
4599 else
4600 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
4601
4602 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
4603 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
4604 else
4605 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
4606 }
4607 else
4608 {
4609 printf("[DVBS]: Left Slope ======================: %d\n", 0);
4610 printf("[DVBS]: Right Slope =====================: %d\n", 0);
4611 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
4612 }
4613 #endif
4614 return status;
4615 }
4616
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)4617 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
4618 {
4619 MS_BOOL bRet = FALSE;
4620 #if 0
4621 MS_U8 u8Data = 0;
4622 MS_U16 u16Data = 0;
4623 MS_U16 u16Address = 0;
4624 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
4625 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
4626 float AGC_IF_Gain;
4627 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
4628 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
4629 float DCR_Offset_I, DCR_Offset_Q;
4630 float FineCFO_loop_input_value, FineCFO_loop_out_value;
4631 double FineCFO_loop_ki_value, TR_loop_ki;
4632 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
4633 float IQB_Phase, IQB_Gain;
4634 MS_U16 IIS_cnt, ConvegenceLen;
4635 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
4636 float Packet_Err, BER;
4637 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
4638 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
4639 float Eq_variance_da, Eq_variance_dd;
4640 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
4641 MS_U16 BitErr, BitErrPeriod;
4642 MS_BOOL BEROver;
4643
4644 //Fb
4645 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
4646 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
4647 if((u8Data&0x02)==0x00) //Manual Tune
4648 {
4649 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
4650 }
4651 else //Blind Scan
4652 {
4653 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4654 u16Data = u8Data;
4655 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4656 u16Data = (u16Data<<8)|u8Data;
4657 u32DebugInfo_Fb = u16Data;
4658 }
4659 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
4660 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
4661 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
4662 //---------------------------------------------------------
4663 //Page1-GAIN & DCR
4664 //---------------------------------------------------------
4665 //GAIN
4666 printf("\n");
4667 printf("========================================================================\n");
4668 printf("Debug Message [GAIN & DCR]==============================================\n");
4669
4670 //Debug select
4671 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
4672 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4673 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
4674 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4675
4676 //Freeze and dump
4677 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4678 //AGC_IF_GAIN
4679 u16Address = (DEBUG_OUT_AGC)&0xffff;
4680 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4681 AGC_IF_Gain=u16Data;
4682 //Unfreeze
4683 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4684
4685 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
4686 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
4687 //---------------------------------------------------------
4688 //Debug select
4689 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
4690 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4691 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
4692 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4693
4694 //Freeze and dump
4695 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4696 //DAGC0_GAIN
4697 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4698 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4699 u16Data = (u16Data>>4);
4700 DAGC0_Gain=(u16Data&0x0fff);
4701 //Unfreeze
4702 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4703 //---------------------------------------------------------
4704 //Debug select
4705 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
4706 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4707 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
4708 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4709
4710 //Freeze and dump
4711 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4712 //DAGC1_GAIN
4713 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4714 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4715 DAGC1_Gain=(u16Data&0x07ff);
4716 //Unfreeze
4717 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4718 //---------------------------------------------------------
4719 //Debug select
4720 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
4721 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4722 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
4723 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4724
4725 //Freeze and dump
4726 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4727 //DAGC2_GAIN
4728 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4729 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4730 DAGC2_Gain=(u16Data&0x0fff);
4731 //Unfreeze
4732 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4733 //---------------------------------------------------------
4734 //Debug select
4735 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
4736 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4737 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
4738 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4739
4740 //Freeze and dump
4741 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4742 //DAGC3_GAIN
4743 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4744 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4745 u16Data = (u16Data>>4);
4746 DAGC3_Gain=(u16Data&0x0fff);
4747 //Unfreeze
4748 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4749 //---------------------------------------------------------
4750
4751 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
4752 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
4753 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
4754 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
4755 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
4756 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
4757 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
4758 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
4759
4760 //---------------------------------------------------------
4761 //ERROR
4762 //Debug select
4763 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
4764 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4765 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
4766 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4767
4768 //Freeze and dump
4769 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4770 //AGC_ERR
4771 u16Address = (DEBUG_OUT_AGC)&0xffff;
4772 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4773 AGC_Err=(u16Data&0x03ff);
4774 //Unfreeze
4775 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4776
4777 //Debug select
4778 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
4779 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4780 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
4781 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4782
4783 //Freeze and dump
4784 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4785 //DAGC0_ERR
4786 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4787 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4788 u16Data = (u16Data>>4);
4789 DAGC0_Err=(u16Data&0x7fff);
4790 //Unfreeze
4791 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4792
4793 //Debug select
4794 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
4795 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4796 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
4797 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4798
4799 //Freeze and dump
4800 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4801 //DAGC1_ERR
4802 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4803 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4804 DAGC1_Err=(u16Data&0x7fff);
4805 //Unfreeze
4806 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4807
4808 //Debug select
4809 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
4810 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4811 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
4812 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4813
4814 //Freeze and dump
4815 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4816 //DAGC2_ERR
4817 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4818 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4819 DAGC2_Err=(u16Data&0x7fff);
4820 //Unfreeze
4821 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4822
4823 //Debug select
4824 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
4825 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4826 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
4827 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4828
4829 //Freeze and dump
4830 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4831 //DAGC3_ERR
4832 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4833 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4834 u16Data = (u16Data>>4);
4835 DAGC3_Err=(u16Data&0x7fff);
4836 //Unfreeze
4837 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4838
4839 if (AGC_Err>=0x200)
4840 AGC_Err=AGC_Err-0x400;
4841 if (DAGC0_Err>=0x4000)
4842 DAGC0_Err=DAGC0_Err-0x8000;
4843 if (DAGC1_Err>=0x4000)
4844 DAGC1_Err=DAGC1_Err-0x8000;
4845 if (DAGC2_Err>=0x4000)
4846 DAGC2_Err=DAGC2_Err-0x8000;
4847 if (DAGC3_Err>=0x4000)
4848 DAGC3_Err=DAGC3_Err-0x8000;
4849
4850 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
4851 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
4852 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
4853 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
4854 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
4855 //---------------------------------------------------------
4856 //PEAK_MEAN
4857 //Debug select
4858 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
4859 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4860 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
4861 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4862
4863 //Freeze and dump
4864 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4865 //DAGC0_PEAK_MEAN
4866 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4867 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4868 u16Data = (u16Data>>4);
4869 DAGC0_Peak_Mean=(u16Data&0x0fff);
4870 //Unfreeze
4871 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4872
4873 //Debug select
4874 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
4875 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4876 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
4877 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4878
4879 //Freeze and dump
4880 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4881 //DAGC1_PEAK_MEAN
4882 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4883 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4884 DAGC1_Peak_Mean=(u16Data&0x0fff);
4885 //Unfreeze
4886 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4887
4888 //Debug select
4889 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
4890 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4891 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
4892 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4893
4894 //Freeze and dump
4895 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4896 //DAGC2_PEAK_MEAN
4897 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4898 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4899 DAGC2_Peak_Mean=(u16Data&0x0fff);
4900 //Unfreeze
4901 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4902
4903 //Debug select
4904 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
4905 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4906 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
4907 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4908
4909 //Freeze and dump
4910 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4911 //DAGC3_PEAK_MEAN
4912 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4913 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4914 u16Data = (u16Data>>4);
4915 DAGC3_Peak_Mean=(u16Data&0x0fff);
4916 //Unfreeze
4917 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4918
4919
4920 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
4921 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
4922 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
4923 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
4924
4925 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
4926 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
4927 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
4928 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
4929 //---------------------------------------------------------
4930 //Freeze and dump
4931 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4932
4933 u16Address = (DCR_OFFSET)&0xffff;
4934 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4935
4936 DCR_Offset_I=(u16Data&0xff);
4937 if (DCR_Offset_I >= 0x80)
4938 DCR_Offset_I = DCR_Offset_I-0x100;
4939 DCR_Offset_I = DCR_Offset_I/0x80;
4940
4941 DCR_Offset_Q=(u16Data>>8)&0xff;
4942 if (DCR_Offset_Q >= 0x80)
4943 DCR_Offset_Q = DCR_Offset_Q-0x100;
4944 DCR_Offset_Q = DCR_Offset_Q/0x80;
4945
4946 //Unfreeze
4947 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4948
4949 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
4950 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
4951 //---------------------------------------------------------
4952 ////Page1-FineCFO & PR & IIS & IQB
4953 //---------------------------------------------------------
4954 //FineCFO
4955 printf("------------------------------------------------------------------------\n");
4956 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
4957 //Debug Select
4958 u16Address = INNER_DEBUG_SEL;
4959 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4960 u16Data=((u16Data&0xC0FF)|0x0400);
4961 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4962
4963 //Freeze and dump
4964 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
4965
4966 u16Address = INNEREXT_FINEFE_DBG_OUT0;
4967 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4968 FineCFO_loop_out_value=u16Data;
4969 u16Address = INNEREXT_FINEFE_DBG_OUT2;
4970 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4971 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
4972
4973 //Too large.Use 10Bit
4974 u16Address = INNEREXT_FINEFE_KI_FF0;
4975 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4976 FineCFO_loop_ki_value=u16Data;
4977 u16Address = INNEREXT_FINEFE_KI_FF2;
4978 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4979 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
4980 u16Address = INNEREXT_FINEFE_KI_FF4;
4981 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4982 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
4983 //Unfreeze
4984 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
4985
4986 //---------------------------------------------------------
4987 //Debug Select
4988 u16Address = INNER_DEBUG_SEL;
4989 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4990 u16Data=((u16Data&0xC0FF)|0x0100);
4991 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4992
4993 //Freeze and dump
4994 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
4995
4996 u16Address = INNEREXT_FINEFE_DBG_OUT0;
4997 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4998 FineCFO_loop_input_value=u16Data;
4999 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5000 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5001 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5002
5003 //Unfreeze
5004 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5005
5006 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5007
5008 if (FineCFO_loop_out_value > 8388608)
5009 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5010 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5011 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5012 if (FineCFO_loop_input_value> 1048576)
5013 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5014
5015 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5016 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5017 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5018
5019 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5020 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5021 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5022
5023 //---------------------------------------------------------
5024 //Phase Recovery
5025 //Debug select
5026 u16Address = INNER_DEBUG_SEL;
5027 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5028 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5029 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5030
5031 //Freeze and dump
5032 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5033
5034 u16Address = INNER_PR_DEBUG_OUT0;
5035 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5036 PR_out_value=u16Data;
5037 if (PR_out_value>=0x1000)
5038 PR_out_value=PR_out_value-0x2000;
5039
5040 //Unfreeze
5041 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5042 //---------------------------------------------------------
5043 //Debug select
5044 u16Address = INNER_DEBUG_SEL;
5045 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5046 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5047 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5048
5049 //Freeze and dump
5050 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5051
5052 u16Address = INNER_PR_DEBUG_OUT0;
5053 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5054 PR_in_value=u16Data;
5055 u16Address = INNER_PR_DEBUG_OUT2;
5056 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5057 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5058 if (PR_in_value>=0x80000)
5059 PR_in_value=PR_in_value-0x100000;
5060
5061 //Unfreeze
5062 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5063 //---------------------------------------------------------
5064 //Debug select
5065 u16Address = INNER_DEBUG_SEL;
5066 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5067 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5068 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5069
5070 //Freeze and dump
5071 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5072
5073 u16Address = INNER_PR_DEBUG_OUT0;
5074 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5075 PR_loop_ki=u16Data;
5076 u16Address = INNER_PR_DEBUG_OUT2;
5077 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5078 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5079 if (PR_loop_ki>=0x800000)
5080 PR_loop_ki=PR_loop_ki-0x1000000;
5081
5082 //Unfreeze
5083 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5084 //---------------------------------------------------------
5085 //Debug select
5086 u16Address = INNER_DEBUG_SEL;
5087 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5088 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5089 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5090
5091 //Freeze and dump
5092 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5093
5094 u16Address = INNER_PR_DEBUG_OUT0;
5095 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5096 PR_loopback_ki=u16Data;
5097 u16Address = INNER_PR_DEBUG_OUT2;
5098 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5099 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5100 if (PR_loopback_ki>=0x800000)
5101 PR_loopback_ki=PR_loopback_ki-0x1000000;
5102
5103 //Unfreeze
5104 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5105
5106 PR_out_value = ((float)PR_out_value/4096);
5107 PR_in_value = ((float)PR_in_value/131072);
5108 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5109 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5110
5111 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5112 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5113 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5114 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5115 //---------------------------------------------------------
5116 //IIS
5117 //Freeze and dump
5118 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5119
5120 u16Address = (IIS_COUNT0)&0xffff;
5121 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5122 IIS_cnt=u16Data;
5123 u16Address = (IIS_COUNT2)&0xffff;
5124 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5125 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5126
5127 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5128
5129 //Unfreeze
5130 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5131 //IQB
5132 //Freeze and dump
5133 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5134
5135 u16Address = (IQB_PHASE)&0xffff;
5136 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5137 IQB_Phase=u16Data&0x3FF;
5138 if (IQB_Phase>=0x200)
5139 IQB_Phase=IQB_Phase-0x400;
5140 IQB_Phase=IQB_Phase/0x400*180;
5141
5142 u16Address = (IQB_GAIN)&0xffff;
5143 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5144 IQB_Gain=u16Data&0x7FF;
5145 IQB_Gain=IQB_Gain/0x400;
5146
5147 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5148 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5149
5150 //Unfreeze
5151 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5152 //---------------------------------------------------------
5153 //SNR
5154 //Freeze and dump
5155 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5156
5157 Eq_variance_da=0;
5158 u16Address = 0x249E;
5159 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5160 Eq_variance_da=u16Data;
5161 u16Address = 0x24A0;
5162 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5163 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5164
5165 if (Eq_variance_da==0)
5166 Eq_variance_da=1;
5167 Linear_SNR_da=1.0/Eq_variance_da;
5168 SNR_da_dB=10*log10(Linear_SNR_da);
5169
5170 Eq_variance_dd=0;
5171 u16Address = 0x24A2;
5172 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5173 Eq_variance_dd=u16Data;
5174 u16Address = 0x24A4;
5175 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5176 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5177
5178 if (Eq_variance_dd==0)
5179 Eq_variance_dd=1;
5180 Linear_SNR_dd=1.0/Eq_variance_dd;
5181 SNR_dd_dB=10*log10(Linear_SNR_dd);
5182
5183 ndasnr_a=0;
5184 u16Address = 0x248C;
5185 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5186 ndasnr_a=u16Data;
5187 u16Address = 0x248E;
5188 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5189 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5190
5191 ndasnr_ab=0;
5192 u16Address = 0x2490;
5193 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5194 ndasnr_ab=u16Data;
5195 u16Address = 0x2492;
5196 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5197 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5198
5199 ndasnr_ab=sqrt(ndasnr_ab);
5200 if (ndasnr_ab==0)
5201 ndasnr_ab=1;
5202 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5203 if (ndasnr_ratio> 1)
5204 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5205 else
5206 SNR_nda_dB=0;
5207
5208 u16Address = 0x24BA;
5209 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5210 Linear_SNR=u16Data;
5211 u16Address = 0x24BC;
5212 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5213 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
5214 if (Linear_SNR==0)
5215 Linear_SNR=1;
5216 Linear_SNR=10*log10(Linear_SNR);
5217
5218 //Unfreeze
5219 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5220 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
5221 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
5222 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
5223 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
5224 //---------------------------------------------------------
5225 printf("------------------------------------------------------------------------\n");
5226 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
5227 //BER
5228 //freeze
5229 u16Address = 0x2103;
5230 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5231 u16Data=u16Data|0x0001;
5232 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5233
5234 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
5235 u16Address = 0x2166;
5236 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5237 Packet_Err=u16Data;
5238
5239 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
5240
5241 /////////// Post-Viterbi BER /////////////
5242 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
5243 // [15:8] reg_bit_err_sblprd_15_8
5244 u16Address = 0x2146;
5245 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5246 BitErrPeriod=u16Data;
5247
5248 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
5249 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
5250 u16Address = 0x216A;
5251 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5252 BitErr=u16Data;
5253 u16Address = 0x216C;
5254 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5255 BitErr=(u16Data<<16)|BitErr;
5256
5257 if (BitErrPeriod ==0 )//protect 0
5258 BitErrPeriod=1;
5259 if (BitErr <=0 )
5260 BER=0.5 / (float)(BitErrPeriod*128*188*8);
5261 else
5262 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
5263
5264 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
5265
5266 // bank 7 0x19 [7] reg_bit_err_num_freeze
5267 u16Address = 0x2103;
5268 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5269 u16Data=u16Data&(~0x0001);
5270 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5271
5272 /////////// Pre-Viterbi BER /////////////
5273 // bank 17 0x08 [3] reg_rd_freezeber
5274 u16Address = 0x2110;
5275 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5276 u16Data=u16Data|0x0008;
5277 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5278
5279 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
5280 // bank 17 0x0c [5:0] reg_ber_timerh
5281 u16Address = 0x2116;
5282 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5283 BitErrPeriod=u16Data;
5284 u16Address = 0x2118;
5285 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5286 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
5287
5288 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
5289 u16Address = 0x211E;
5290 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5291 BitErr=u16Data;
5292
5293 // bank 17 0x0D [13:8] reg_cor_intstat_reg
5294 u16Address = 0x211A;
5295 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5296 if (u16Data & 0x1000)
5297 {
5298 BEROver = true;
5299 }
5300 else
5301 {
5302 BEROver = false;
5303 }
5304
5305 if (BitErrPeriod ==0 )//protect 0
5306 BitErrPeriod=1;
5307 if (BitErr <=0 )
5308 BER=0.5 / (float)(BitErrPeriod) / 256;
5309 else
5310 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
5311 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
5312
5313 // bank 17 0x08 [3] reg_rd_freezeber
5314 u16Address = 0x2110;
5315 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5316 u16Data=u16Data&(~0x0008);
5317 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5318
5319 u16Address = 0x2188;
5320 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5321 ConvegenceLen = ((u16Data>>8)&0xFF);
5322 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
5323
5324 //---------------------------------------------------------
5325 //Timing Recovery
5326 //Debug select
5327 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
5328 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5329 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
5330 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5331
5332 //Freeze and dump
5333 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5334
5335 u16Address = (TR_INDICATOR_FF0)&0xffff;
5336 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5337 TR_Indicator_ff=u16Data;
5338 u16Address = (TR_INDICATOR_FF0)&0xffff;
5339 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5340 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
5341 if (TR_Indicator_ff >= 0x400000)
5342 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
5343
5344 //Unfreeze
5345 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5346
5347 //Debug select
5348 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
5349 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5350 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
5351 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5352
5353 //Freeze and dump
5354 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5355
5356 u16Address = (TR_INDICATOR_FF0)&0xffff;
5357 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5358 TR_SFO_Converge=u16Data;
5359 u16Address = (TR_INDICATOR_FF0)&0xffff;
5360 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5361 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
5362 if (TR_SFO_Converge >= 0x400000)
5363 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
5364
5365 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
5366 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5367 TR_loop_ki=u16Data;
5368 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
5369 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5370 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
5371 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
5372 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5373 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
5374 if (TR_loop_ki>=pow(2.0, 40))
5375 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
5376
5377 //Unfreeze
5378 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5379
5380 //Debug select
5381 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
5382 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5383 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
5384 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5385
5386 //Freeze and dump
5387 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5388
5389 u16Address = (TR_INDICATOR_FF0)&0xffff;
5390 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5391 TR_loop_input=u16Data;
5392 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
5393 //addr=(TR_INDICATOR_FF1)&0xff;
5394 //if(InformRead(banknum, addr, &data)==FALSE) return;
5395 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
5396 if (TR_loop_input >= 0x8000)
5397 TR_loop_input=TR_loop_input - 0x10000;
5398
5399 //Unfreeze
5400 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5401
5402 Fs_value=u32DebugInfo_Fs;
5403 Fb_value=u32DebugInfo_Fb;
5404 TR_tmp0=(float)TR_SFO_Converge/0x200000;
5405 TR_tmp2=TR_loop_ki/pow(2.0, 39);
5406 TR_tmp1=(float)Fs_value/2/Fb_value;
5407
5408 TR_Indicator_ff = (TR_Indicator_ff/0x400);
5409 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
5410 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
5411 TR_loop_input = (TR_loop_input/0x8000);
5412
5413 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
5414 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
5415 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
5416 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
5417 #endif
5418 bRet=true;
5419 return bRet;
5420 }
5421
5422 //------------------------------------------------------------------
5423 // END Get And Show Info Function
5424 //------------------------------------------------------------------
5425
5426 //------------------------------------------------------------------
5427 // BlindScan Function
5428 //------------------------------------------------------------------
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)5429 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
5430 {
5431 MS_BOOL status=TRUE;
5432 MS_U8 u8Data=0;
5433
5434 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Start+\n"));
5435
5436 _u16BlindScanStartFreq=u16StartFreq;
5437 _u16BlindScanEndFreq=u16EndFreq;
5438 _u16TunerCenterFreq=0;
5439 _u16ChannelInfoIndex=0;
5440
5441 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5442 u8Data&=0xd0;
5443 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5444
5445 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
5446 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
5447
5448 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
5449
5450 return status;
5451 }
5452
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)5453 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
5454 {
5455 MS_BOOL status=TRUE;
5456 MS_U8 u8Data=0;
5457
5458 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq+\n"));
5459
5460 * bBlindScanEnd=FALSE;
5461
5462 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
5463 {
5464 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
5465 * bBlindScanEnd=TRUE;
5466
5467 return status;
5468 }
5469 //Set Tuner Frequency
5470 MsOS_DelayTask(10);
5471
5472 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5473 if ((u8Data&0x02)==0x00)//Manual Tune
5474 {
5475 u8Data&=~(0x28);
5476 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5477 u8Data|=0x02;
5478 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5479 u8Data|=0x01;
5480 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5481 }
5482 else
5483 {
5484 u8Data&=~(0x28);
5485 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5486 }
5487
5488 return status;
5489 }
5490
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)5491 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
5492 {
5493 MS_BOOL status=TRUE;
5494 MS_U8 u8Data=0;
5495 MS_U16 u16WaitCount;
5496 MS_U16 u16TunerCutOff;
5497
5498 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_SetTunerFreq+\n"));
5499
5500 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5501 if ((u8Data&0x02)==0x02)
5502 {
5503 u8Data|=0x08;
5504 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5505 u16WaitCount=0;
5506 do
5507 {
5508 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5509 u16WaitCount++;
5510 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5511 MsOS_DelayTask(1);
5512 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5513 }
5514 else if((u8Data&0x01)==0x01)
5515 {
5516 u8Data|=0x20;
5517 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5518 u16WaitCount=0;
5519 do
5520 {
5521 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5522 u16WaitCount++;
5523 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5524 MsOS_DelayTask(1);
5525 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5526 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5527 u8Data|=0x02;
5528 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5529 }
5530 u16WaitCount=0;
5531
5532 _u16TunerCenterFreq=0;
5533
5534 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5535 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
5536 _u16TunerCenterFreq=u8Data;
5537 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5538 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
5539 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
5540
5541 *u16TunerCenterFreq = _u16TunerCenterFreq;
5542 //claire test
5543 u16TunerCutOff=44000;
5544 if(_u16TunerCenterFreq<=990)//980
5545 {
5546
5547 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
5548 if(u8Data==0x01)
5549 {
5550 if(_u16TunerCenterFreq<970)//970
5551 {
5552 u16TunerCutOff=10000;
5553 }
5554 else
5555 {
5556 u16TunerCutOff=20000;
5557 }
5558 u8Data=0x02;
5559 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5560 }
5561 else if(u8Data==0x02)
5562 {
5563 u8Data=0x00;
5564 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5565 }
5566 }
5567 if(u16TunerCutOffFreq != NULL)
5568 {
5569 *u16TunerCutOffFreq = u16TunerCutOff;
5570 }
5571
5572
5573 //end claire test
5574
5575 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_SetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
5576
5577
5578 return status;
5579 }
5580
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum)5581 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum)
5582 {
5583 MS_BOOL status=TRUE;
5584 MS_U32 u32Data=0;
5585 MS_U16 u16Data=0;
5586 MS_U8 u8Data=0, u8Data2=0;
5587 MS_U16 u16WaitCount;
5588
5589 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
5590
5591 u16WaitCount=0;
5592 *u8FindNum=0;
5593 *u8Progress=0;
5594
5595 do
5596 {
5597 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
5598 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
5599 u16WaitCount++;
5600 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
5601 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
5602
5603 MsOS_DelayTask(1);
5604 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
5605
5606
5607
5608 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
5609 u16Data=u8Data;
5610
5611
5612 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
5613
5614 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
5615 {
5616 status=false;
5617 printf("Debug blind scan wait finished time out!!!!\n");
5618 }
5619 else
5620 {
5621
5622 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
5623 if (u8Data==0)
5624 {
5625
5626 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5627 u32Data=u8Data;
5628 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5629 u32Data=(u32Data<<8)|u8Data;
5630 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5631 u32Data=(u32Data<<8)|u8Data;
5632 _u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((u32Data+500)/1000);
5633 _u16LockedCenterFreq=((u32Data+500)/1000); //Center Freq
5634
5635
5636 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5637 u16Data=u8Data;
5638 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5639 u16Data=(u16Data<<8)|u8Data;
5640 _u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
5641 _u16LockedSymbolRate=u16Data;
5642 _u16ChannelInfoIndex++;
5643 *u8FindNum=_u16ChannelInfoIndex;
5644 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
5645
5646
5647 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5648 u16Data=u8Data;
5649 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5650 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
5651 if (u16Data*1000 >= 0x8000)
5652 {
5653 u16Data=0x10000- u16Data*1000;
5654 _s16CurrentCFO=-1*u16Data/1000;
5655 }
5656 else
5657 {
5658 _s16CurrentCFO=u16Data;
5659 }
5660
5661 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5662 u16Data=u8Data;
5663 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5664 u16Data=(u16Data<<8)|u8Data;
5665 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5666
5667
5668 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5669 u16Data=u8Data;
5670 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5671 u16Data=(u16Data<<8)|u8Data;
5672 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5673
5674
5675 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5676 u16Data=u8Data;
5677 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5678 u16Data=(u16Data<<8)|u8Data;
5679 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5680
5681
5682 DBG_INTERN_DVBS(printf("Current Locked CF:%d BW:%d BWH:%d BWL:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _s16CurrentCFO, _u16CurrentStepSize));
5683 }
5684 else if (u8Data==1)
5685 {
5686 //printf("claire debug blind scan: no find TP\n");
5687
5688
5689 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5690 u16Data=u8Data;
5691 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5692 u16Data=(u16Data<<8)|u8Data;
5693 _u16NextCenterFreq=u16Data;
5694
5695
5696 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5697 u16Data=u8Data;
5698 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5699 u16Data=(u16Data<<8)|u8Data;
5700 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5701
5702
5703
5704 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5705 u16Data=u8Data;
5706 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5707 u16Data=(u16Data<<8)|u8Data;
5708 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5709
5710
5711 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5712 u16Data=u8Data;
5713 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5714 u16Data=(u16Data<<8)|u8Data;
5715 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
5716
5717
5718 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5719 u16Data=u8Data;
5720 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5721 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
5722 if (u16Data*1000 >= 0x8000)
5723 {
5724 u16Data=0x1000- u16Data*1000;
5725 _s16CurrentCFO=-1*u16Data/1000;
5726 }
5727 else
5728 {
5729 _s16CurrentCFO=u16Data;
5730 }
5731
5732 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5733 u16Data=u8Data;
5734 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5735 u16Data=(u16Data<<8)|u8Data;
5736 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5737
5738
5739 DBG_INTERN_DVBS(printf("Pre Locked CF:%d BW:%d HBW:%d LBW:%d Current CF:%d BW:%d CFO:%d Step:%d\n", _u16LockedCenterFreq, _u16LockedSymbolRate,_u16PreLockedHB, _u16PreLockedLB, _u16NextCenterFreq-_u16CurrentStepSize, _u16CurrentSymbolRate, _s16CurrentCFO, _u16CurrentStepSize));
5740 }
5741 }
5742 *u8Progress=100;
5743
5744 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
5745
5746 return status;
5747 }
5748
INTERN_DVBS_BlindScan_Cancel(void)5749 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
5750 {
5751 MS_BOOL status=TRUE;
5752 MS_U8 u8Data=0;
5753 MS_U16 u16Data;
5754
5755 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Cancel+\n"));
5756
5757 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5758 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5759 u8Data&=0xF0;
5760 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5761 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5762
5763 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5764 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5765 u16Data = 0x0000;
5766 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5767 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5768
5769 _u16TunerCenterFreq=0;
5770 _u16ChannelInfoIndex=0;
5771
5772 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_Cancel-\n"));
5773
5774 return status;
5775 }
5776
INTERN_DVBS_BlindScan_End(void)5777 MS_BOOL INTERN_DVBS_BlindScan_End(void)
5778 {
5779 MS_BOOL status=TRUE;
5780 MS_U8 u8Data=0;
5781 MS_U16 u16Data;
5782
5783 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_End+\n"));
5784
5785 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5786 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5787 u8Data&=0xF0;
5788 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5789 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5790
5791 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5792 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5793 u16Data = 0x0000;
5794 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5795 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5796
5797 _u16TunerCenterFreq=0;
5798 _u16ChannelInfoIndex=0;
5799
5800 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_End-\n"));
5801
5802 return status;
5803 }
5804
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)5805 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
5806 {
5807 MS_BOOL status=TRUE;
5808 MS_U16 u16TableIndex;
5809
5810 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
5811 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
5812 {
5813 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
5814 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
5815 DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", pTable[u16TableIndex].u32Frequency, pTable[u16TableIndex].SatParam.u32SymbolRate));
5816 }
5817 DBG_INTERN_DVBS(printf("INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
5818
5819 return status;
5820 }
5821
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)5822 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
5823 {
5824 MS_BOOL status=TRUE;
5825 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
5826
5827 *u32CurrentFeq=_u16TunerCenterFreq;
5828 DBG_INTERN_DVBS(printf("INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
5829 return status;
5830 }
5831 //------------------------------------------------------------------
5832 // END BlindScan Function
5833 //------------------------------------------------------------------
5834
5835 //------------------------------------------------------------------
5836 // DiSEqc Function
5837 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)5838 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
5839 {
5840 MS_BOOL status = true;
5841 MS_U8 u8Data = 0;
5842
5843 //Clear status
5844 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5845 u8Data=(u8Data|0x3E)&(~0x3E);
5846 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5847
5848 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
5849 //Tone En
5850 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
5851 u8Data=(u8Data&(~0x06))|(0x06);
5852 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
5853
5854 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_Init\n"));
5855
5856 return status;
5857 }
5858
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)5859 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
5860 {
5861 MS_BOOL status=TRUE;
5862 MS_U8 u8Data=0;
5863 MS_U8 u8ReSet22k=0;
5864
5865 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
5866 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
5867 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
5868
5869 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
5870 u8ReSet22k=u8Data;
5871
5872 if (bTone1==TRUE)
5873 {
5874 //Tone burst 1
5875 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
5876 _u8ToneBurstFlag=1;
5877 }
5878 else
5879 {
5880 //Tone burst 0
5881 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
5882 _u8ToneBurstFlag=2;
5883 }
5884 //DIG_DISEQC_TX_EN
5885 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5886 //u8Data=u8Data&~(0x01);//Tx Disable
5887 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5888
5889 MsOS_DelayTask(1);
5890 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
5891 u8Data=u8Data|0x3E; //Status clear
5892 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5893 MsOS_DelayTask(10);
5894 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5895 u8Data=u8Data&~(0x3E);
5896 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5897 MsOS_DelayTask(1);
5898
5899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5900 u8Data=u8Data|0x01; //Tx Enable
5901 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5902
5903 MsOS_DelayTask(30);//(100)
5904 //For ToneBurst 22k issue.
5905 u8Data=u8ReSet22k;
5906 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
5907
5908 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
5909 //MsOS_DelayTask(100);
5910 return status;
5911 }
5912
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)5913 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
5914 {
5915 MS_BOOL status=TRUE;
5916 MS_U8 u8Data=0;
5917
5918 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
5919 if (bLow==TRUE)
5920 {
5921 u8Data=(u8Data|0x40); //13V
5922 }
5923 else
5924 {
5925 u8Data=(u8Data&(~0x40));//18V
5926 }
5927 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
5928
5929 return status;
5930 }
5931
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)5932 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
5933 {
5934 MS_BOOL status=TRUE;
5935 MS_U8 u8Data=0;
5936
5937 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
5938 if( (u8Data&0x40)==0x40)
5939 {
5940 * bLNBOutLow=TRUE;
5941 }
5942 else
5943 {
5944 * bLNBOutLow=FALSE;
5945 }
5946
5947 return status;
5948 }
5949
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)5950 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
5951 {
5952 MS_BOOL status=TRUE;
5953 MS_U8 u8Data=0;
5954
5955 //Set DiSeqC 22K
5956 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
5957
5958 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
5959
5960 if (b22kOn==TRUE)
5961 {
5962 u8Data=(u8Data&0xc7);
5963 u8Data=(u8Data|0x08);
5964 }
5965 else
5966 {
5967 u8Data=(u8Data&0xc7);
5968 }
5969 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
5970
5971 DBG_INTERN_DVBS(printf("INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
5972 return status;
5973 }
5974
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)5975 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
5976 {
5977 MS_BOOL status=TRUE;
5978 MS_U8 u8Data=0;
5979
5980 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
5981 if ((u8Data&0x38)==0x08)
5982 {
5983 *b22kOn=TRUE;
5984 }
5985 else
5986 {
5987 *b22kOn=FALSE;
5988 }
5989
5990 return status;
5991 }
5992
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)5993 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
5994 {
5995 MS_BOOL status=TRUE;
5996 MS_U8 u8Data;
5997 MS_U8 u8Index;
5998 MS_U16 u16WaitCount;
5999 /*
6000 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6001 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6002 u8Data=(u8Data&~(0x10));
6003 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6004 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6005 */
6006 #if 0 //For Unicable command timing
6007 u16WaitCount=0;
6008 do
6009 {
6010 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6011 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6012 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6013 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6014 MsOS_DelayTask(1);
6015 u16WaitCount++;
6016 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6017
6018 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6019 {
6020 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6021 return FALSE;
6022 }
6023 #endif
6024
6025 //u16Address=0x0BC4;
6026 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6027 {
6028 u8Data=*(pCmd+u8Index);
6029 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6030 DBG_INTERN_DVBS(printf("=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6031 }
6032
6033 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6034 u8Data=((u8CmdSize-1)&0x07)|0x40;
6035 if (_u8ToneBurstFlag==1)
6036 {
6037 u8Data|=0x80;//0x20;
6038 }
6039 else if (_u8ToneBurstFlag==2)
6040 {
6041 u8Data|=0x20;//0x80;
6042 }
6043 _u8ToneBurstFlag=0;
6044 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6045
6046 //add this only for check mailbox R/W
6047 #if 1
6048 DBG_INTERN_DVBS(printf(" Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6049 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6050 DBG_INTERN_DVBS(printf(" Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6051 #endif
6052
6053 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6054 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6055 //u8Data=u8Data|0x10;
6056 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data|0x10);//enable DiSEqC_Data_Tx
6057 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6058 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6059
6060 #if 1 //For Unicable command timing???
6061 u16WaitCount=0;
6062 do
6063 {
6064 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6065 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6066 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6067 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6068 MsOS_DelayTask(1);
6069 u16WaitCount++;
6070 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6071
6072 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6073 {
6074 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6075 return FALSE;
6076 }
6077 else
6078 {
6079 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6080 return TRUE;
6081 }
6082
6083
6084 #endif
6085 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6086 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6087
6088 return status;
6089 }
6090
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6091 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6092 {
6093 MS_BOOL status=TRUE;
6094 MS_U8 u8Data=0;
6095
6096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6097 if (bTxTone22kOff==TRUE)
6098 {
6099 u8Data=(u8Data|0x80); //1: without 22K.
6100 }
6101 else
6102 {
6103 u8Data=(u8Data&(~0x80)); //0: with 22K.
6104 }
6105 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6106
6107 return status;
6108 }
6109
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6110 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6111 {
6112 //MS_BOOL status = TRUE;
6113 MS_U8 u8Data=0;
6114
6115 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6116
6117 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6118 u8Data &= 0xFE;//clean bit0
6119 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6120
6121 if (pbAGCCheckPower == FALSE)//0
6122 {
6123 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6124 u8Data &= 0xFE;//clean bit0
6125 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6126 //printf("CMD=MS_FALSE==============================\n");
6127 }
6128 else
6129 {
6130 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6131 u8Data |= 0x01; //bit1=1
6132 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6133 //printf("CMD=MS_TRUE==============================\n");
6134 }
6135
6136 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6137 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6138 u8Data &= 0xF0;
6139 u8Data |= 0x01;
6140 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6141 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6142 MsOS_DelayTask(500);
6143
6144 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6145 u8Data &= 0x80; //Read bit7
6146 if (u8Data == 0x80)
6147 {
6148 u8Data = 0x00;
6149 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6150 u8Data = 0x00;
6151 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6152 return TRUE;
6153 }
6154 else
6155 {
6156 u8Data = 0x00;
6157 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6158 u8Data = 0x00;
6159 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6160 return FALSE;
6161 }
6162 }
6163
6164 //------------------------------------------------------------------
6165 // END DiSEqc Function
6166 //------------------------------------------------------------------
6167 //------------------------------------------------------------------
6168 // R/W Function
6169 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6170 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6171 {
6172 MS_BOOL bRet= TRUE;
6173 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6174 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6175 return bRet;
6176 }
6177
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6178 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6179 {
6180 MS_BOOL bRet= TRUE;
6181 MS_U8 u8Data =0;
6182 MS_U16 u16Data =0;
6183
6184 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6185 u16Data = u8Data;
6186 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6187 *pu16Data = (u16Data<<8)|u8Data;
6188
6189 return bRet;
6190 }
6191
6192 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6193 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6194 {
6195 MS_BOOL bRet= TRUE;
6196 MS_U16 u16Address;
6197 MS_U16 u16Data=0;
6198
6199 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6200 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6201 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6202 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6203
6204 return bRet;
6205 }
6206
INTERN_DVBS_DTV_FrontendUnFreeze(void)6207 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
6208 {
6209 MS_BOOL bRet= TRUE;
6210 MS_U16 u16Address;
6211 MS_U16 u16Data=0;
6212
6213 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6214 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6215 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
6216 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6217
6218 return bRet;
6219 }
6220
6221 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)6222 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
6223 {
6224 MS_BOOL bRet= TRUE;
6225 MS_U16 u16Address;
6226 MS_U16 u16Data=0;
6227
6228 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6229 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6230 u16Data|=(INNER_FREEZE_DUMP&0xffff);
6231 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6232
6233 return bRet;
6234 }
6235
INTERN_DVBS_DTV_InnerUnFreeze(void)6236 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
6237 {
6238 MS_BOOL bRet= TRUE;
6239 MS_U16 u16Address;
6240 MS_U16 u16Data=0;
6241
6242 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6243 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6244 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
6245 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6246
6247 return bRet;
6248 }
6249 //------------------------------------------------------------------
6250 // END R/W Function
6251 //------------------------------------------------------------------
6252
6253
6254 /***********************************************************************************
6255 Subject: read register
6256 Function: MDrv_1210_IIC_Bypass_Mode
6257 Parmeter:
6258 Return:
6259 Remark:
6260 ************************************************************************************/
6261 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
6262 //{
6263 // UNUSED(enable);
6264 // if (enable)
6265 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
6266 // else
6267 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
6268 //}
6269
6270