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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 #include "MsCommon.h"
103 #include "MsIRQ.h"
104 #include "MsOS.h"
105 #include "MsTypes.h"
106 #include "drvMMIO.h"
107 #include "drvDMD_common.h"
108 #include "drvDMD_VD_MBX.h"
109 #include "halDMD_INTERN_common.h"
110 #include "ULog.h"
111 #if defined (__aeon__) // Non-OS
112 #define BASEADDR_RIU 0xA0000000UL
113 //#elif ( OS_TYPE == linux ) // Linux
114 // #define RIU_BASE u32RegOSBase // MDrv_MIOMap_GetBASE(u32RegOSBase, puSize, MAP_NONPM_BANK)
115 #else // ecos
116 #define BASEADDR_RIU 0xBF800000UL
117 #endif
118
119 #define RIU_MACRO_START do {
120 #define RIU_MACRO_END } while (0)
121
122 // Address bus of RIU is 16 bits.
123 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_DMD.virtDMDBaseAddr + (addr) ) )
124 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_DMD.virtDMDBaseAddr + (addr) ) )
125 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_DMD.virtDMDBaseAddr + (addr), val) }
126 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_DMD.virtDMDBaseAddr + (addr), val) }
127
128 //=============================================================
129 // Standard Form
130
131 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
132
133 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
134
135 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
136
137 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
138 RIU_MACRO_START \
139 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
140 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
141 RIU_MACRO_END
142
143 #define RIU_WriteByte( u32Reg, u8Val ) \
144 RIU_MACRO_START \
145 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
146 RIU_MACRO_END
147
148 #define RIU_Write2Byte( u32Reg, u16Val ) \
149 RIU_MACRO_START \
150 if ( ((u32Reg) & 0x01) ) \
151 { \
152 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
153 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
154 } \
155 else \
156 { \
157 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
158 } \
159 RIU_MACRO_END
160
161 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
162 RIU_MACRO_START \
163 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
164 RIU_MACRO_END
165
166
167 typedef struct
168 {
169 MS_VIRT virtDMDBaseAddr;
170 MS_BOOL bBaseAddrInitialized;
171 } hal_DMD_t;
172
173 static hal_DMD_t _hal_DMD = // TODO: review, it would be init in Config()
174 {
175 .virtDMDBaseAddr = BASEADDR_RIU,
176 .bBaseAddrInitialized = 0,
177 };
178
179 extern s_I2C_Interface_func sI2cInterfaceFunc;
180
HAL_DMD_RegInit(void)181 MS_BOOL HAL_DMD_RegInit (void)
182 {
183 MS_VIRT virtNonPMBank;
184 MS_PHY phyNonPMBankSize;
185
186 if (!MDrv_MMIO_GetBASE( &virtNonPMBank, &phyNonPMBankSize, MS_MODULE_PM))
187 {
188 #ifdef MS_DEBUG
189 ULOGE("DEMOD","HAL_DMD_RegInit failure to get MS_MODULE_PM\n");
190 #endif
191 _hal_DMD.virtDMDBaseAddr = BASEADDR_RIU; // TODO what to do if failed??
192 _hal_DMD.bBaseAddrInitialized = 0;
193 return FALSE;
194 }
195
196 //HAL_ParFlash_Config(u32NonPMBank);
197 _hal_DMD.virtDMDBaseAddr=virtNonPMBank;
198 _hal_DMD.bBaseAddrInitialized = 1;
199 return TRUE;
200 }
201
HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)202 MS_U8 HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
203 {
204 if (_hal_DMD.bBaseAddrInitialized)
205 {
206 return RIU_ReadByte(u32Addr);
207 }
208 else
209 {
210 #ifdef MS_DEBUG
211 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
212 #endif
213 }
214 return 0;
215 }
216
HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr,MS_U8 u8Mask)217 MS_U8 HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr, MS_U8 u8Mask)
218 {
219 if (_hal_DMD.bBaseAddrInitialized)
220 {
221 return RIU_ReadRegBit(u32Addr, u8Mask);
222 }
223 else
224 {
225 #ifdef MS_DEBUG
226 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
227 #endif
228 }
229 return 0;
230 }
HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * pu8Data)231 MS_U8 HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *pu8Data)
232 {
233
234 MS_BOOL bRet=TRUE;
235 MS_U8 u8MsbData[6] = {0};
236
237 u8MsbData[0] = 0x10;
238 u8MsbData[1] = 0x00;
239 u8MsbData[2] = 0x00;
240 u8MsbData[3] = (u32Addr >> 8) &0xff;
241 u8MsbData[4] = u32Addr &0xff;
242
243 u8MsbData[0] = 0x35;
244 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
245
246 u8MsbData[0] = 0x10;
247 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 5, u8MsbData);
248 bRet &= sI2cInterfaceFunc.I2C_ReadBytes(u16SlaveAddr, 0, 0, 1, pu8Data);
249
250 u8MsbData[0] = 0x34;
251 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
252
253 return bRet;
254 }
HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)255 MS_U16 HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)
256 {
257 if (_hal_DMD.bBaseAddrInitialized)
258 {
259 return RIU_Read2Byte(u32Addr);
260 }
261 else
262 {
263 #ifdef MS_DEBUG
264 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
265 #endif
266 }
267 return 0;
268 }
269
HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 u8Data)270 MS_U8 HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 u8Data)
271 {
272 MS_BOOL bRet=TRUE;
273 MS_U8 u8MsbData[6] = {0};
274
275 u8MsbData[0] = 0x10;
276 u8MsbData[1] = 0x00;
277 u8MsbData[2] = 0x00;
278 u8MsbData[3] = (u32Addr >> 8) &0xff;
279 u8MsbData[4] = u32Addr &0xff;
280 u8MsbData[5] = u8Data;
281
282 u8MsbData[0] = 0x35;
283 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
284 u8MsbData[0] = 0x10;
285 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 6, u8MsbData);
286 u8MsbData[0] = 0x34;
287 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
288
289 return bRet;
290 }
HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * u8Data,MS_U8 u8Len)291 MS_U8 HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *u8Data, MS_U8 u8Len)
292 {
293 MS_BOOL bRet=TRUE;
294 MS_U16 index;
295 MS_U8 Data[0x80+5];
296
297 Data[0] = 0x10;
298 Data[1] = 0x00;
299 Data[2] = 0x00;
300 Data[3] = (u32Addr >> 8) &0xff;
301 Data[4] = u32Addr &0xff;
302
303 for(index = 0; index < u8Len ; index++)
304 {
305 Data[5+index] = u8Data[index];
306 }
307
308 Data[0] = 0x35;
309 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
310 Data[0] = 0x10;
311 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
312 sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, (5 + u8Len), Data);
313 Data[0] = 0x34;
314 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
315
316 return bRet;
317 }
318
HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr,MS_U8 ch_num)319 MS_BOOL HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr, MS_U8 ch_num)
320 {
321 MS_BOOL bRet=TRUE;
322 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
323 //Exit
324 Data[0] = 0x34;
325 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
326 Data[0]=(ch_num & 0x01)? 0x36 : 0x45;
327 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
328 //Init
329 Data[0] = 0x53;
330 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 5, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 5);
331 Data[0]=(ch_num & 0x04)? 0x80 : 0x81;
332 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
333 if ((ch_num==4)||(ch_num==5)||(ch_num==1))
334 Data[0]=0x82;
335 else
336 Data[0] = 0x83;
337 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
338
339 if ((ch_num==4)||(ch_num==5))
340 Data[0]=0x85;
341 else
342 Data[0] = 0x84;
343
344 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
345 Data[0]=(ch_num & 0x01)? 0x51 : 0x53;
346 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
347 Data[0]=(ch_num & 0x01)? 0x37 : 0x7F;
348 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
349 Data[0] = 0x35;
350 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
351 Data[0] = 0x71;
352 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
353 // MsOS_ReleaseMutex(_s32MutexId);
354 return bRet;
355 }
356
HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr,MS_U8 ch_num)357 MS_BOOL HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr, MS_U8 ch_num)
358 {
359 MS_BOOL bRet=TRUE;
360 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
361 Data[0] = (ch_num & 0x01)? 0x81 : 0x80;
362 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
363 Data[0] = (ch_num & 0x02)? 0x83 : 0x82;
364 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
365 Data[0] = (ch_num & 0x04)? 0x85 : 0x84;
366 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
367
368 return bRet;
369 }
HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)370 void HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
371 {
372 if (_hal_DMD.bBaseAddrInitialized)
373 {
374 RIU_WriteByte(u32Addr, u8Value);
375 }
376 else
377 {
378 #ifdef MS_DEBUG
379 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
380 #endif
381 }
382 }
383
HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr,MS_BOOL bEnable,MS_U8 u8Mask)384 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask)
385 {
386 if (_hal_DMD.bBaseAddrInitialized)
387 {
388 RIU_WriteRegBit(u32Addr, bEnable, u8Mask);
389 }
390 else
391 {
392 #ifdef MS_DEBUG
393 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
394 #endif
395 }
396 }
397
HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)398 void HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
399 {
400 if (_hal_DMD.bBaseAddrInitialized)
401 {
402 RIU_WriteByteMask(u32Addr, u8Value, u8Mask);
403 }
404 else
405 {
406 #ifdef MS_DEBUG
407 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
408 #endif
409 }
410 }
411
HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr,MS_U16 u16Value)412 void HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr, MS_U16 u16Value)
413 {
414 if (_hal_DMD.bBaseAddrInitialized)
415 {
416 RIU_Write2Byte(u32Addr, u16Value);
417 }
418 else
419 {
420 #ifdef MS_DEBUG
421 ULOGE("DEMOD","%s base address un-initialized\n", __FUNCTION__);
422 #endif
423 }
424 }
425
HAL_DMD_GetRFLevel(float * fRFPowerDbmResult,float fRFPowerDbm,MS_U8 u8SarValue,DMD_RFAGC_SSI * pRfagcSsi,MS_U16 u16RfagcSsi_Size,DMD_IFAGC_SSI * pIfagcSsi_HiRef,MS_U16 u16IfagcSsi_HiRef_Size,DMD_IFAGC_SSI * pIfagcSsi_LoRef,MS_U16 u16IfagcSsi_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_LoRef,MS_U16 u16IfagcErr_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_HiRef,MS_U16 u16IfagcErr_HiRef_Size)426 MS_BOOL HAL_DMD_GetRFLevel(float *fRFPowerDbmResult, float fRFPowerDbm, MS_U8 u8SarValue,
427 DMD_RFAGC_SSI *pRfagcSsi, MS_U16 u16RfagcSsi_Size,
428 DMD_IFAGC_SSI *pIfagcSsi_HiRef, MS_U16 u16IfagcSsi_HiRef_Size,
429 DMD_IFAGC_SSI *pIfagcSsi_LoRef, MS_U16 u16IfagcSsi_LoRef_Size,
430 DMD_IFAGC_ERR *pIfagcErr_LoRef, MS_U16 u16IfagcErr_LoRef_Size,
431 DMD_IFAGC_ERR *pIfagcErr_HiRef, MS_U16 u16IfagcErr_HiRef_Size)
432 {
433 DMD_IFAGC_SSI *ifagc_ssi;
434 DMD_IFAGC_ERR *ifagc_err;
435 float ch_power_db=0.0f;
436 float ch_power_rf=0.0f;
437 float ch_power_if=0.0f, ch_power_ifa = 0.0f, ch_power_ifb =0.0f;
438 float ch_power_takeover=0.0f;
439 MS_U16 if_agc_err = 0;
440 MS_U8 status = true;
441 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0,rf_agc_val =0,if_agc_val =0, if_agc_vala =0, if_agc_valb =0, if_agc_val_lsb =0, i;
442 MS_U8 ssi_tbl_len = 0, err_tbl_len = 0;
443
444 if ((pIfagcSsi_HiRef != NULL) && (pIfagcSsi_LoRef !=NULL))
445 {
446 // get RFAGC level
447 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
448 {
449 rf_agc_val = u8SarValue;
450
451 ch_power_rf=pRfagcSsi[u16RfagcSsi_Size-1].power_db;
452 if (rf_agc_val >=pRfagcSsi[0].sar3_val)
453 {
454 float ch_power_rfa = 0, ch_power_rfb =0;
455 MS_U8 rf_agc_vala =0, rf_agc_valb =0;
456 for(i = 1; i < u16RfagcSsi_Size; i++)
457 {
458 if (rf_agc_val < pRfagcSsi[i].sar3_val)
459 {
460 rf_agc_valb = pRfagcSsi[i].sar3_val;
461 ch_power_rfb = pRfagcSsi[i].power_db;
462
463 i--;
464 rf_agc_vala = pRfagcSsi[i].sar3_val;
465 ch_power_rfa=pRfagcSsi[i].power_db;
466 while ((i>1) && (rf_agc_vala==pRfagcSsi[i-1].sar3_val))
467 {
468 ch_power_rfa=pRfagcSsi[i-1].power_db;
469 i--;
470 }
471 ch_power_rf = ch_power_rfa+(ch_power_rfb-ch_power_rfa)*(float)(rf_agc_val-rf_agc_vala)/(rf_agc_valb-rf_agc_vala);
472 break;
473 }
474 }
475 #ifdef MS_DEBUG
476 ULOGD("DEMOD","RF Level from SAR:%f\n", ch_power_rf);
477 ULOGD("DEMOD","SSI_RFAGC (SAR-4) = 0x%x\n", rf_agc_val);
478 ULOGD("DEMOD","rf prev %f %x\n", ch_power_rfa, rf_agc_vala);
479 ULOGD("DEMOD","rf next %f %x\n", ch_power_rfb, rf_agc_valb);
480 #endif
481 }
482 }
483 else
484 {
485 #ifdef MS_DEBUG
486 ULOGD("DEMOD","RF Level from tuner: %f\n",fRFPowerDbm);
487 #endif
488 ch_power_rf = fRFPowerDbm;
489 }
490
491 // get IFAGC status
492 {
493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13, ®_tmp);
494
495 #ifdef MS_DEBUG
496 ULOGD("DEMOD","AGC_REF = %d\n", (MS_U16)reg_tmp);
497 #endif
498
499 if (reg_tmp > 200)
500 {
501 ifagc_ssi = pIfagcSsi_HiRef;
502 ssi_tbl_len = u16IfagcSsi_HiRef_Size;
503 ifagc_err = pIfagcErr_HiRef;
504 err_tbl_len = u16IfagcErr_HiRef_Size;
505 }
506 else
507 {
508 ifagc_ssi = pIfagcSsi_LoRef;
509 ssi_tbl_len = u16IfagcSsi_LoRef_Size;
510 ifagc_err = pIfagcErr_LoRef;
511 err_tbl_len = u16IfagcErr_LoRef_Size;
512 }
513
514 // bank 5 0x24 [15:0] reg_agc_gain2_out
515 // use only high byte value
516
517 // select IF gain to read
518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
522 if_agc_val = reg_tmp;
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp);
524 if_agc_val_lsb = reg_tmp;
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
526 #ifdef MS_DEBUG
527 ULOGD("DEMOD","SSI_IFAGC_H = 0x%x 0x%x\n", if_agc_val,if_agc_val_lsb);
528 #endif
529
530 ch_power_if=ifagc_ssi[0].power_db;
531 if (if_agc_val >=ifagc_ssi[0].agc_val)
532 {
533 for(i = 1; i < ssi_tbl_len; i++)
534 {
535 if (if_agc_val < ifagc_ssi[i].agc_val)
536 {
537 if_agc_valb = ifagc_ssi[i].agc_val;
538 ch_power_ifb = ifagc_ssi[i].power_db;
539
540 i--;
541 if_agc_vala = ifagc_ssi[i].agc_val;
542 ch_power_ifa=ifagc_ssi[i].power_db;
543 while ((i>1) && (if_agc_vala==ifagc_ssi[i-1].agc_val))
544 {
545 ch_power_ifa=ifagc_ssi[i-1].power_db;
546 i--;
547 }
548 ch_power_if = ch_power_ifa+(ch_power_ifb-ch_power_ifa)*(float)((if_agc_val-if_agc_vala)*256+if_agc_val_lsb)/((if_agc_valb-if_agc_vala)*256);
549 break;
550 }
551 }
552 }
553 #ifdef MS_DEBUG
554 ULOGD("DEMOD","if prev %f %x\n", ch_power_ifa, if_agc_vala);
555 ULOGD("DEMOD","if next %f %x\n", ch_power_ifb, if_agc_valb);
556 #endif
557
558 for(i = 0; i < ssi_tbl_len; i++)
559 {
560 if (ifagc_ssi[i].agc_val <= ifagc_ssi[i+1].agc_val)
561 {
562 ch_power_takeover = ifagc_ssi[i+1].power_db;
563 break;
564 }
565 }
566
567 #ifdef MS_DEBUG
568 ULOGD("DEMOD","ch_power_rf = %f\n", ch_power_rf);
569 ULOGD("DEMOD","ch_power_if = %f\n", ch_power_if);
570 ULOGD("DEMOD","ch_power_takeover = %f\n", ch_power_takeover);
571 #endif
572
573 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_rf : ch_power_if;
574
575 if(ch_power_rf > (ch_power_takeover + 0.5))
576 {
577 ch_power_db = ch_power_rf;
578 }
579 else if(ch_power_if < (ch_power_takeover - 0.5))
580 {
581 ch_power_db = ch_power_if;
582 }
583 else
584 {
585 ch_power_db = (ch_power_if + ch_power_rf)/2;
586 }
587
588 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_if : ch_power_rf;
589
590 ///////// IF-AGC Error for Add. Attnuation /////////////
591 if(if_agc_val == 0xff)
592 {
593 #if 0
594 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, ®_tmp);
596 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (reg_tmp&0xf0));
597 #endif
598 #endif
599 // bank 5 0x04 [15] reg_tdp_lat
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00);
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
603 #if 0
604 //#if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
605 // bank 5 0x2c [9:0] reg_agc_error
606 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, ®_tmp);
607 // if_agc_err = reg_tmp & 0x03;
608 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, ®_tmp2);
609 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
610 //#else
611 #endif
612 // bank 5 0x2c [9:0] reg_agc_error
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
614 // if_agc_err = reg_tmp & 0x03;
615 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp2);
616 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
617 //#endif
618
619 if(reg_tmp&0x2)
620 {
621 if_agc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
622 }
623 else
624 {
625 if_agc_err = reg_tmp<<8|reg_tmp2;
626 }
627
628 // release latch
629 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
630
631 for(i = 0; i < err_tbl_len; i++)
632 {
633 if ( if_agc_err <= ifagc_err[i].agc_err ) // signed char comparison
634 {
635 ch_power_db += ifagc_err[i].attn_db;
636 break;
637 }
638 }
639 #ifdef MS_DEBUG
640 ULOGD("DEMOD","if_agc_err = 0x%x\n", if_agc_err);
641 #endif
642 }
643
644 // BY 20110812 temporaily remove ch_power_db += SIGNAL_LEVEL_OFFSET;
645 }
646 }
647 else
648 {
649 #ifdef MS_DEBUG
650 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
651 {
652 ULOGE("DEMOD","Error!! please add AGC table\n");
653 }
654 #endif
655 ch_power_db = fRFPowerDbm;
656 }
657 *fRFPowerDbmResult=ch_power_db;
658 return status;
659 }
660
HAL_DMD_GetNordigSSI(float fPrel,MS_U16 * strength)661 void HAL_DMD_GetNordigSSI(float fPrel, MS_U16 *strength)
662 {
663 if (fPrel<-15.0f)
664 {
665 *strength = 0;
666 }
667 else if (fPrel<0.0f)
668 {
669 *strength = (MS_U16)((2.0f/3.0f)*(fPrel+15.0f));
670 }
671 else if (fPrel<20.0f)
672 {
673 *strength = (MS_U16)(4.0f*fPrel+10.0f);
674 }
675 else if (fPrel<35.0f)
676 {
677 *strength = (MS_U16)((2.0f/3.0f)*(fPrel-20.0f)+90.0f);
678 }
679 else
680 {
681 *strength = 100;
682 }
683
684 }
685 /*
686 from Steven.Hung
687 2. �n��T12 TS1 TS bus tristate
688 Set Bank CHIPTOP, 0x57[13:11]=3��h0; (reg_ts1config[2:0]=0)
689 3. �n��T12 IFAGC tristate
690 Set Bank CHIPTOP, 0x2[12]=1��h1; (reg_if_agc_pad_oen=1)
691 */
HAL_DMD_TS1_Tristate(MS_BOOL bEnable)692 void HAL_DMD_TS1_Tristate(MS_BOOL bEnable)
693 {
694 #ifdef MS_DEBUG
695 ULOGD("DEMOD","HAL_DMD_TS1_Tristate %d\n",bEnable);
696 #endif
697 if (bEnable)
698 {
699 HAL_DMD_RIU_WriteByteMask(0x101EAF, 0, BMASK(5:3));
700 }
701 else
702 {
703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3));
704 }
705 }
706
HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)707 void HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)
708 {
709 MS_U8 u8RegMuxBackup = 0;
710
711 #ifdef MS_DEBUG
712 ULOGD("DEMOD","HAL_DMD_RFAGC_Tristate %d\n",bEnable);
713 #endif
714 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
715 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
716 if (bEnable)
717 {
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0)));
719
720 }
721 else
722 {
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0)));
724 }
725 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
726 }
727
HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)728 void HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)
729 {
730 MS_U8 u8RegMuxBackup = 0;
731
732 #ifdef MS_DEBUG
733 ULOGD("DEMOD","HAL_DMD_IFAGC_Tristate %d\n",bEnable);
734 #endif
735 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
736 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
737 if (bEnable)
738 {
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4)));
740 }
741 else
742 {
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4)));
744 }
745 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
746 }
747
HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)748 void HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)
749 {
750 #ifdef MS_DEBUG
751 ULOGD("DEMOD","HAL_DMD_IFAGC_TS_Tristate %d\n",bEnable);
752 #endif
753 HAL_DMD_TS1_Tristate(bEnable);
754 HAL_DMD_IFAGC_Tristate(bEnable);
755 }
756
HAL_DMD_TS_GetClockRate(float * fTS_CLK)757 MS_BOOL HAL_DMD_TS_GetClockRate(float *fTS_CLK)
758 {
759 // from Raymond
760 *fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x103300)&BMASK(4:0))+1));
761 return TRUE;
762 }
763
HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)764 static void HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
765 {
766 if (u8PadSel==0)
767 {
768 HAL_DMD_RIU_WriteByteMask(0x112802, 4<<4, BMASK(6:4));
769 }
770 else
771 {
772 if (bPGAEnable)
773 {
774 HAL_DMD_RIU_WriteByteMask(0x112802, 1<<4, BMASK(6:4));
775 }
776 else
777 {
778 HAL_DMD_RIU_WriteByteMask(0x112802, 2<<4, BMASK(6:4));
779 }
780 }
781 }
782
HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)783 static void HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
784 {
785 if (u8PadSel==0)
786 {
787 HAL_DMD_RIU_WriteByteMask(0x112803, 4, BMASK(2:0));
788 }
789 else
790 {
791 if (bPGAEnable)
792 {
793 HAL_DMD_RIU_WriteByteMask(0x112803, 1, BMASK(2:0));
794 }
795 else
796 {
797 HAL_DMD_RIU_WriteByteMask(0x112803, 2, BMASK(2:0));
798 }
799 }
800 }
801
802
HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)803 static void HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)
804 {
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping
807 }
808
HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)809 static void HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)
810 {
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping
813 }
814
815 /************************************************************************************************
816 Subject: ADC I/Q Switch (After Init CLKGen)
817 Function: HAL_DMD_ADC_IQ_Switch
818 Parmeter: u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
819 Parmeter: u8PadSel : 0=Normal, 1=analog pad
820 Parmeter: bPGAEnable : 0=disable, 1=enable
821 Parmeter: u8PGAGain : default 5
822 Return: MS_BOOL :
823 Remark:
824 *************************************************************************************************/
HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain)825 MS_BOOL HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain)
826 {
827 MS_U8 u8RegMuxBackup = 0;
828 u8PGAGain=u8PGAGain;
829 #ifdef MS_DEBUG
830 ULOGD("DEMOD","HAL_DMD_ADC_IQ_Switch %d %d %d %d\n",u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
831 #endif
832
833 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
834 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
835 #ifdef MS_DEBUG
836 ULOGD("DEMOD","before 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
837 #endif
838 switch(u8ADCIQMode)
839 {
840 case 0://Normal case, I path
841 default:
842 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC
843 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC
844 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
845 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q
846 HAL_DMD_ADC_IMUX_Sel(u8PadSel, bPGAEnable);
847 HAL_DMD_SIF_PGA_Ctl(bPGAEnable);
848 HAL_DMD_VIF_PGA_Ctl(FALSE);
849 break;
850 case 1://VIF, Q path, for internal signal saw
851 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC
852 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(1)); // power on Q ADC
853 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
854 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(5)); // ADC clock out select 0:I, 1:Q
855 HAL_DMD_ADC_QMUX_Sel(u8PadSel, bPGAEnable);
856 HAL_DMD_SIF_PGA_Ctl(FALSE);
857 HAL_DMD_VIF_PGA_Ctl(bPGAEnable);
858 break;
859 case 2://both IQ, for ZIF tuner
860 break;
861 }
862 #ifdef MS_DEBUG
863 ULOGD("DEMOD","after 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
864 #endif
865 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
866 return TRUE;
867 }
868
869 /************************************************************************************************
870 Subject: HAL_DMD_TSO_Clk_Control
871 Function: ts output clock frequency and phase configure
872 Parmeter: u8cmd_array, clock div, 0x01, div (0x00~0x1f),
873 clock phase inv, 0x02, inv_en (0,1),
874 clock phase tuning, 0x03, phase_tuning_en (0,1), tuning_num (0x00~0x1f)
875 Return: MS_BOOL
876 Remark:
877 *************************************************************************************************/
HAL_DMD_TSO_Clk_Control(MS_U8 * u8cmd_array)878 MS_BOOL HAL_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array)
879 {
880 MS_U8 u8Temp;
881
882 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
883
884 if ( (u8Temp&0x01) == 0x00)
885 {
886 ULOGE("DEMOD","[DEMOD][halDMD]Error!!!, we shall select clk_dmplldiv3\n");
887 return false;
888 }
889 switch (u8cmd_array[0])
890 {
891 case 0x01: // clock frequency,div
892 {
893 MS_U8 u8data = 0;
894 u8data = HAL_DMD_RIU_ReadByte(0x103300);
895 u8data &= (0xff-0x1f);
896 u8data |= (u8cmd_array[1]&0x1f);
897 HAL_DMD_RIU_WriteByte(0x103300, u8data);
898 }
899 break;
900 case 0x02: // clock phase inv or not.
901 {
902 MS_U8 u8data = 0;
903 u8data = HAL_DMD_RIU_ReadByte(0x103301);
904 u8data &= (0xff-0x02);
905 u8data |= ((u8cmd_array[1]&0x01)<<1);
906 HAL_DMD_RIU_WriteByte(0x103301, u8data);
907 }
908 break;
909 case 0x03:
910 {
911 MS_U8 u8data = 0;
912
913 u8data = HAL_DMD_RIU_ReadByte(0x103301);
914 u8data &= (0xff-0x10);
915 u8data |= ((u8cmd_array[1]&0x01)<<4);
916 HAL_DMD_RIU_WriteByte(0x103301, u8data);
917
918 u8data = HAL_DMD_RIU_ReadByte(0x103300+(0x05<<1)+1);
919 u8data &= (0xff-0x1f);
920 u8data |= (u8cmd_array[2]&0x1f);
921 HAL_DMD_RIU_WriteByte(0x103300+(0x05<<1)+1, u8data);
922 }
923 break;
924 default:
925 ULOGE("DEMOD","[DEMOD][halDMD]Error!!!, cmd invalid\n");
926 break;
927
928 }
929 #ifdef MS_DEBUG
930 ULOGD("DEMOD","0x103300: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103300));
931 ULOGD("DEMOD","0x103301: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103301));
932 ULOGD("DEMOD","0x10330B: 0x%x\n",HAL_DMD_RIU_ReadByte(0x10330B));
933 #endif
934 return true;
935 }
936
937 /****************************************************************************
938 Subject: Function providing approx. result of Log10(X)
939 Function: Log10Approx
940 Parmeter: Operand X in float
941 Return: Approx. value of Log10(X) in float
942 Remark: Ouput range from 0.0, 0.3 to 9.6 (input 1 to 2^32)
943 *****************************************************************************/
944 #if 1
945 const float _LogApproxTableX[80] =
946 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
947 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
948 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
949 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
950 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
951 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
952 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
953 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
954 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
955 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
956 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
957 456767058.24, 593797175.72, 771936328.43, 1003517226.96
958 };
959
960 const float _LogApproxTableY[80] =
961 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
962 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
963 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
964 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
965 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
966 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
967 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
968 };
969
Log10Approx(float flt_x)970 float Log10Approx(float flt_x)
971 {
972 MS_U8 indx = 0;
973
974 do {
975 if (flt_x < _LogApproxTableX[indx])
976 break;
977 indx++;
978 }while (indx < 79); //stop at indx = 80
979
980 return _LogApproxTableY[indx];
981 }
982 #else
Log10Approx(float flt_x)983 float Log10Approx(float flt_x)
984 {
985 MS_U32 u32_temp = 1;
986 MS_U8 indx = 0;
987
988 do {
989 u32_temp = u32_temp << 1;
990 if (flt_x < (float)u32_temp)
991 break;
992 }while (++indx < 32);
993
994 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
995 return (float)0.3 * indx;
996 }
997 #endif
998
999