1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ISDBT.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ISDBT_CHIP_EULER 0x00
112 #define DMD_ISDBT_CHIP_NUGGET 0x01
113 #define DMD_ISDBT_CHIP_KAPPA 0x02
114 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
115 #define DMD_ISDBT_CHIP_NAPOLI 0x04
116 #define DMD_ISDBT_CHIP_MONACO 0x05
117 #define DMD_ISDBT_CHIP_MIAMI 0x06
118 #define DMD_ISDBT_CHIP_MUJI 0x07
119 #define DMD_ISDBT_CHIP_MUNICH 0x08
120 #define DMD_ISDBT_CHIP_MANHATTAN 0x09
121 #define DMD_ISDBT_CHIP_MULAN 0x0A
122 #define DMD_ISDBT_CHIP_MESSI 0x0B
123 #define DMD_ISDBT_CHIP_MASERATI 0x0C
124 #define DMD_ISDBT_CHIP_KIWI 0x0D
125 #define DMD_ISDBT_CHIP_MACAN 0x0E
126 #define DMD_ISDBT_CHIP_MUSTANG 0x0F
127 #define DMD_ISDBT_CHIP_MAXIM 0x10
128 #if defined(CHIP_EULER)
129 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
130 #elif defined(CHIP_NUGGET)
131 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
132 #elif defined(CHIP_KAPPA)
133 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
134 #elif defined(CHIP_EINSTEIN)
135 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
136 #elif defined(CHIP_NAPOLI)
137 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
138 #elif defined(CHIP_MIAMI)
139 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
140 #elif defined(CHIP_MUJI)
141 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
142 #elif defined(CHIP_MUNICH)
143 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUNICH
144 #elif defined(CHIP_MANHATTAN)
145 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MANHATTAN
146 #elif defined(CHIP_MULAN)
147 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MULAN
148 #elif defined(CHIP_MESSI)
149 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MESSI
150 #elif defined(CHIP_MASERATI)
151 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MASERATI
152 #elif defined(CHIP_KIWI)
153 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KIWI
154 #elif defined(CHIP_MACAN)
155 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MACAN
156 #elif defined(CHIP_MUSTANG)
157 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUSTANG
158 #elif defined(CHIP_MAXIM)
159 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAXIM
160 #else
161 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
162 #endif
163
164 //-------------------------------------------------------------------------------------------------
165 // Local Defines
166 //-------------------------------------------------------------------------------------------------
167 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN)
168 #define DMD_ISDBT_TBVA_EN 1
169 #else
170 #define DMD_ISDBT_TBVA_EN 0
171 #endif
172 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr) ) )
173 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr), val) )
174
175 #define HAL_INTERN_ISDBT_DBINFO(y) //y
176 #ifndef MBRegBase
177 #define MBRegBase 0x112600UL
178 #endif
179 #ifndef MBRegBase_DMD1
180 #define MBRegBase_DMD1 0x112400UL
181 #endif
182 #ifndef DMDMcuBase
183 #define DMDMcuBase 0x103480UL
184 #endif
185
186 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_MESSI) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_KIWI)
187 #define REG_ISDBT_LOCK_STATUS 0x11F5
188 #define ISDBT_TDP_REG_BASE 0x1400
189 #define ISDBT_FDP_REG_BASE 0x1500
190 #define ISDBT_FDPEXT_REG_BASE 0x1600
191 #define ISDBT_OUTER_REG_BASE 0x1700
192 #else
193 #define REG_ISDBT_LOCK_STATUS 0x36F5
194 #define ISDBT_TDP_REG_BASE 0x3700
195 #define ISDBT_FDP_REG_BASE 0x3800
196 #define ISDBT_FDPEXT_REG_BASE 0x3900
197 #define ISDBT_OUTER_REG_BASE 0x3A00
198 #endif
199
200 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
201 #define ISDBT_MIU_CLIENTW_ADDR 0xF5
202 #define ISDBT_MIU_CLIENTR_ADDR 0xF5
203 #define ISDBT_MIU_CLIENTW_MASK 0x87
204 #define ISDBT_MIU_CLIENTR_MASK 0x87
205 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x01
206 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x02
207 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO) || \
208 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN) || \
209 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
210 #define ISDBT_MIU_CLIENTW_ADDR 0xF2
211 #define ISDBT_MIU_CLIENTR_ADDR 0xF2
212 #define ISDBT_MIU_CLIENTW_MASK 0x66
213 #define ISDBT_MIU_CLIENTR_MASK 0x66
214 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
215 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x04
216 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
217 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
218 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
219 #define ISDBT_MIU_CLIENTW_MASK 0x47
220 #define ISDBT_MIU_CLIENTR_MASK 0x46
221 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
222 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
223 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
224 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
225 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
226 #define ISDBT_MIU_CLIENTW_MASK 0x47
227 #define ISDBT_MIU_CLIENTR_MASK 0x46
228 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x04
229 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
230 #endif
231 //-------------------------------------------------------------------------------------------------
232 // Local Variables
233 //-------------------------------------------------------------------------------------------------
234
235 const MS_U8 INTERN_ISDBT_table[] = {
236 #include "DMD_INTERN_ISDBT.dat"
237 };
238
239 #ifndef UTPA2
240 static const float _LogApproxTableX[80] =
241 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
242 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
243 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
244 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
245 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
246 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
247 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
248 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
249 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
250 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
251 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
252 456767058.24, 593797175.72, 771936328.43, 1003517226.96
253 };
254
255 static const float _LogApproxTableY[80] =
256 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
257 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
258 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
259 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
260 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
261 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
262 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
263 };
264 #endif
265
266 //-------------------------------------------------------------------------------------------------
267 // Global Variables
268 //-------------------------------------------------------------------------------------------------
269
270 extern MS_U8 u8DMD_ISDBT_DMD_ID;
271
272 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
273
274 //-------------------------------------------------------------------------------------------------
275 // Local Functions
276 //-------------------------------------------------------------------------------------------------
277 #ifndef UTPA2
278
279 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)280 static float Log10Approx(float flt_x)
281 {
282 MS_U8 indx = 0;
283
284 do {
285 if (flt_x < _LogApproxTableX[indx])
286 break;
287 indx++;
288 }while (indx < 79); //stop at indx = 80
289
290 return _LogApproxTableY[indx];
291 }
292 #endif
293
_CALCULATE_SQI(float fber)294 static MS_U16 _CALCULATE_SQI(float fber)
295 {
296 float flog_ber;
297 MS_U16 u16SQI;
298
299 #ifdef MSOS_TYPE_LINUX
300 flog_ber = (float)log10((double)fber);
301 #else
302 if (fber != 0.0)
303 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
304 else
305 flog_ber = -8.0;//when fber=0 means u16SQI=100
306 #endif
307
308 //printf("dan fber = %f\n", fber);
309 //printf("dan flog_ber = %f\n", flog_ber);
310 // Part 2: transfer ber value to u16SQI value.
311 if (flog_ber <= ( - 7.0))
312 {
313 u16SQI = 100; //*quality = 100;
314 }
315 else if (flog_ber < -6.0)
316 {
317 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
318 }
319 else if (flog_ber < -5.5)
320 {
321 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
322 }
323 else if (flog_ber < -5.0)
324 {
325 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
326 }
327 else if (flog_ber < -4.5)
328 {
329 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
330 }
331 else if (flog_ber < -4.0)
332 {
333 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
334 }
335 else if (flog_ber < -3.5)
336 {
337 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
338 }
339 else if (flog_ber < -3.0)
340 {
341 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
342 }
343 else if (flog_ber < -2.5)
344 {
345 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
346 }
347 else if (flog_ber < -2.0)
348 {
349 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
350 }
351 else
352 {
353 u16SQI = 0;
354 }
355
356 return u16SQI;
357 }
358 #endif
359
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)360 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
361 {
362 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
363 }
364
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)365 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
366 {
367 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
368 }
369
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)370 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
371 {
372 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
373 }
374
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)375 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
376 {
377 MS_U8 u8CheckCount;
378 MS_U8 u8CheckFlag = 0xFF;
379 MS_U32 u32MBRegBase = MBRegBase;
380
381 if (u8DMD_ISDBT_DMD_ID == 0)
382 u32MBRegBase = MBRegBase;
383 else if (u8DMD_ISDBT_DMD_ID == 1)
384 u32MBRegBase = MBRegBase_DMD1;
385
386 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
387 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
388 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
389 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
390
391 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
392 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
393
394 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
395 {
396 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
397 if ((u8CheckFlag&0x01)==0)
398 break;
399 MsOS_DelayTask(1);
400 }
401
402 if (u8CheckFlag&0x01)
403 {
404 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
405 return FALSE;
406 }
407
408 return TRUE;
409 }
410
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)411 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
412 {
413 MS_U8 u8CheckCount;
414 MS_U8 u8CheckFlag = 0xFF;
415 MS_U32 u32MBRegBase = MBRegBase;
416
417 if (u8DMD_ISDBT_DMD_ID == 0)
418 u32MBRegBase = MBRegBase;
419 else if (u8DMD_ISDBT_DMD_ID == 1)
420 u32MBRegBase = MBRegBase_DMD1;
421
422 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
423 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
424 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
425
426 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
427 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
428
429 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
430 {
431 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
432 if ((u8CheckFlag&0x02)==0)
433 {
434 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
435 break;
436 }
437 MsOS_DelayTask(1);
438 }
439
440 if (u8CheckFlag&0x02)
441 {
442 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
443 return FALSE;
444 }
445
446 return TRUE;
447 }
448
449
450
451 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)452 static void _HAL_INTERN_ISDBT_InitClk(void)
453 {
454 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EULER--------------\n"));
455
456 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
457
458 // Init by HKMCU
459 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
460 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
461 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
462 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
463 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
464 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
465 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
466
467 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
468 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
469 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
470 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
472 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
473 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
475 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
483 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
484 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
485 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
489 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
490
491 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
492 }
493 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)494 static void _HAL_INTERN_ISDBT_InitClk(void)
495 {
496 MS_U8 u8Val = 0;
497
498 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n"));
499
500 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
501
502 // Init by HKMCU
503 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
504 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
505 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
506 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
507 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
508 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
509 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
510 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
511 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
512
513 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
514 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
515 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
516 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
517 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
519 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
520 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
521 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
522 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
523 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
530 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
533 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
534 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
535 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
536 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
537
538 u8Val = _HAL_DMD_RIU_ReadByte(0x1006F5);
539 _HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
540
541 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
542 }
543 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)544 static void _HAL_INTERN_ISDBT_InitClk(void)
545 {
546 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n"));
547
548 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
549
550 // Init by HKMCU
551 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
552 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
553 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
554 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
555 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
556 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
557 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
558
559 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
560 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
561 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
562 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
563 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
564 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
565 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
566 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
567 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
568 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
569 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
570 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
571 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
573 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
574 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
575 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
576 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
581 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
582
583 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
584 }
585 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)586 static void _HAL_INTERN_ISDBT_InitClk(void)
587 {
588 MS_U8 u8Val = 0;
589
590 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n"));
591
592 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
593
594 // Init by HKMCU
595 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
596 u8Val &= ~0x01;
597 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
598
599 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
600 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
601 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
602 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
603 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
604 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
605 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
606 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
607 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
608
609 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
610 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
611 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
612 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
613 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
614 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
615 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
616 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
617 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
618 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
619 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
620 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
624 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
625 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
626 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
627 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
630 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
632 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
633
634 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
635 }
636 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)637 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
638 {
639 MS_U8 u8Val = 0;
640
641 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n"));
642
643 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
644
645 // Init by HKMCU
646 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
647 u8Val &= ~0x01;
648 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
649
650 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
651 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
652 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
653 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
654 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
655 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
656 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
657 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
658 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
659
660 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
661 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
662 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
663 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
666 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
667 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
669 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
671 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
673 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
674 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
675 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
676 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
677 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
678 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
679 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
680 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
682 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
683 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
684
685 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
686 }
687 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)688 static void _HAL_INTERN_ISDBT_InitClk(void)
689 {
690 MS_U8 u8Val = 0;
691
692 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n"));
693
694 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
695
696 // Init by HKMCU
697 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
698 u8Val &= ~0x01;
699 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
700
701 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
702 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
703 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
704 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
705 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
706 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
707 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
708 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
709
710 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
711 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
712 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
713 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
716 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
717 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
719 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
720 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
721 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
723 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
724 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
725 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
727 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
732 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
733 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
734 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
735 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
736 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
737 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
738
739 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
740 }
741 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)742 static void _HAL_INTERN_ISDBT_InitClk(void)
743 {
744 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n"));
745
746 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
747
748 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
749 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
750 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
751 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
752 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
753 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
754 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
755 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
756
757 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
758 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
759 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
760 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
761 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
762 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
763 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
764 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
765 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
768 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
769 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
771 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
772 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
773 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
774 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
775 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
776 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
777 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
779 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
780 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
781 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
782 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
783 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
784 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
785
786 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
787 }
788 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)789 static void _HAL_INTERN_ISDBT_InitClk(void)
790 {
791 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n"));
792
793 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
794
795 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
796 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
797 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
798 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
799 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
800 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
803 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
804
805 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
806 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
807 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
809 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
810 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
811 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
812 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
813 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
814 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
815 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
816 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
818 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
819 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
822 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
823 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
824 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
828 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
829 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
830 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
831 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
832 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
833 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
834 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
835 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
836 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
837 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
838 _HAL_DMD_RIU_WriteByte(0x112091, 0x46);
839 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
840
841 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
842 }
843 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
_HAL_INTERN_ISDBT_InitClk(void)844 static void _HAL_INTERN_ISDBT_InitClk(void)
845 {
846 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUNICH--------------\n"));
847
848 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
849
850 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
851 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
852 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
853 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
854 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
855 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
856 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
857 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
858
859 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
860 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
861 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
862 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
863 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
864 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
865 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
866 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
867 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
868 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
869 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
870 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
871 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
872 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
873 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
874 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
875 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
876 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
877 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
879 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
880 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
881 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
882 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
883 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
884 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
885 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
886 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
887
888 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
889 }
890 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN)
_HAL_INTERN_ISDBT_InitClk(void)891 static void _HAL_INTERN_ISDBT_InitClk(void)
892 {
893 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MANHATTAN--------------\n"));
894
895 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
896
897 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
898 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
899 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
900 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
901 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
902 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
903 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
904 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
905 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
906
907 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
908 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
909 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
910 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
911 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
912 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
913 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
914 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
915 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
916 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
917 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
918 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
919 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
920 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
921 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
923 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
924 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
925 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
926 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
927 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
928 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
929 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
930 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
931 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
932 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
933 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
934 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
935 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
936 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
938 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
939 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
940 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
941 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
942 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
943 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
944 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
945 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
946 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
947 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
948
949 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
950 }
951 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MULAN)
_HAL_INTERN_ISDBT_InitClk(void)952 static void _HAL_INTERN_ISDBT_InitClk(void)
953 {
954 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MULAN--------------\n"));
955
956 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
957
958 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
959 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
960 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
961 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
962 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
963 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
964 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
965 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
966 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //reset ts divider
967
968 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
969 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
970 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
971 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
972 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
973 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
974 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
975 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
976 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
977 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
978 _HAL_DMD_RIU_WriteByte(0x111f24, 0x05);
979 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
980 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
981 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
982 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
983 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
984 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
985 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
986 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
987 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
988 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
989 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
990 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
991 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
992 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
993 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
994 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
995 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
996 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
997 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
998 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
999 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1000 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1001 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1002 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1003 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1004 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1005 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1006 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1007 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1008 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1009 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1010 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1011 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x88);
1012 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1013 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1014 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1015 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1016 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1017 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1018
1019 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //reset ts divider
1020
1021 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1022 }
1023 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
_HAL_INTERN_ISDBT_InitClk(void)1024 static void _HAL_INTERN_ISDBT_InitClk(void)
1025 {
1026 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MESSI--------------\n"));
1027
1028 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1029
1030 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1031 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1032 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1033 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1034 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1035 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1036 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1037 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1038 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1039
1040 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1041 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
1042 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1043 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1044 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1045 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1046 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1047 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1048 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1049 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1050 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1051 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1052 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1053 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1055 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1056 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
1057 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1058 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
1059 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1061 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
1062 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
1064 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
1065 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
1066 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
1067 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
1068 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
1069 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1070 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
1071 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x0C);
1072 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
1073 _HAL_DMD_RIU_WriteByte(0x111f51, 0x48);
1074 _HAL_DMD_RIU_WriteByte(0x111f50, 0x44);
1075 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
1076 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
1077 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
1078 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
1079 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
1080 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
1081 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
1082 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
1083 _HAL_DMD_RIU_WriteByte(0x111f89, 0x44);
1084 _HAL_DMD_RIU_WriteByte(0x111f88, 0x44);
1085 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1086 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x44);
1087 _HAL_DMD_RIU_WriteByte(0x111f8d, 0x18);
1088 _HAL_DMD_RIU_WriteByte(0x111f8c, 0x44);
1089 _HAL_DMD_RIU_WriteByte(0x111f8f, 0x00);
1090 _HAL_DMD_RIU_WriteByte(0x111f8e, 0x44);
1091
1092 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1093 }
1094
1095 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MASERATI)
_HAL_INTERN_ISDBT_InitClk(void)1096 static void _HAL_INTERN_ISDBT_InitClk(void)
1097 {
1098 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MASERATI--------------\n"));
1099
1100 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1101
1102 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1103 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1104 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1105 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1106 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1107 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1108 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1109 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1110 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1111
1112 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1113 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1114 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1115 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1116 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1117 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1118 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1119 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1120 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1121 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1122 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1123 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1124 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1125 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1126 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1127 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1128 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1129 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1130 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1131 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1132 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1133 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1134 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1135 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1136 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1137 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1138 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1139 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1140 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1141 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1142 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1143 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1144 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1145 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1146 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1147 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1148 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1149 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1150 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1151 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1152 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1153 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1154 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1155 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1156 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1157 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1158 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1159 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1160 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1161 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1162 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1163 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1164 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1165 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1166 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1167 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1168 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1169 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1170 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1171 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1172 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1173 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1174 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1175
1176 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1177 }
1178 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MACAN)
_HAL_INTERN_ISDBT_InitClk(void)1179 static void _HAL_INTERN_ISDBT_InitClk(void)
1180 {
1181 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MACAN--------------\n"));
1182
1183 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1184
1185 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1186 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1187 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1188 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1189 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1190 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1191 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1192 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1193 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1194
1195 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1196 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1197 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1198 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1199 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1200 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1201 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1202 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1203 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1204 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1205 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1206 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1207 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1208 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1209 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1210 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1211 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1212 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1213 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1214 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1215 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1216 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1217 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1218 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1219 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1220 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1221 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1222 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1223 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1224 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1225 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1226 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1227 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1228 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1229 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1230 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1231 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1232 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1233 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1234 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1235 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1236 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1237 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1238 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1239 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1240 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1241 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1242 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1243 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1244 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1245 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1246 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1247 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1248 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1249 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1250 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1251 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1252 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1253 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1254 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1255 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1256 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1257 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1258
1259 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1260 }
1261 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG)
_HAL_INTERN_ISDBT_InitClk(void)1262 static void _HAL_INTERN_ISDBT_InitClk(void)
1263 {
1264 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUSTANG--------------\n"));
1265
1266 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1267
1268 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1269 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1270 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1271 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1272 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1273 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1274 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1275 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1276 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1277
1278 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1279 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1280 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1281 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1282 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1283 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1284 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1285 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1286 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1287 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1288 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1289 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1290 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1291 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1292 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1293 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1294 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1295 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1296 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1297 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1298 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1299 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1300 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1301 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1302 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1303 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1304 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1305 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1306 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1307 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1308 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1309 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1310 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1311 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1312 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1313 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1314 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1315 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1316 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1317 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1318 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1319 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1320 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1321 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1322 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1323 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1324 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1325 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1326 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1327 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1328 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1329 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1330 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1331 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1332 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1333 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1334 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1335 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1336 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1337 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1338 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1339 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1340 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1341
1342 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1343 }
1344 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAXIM)
_HAL_INTERN_ISDBT_InitClk(void)1345 static void _HAL_INTERN_ISDBT_InitClk(void)
1346 {
1347 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MAXIM--------------\n"));
1348
1349 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1350
1351 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1352 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1353
1354 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1355 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1356 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1357 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1358 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1359 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1360 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00); //ADC SYNC FLOW
1361 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00); //ADC SYNC FLOW
1362 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1363 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1364
1365 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00); //Add in MAXIM //ADC SYNC FLOW
1366 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00); //Add in MAXIM //ADC SYNC FLOW
1367
1368 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1369 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1370
1371 _HAL_DMD_RIU_WriteByte(0x103321, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1372 _HAL_DMD_RIU_WriteByte(0x103320, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1373
1374 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00); // DMD_ANA_ADC_SYNC CLK_W
1375
1376 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1377 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1378 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1379 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1380 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1381 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1382 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1383 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1384 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1385 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1386 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1387 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1388 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1389 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1390 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1391 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1392 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1393 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1394 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1395 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1396 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1397 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1398 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1399 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1400 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1401 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1402 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1403 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1404 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1405 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1406 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1407 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1408 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1409 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1410 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1411 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1412 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1413 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1414 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1415 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1416 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1417 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1418 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1419 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1420 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1421 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1422 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1423 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1424 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1425 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1426 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1427 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1428 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1429 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1430 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1431 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1432 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1433 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1434
1435 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1436 //_HAL_DMD_RIU_WriteByteMask(0x103480, 0x00, 0x02);
1437 }
1438 #else
_HAL_INTERN_ISDBT_InitClk(void)1439 static void _HAL_INTERN_ISDBT_InitClk(void)
1440 {
1441 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
1442 }
1443 #endif
1444
_HAL_INTERN_ISDBT_Ready(void)1445 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
1446 {
1447 MS_U8 udata = 0x00;
1448
1449 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1450
1451 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1452 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1453
1454 MsOS_DelayTask(1);
1455
1456 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1457
1458 if (udata) return FALSE;
1459
1460 return TRUE;
1461 }
1462
_HAL_INTERN_ISDBT_Download(void)1463 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
1464 {
1465 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
1466
1467 MS_U8 udata = 0x00;
1468 MS_U16 i = 0;
1469 MS_U16 fail_cnt = 0;
1470 MS_U8 u8TmpData;
1471 MS_U16 u16AddressOffset;
1472 const MS_U8 *ISDBT_table;
1473 MS_U16 u16Lib_size;
1474
1475 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
1476 {
1477 if (_HAL_INTERN_ISDBT_Ready())
1478 {
1479 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1480 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1481 #endif
1482 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1483 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03);
1484
1485 MsOS_DelayTask(20);
1486 return TRUE;
1487 }
1488 }
1489
1490 ISDBT_table = &INTERN_ISDBT_table[0];
1491 u16Lib_size = sizeof(INTERN_ISDBT_table);
1492
1493 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1494 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1495 #endif
1496 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1497 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1498
1499 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x01); // release MCU, madison patch
1500
1501 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1502 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1503 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1504 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1505
1506 //// Load code thru VDMCU_IF ////
1507 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
1508
1509 for (i = 0; i < u16Lib_size; i++)
1510 {
1511 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
1512 }
1513
1514 //// Content verification ////
1515 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
1516
1517 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1518 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1519
1520 for (i = 0; i < u16Lib_size; i++)
1521 {
1522 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1523
1524 if (udata != ISDBT_table[i])
1525 {
1526 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
1527 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
1528 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
1529
1530 if (fail_cnt++ > 10)
1531 {
1532 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
1533 return FALSE;
1534 }
1535 }
1536 }
1537
1538 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
1539
1540 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1541 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1542
1543 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
1544 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1545 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
1546 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1547 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
1548 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1549 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
1550 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1551 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
1552 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1553 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
1554 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1555 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
1556 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1557 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
1558 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1559 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
1560 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1561
1562 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1563 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1564
1565 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset MCU, madison patch
1566
1567 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1568 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03); // release VD_MCU
1569
1570 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
1571
1572 MsOS_DelayTask(20);
1573
1574 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
1575
1576 return TRUE;
1577 }
1578
_HAL_INTERN_ISDBT_FWVERSION(void)1579 static void _HAL_INTERN_ISDBT_FWVERSION(void)
1580 {
1581 MS_U8 data1 = 0;
1582 MS_U8 data2 = 0;
1583 MS_U8 data3 = 0;
1584
1585 _MBX_ReadReg(0x20C4, &data1);
1586 _MBX_ReadReg(0x20C5, &data2);
1587 _MBX_ReadReg(0x20C6, &data3);
1588
1589 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1590 }
1591
_HAL_INTERN_ISDBT_Exit(void)1592 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
1593 {
1594 MS_U8 u8CheckCount = 0;
1595 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1596 MS_U8 u8RegValTmp = 0;
1597
1598 _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR, &u8RegValTmp);
1599 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1600 {
1601 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1602 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1603 }
1604 else
1605 {
1606 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1607 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1608 }
1609 #endif
1610 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1611
1612 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1613 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1614
1615 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1616 {
1617 MsOS_DelayTaskUs(10);
1618
1619 if (u8CheckCount++ == 0xFF)
1620 {
1621 printf(">> ISDBT Exit Fail!\n");
1622 return FALSE;
1623 }
1624 }
1625
1626 printf(">> ISDBT Exit Ok!\n");
1627
1628 return TRUE;
1629 }
1630
_HAL_INTERN_ISDBT_SoftReset(void)1631 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
1632 {
1633 MS_U8 u8Data = 0;
1634
1635 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1636 MS_U8 u8RegValTmp = 0;
1637
1638 _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR, &u8RegValTmp);
1639 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1640 {
1641 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1642 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1643 }
1644 else
1645 {
1646 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1647 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1648 }
1649 #endif
1650
1651 //Reset FSM
1652 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1653
1654 while (u8Data!=0x02)
1655 {
1656 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1657 }
1658
1659 return TRUE;
1660 }
1661
_HAL_INTERN_ISDBT_SetACICoef(void)1662 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
1663 {
1664 return TRUE;
1665 }
1666
_HAL_INTERN_ISDBT_SetIsdbtMode(void)1667 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
1668 {
1669 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1670 MS_U8 u8RegValTmp = 0;
1671
1672 _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR, &u8RegValTmp);
1673 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1674 {
1675 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1676 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1677 }
1678 else
1679 {
1680 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1681 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1682 }
1683 #endif
1684
1685 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
1686 return _MBX_WriteReg(0x20C0, 0x04);
1687 }
1688
_HAL_INTERN_ISDBT_SetModeClean(void)1689 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
1690 {
1691 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1692 return _MBX_WriteReg(0x20C0, 0x00);
1693 }
1694
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)1695 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
1696 {
1697 MS_BOOL bCheckPass = FALSE;
1698 MS_U8 u8Data = 0;
1699
1700 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1701
1702 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
1703 bCheckPass = TRUE;
1704
1705 return bCheckPass;
1706 }
1707
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)1708 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
1709 {
1710 MS_BOOL bCheckPass = FALSE;
1711 MS_U8 u8Data = 0;
1712
1713 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1714
1715 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
1716 bCheckPass = TRUE;
1717
1718 return bCheckPass;
1719 }
1720
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)1721 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
1722 {
1723 MS_BOOL bCheckPass = FALSE;
1724 MS_U8 u8Data = 0;
1725
1726 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1727
1728 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
1729 bCheckPass = TRUE;
1730
1731 return bCheckPass;
1732 }
1733
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)1734 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
1735 {
1736 MS_BOOL bCheckPass = FALSE;
1737 MS_U8 u8Data = 0;
1738
1739 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1740
1741 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
1742 bCheckPass = TRUE;
1743
1744 return bCheckPass;
1745 }
1746
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)1747 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
1748 {
1749 MS_BOOL bRet = TRUE;
1750 MS_U8 u8Data = 0;
1751 MS_U8 u8CodeRate = 0;
1752
1753 switch (eLayerIndex)
1754 {
1755 case E_ISDBT_Layer_A:
1756 // [10:8] reg_tmcc_cur_convolution_code_rate_a
1757 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1758 u8CodeRate = u8Data & 0x07;
1759 break;
1760 case E_ISDBT_Layer_B:
1761 // [10:8] reg_tmcc_cur_convolution_code_rate_b
1762 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1763 u8CodeRate = u8Data & 0x07;
1764 break;
1765 case E_ISDBT_Layer_C:
1766 // [10:8] reg_tmcc_cur_convolution_code_rate_c
1767 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1768 u8CodeRate = u8Data & 0x07;
1769 break;
1770 default:
1771 u8CodeRate = 15;
1772 break;
1773 }
1774
1775 switch (u8CodeRate)
1776 {
1777 case 0:
1778 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
1779 break;
1780 case 1:
1781 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
1782 break;
1783 case 2:
1784 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
1785 break;
1786 case 3:
1787 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
1788 break;
1789 case 4:
1790 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
1791 break;
1792 default:
1793 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
1794 break;
1795 }
1796
1797 return bRet;
1798 }
1799
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)1800 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
1801 {
1802 MS_BOOL bRet = TRUE;
1803 MS_U8 u8Data = 0;
1804 MS_U8 u8CP = 0;
1805
1806 // [7:6] reg_mcd_out_cp
1807 // output cp -> 00: 1/4
1808 // 01: 1/8
1809 // 10: 1/16
1810 // 11: 1/32
1811 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1812
1813 u8CP = (u8Data >> 6) & 0x03;
1814
1815 switch (u8CP)
1816 {
1817 case 0:
1818 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
1819 break;
1820 case 1:
1821 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
1822 break;
1823 case 2:
1824 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
1825 break;
1826 case 3:
1827 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
1828 break;
1829 }
1830
1831 return bRet;
1832 }
1833
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)1834 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
1835 {
1836 MS_BOOL bRet = TRUE;
1837 MS_U8 u8Data = 0;
1838 MS_U8 u8Mode = 0;
1839 MS_U8 u8Tdi = 0;
1840
1841 // [5:4] reg_mcd_out_mode
1842 // output mode -> 00: 2k
1843 // 01: 4k
1844 // 10: 8k
1845 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1846
1847 u8Mode = (u8Data >> 4) & 0x03;
1848
1849 switch (eLayerIndex)
1850 {
1851 case E_ISDBT_Layer_A:
1852 // [14:12] reg_tmcc_cur_interleaving_length_a
1853 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1854 u8Tdi = (u8Data >> 4) & 0x07;
1855 break;
1856 case E_ISDBT_Layer_B:
1857 // [14:12] reg_tmcc_cur_interleaving_length_b
1858 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1859 u8Tdi = (u8Data >> 4) & 0x07;
1860 break;
1861 case E_ISDBT_Layer_C:
1862 // [14:12] reg_tmcc_cur_interleaving_length_c
1863 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1864 u8Tdi = (u8Data >> 4) & 0x07;
1865 break;
1866 default:
1867 u8Tdi = 15;
1868 break;
1869 }
1870
1871 // u8Tdi+u8Mode*4
1872 // => 0~3: 2K
1873 // => 4~7: 4K
1874 // => 8~11:8K
1875 switch (u8Tdi+u8Mode*4)
1876 {
1877 case 0:
1878 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
1879 break;
1880 case 1:
1881 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
1882 break;
1883 case 2:
1884 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
1885 break;
1886 case 3:
1887 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
1888 break;
1889 case 4:
1890 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
1891 break;
1892 case 5:
1893 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
1894 break;
1895 case 6:
1896 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
1897 break;
1898 case 7:
1899 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
1900 break;
1901 case 8:
1902 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
1903 break;
1904 case 9:
1905 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
1906 break;
1907 case 10:
1908 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
1909 break;
1910 case 11:
1911 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
1912 break;
1913 default:
1914 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
1915 break;
1916 }
1917
1918 return bRet;
1919 }
1920
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)1921 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
1922 {
1923 MS_BOOL bRet = TRUE;
1924 MS_U8 u8Data = 0;
1925 MS_U8 u8Mode = 0;
1926
1927 // [5:4] reg_mcd_out_mode
1928 // output mode -> 00: 2k
1929 // 01: 4k
1930 // 10: 8k
1931 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1932
1933 u8Mode = (u8Data >> 4) & 0x03;
1934
1935 switch (u8Mode)
1936 {
1937 case 0:
1938 *peIsdbtFFT = E_ISDBT_FFT_2K;
1939 break;
1940 case 1:
1941 *peIsdbtFFT = E_ISDBT_FFT_4K;
1942 break;
1943 case 2:
1944 *peIsdbtFFT = E_ISDBT_FFT_8K;
1945 break;
1946 default:
1947 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
1948 break;
1949 }
1950
1951 return bRet;
1952 }
1953
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)1954 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
1955 {
1956 MS_BOOL bRet = TRUE;
1957 MS_U8 u8Data = 0;
1958 MS_U8 u8QAM = 0;
1959
1960 switch(eLayerIndex)
1961 {
1962 case E_ISDBT_Layer_A:
1963 // [6:4] reg_tmcc_cur_carrier_modulation_a
1964 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
1965 u8QAM = (u8Data >> 4) & 0x07;
1966 break;
1967 case E_ISDBT_Layer_B:
1968 // [6:4] reg_tmcc_cur_carrier_modulation_b
1969 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
1970 u8QAM = (u8Data >> 4) & 0x07;
1971 break;
1972 case E_ISDBT_Layer_C:
1973 // [6:4] reg_tmcc_cur_carrier_modulation_c
1974 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
1975 u8QAM = (u8Data >> 4) & 0x07;
1976 break;
1977 default:
1978 u8QAM = 15;
1979 break;
1980 }
1981
1982 switch(u8QAM)
1983 {
1984 case 0:
1985 *peIsdbtConstellation = E_ISDBT_DQPSK;
1986 break;
1987 case 1:
1988 *peIsdbtConstellation = E_ISDBT_QPSK;
1989 break;
1990 case 2:
1991 *peIsdbtConstellation = E_ISDBT_16QAM;
1992 break;
1993 case 3:
1994 *peIsdbtConstellation = E_ISDBT_64QAM;
1995 break;
1996 default:
1997 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
1998 break;
1999 }
2000
2001 return bRet;
2002 }
2003
_HAL_INTERN_ISDBT_ReadIFAGC(void)2004 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
2005 {
2006 MS_U8 data = 0;
2007
2008 _MBX_ReadReg(0x28FD, &data);
2009
2010 return data;
2011 }
2012
2013 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 * pFFT_Mode,MS_S32 * pTdCfoRegValue,MS_S32 * pFdCfoRegValue,MS_S16 * pIcfoRegValue)2014 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 *pFFT_Mode, MS_S32 *pTdCfoRegValue, MS_S32 *pFdCfoRegValue, MS_S16 *pIcfoRegValue)
2015 #else
2016 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
2017 #endif
2018 {
2019 MS_BOOL bRet = TRUE;
2020 MS_U8 u8Data = 0;
2021 MS_S32 s32TdCfoRegValue = 0;
2022 MS_S32 s32FdCfoRegValue = 0;
2023 MS_S16 s16IcfoRegValue = 0;
2024 #ifndef UTPA2
2025 float fTdCfoFreq = 0.0;
2026 float fICfoFreq = 0.0;
2027 float fFdCfoFreq = 0.0;
2028 #endif
2029
2030 //Get TD CFO
2031 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2032 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
2033
2034 //read td_freq_error
2035 //Read <29,38>
2036 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2037 s32TdCfoRegValue = u8Data;
2038 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
2039 s32TdCfoRegValue |= u8Data << 8;
2040 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
2041 s32TdCfoRegValue = u8Data << 16;
2042 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
2043 s32TdCfoRegValue |= u8Data << 24;
2044
2045 if (u8Data >= 0x10)
2046 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
2047
2048 s32TdCfoRegValue >>=4;
2049
2050 //TD_cfo_Hz = RegCfoTd * fb
2051 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2052 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
2053
2054 #ifndef UTPA2
2055 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
2056 fTdCfoFreq = fTdCfoFreq * 8126980.0;
2057 #endif
2058
2059 //Get FD CFO
2060 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2061 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2062 //load
2063 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2064 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2065
2066 //read CFO_KI
2067 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
2068 s32FdCfoRegValue = u8Data;
2069 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
2070 s32FdCfoRegValue |= u8Data << 8;
2071 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
2072 s32FdCfoRegValue |= u8Data << 16;
2073 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
2074 s32FdCfoRegValue |= u8Data << 24;
2075
2076 if(u8Data >= 0x01)
2077 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
2078
2079 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2080 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2081 //load
2082 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2083 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2084
2085 #ifndef UTPA2
2086 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
2087 fFdCfoFreq = fFdCfoFreq * 8126980.0;
2088 #endif
2089
2090 //Get ICFO
2091 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
2092 s16IcfoRegValue = u8Data;
2093 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
2094 s16IcfoRegValue |= u8Data << 8;
2095 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
2096
2097 if(s16IcfoRegValue >= 0x400)
2098 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
2099
2100 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
2101
2102 #ifdef UTPA2
2103 *pFFT_Mode = u8Data;
2104 *pTdCfoRegValue = s32TdCfoRegValue;
2105 *pFdCfoRegValue = s32TdCfoRegValue;
2106 *pIcfoRegValue = s16IcfoRegValue;
2107 #else
2108 if((u8Data & 0x30) == 0x0000) // 2k
2109 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
2110 else if((u8Data & 0x0030) == 0x0010) // 4k
2111 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
2112 else //if(u16data & 0x0030 == 0x0020) // 8k
2113 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
2114
2115 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
2116
2117 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
2118 #endif
2119
2120 return bRet;
2121 }
2122
2123 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2124 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2125 #else
2126 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2127 #endif
2128 {
2129 MS_BOOL bRet = TRUE;
2130 MS_U8 u8Data = 0;
2131 MS_U16 u16BerValue = 0;
2132 MS_U32 u32BerPeriod = 0;
2133
2134 // reg_rd_freezeber
2135 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2136 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
2137
2138 if (eLayerIndex == E_ISDBT_Layer_A)
2139 {
2140 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
2141 u16BerValue=u8Data;
2142 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
2143 u16BerValue |= (u8Data << 8);
2144 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
2145 u32BerPeriod = (u8Data&0x3F);
2146 u32BerPeriod <<= 16;
2147 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
2148 u32BerPeriod |= u8Data;
2149 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
2150 u32BerPeriod |= (u8Data << 8);
2151 }
2152 else if (eLayerIndex == E_ISDBT_Layer_B)
2153 {
2154 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
2155 u16BerValue=u8Data;
2156 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
2157 u16BerValue |= (u8Data << 8);
2158 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
2159 u32BerPeriod = (u8Data&0x3F);
2160 u32BerPeriod <<= 16;
2161 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
2162 u32BerPeriod |= u8Data;
2163 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
2164 u32BerPeriod |= (u8Data << 8);
2165 }
2166 else if (eLayerIndex == E_ISDBT_Layer_C)
2167 {
2168 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
2169 u16BerValue=u8Data;
2170 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
2171 u16BerValue |= (u8Data << 8);
2172 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
2173 u32BerPeriod = (u8Data&0x003F);
2174 u32BerPeriod <<= 16;
2175 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
2176 u32BerPeriod |= u8Data;
2177 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
2178 u32BerPeriod |= (u8Data << 8);
2179 }
2180 else
2181 {
2182 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2183 bRet = FALSE;
2184 }
2185
2186 // reg_rd_freezeber
2187 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2188 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
2189
2190 u32BerPeriod <<= 8; // *256
2191
2192 if(u32BerPeriod == 0) u32BerPeriod = 1;
2193
2194 #ifdef UTPA2
2195 *pBerPeriod = u32BerPeriod;
2196 *pBerValue = u16BerValue;
2197 #else
2198 *pfber = (float)u16BerValue/u32BerPeriod;
2199 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
2200 #endif
2201
2202 return bRet;
2203 }
2204
2205 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2206 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2207 #else
2208 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2209 #endif
2210 {
2211 MS_BOOL bRet = TRUE;
2212 MS_U8 u8Data = 0;
2213 MS_U8 u8FrzData = 0;
2214 MS_U32 u32BerValue = 0;
2215 MS_U16 u16BerPeriod = 0;
2216
2217 // reg_rd_freezeber
2218 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2219 u8Data = u8FrzData | 0x01;
2220 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2221
2222 if (eLayerIndex == E_ISDBT_Layer_A)
2223 {
2224 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
2225 u32BerValue = u8Data;
2226 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
2227 u32BerValue |= u8Data << 8;
2228 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
2229 u32BerValue |= u8Data << 16;
2230 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
2231 u32BerValue |= u8Data << 24;
2232
2233 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
2234 u16BerPeriod = u8Data;
2235 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
2236 u16BerPeriod |= u8Data << 8;
2237 }
2238 else if (eLayerIndex == E_ISDBT_Layer_B)
2239 {
2240 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
2241 u32BerValue = u8Data;
2242 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
2243 u32BerValue |= u8Data << 8;
2244 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
2245 u32BerValue |= u8Data << 16;
2246 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
2247 u32BerValue |= u8Data << 24;
2248
2249 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
2250 u16BerPeriod = u8Data;
2251 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
2252 u16BerPeriod |= u8Data << 8;
2253 }
2254 else if (eLayerIndex == E_ISDBT_Layer_C)
2255 {
2256 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
2257 u32BerValue = u8Data;
2258 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
2259 u32BerValue |= u8Data << 8;
2260 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2261 u32BerValue |= u8Data << 16;
2262 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
2263 u32BerValue |= u8Data << 24;
2264
2265 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
2266 u16BerPeriod = u8Data;
2267 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
2268 u16BerPeriod |= u8Data << 8;
2269 }
2270 else
2271 {
2272 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2273 bRet = FALSE;
2274 }
2275
2276 // reg_rd_freezeber
2277 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2278
2279 if(u16BerPeriod == 0) u16BerPeriod = 1;
2280
2281 #ifdef UTPA2
2282 *pBerPeriod = u16BerPeriod;
2283 *pBerValue = u32BerValue;
2284 #else
2285 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
2286 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
2287 #endif
2288 return bRet;
2289 }
2290
2291 #ifndef UTPA2
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)2292 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
2293 {
2294 float fber;
2295 MS_BOOL bRet = TRUE;
2296 EN_ISDBT_Layer eLayerIndex;
2297 MS_U16 u16SQI;
2298
2299 // Tmp solution
2300 eLayerIndex = E_ISDBT_Layer_A;
2301
2302 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2303 {
2304 //printf("Dan Demod unlock!!!\n");
2305 u16SQI = 0;
2306 }
2307 else
2308 {
2309 // Part 1: get ber value from demod.
2310 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2311
2312 u16SQI = _CALCULATE_SQI(fber);
2313 }
2314
2315 //printf("dan SQI = %d\n", SQI);
2316 return u16SQI;
2317 }
2318
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)2319 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
2320 {
2321 float fber;
2322 MS_BOOL bRet = TRUE;
2323 EN_ISDBT_Layer eLayerIndex;
2324 MS_U16 u16SQI;
2325
2326 // Tmp solution
2327 eLayerIndex = E_ISDBT_Layer_B;
2328
2329 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2330 {
2331 //printf("Dan Demod unlock!!!\n");
2332 u16SQI = 0;
2333 }
2334 else
2335 {
2336 // Part 1: get ber value from demod.
2337 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2338
2339 u16SQI = _CALCULATE_SQI(fber);
2340 }
2341
2342 //printf("dan SQI = %d\n", SQI);
2343 return u16SQI;
2344 }
2345
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)2346 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
2347 {
2348 float fber;
2349 MS_BOOL bRet = TRUE;
2350 EN_ISDBT_Layer eLayerIndex;
2351 MS_U16 u16SQI;
2352
2353 // Tmp solution
2354 eLayerIndex = E_ISDBT_Layer_C;
2355
2356 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2357 {
2358 //printf("Dan Demod unlock!!!\n");
2359 u16SQI = 0;
2360 }
2361 else
2362 {
2363 // Part 1: get ber value from demod.
2364 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2365
2366 u16SQI = _CALCULATE_SQI(fber);
2367 }
2368
2369 //printf("dan SQI = %d\n", SQI);
2370 return u16SQI;
2371 }
2372
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)2373 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
2374 {
2375 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
2376 MS_U16 u16SQI;
2377 EN_ISDBT_Layer eLayerIndex;
2378 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
2379
2380 //Get modulation of each layer
2381 eLayerIndex = E_ISDBT_Layer_A;
2382 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
2383 eLayerIndex = E_ISDBT_Layer_B;
2384 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
2385 eLayerIndex = E_ISDBT_Layer_C;
2386 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
2387
2388 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
2389 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
2390 else
2391 s8LayerAValue = -1;
2392
2393 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
2394 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
2395 else
2396 s8LayerBValue = -1;
2397
2398 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
2399 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
2400 else
2401 s8LayerCValue = -1;
2402
2403 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
2404 if (s8LayerAValue >= s8LayerBValue)
2405 {
2406 if (s8LayerCValue >= s8LayerAValue)
2407 {
2408 //Get Layer C u16SQI
2409 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2410 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
2411 }
2412 else //A>C
2413 {
2414 //Get Layer A u16SQI
2415 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2416 //printf("dan u16SQI Layer A: %d\n", u16SQI);
2417 }
2418 }
2419 else // B >= A
2420 {
2421 if (s8LayerCValue >= s8LayerBValue)
2422 {
2423 //Get Layer C u16SQI
2424 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2425 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
2426 }
2427 else //B>C
2428 {
2429 //Get Layer B u16SQI
2430 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2431 //printf("dan u16SQI Layer B: %d\n", u16SQI);
2432 }
2433 }
2434
2435 return u16SQI;
2436 }
2437 #endif
2438
2439 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetSNR(MS_U32 * pRegSNR,MS_U16 * pRegSnrObsNum)2440 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(MS_U32 *pRegSNR, MS_U16 *pRegSnrObsNum)
2441 #else
2442 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
2443 #endif
2444 {
2445 MS_BOOL bRet = TRUE;
2446 MS_U8 u8Data = 0;
2447 MS_U32 u32RegSNR = 0;
2448 MS_U16 u16RegSnrObsNum = 0;
2449 #ifndef UTPA2
2450 float fSNRAvg = 0.0;
2451 #endif
2452
2453 //set freeze
2454 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2455 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2456 //load
2457 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2458 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2459
2460 // ==============Average SNR===============//
2461 // [26:0] reg_snr_accu
2462 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
2463 u32RegSNR = u8Data&0x07;
2464 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
2465 u32RegSNR = (u32RegSNR<<8) | u8Data;
2466 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
2467 u32RegSNR = (u32RegSNR<<8) | u8Data;
2468 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
2469 u32RegSNR = (u32RegSNR<<8) | u8Data;
2470
2471 // [12:0] reg_snr_observe_sum_num
2472 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
2473 u16RegSnrObsNum = u8Data&0x1f;
2474 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
2475 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
2476
2477 //release freeze
2478 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2479 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2480 //load
2481 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2482 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2483
2484 if (u16RegSnrObsNum == 0)
2485 u16RegSnrObsNum = 1;
2486
2487
2488 #ifdef UTPA2
2489 *pRegSNR = u32RegSNR;
2490 *pRegSnrObsNum = u16RegSnrObsNum;
2491 #else
2492 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
2493 if (fSNRAvg == 0) //protect value 0
2494 fSNRAvg = 0.01;
2495
2496 #ifdef MSOS_TYPE_LINUX
2497 *pf_snr = 10.0f*(float)log10f((double)fSNRAvg/2);
2498 #else
2499 *pf_snr = 10.0f*(float)Log10Approx((double)fSNRAvg/2);
2500 #endif
2501 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
2502 #endif
2503
2504 return bRet;
2505 }
2506
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)2507 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
2508 {
2509 MS_U8 bRet = true;
2510 MS_U8 u8Data = 0;
2511 MS_U8 u8FrzData = 0;
2512 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
2513 #if DMD_ISDBT_TBVA_EN
2514 MS_U8 bTbvaBypass = 0;
2515 MS_U8 u8TbvaLayer = 0;
2516 #endif
2517 // Read packet errors of three layers
2518 // OUTER_FUNCTION_ENABLE
2519 // [8] reg_biterr_num_pcktprd_freeze
2520 // Freeze Packet error
2521 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2522 u8Data = u8FrzData | 0x01;
2523 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2524 #if DMD_ISDBT_TBVA_EN
2525 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x10*2, &u8Data);
2526 bTbvaBypass = u8Data & 0x01;
2527 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x11*2, &u8Data);
2528 u8TbvaLayer = u8Data & 0x03;
2529 switch(eLayerIndex)
2530 {
2531 case E_ISDBT_Layer_A:
2532 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2533 if (!bTbvaBypass && u8TbvaLayer == 0)
2534 {
2535 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2536 u16PacketErrA = u8Data << 8;
2537 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2538 u16PacketErrA = u16PacketErrA | u8Data;
2539 *pu16PacketErr = u16PacketErrA;
2540 }
2541 else
2542 {
2543 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2544 u16PacketErrA = u8Data << 8;
2545 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2546 u16PacketErrA = u16PacketErrA | u8Data;
2547 *pu16PacketErr = u16PacketErrA;
2548 }
2549 break;
2550 case E_ISDBT_Layer_B:
2551 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2552 if (!bTbvaBypass && u8TbvaLayer == 1)
2553 {
2554 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2555 u16PacketErrB = u8Data << 8;
2556 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2557 u16PacketErrB = u16PacketErrB | u8Data;
2558 *pu16PacketErr = u16PacketErrB;
2559 }
2560 else
2561 {
2562 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2563 u16PacketErrB = u8Data << 8;
2564 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2565 u16PacketErrB = u16PacketErrB | u8Data;
2566 *pu16PacketErr = u16PacketErrB;
2567 }
2568 break;
2569 case E_ISDBT_Layer_C:
2570 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2571 if (!bTbvaBypass && u8TbvaLayer == 2)
2572 {
2573 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2574 u16PacketErrC = u8Data << 8;
2575 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2576 u16PacketErrC = u16PacketErrC | u8Data;
2577 *pu16PacketErr = u16PacketErrC;
2578 }
2579 else
2580 {
2581 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2582 u16PacketErrC = u8Data << 8;
2583 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2584 u16PacketErrC = u16PacketErrC | u8Data;
2585 *pu16PacketErr = u16PacketErrC;
2586 }
2587 break;
2588 default:
2589 *pu16PacketErr = 0xFFFF;
2590 break;
2591 }
2592 #else
2593 switch(eLayerIndex)
2594 {
2595 case E_ISDBT_Layer_A:
2596 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2597 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2598 u16PacketErrA = u8Data << 8;
2599 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2600 u16PacketErrA = u16PacketErrA | u8Data;
2601 *pu16PacketErr = u16PacketErrA;
2602 break;
2603 case E_ISDBT_Layer_B:
2604 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2605 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2606 u16PacketErrB = u8Data << 8;
2607 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2608 u16PacketErrB = u16PacketErrB | u8Data;
2609 *pu16PacketErr = u16PacketErrB;
2610 break;
2611 case E_ISDBT_Layer_C:
2612 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2613 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2614 u16PacketErrC = u8Data << 8;
2615 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2616 u16PacketErrC = u16PacketErrC | u8Data;
2617 *pu16PacketErr = u16PacketErrC;
2618 break;
2619 default:
2620 *pu16PacketErr = 0xFFFF;
2621 break;
2622 }
2623 #endif
2624 // Unfreeze Packet error
2625 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2626
2627 return bRet;
2628 }
2629
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2630 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2631 {
2632 return _MBX_ReadReg(u16Addr, pu8Data);
2633 }
2634
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2635 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2636 {
2637 return _MBX_WriteReg(u16Addr, u8Data);
2638 }
2639
2640 //-------------------------------------------------------------------------------------------------
2641 // Global Functions
2642 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)2643 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
2644 {
2645 MS_BOOL bResult = TRUE;
2646
2647 switch(eCmd)
2648 {
2649 case DMD_ISDBT_HAL_CMD_Exit:
2650 bResult = _HAL_INTERN_ISDBT_Exit();
2651 break;
2652 case DMD_ISDBT_HAL_CMD_InitClk:
2653 _HAL_INTERN_ISDBT_InitClk();
2654 break;
2655 case DMD_ISDBT_HAL_CMD_Download:
2656 bResult = _HAL_INTERN_ISDBT_Download();
2657 break;
2658 case DMD_ISDBT_HAL_CMD_FWVERSION:
2659 _HAL_INTERN_ISDBT_FWVERSION();
2660 break;
2661 case DMD_ISDBT_HAL_CMD_SoftReset:
2662 bResult = _HAL_INTERN_ISDBT_SoftReset();
2663 break;
2664 case DMD_ISDBT_HAL_CMD_SetACICoef:
2665 bResult = _HAL_INTERN_ISDBT_SetACICoef();
2666 break;
2667 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
2668 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
2669 break;
2670 case DMD_ISDBT_HAL_CMD_SetModeClean:
2671 bResult = _HAL_INTERN_ISDBT_SetModeClean();
2672 break;
2673 case DMD_ISDBT_HAL_CMD_Active:
2674 break;
2675 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
2676 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
2677 break;
2678 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
2679 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
2680 break;
2681 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
2682 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
2683 break;
2684 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
2685 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
2686 break;
2687 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
2688 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
2689 break;
2690 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
2691 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
2692 break;
2693 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
2694 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
2695 break;
2696 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
2697 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
2698 break;
2699 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
2700 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
2701 break;
2702 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
2703 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
2704 break;
2705 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
2706 #ifdef UTPA2
2707 bResult = _HAL_INTERN_ISDBT_GetFreqOffset(&((*((DMD_ISDBT_CFO_DATA*)pArgs)).FFT_Mode), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).TdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).FdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).IcfoRegValue));
2708 #else
2709 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
2710 #endif
2711 break;
2712 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
2713 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
2714 #ifndef UTPA2
2715 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2716 #endif
2717 break;
2718 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
2719 #ifndef UTPA2
2720 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2721 #endif
2722 break;
2723 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
2724 #ifndef UTPA2
2725 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2726 #endif
2727 break;
2728 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
2729 #ifndef UTPA2
2730 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
2731 #endif
2732 break;
2733 case DMD_ISDBT_HAL_CMD_GetSNR:
2734 #ifdef UTPA2
2735 bResult = _HAL_INTERN_ISDBT_GetSNR(&((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSNR), &((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSnrObsNum));
2736 #else
2737 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
2738 #endif
2739 break;
2740 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
2741 #ifdef UTPA2
2742 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2743 #else
2744 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2745 #endif
2746 break;
2747 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
2748 #ifdef UTPA2
2749 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2750 #else
2751 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2752 #endif
2753 break;
2754 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
2755 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
2756 break;
2757 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
2758 break;
2759 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
2760 break;
2761 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
2762 break;
2763 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
2764 break;
2765 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
2766 break;
2767 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
2768 break;
2769 case DMD_ISDBT_HAL_CMD_GET_REG:
2770 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
2771 break;
2772 case DMD_ISDBT_HAL_CMD_SET_REG:
2773 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
2774 break;
2775 default:
2776 break;
2777 }
2778
2779 return bResult;
2780 }
2781
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)2782 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
2783 {
2784 return TRUE;
2785 }
2786
2787