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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT2.c
98 /// @brief INTERN_DVBT2 DVBT2
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT2_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 //#include "BinInfo.h"
114 #include "drvDMD_VD_MBX.h"
115 #include "drvDMD_INTERN_DVBT2.h"
116 #include "halDMD_INTERN_DVBT2.h"
117 #include "halDMD_INTERN_common.h"
118
119 extern void *memcpy(void *destination, const void *source, size_t num);
120
121 #define TEST_EMBEDED_DEMOD 0
122 //U8 load_data_variable=1;
123 //-----------------------------------------------------------------------
124 #define BIN_ID_INTERN_DVBT2_DEMOD BIN_ID_INTERN_DVBT
125
126 #define TDE_REG_BASE 0x2400
127 #define DIV_REG_BASE 0x2500
128 #define TR_REG_BASE 0x2600
129 #define FTN_REG_BASE 0x2700
130 #define FTNEXT_REG_BASE 0x2800
131
132
133
134 #if 0//ENABLE_SCAN_ONELINE_MSG
135 #define DBG_INTERN_DVBT2_ONELINE(x) x
136 #else
137 #define DBG_INTERN_DVBT2_ONELINE(x) // x
138 #endif
139
140 #ifdef MS_DEBUG
141 #define DBG_INTERN_DVBT2(x) x
142 #define DBG_GET_SIGNAL(x) x
143 #define DBG_INTERN_DVBT2_TIME(x) x
144 #define DBG_INTERN_DVBT2_LOCK(x) x
145 #else
146 #define DBG_INTERN_DVBT2(x) //x
147 #define DBG_GET_SIGNAL(x) //x
148 #define DBG_INTERN_DVBT2_TIME(x) // x
149 #define DBG_INTERN_DVBT2_LOCK(x) //x
150 #endif
151 #define DBG_DUMP_LOAD_DSP_TIME 0
152
153 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0
154 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1
155 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1
156 #define INTERN_DVBT2_INTERNAL_DEBUG 1
157
158 #define SIGNAL_LEVEL_OFFSET 0.00
159 #define TAKEOVERPOINT -59.0
160 #define TAKEOVERRANGE 0.5
161 #define LOG10_OFFSET -0.21
162 #define INTERN_DVBT2_USE_SAR_3_ENABLE 0
163 #define INTERN_DVBT2_GET_TIME msAPI_Timer_GetTime0()
164 #define AUTO_TS_DATA_RATE 1
165
166 #if(AUTO_TS_DATA_RATE)
167 #define TS_DATA_RATE_RATIO 1.01
168 #define DBG_AUTO_TS_DATA_RATE(x)
169 #endif
170
171 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
172 #define TUNER_VPP 2
173 #define IF_AGC_VPP 2
174 #else
175 #define TUNER_VPP 1
176 #define IF_AGC_VPP 2
177 #endif
178
179 #if (TUNER_VPP == 1)
180 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
181 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
182 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
183 #endif
184
185 /*BEG INTERN_DVBT2_DSPREG_TABLE*/
186 #define DVBT2_FS 24000
187
188 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
189 #define T2_BW_VAL 0x04
190 // FC: FC = FS = 5000 = 0x1388 (5.0MHz IF)
191 #define T2_FC_L_VAL 0x88 // 5.0M
192 #define T2_FC_H_VAL 0x13
193 #define T2_TS_SERIAL_VAL 0x00
194 #define T2_TS_CLK_RATE_VAL 0x06
195 #define T2_TS_OUT_INV_VAL 0x00
196 #define T2_TS_DATA_SWAP_VAL 0x00
197 #define T2_IF_AGC_INV_PWM_EN_VAL 0x00
198 #define T2_LITE_VAL 0x00
199 #define T2_AGC_REF_VAL 0x40
200
201 #define DVBT2_BER_TH_HY 0.1
202
203 /*END INTERN_DVBT2_DSPREG_TABLE*/
204 //-----------------------------------------------------------------------
205 /****************************************************************
206 *Local Variables *
207 ****************************************************************/
208 static MS_BOOL bFECLock=0;
209 static MS_BOOL bP1Lock = 0;
210 static MS_U32 u32ChkScanTimeStart = 0;
211 static MS_U32 u32FecFirstLockTime=0;
212 static MS_U32 u32FecLastLockTime=0;
213 static float fLDPCBerFiltered=-1;
214 static float fBerFilteredDVBT2 = -1.0;
215
216 //Global Variables
217 S_CMDPKTREG gsCmdPacket;
218 //U8 gCalIdacCh0, gCalIdacCh1;
219 extern MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
220 extern MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
221 extern MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
222 extern MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
223 extern MS_U32 u32DMD_DVBT2_FW_START_ADDR;
224
225 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
226 MS_U8 INTERN_DVBT2_table[] = {
227 #include "fwDMD_INTERN_DVBT2.dat"
228 };
229
230 #endif
231 /*
232 static DMD_T2_SSI_DBM_NORDIGP1 dvbt2_ssi_dbm_nordigp1[] =
233 {
234 {_T2_QPSK, _T2_CR1Y2, -95.7},
235 {_T2_QPSK, _T2_CR3Y5, -94.4},
236 {_T2_QPSK, _T2_CR2Y3, -93.6},
237 {_T2_QPSK, _T2_CR3Y4, -92.6},
238 {_T2_QPSK, _T2_CR4Y5, -92.0},
239 {_T2_QPSK, _T2_CR5Y6, -91.5},
240
241 {_T2_16QAM, _T2_CR1Y2, -90.8},
242 {_T2_16QAM, _T2_CR3Y5, -89.1},
243 {_T2_16QAM, _T2_CR2Y3, -87.9},
244 {_T2_16QAM, _T2_CR3Y4, -86.7},
245 {_T2_16QAM, _T2_CR4Y5, -85.8},
246 {_T2_16QAM, _T2_CR5Y6, -85.2},
247
248 {_T2_64QAM, _T2_CR1Y2, -86.9},
249 {_T2_64QAM, _T2_CR3Y5, -84.6},
250 {_T2_64QAM, _T2_CR2Y3, -83.2},
251 {_T2_64QAM, _T2_CR3Y4, -81.4},
252 {_T2_64QAM, _T2_CR4Y5, -80.3},
253 {_T2_64QAM, _T2_CR5Y6, -79.7},
254
255 {_T2_256QAM, _T2_CR1Y2, -83.5},
256 {_T2_256QAM, _T2_CR3Y5, -80.4},
257 {_T2_256QAM, _T2_CR2Y3, -78.6},
258 {_T2_256QAM, _T2_CR3Y4, -76.0},
259 {_T2_256QAM, _T2_CR4Y5, -74.4},
260 {_T2_256QAM, _T2_CR5Y6, -73.3},
261 {_T2_QAM_UNKNOWN, _T2_CR_UNKNOWN, 0.0}
262 };
263 */
264 static float dvbt2_ssi_dbm_nordigp1[][6] =
265 {
266 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
267 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
268 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
269 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
270 };
271
272 // cr, 3/5(1), 2/3(2), 3/4 (3)
273 float fT2_SSI_formula[][12]=
274 {
275 {1.0/5, 97.0, 3.0/2, 82.0, 16.0/5, 50.0, 29.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/5
276 {2.0/3, 95.0, 9.0/5, 77.0, 17.0/5, 43.0, 14.0/5.0, 15.0, 13.0/15, 2.0, 2.0/5, 0.0}, // CR2/3
277 {1.0/2, 93.0, 19.0/10, 74.0, 31.0/10, 43.0, 22.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/4
278 };
279 static void INTERN_DVBT2_SignalQualityReset(void);
280 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void);
281
282 #if (AUTO_TS_DATA_RATE)
283 MS_BOOL INTERN_DVBT2_GetTsDivNum(MS_U8* u8TSDivNum);
284 #endif
285
INTERN_DVBT2_SignalQualityReset(void)286 static void INTERN_DVBT2_SignalQualityReset(void)
287 {
288 u32FecFirstLockTime=0;
289 fLDPCBerFiltered=-1;
290 }
291
INTERN_DVBT2_DSPReg_Init(const MS_U8 * u8DVBT2_DSPReg,MS_U8 u8Size)292 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT2_DSPReg, MS_U8 u8Size)
293 {
294 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
295 MS_BOOL status = TRUE;
296 MS_U16 u16DspAddr = 0;
297
298 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_DSPReg_Init\n"));
299
300 //for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
301 // status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
302 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_BW, T2_BW_VAL) != TRUE)
303 {
304 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
305 }
306 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_L, T2_FC_L_VAL) != TRUE)
307 {
308 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
309 }
310 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_H, T2_FC_H_VAL) != TRUE)
311 {
312 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
313 }
314 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_SERIAL, T2_TS_SERIAL_VAL) != TRUE)
315 {
316 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
317 }
318 //if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_CLK_RATE, T2_TS_CLK_RATE_VAL) != TRUE)
319 //{
320 // printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
321 //}
322 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_OUT_INV, T2_TS_OUT_INV_VAL) != TRUE)
323 {
324 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
325 }
326 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_SWAP, T2_TS_DATA_SWAP_VAL) != TRUE)
327 {
328 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
329 }
330 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_IF_AGC_INV_PWM_EN, T2_IF_AGC_INV_PWM_EN_VAL) != TRUE)
331 {
332 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
333 }
334 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_LITE, T2_LITE_VAL) != TRUE)
335 {
336 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
337 }
338
339 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_AGC_REF, T2_AGC_REF_VAL) != TRUE) //brown:0x40->agc_ref
340 {
341 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
342 }
343
344 if (u8DVBT2_DSPReg != NULL)
345 {
346 /*temp solution until new dsp table applied.*/
347 // if (INTERN_DVBT2_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
348 if (u8DVBT2_DSPReg[0] >= 1)
349 {
350 u8DVBT2_DSPReg+=2;
351 for (idx = 0; idx<u8Size; idx++)
352 {
353 u16DspAddr = *u8DVBT2_DSPReg;
354 u8DVBT2_DSPReg++;
355 u16DspAddr = (u16DspAddr) + ((*u8DVBT2_DSPReg)<<8);
356 u8DVBT2_DSPReg++;
357 u8Mask = *u8DVBT2_DSPReg;
358 u8DVBT2_DSPReg++;
359 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
360 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT2_DSPReg) & (u8Mask));
361 u8DVBT2_DSPReg++;
362 DBG_INTERN_DVBT2(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
363 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
364 }
365 }
366 else
367 {
368 printf("FATAL: parameter version incorrect\n");
369 }
370 }
371
372 return status;
373 }
374
375 /***********************************************************************************
376 Subject: SoftStop
377 Function: INTERN_DVBT2_SoftStop
378 Parmeter:
379 Return: MS_BOOL
380 Remark:
381 ************************************************************************************/
382
INTERN_DVBT2_SoftStop(void)383 MS_BOOL INTERN_DVBT2_SoftStop ( void )
384 {
385 MS_U16 u8WaitCnt=0;
386 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
387 {
388 printf(">> MB Busy!\n");
389 return FALSE;
390 }
391
392 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
393
394 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
395 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
396
397 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
398 {
399 if (u8WaitCnt++ >= 0xFFF)
400 {
401 printf(">> DVBT2 SoftStop Fail!\n");
402 return FALSE;
403 }
404 }
405
406 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
407 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
408 return TRUE;
409 }
410
INTERN_DVBT2_SoftReset(void)411 MS_BOOL INTERN_DVBT2_SoftReset ( void )
412 {
413 MS_BOOL bRet=TRUE;
414 //MS_U8 u8Data, fdp_fifo_done, djb_fifo_done, tdi_fifo_done;
415 MS_U8 u8Data = 0, fdp_fifo_done = 0, tdi_fifo_done = 0;
416 MS_U8 u8_timeout = 0;
417
418 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_SoftReset\n"));
419
420 //stop FSM_EN
421 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN
422
423 MsOS_DelayTask(5);
424
425 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
426 DBG_INTERN_DVBT2(printf("@@@TOP_RESET:0x%x\n", u8Data));
427 // MIU hold function
428 if((u8Data & 0x20) == 0x00)
429 {
430 // mask miu service with fdp, djb, tdi
431 //fdp 0x17 [12] reg_fdp_fifo_stop=1'b1
432 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
433 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10));
434 // [8] reg_fdp_load, fdp register dynamic change protection, 1->load register
435 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10);
436 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
437 //printf("@@@@@@ DVBT2 [reg_fdp_fifo_stop]=0x%x\n", u8Data);
438 //djb 0x65 [0] reg_stop_mu_request
439 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
440 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01));
441 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
442 //printf("@@@@@@ DVBT2 [reg_stop_mu_request]=0x%x\n", u8Data);
443 //snr 0x23 [8] reg_tdi_miu_off
444 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01));
446 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
447 //printf("@@@@@@ DVBT2 [reg_tdi_miu_off]=0x%x\n", u8Data);
448 // ---------------------------------------------
449 // Wait MIU mask or timeout!
450 // DVBT2_TIMER_INT[ 7:0] : indicator of the selected Timer's max count(15:8) (r)
451 // DVBT2_TIMER_INT[11:8] : timer3~timer0 interrupt (r)
452 // ---------------------------------------------
453 //fdp 0x18 [2] reg_fdp_fifo_req_done
454 //djb 0x65 [8] reg_miu_req_terminate_done
455 //tdi 0x23 [9] reg_tdi_miu_off_done
456 do
457 {
458 // Wait MIU mask done or timeout!
459 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data);
460 fdp_fifo_done = u8Data & 0x04;
461 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2)+1, &u8Data);
462 //djb_fifo_done = u8Data & 0x01;
463 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
464 tdi_fifo_done = u8Data & 0x02;
465
466 u8_timeout++;
467 }
468 //while(((fdp_fifo_done != 0x04)||(djb_fifo_done != 0x01)||(tdi_fifo_done != 0x02))
469 while(((fdp_fifo_done != 0x04)||(tdi_fifo_done != 0x02))
470 && u8_timeout != 0x7f);
471
472 //printf(">> DVBT2 fdp_fifo_done=%d, djb_fifo_done=%d, tdi_fifo_done=%d \n", fdp_fifo_done, djb_fifo_done, tdi_fifo_done);
473 printf(">> DVBT2 [fdp_fifo_done]=%d, [tdi_fifo_done]=%d \n", fdp_fifo_done, tdi_fifo_done);
474
475 MsOS_DelayTask(2);
476
477 if(u8_timeout == 0x7f)
478 {
479 printf(">> DVBT2 MIU hold function Fail!\n");
480 //return FALSE;
481 }
482 else
483 {
484 printf(">> DVBT2 MIU hold function done!!\n");
485 }
486 }
487 else
488 printf(">> No need DVBT2 MIU hold function!!\n");
489
490 // demod_top reset
491 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
492 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data|0x20));
493
494 MsOS_DelayTask(1);
495
496 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data&(~0x20)));
497
498 DBG_INTERN_DVBT2(printf("@INTERN_DVBT2_SoftReset done!!\n"));
499
500 return bRet;
501 }
502
503
504 /***********************************************************************************
505 Subject: Reset
506 Function: INTERN_DVBT2_Reset
507 Parmeter:
508 Return: MS_BOOL
509 Remark:
510 ************************************************************************************/
511 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT2_Reset(void)512 MS_BOOL INTERN_DVBT2_Reset ( void )
513 {
514 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_reset\n"));
515
516 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Reset, t = %ld\n",MsOS_GetSystemTime()));
517
518 //INTERN_DVBT2_SoftStop();
519
520
521 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
522 MsOS_DelayTask(5);
523 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
524
525 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
526 MsOS_DelayTask(5);
527
528 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
529 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
530
531 bFECLock = FALSE;
532 bP1Lock = FALSE;
533 u32ChkScanTimeStart = MsOS_GetSystemTime();
534 return TRUE;
535 }
536
537 /***********************************************************************************
538 Subject: Exit
539 Function: INTERN_DVBT2_Exit
540 Parmeter:
541 Return: MS_BOOL
542 Remark:
543 ************************************************************************************/
INTERN_DVBT2_Exit(void)544 MS_BOOL INTERN_DVBT2_Exit ( void )
545 {
546 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_Exit\n"));
547
548 INTERN_DVBT2_SoftStop();
549
550
551 //diable clk gen
552 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
553 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
554 /*
555 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
556 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
557
558 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
559 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
560
561 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
562 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
563
564 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
565 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
566
567 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
568 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
569
570 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
571 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
572
573 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
574 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
575
576 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
577 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
578
579 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
580 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
581
582 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
583 */
584 return TRUE;
585 }
586 /*
587 MS_BOOL INTERN_DVBT2_Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length)
588 {
589
590 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Load2Sdram, len=0x%x, \n",data_length));
591 MS_U8 addrhi, addrlo;
592 int i, j, k, old_i=0;
593 int sdram_start_addr = 0;//1024 >> 2; //StrToInt(ed_sdram_start->Text)>>2; // 4KB alignment
594
595 //I2C_CH_Exit(); // exit CH4
596 //I2C_CH5_Reset(); // switch to CH5
597 //MDrv_DMD_I2C_Channel_Change(5);
598 //--------------------------------------------------------------------------
599 // Set xData map for DRAM
600 //--------------------------------------------------------------------------
601
602 //banknum = 0x1d; //dmdmcu51_xdmiu
603
604 //set xData map upper and low bound for 64k DRAM window
605 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x2020);
606 if(SLAVE_I2CWrite16(banknum,0x63,0x2020)==false)
607 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
608
609 //set xData map offset for 64k DRAM window
610 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x64, 0x0000);
611 if(SLAVE_I2CWrite16(banknum,0x64,0x0000)==false)
612 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
613
614 //set xData map upper and low bound for 4k DRAM window
615 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x65, 0x2420);
616 if(SLAVE_I2CWrite16(banknum,0x65,0x2420)==false)
617 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
618
619 //set xData map offset for 4k DRAM window
620 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, sdram_start_addr);
621 if(SLAVE_I2CWrite16(banknum,0x66,sdram_start_addr)==false)
622 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
623
624 //I2C_CH_Exit(); // exit CH5
625 //EnterDebugMode(1); // switch to CH1
626
627 //enable xData map for DRAM
628 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x0007);
629 if(SLAVE_I2CWrite16(banknum,0x62,0x0007)==false)
630 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
631
632
633 for ( i = 0, j = SDRAM_BASE, k = sdram_start_addr + 0x01; i < size;)
634 {
635 if (j == SDRAM_BASE + 0x1000)
636 {
637 //I2C_CH_Exit(); // exit CH1
638 //I2C_CH5_Reset(); // switch to CH5
639 //set xData map offset for 4k DRAM window
640 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, k++);
641 if(SLAVE_I2CWrite16(banknum,0x66,k++)==false)
642 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
643 j = SDRAM_BASE;
644
645 //I2C_CH_Exit(); // exit CH5
646 //EnterDebugMode(1); // switch to CH1
647
648 }
649
650 addrhi = (j >> 8) & 0xff;
651 addrlo = j & 0xff;
652
653 if (i+EZUSB_Write_Buffer<size)
654 {
655 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,EZUSB_Write_Buffer)==FALSE)
656 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
657
658 j=j+EZUSB_Write_Buffer;
659 i=i+EZUSB_Write_Buffer;
660 }
661 else
662 {
663 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,size-i)==FALSE)
664 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
665
666 i=size;
667 }
668
669 if ((i-old_i)>=2048)
670 {
671 ShowMCUDL_Progress(0,3*i,size);
672 old_i=i;
673 }
674 }//end for
675
676
677 FWDLRichEdit->Lines->Add(">SDRAM Down Load OK!");
678
679 I2C_CH_Exit(); // exit CH1
680 I2C_CH5_Reset(); // switch to CH5
681
682 //--------------------------------------------------------------------------
683 // Release xData map for SDRAM
684 //--------------------------------------------------------------------------
685
686 if(SLAVE_I2CWrite16(banknum,0x62,0x0000)==false)
687 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
688
689 }
690 */
691 /***********************************************************************************
692 Subject: Load DSP code to chip
693 Function: INTERN_DVBT2_LoadDSPCode
694 Parmeter:
695 Return: MS_BOOL
696 Remark:
697 ************************************************************************************/
INTERN_DVBT2_LoadDSPCode(void)698 static MS_BOOL INTERN_DVBT2_LoadDSPCode(void)
699 {
700 MS_U8 u8data = 0x00;
701 MS_U16 i;
702 MS_U16 fail_cnt=0;
703 //MS_U16 u16AddressOffset;
704 MS_U32 u32VA_DramCodeAddr;
705
706 #if (DBG_DUMP_LOAD_DSP_TIME==1)
707 MS_U32 u32Time;
708 #endif
709
710
711 #ifndef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
712 BININFO BinInfo;
713 MS_BOOL bResult;
714 MS_U32 u32GEAddr;
715 MS_U8 Data;
716 MS_S8 op;
717 MS_U32 srcaddr;
718 MS_U32 len;
719 MS_U32 SizeBy4K;
720 MS_U16 u16Counter=0;
721 MS_U8 *pU8Data;
722 #endif
723
724 #if 0
725 if(HAL_DMD_RIU_ReadByte(0x101E3E))
726 {
727 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
728 return FALSE;
729 }
730 #endif
731
732 // MDrv_Sys_DisableWatchDog();
733
734
735 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
736 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
737 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
738 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
739 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
740 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
741
742 //// Load code thru VDMCU_IF ////
743 DBG_INTERN_DVBT2(printf(">Load Code...\n"));
744 //#ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
745 //for ( i = 0; i < sizeof(INTERN_DVBT2_table); i++)
746 //{
747 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
748 //}
749 if (sizeof(INTERN_DVBT2_table) < 0x8000)
750 {
751 printf("----->Bin file Size is not match...\n");
752 }
753 else
754 {
755 // load half code to SRAM
756 for ( i = 0; i < 0x8000; i++)
757 {
758 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
759 }
760 DBG_INTERN_DVBT2(printf(">Load SRAM code done...\n"));
761
762
763 if((u32DMD_DVBT2_FW_START_ADDR & 0x8000) != 0x8000)
764 {
765 printf(">DVB-T2 DRAM Start address is not correct!!\n");
766 }
767 else
768 {
769 // load another half code to SDRAM
770 // VA = MsOS_PA2KSEG1(PA); //NonCache
771 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
772 u32VA_DramCodeAddr = MsOS_PA2KSEG1(u32DMD_DVBT2_FW_START_ADDR);
773 memcpy((void*)(MS_VIRT)u32VA_DramCodeAddr, &INTERN_DVBT2_table[0x8000], sizeof(INTERN_DVBT2_table) - 0x8000);
774
775 DBG_INTERN_DVBT2(printf(">Load DRAM code done...\n"));
776 }
777 }
778
779 //#endif
780
781 //// Content verification ////
782 DBG_INTERN_DVBT2(printf(">Verify Code...\n"));
783
784 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
785 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
786
787 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
788 for ( i = 0; i < 0x8000; i++)
789 {
790 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
791 if (u8data != INTERN_DVBT2_table[i])
792 {
793 printf(">fail add = 0x%x\n", i);
794 printf(">code = 0x%x\n", INTERN_DVBT2_table[i]);
795 printf(">data = 0x%x\n", u8data);
796
797 if (fail_cnt++ > 10)
798 {
799 printf(">DVB-T2 DSP SRAM Loadcode fail!\n");
800 return false;
801 }
802 }
803 }
804 #else
805 for (i=0;i<=SizeBy4K;i++)
806 {
807 if(i==SizeBy4K)
808 len=BinInfo.B_Len%0x1000;
809 else
810 len=0x1000;
811
812 srcaddr = u32GEAddr+(0x1000*i);
813 //printf("\t i = %08LX\n", i);
814 //printf("\t len = %08LX\n", len);
815 op = 1;
816 u16Counter = 0 ;
817 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
818 while(len--)
819 {
820 u16Counter ++ ;
821 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
822 //pU8Data = (U8 *)(srcaddr|0x80000000);
823 #if OBA2
824 pU8Data = (U8 *)(srcaddr);
825 #else
826 pU8Data = (U8 *)(srcaddr|0x80000000);
827 #endif
828 Data = *pU8Data;
829
830 #if 0
831 if(u16Counter < 0x100)
832 printf("0x%bx,", Data);
833 #endif
834 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
835 if (u8data != Data)
836 {
837 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
838 printf(">code = 0x%x\n", Data);
839 printf(">data = 0x%x\n", u8data);
840
841 if (fail_cnt++ > 10)
842 {
843 printf(">DVB-T DSP Loadcode fail!");
844 return false;
845 }
846 }
847
848 srcaddr += op;
849 }
850 // printf("\n\n\n");
851 }
852 #endif
853
854 // add T2 DRAM bufer start address into fixed location
855 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
856 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
857
858 // write Start address to VD MCU 51 code sram
859 // //0x30~0x33
860 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR);
861 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 8));
862 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 16));
863 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 24));
864 //0x30~0x33
865 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_EQ_START_ADDR);
866 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 8));
867 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 16));
868 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 24));
869 //0x34~0x37
870 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_TDI_START_ADDR);
871 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 8));
872 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 16));
873 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 24));
874 //0x38~0x3b
875 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_DJB_START_ADDR);
876 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 8));
877 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 16));
878 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 24));
879 //0x3c~0x3f
880 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_FW_START_ADDR);
881 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 8));
882 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 16));
883 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 24));
884
885 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR));
886 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR));
887 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR));
888 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
889
890 #if 0
891 // DEBUG
892 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
893 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
894
895 // for ( i = 0; i < 16; i++)
896 // {
897 // u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
898 // printf(">add = 0x%x\t", i);
899 // printf(">data = 0x%x\n", u8data);
900 // }
901
902 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR);
903 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR);
904 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR);
905 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR);
906 #endif
907
908 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
909 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
910 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
911 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
912
913 DBG_INTERN_DVBT2(printf(">DSP Loadcode done."));
914 //while(load_data_variable);
915
916 return TRUE;
917 }
918
919 /***********************************************************************************
920 Subject: DVB-T CLKGEN initialized function
921 Function: INTERN_DVBT2_Power_On_Initialization
922 Parmeter:
923 Return: MS_BOOL
924 Remark:
925 ************************************************************************************/
INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)926 void INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)
927 {
928 MS_U8 temp_val;
929 MS_U16 u16_temp_val;
930
931 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_InitClkgen\n"));
932
933 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
934 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
935 // ----------------------------------------------
936 // start demod CLKGEN setting
937 // ----------------------------------------------
938 // *** Set register at CLKGEN1
939 // enable DMD MCU clock "bit[0] set 0"
940 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
941 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
942 // CLK_DMDMCU clock setting
943 // [0] disable clock
944 // [1] invert clock
945 // [4:2]
946 // 000:170 MHz(MPLL_DIV_BUf)
947 // 001:160MHz
948 // 010:144MHz
949 // 011:123MHz
950 // 100:108MHz
951 // 101:mem_clcok
952 // 110:mem_clock div 2
953 // 111:select XTAL
954 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
955 // HAL_DMD_RIU_WriteByte(0x10331e,0x1c); // 24MHz
956 HAL_DMD_RIU_WriteByte(0x10331e,0x10); // 108MHz
957
958 // set parallet ts clock
959 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
960 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
961 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0615
962 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
963 temp_val|=0x05;
964 // temp_val|=0x07;
965 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
966
967 HAL_DMD_RIU_WriteByte(0x103300,0x10);
968
969 // enable DVBTC ts clock
970 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
971 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
972 HAL_DMD_RIU_WriteByte(0x103309,0x00);
973 HAL_DMD_RIU_WriteByte(0x103308,0x00);
974
975 // enable dvbc adc clock
976 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
977 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
978 HAL_DMD_RIU_WriteByte(0x103315,0x00);
979 HAL_DMD_RIU_WriteByte(0x103314,0x00);
980
981 // ----------------------------------------------
982 // start demod_0 CLKGEN setting
983 // ----------------------------------------------
984
985 // enable clk_atsc_adcd_sync
986 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
987 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
988 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
989 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
990
991 //reg_ckg_dvbt_inner
992 HAL_DMD_RIU_WriteByte(0x111f21,0x11);
993 HAL_DMD_RIU_WriteByte(0x111f20,0x10);
994
995 //reg_ckg_dvbt_outer
996 HAL_DMD_RIU_WriteByte(0x111f23,0x01);
997 HAL_DMD_RIU_WriteByte(0x111f22,0x11);
998
999 //reg_ckg_acifir
1000 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
1001
1002 //reg_ckg_dvbtm_sram_t1o2x_t22x
1003 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
1005
1006 //reg_ckg_dvbtm_sram_adc_t22x
1007 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
1008 HAL_DMD_RIU_WriteByte(0x111f2c,0x01);
1009
1010 //reg_ckg_dvbtm_sram_t12x_t24x
1011 HAL_DMD_RIU_WriteByte(0x111f2f,0x00);
1012 HAL_DMD_RIU_WriteByte(0x111f2e,0x00);
1013
1014 //reg_ckg_dvbtm_ts_in
1015 HAL_DMD_RIU_WriteByte(0x111f31,0x04);
1016 HAL_DMD_RIU_WriteByte(0x111f30,0x00);
1017
1018 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
1019 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
1020
1021 HAL_DMD_RIU_WriteByte(0x111f35,0x00);
1022 HAL_DMD_RIU_WriteByte(0x111f34,0x00);
1023
1024 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
1025 HAL_DMD_RIU_WriteByte(0x111f36,0x00);
1026
1027 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
1028 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
1029
1030 HAL_DMD_RIU_WriteByte(0x111f3d,0x00);
1031 HAL_DMD_RIU_WriteByte(0x111f3c,0x00);
1032
1033 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1034 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1035
1036 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1037 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1038
1039 HAL_DMD_RIU_WriteByte(0x111fe1,0x00);
1040 HAL_DMD_RIU_WriteByte(0x111fe0,0x00);
1041
1042 HAL_DMD_RIU_WriteByte(0x111fe3,0x00);
1043 HAL_DMD_RIU_WriteByte(0x111fe2,0x00);
1044
1045 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1046 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1047
1048 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1049 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1050
1051 HAL_DMD_RIU_WriteByte(0x111fe9,0x00);
1052 HAL_DMD_RIU_WriteByte(0x111fe8,0x00);
1053
1054 HAL_DMD_RIU_WriteByte(0x111feb,0xc8);
1055 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1056
1057 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1058 HAL_DMD_RIU_WriteByte(0x111fec,0x0c);
1059
1060 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1061 HAL_DMD_RIU_WriteByte(0x111fee,0x00);
1062
1063 // Maserati special
1064 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1065 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1066
1067 HAL_DMD_RIU_WriteByte(0x111ff0,0x00);
1068
1069 // Mulan special
1070 // TEQ CLK for DVBT2
1071 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1072
1073 // SRAM share
1074 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
1075 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
1076
1077 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1078 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1079
1080 HAL_DMD_RIU_WriteByte(0x111f79,0x00);
1081 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
1082
1083 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
1084 HAL_DMD_RIU_WriteByte(0x111f7a,0x00);
1085
1086 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1087 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1088
1089 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
1090 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
1091
1092 // 32+4K xdata sram
1093 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
1094 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1095 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
1096 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1097
1098 // SRAM allocation
1099 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1100 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1101
1102 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1103 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1104
1105 HAL_DMD_RIU_WriteByte(0x111703,0x00);
1106 HAL_DMD_RIU_WriteByte(0x111702,0x00);
1107
1108 HAL_DMD_RIU_WriteByte(0x111707,0x7f);
1109 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1110
1111 // SDRAM address offset
1112 u16_temp_val = (MS_U16)(u32DMD_DVBT2_FW_START_ADDR>>16);
1113 HAL_DMD_RIU_WriteByte(0x11171b,(MS_U8)(u16_temp_val>>8));
1114 HAL_DMD_RIU_WriteByte(0x11171a,(MS_U8)u16_temp_val);
1115
1116 // DRAM allocation
1117 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1118 HAL_DMD_RIU_WriteByte(0x111708,0x00);
1119
1120 HAL_DMD_RIU_WriteByte(0x11170d,0x80);
1121 HAL_DMD_RIU_WriteByte(0x11170c,0x00);
1122
1123 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1124 HAL_DMD_RIU_WriteByte(0x11170a,0x00);
1125
1126 HAL_DMD_RIU_WriteByte(0x11170f,0xff);
1127 HAL_DMD_RIU_WriteByte(0x11170e,0xff);
1128
1129 // DRAM EN
1130 HAL_DMD_RIU_WriteByte(0x111718,0x04);
1131
1132 // [0]switch dram address mode:
1133 // 0: address from dmdmcu51 bank (old mode)
1134 // 1: address from dmdmcu51_top bank (new mode)
1135 HAL_DMD_RIU_WriteByte(0x11171c,0x01);
1136
1137 // ----------------------------------------------
1138 // start demod CLKGEN setting
1139 // ----------------------------------------------
1140 // select DMD MCU
1141 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1142 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1143 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1144
1145 // stream2miu_en, activate rst_wadr
1146 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1147 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1148 // stream2miu_en, turn off rst_wadr
1149 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1150
1151 }
1152
1153 /***********************************************************************************
1154 Subject: Power on initialized function
1155 Function: INTERN_DVBT2_Power_On_Initialization
1156 Parmeter:
1157 Return: MS_BOOL
1158 Remark:
1159 ************************************************************************************/
1160
INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT2_DSPRegInitExt,MS_U8 u8DMD_DVBT2_DSPRegInitSize)1161 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT2_DSPRegInitExt, MS_U8 u8DMD_DVBT2_DSPRegInitSize)
1162 {
1163 MS_U16 status = true;
1164
1165 // MS_U8 temp_val;
1166 //MS_U8 cData = 0;
1167 //U8 cal_done;
1168 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Power_On_Initialization\n"));
1169
1170 #if defined(PWS_ENABLE)
1171 Mapi_PWS_Stop_VDMCU();
1172 #endif
1173 // No definition for Mulan
1174 #if 0
1175 // Global demod reset. To fix DVBS -> DVBT2 or DVBS blind scan -> DVBT2 unlock issue.
1176 temp_val=HAL_DMD_RIU_ReadByte(0x101e3a);
1177 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val|0x02);
1178
1179 MsOS_DelayTask(1);
1180
1181 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val&(~0x02));
1182 #endif
1183
1184 INTERN_DVBT2_InitClkgen(bRFAGCTristateEnable);
1185 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1186 //// Firmware download //////////
1187 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Load DSP...\n"));
1188 //MsOS_DelayTask(100);
1189
1190 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1191 {
1192 if (INTERN_DVBT2_LoadDSPCode() == FALSE)
1193 {
1194 printf("DVB-T2 Load DSP Code Fail\n");
1195 return FALSE;
1196 }
1197 else
1198 {
1199 DBG_INTERN_DVBT2(printf("DVB-T2 Load DSP Code OK\n"));
1200 }
1201 }
1202
1203
1204 //// MCU Reset //////////
1205 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Reset...\n"));
1206 if (INTERN_DVBT2_Reset() == FALSE)
1207 {
1208 DBG_INTERN_DVBT2(printf("Fail\n"));
1209 return FALSE;
1210 }
1211 else
1212 {
1213 DBG_INTERN_DVBT2(printf("OK\n"));
1214 }
1215
1216 // SRAM setting, DVB-T use it.
1217 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1218 //MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1219 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1220
1221 status &= INTERN_DVBT2_DSPReg_Init(u8DMD_DVBT2_DSPRegInitExt, u8DMD_DVBT2_DSPRegInitSize);
1222 return status;
1223 }
1224
1225 /************************************************************************************************
1226 Subject: Driving control
1227 Function: INTERN_DVBT2_Driving_Control
1228 Parmeter: bInversionEnable : TRUE For High
1229 Return: void
1230 Remark:
1231 *************************************************************************************************/
INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)1232 void INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)
1233 {
1234 MS_U8 u8Temp;
1235
1236 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1237
1238 if (bEnable)
1239 {
1240 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1241 }
1242 else
1243 {
1244 u8Temp = u8Temp & (~0x01);
1245 }
1246
1247 DBG_INTERN_DVBT2(printf("---> INTERN_DVBT2_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1248 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1249 }
1250 /************************************************************************************************
1251 Subject: Clk Inversion control
1252 Function: INTERN_DVBT2_Clk_Inversion_Control
1253 Parmeter: bInversionEnable : TRUE For Inversion Action
1254 Return: void
1255 Remark:
1256 *************************************************************************************************/
INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)1257 void INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1258 {
1259 MS_U8 u8Temp;
1260
1261 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1262
1263 if (bInversionEnable)
1264 {
1265 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1266 }
1267 else
1268 {
1269 u8Temp = u8Temp & (~0x02);
1270 }
1271
1272 DBG_INTERN_DVBT2(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1273 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1274 }
1275 /************************************************************************************************
1276 Subject: Transport stream serial/parallel control
1277 Function: INTERN_DVBT2_Serial_Control
1278 Parmeter: bEnable : TRUE For serial
1279 Return: MS_BOOL :
1280 Remark:
1281 *************************************************************************************************/
INTERN_DVBT2_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1282 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1283 {
1284 MS_U8 status = true;
1285 MS_U8 temp_val;
1286 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_ts... u8TSClk=%d\n",u8TSClk));
1287
1288 if (u8TSClk == 0xFF) u8TSClk=0x13;
1289 if (bEnable) //Serial mode for TS pad
1290 {
1291 // serial
1292 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1293 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1294
1295 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1296 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1297 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1298
1299 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1300 temp_val|=0x04;
1301 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1302 #else
1303 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1304 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1305 temp_val|=0x07;
1306 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1307 #endif
1308 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1309 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1310 }
1311 else
1312 {
1313 //parallel
1314 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1315 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1316
1317 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1318 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1319 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1320 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1321 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1322 temp_val|=0x05;
1323 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1324 #else
1325 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1326 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1327 temp_val|=0x07;
1328 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1329 #endif
1330
1331 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1332 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1333 }
1334
1335 //DBG_INTERN_DVBT2(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1336
1337 INTERN_DVBT2_Driving_Control(INTERN_DVBT2_DTV_DRIVING_LEVEL);
1338 return status;
1339 }
1340
1341 /************************************************************************************************
1342 Subject: TS1 output control
1343 Function: INTERN_DVBT2_PAD_TS1_Enable
1344 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1345 Return: void
1346 Remark:
1347 *************************************************************************************************/
INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)1348 void INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)
1349 {
1350 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_TS1_Enable... \n"));
1351
1352 if(flag) // PAD_TS1 Enable TS CLK PAD
1353 {
1354 //printf("=== TS1_Enable ===\n");
1355 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1356 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1357 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1358 }
1359 else // PAD_TS1 Disable TS CLK PAD
1360 {
1361 //printf("=== TS1_Disable ===\n");
1362 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1363 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1364 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1365 }
1366 }
1367
1368 /************************************************************************************************
1369 Subject: channel change config
1370 Function: INTERN_DVBT2_Config
1371 Parmeter: BW: bandwidth
1372 Return: MS_BOOL :
1373 Remark:
1374 *************************************************************************************************/
INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U8 u8PlpID)1375 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID)
1376 {
1377 MS_U8 bandwidth;
1378 MS_U8 status = true;
1379 //MS_U8 temp_val;
1380 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_config %d %d %d %ld %d\n", BW, bSerialTS, u8TSClk, u32IFFreq, u8PlpID));
1381 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Config, t = %ld\n",MsOS_GetSystemTime()));
1382
1383 if (u8TSClk == 0xFF) u8TSClk=0x13;
1384 switch(BW)
1385 {
1386 case E_DMD_T2_RF_BAND_5MHz:
1387 bandwidth = 1;
1388 break;
1389 case E_DMD_T2_RF_BAND_6MHz:
1390 bandwidth = 2;
1391 break;
1392 case E_DMD_T2_RF_BAND_7MHz:
1393 bandwidth = 3;
1394 break;
1395 case E_DMD_T2_RF_BAND_10MHz:
1396 bandwidth = 5;
1397 break;
1398 case E_DMD_T2_RF_BAND_1p7MHz:
1399 bandwidth = 0;
1400 break;
1401 case E_DMD_T2_RF_BAND_8MHz:
1402 default:
1403 bandwidth = 4;
1404 break;
1405 }
1406
1407 status &= INTERN_DVBT2_Reset();
1408
1409 // BW mode
1410 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_BW, BW);
1411 // TS mode
1412 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_T2_TS_SERIAL, bSerialTS? 0x01:0x00);
1413 // FC
1414 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_L, u32IFFreq&0xff);
1415 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_H, (u32IFFreq>>8)&0xff);
1416 // PLP_ID
1417 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
1418
1419 /*
1420 if(bSerialTS)
1421 {
1422 // serial
1423 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1424 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1425
1426 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1427 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1428 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1429 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1430 temp_val|=0x04;
1431 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1432 #else
1433 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1434 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1435 temp_val|=0x07;
1436 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1437 #endif
1438 }
1439 else
1440 {
1441 //parallel
1442 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1443 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1444
1445 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1446 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1447 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1448 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1449 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1450 temp_val|=0x05;
1451 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1452 #else
1453 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1454 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1455 temp_val|=0x07;
1456 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1457 #endif
1458 }
1459 */
1460 return status;
1461 }
1462 /************************************************************************************************
1463 Subject: enable hw to lock channel
1464 Function: INTERN_DVBT2_Active
1465 Parmeter: bEnable
1466 Return: MS_BOOL
1467 Remark:
1468 *************************************************************************************************/
INTERN_DVBT2_Active(MS_BOOL bEnable)1469 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable)
1470 {
1471 MS_U8 status = true;
1472
1473 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_active\n"));
1474
1475 //// INTERN_DVBT2 Finite State Machine on/off //////////
1476 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1477
1478 INTERN_DVBT2_SignalQualityReset();
1479
1480 //printf("++++++++++++++++++Active! While(1)+++++++++++++++++++++\n");
1481 //while(1);
1482
1483 return status;
1484 }
1485 /************************************************************************************************
1486 Subject: Return lock status
1487 Function: INTERN_DVBT2_Lock
1488 Parmeter: eStatus :
1489 Return: MS_BOOL
1490 Remark:
1491 *************************************************************************************************/
INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout,MS_U16 u16DMD_DVBT2_FEC_Timeout)1492 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout)
1493 {
1494 float fBER=0.0f;
1495 #if (AUTO_TS_DATA_RATE)
1496 MS_U8 u8TSDivNum =0;
1497 MS_U8 u8_tmp =0;
1498 #endif
1499
1500
1501 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK))
1502 {
1503 // copy from msb1240 >>>>>
1504 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1505 {
1506 if ((fBerFilteredDVBT2 <= 0.0) || ((fBerFilteredDVBT2/fBER) > 30.0 || (fBerFilteredDVBT2/fBER) < 0.03))
1507 fBerFilteredDVBT2 = fBER;
1508 else
1509 fBerFilteredDVBT2 = 0.9f*fBerFilteredDVBT2+0.1f*fBER;
1510 }
1511 // <<<<< copy from msb1240
1512
1513 if (bFECLock == FALSE)
1514 {
1515 u32FecFirstLockTime = MsOS_GetSystemTime();
1516 DBG_INTERN_DVBT2(printf("++++++++[utopia]dvbt2 lock\n"));
1517 }
1518
1519 #if (AUTO_TS_DATA_RATE) //check if TS DATA RATE change
1520 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_CHANGE_IND, &u8_tmp) == FALSE)
1521 {
1522 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1523 return FALSE;
1524 }
1525
1526 if (u8_tmp ==1)
1527 {
1528 INTERN_DVBT2_GetTsDivNum(&u8TSDivNum);
1529 DBG_INTERN_DVBT2(printf(">>>INTERN_DVBT2_GetLock TsClkDivNum = 0x%x<<<\n", u8TSDivNum));
1530 DBG_AUTO_TS_DATA_RATE(printf(">>>TS_DATA_RATE_CHANGE Detected: TsClkDivNum = 0x%x<<<\n", u8TSDivNum));
1531 // ** Caution: for TS parallel mode
1532 HAL_DMD_RIU_WriteByte(0x103300, u8TSDivNum);
1533 MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_RATE_CHANGE_IND,0x00);
1534 }
1535
1536 #endif
1537
1538 #if 0
1539 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1540 {
1541 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1542 {
1543 if(fLDPCBerFiltered <= 0.0)
1544 fLDPCBerFiltered = fBER;
1545 else
1546 fLDPCBerFiltered = 0.9f*fLDPCBerFiltered+0.1f*fBER;
1547 }
1548 DBG_INTERN_DVBT2(printf("[dvbt2]f_ber=%8.3e, g_ldpc_ber=%8.3e\n",fBER,fLDPCBerFiltered));
1549 }
1550 #endif
1551 u32FecLastLockTime = MsOS_GetSystemTime();
1552 bFECLock = TRUE;
1553 return E_DMD_T2_LOCK;
1554 }
1555 else
1556 {
1557 #if 0
1558 INTERN_DVBT2_SignalQualityReset();
1559 #endif
1560 if (bFECLock == TRUE)
1561 {
1562 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1563 {
1564 return E_DMD_T2_LOCK;
1565 }
1566 }
1567 bFECLock = FALSE;
1568 }
1569 /*
1570 #ifdef CHIP_KRITI
1571 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_NO_CHANNEL))
1572 {
1573 // DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- E_DMD_DVBT2_NO_CHANNEL \n"););
1574 return E_DMD_T2_UNLOCK;
1575 }
1576 #endif
1577 */
1578 if(!bP1Lock)
1579 {
1580 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_EVER_LOCK))
1581 {
1582 DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- P1Lock \n"));
1583 bP1Lock = TRUE;
1584 }
1585 }
1586 if(bP1Lock)
1587 {
1588 DBG_INTERN_DVBT2(printf("P1Lock %ld\n",MsOS_GetSystemTime()));
1589 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_FEC_Timeout)
1590 {
1591 return E_DMD_T2_CHECKING;
1592 }
1593 }
1594 else
1595 {
1596 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_P1_Timeout)
1597 {
1598 return E_DMD_T2_CHECKING;
1599 }
1600 }
1601 return E_DMD_T2_UNLOCK;
1602
1603 }
1604
1605
INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)1606 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)
1607 {
1608 MS_U16 u16Address = 0;
1609 MS_U8 cData = 0;
1610 MS_U8 cBitMask = 0;
1611 MS_U8 use_dsp_reg = 0;
1612
1613 switch( eStatus )
1614 {
1615 case E_DMD_DVBT2_FEC_LOCK:
1616 use_dsp_reg = 1;
1617 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //FEC lock,
1618 cBitMask = BIT(7);
1619 break;
1620
1621 case E_DMD_DVBT2_P1_LOCK:
1622 u16Address = 0x3082; //P1 HW Lock,
1623 cBitMask = BIT(3);
1624 break;
1625
1626 case E_DMD_DVBT2_DCR_LOCK:
1627 use_dsp_reg = 1;
1628 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //DCR Lock,
1629 cBitMask = BIT(2);
1630 break;
1631
1632 case E_DMD_DVBT2_AGC_LOCK:
1633 use_dsp_reg = 1;
1634 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //AGC Lock,
1635 cBitMask = BIT(0);
1636 break;
1637
1638 case E_DMD_DVBT2_MODE_DET:
1639 u16Address = 0x3082; //Mode CP Detect,
1640 cBitMask = BIT(1);
1641 break;
1642
1643 case E_DMD_DVBT2_P1_EVER_LOCK:
1644 use_dsp_reg = 1;
1645 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //P1 Ever Lock,
1646 cBitMask = BIT(5);
1647 break;
1648
1649 case E_DMD_DVBT2_L1_CRC_LOCK:
1650 u16Address = 0x2B41; //P1 Ever Lock,
1651 cBitMask = BIT(5)|BIT(6)|BIT(7);
1652 break;
1653
1654 case E_DMD_DVBT2_NO_CHANNEL:
1655 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1656 cBitMask = BIT(7);
1657 break;
1658
1659
1660 default:
1661 return FALSE;
1662 }
1663
1664 if (use_dsp_reg == 1)
1665 {
1666 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Address, &cData) == FALSE)
1667 {
1668 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1669 return FALSE;
1670 }
1671 }
1672 else
1673 {
1674 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1675 {
1676 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadReg fail \n"));
1677 return FALSE;
1678 }
1679 }
1680
1681 #ifdef MS_DEBUG
1682 MS_U8 u8tmp;
1683 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20c4, &u8tmp);
1684 DBG_INTERN_DVBT2(printf(">>>>>>>>>> DVBT2 State=%d \n", u8tmp));
1685 #endif
1686
1687 if ((cData & cBitMask) == cBitMask)
1688 {
1689 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is lock \n", eStatus));
1690 return TRUE;
1691 }
1692 else
1693 {
1694 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is unlock \n", eStatus));
1695 return FALSE;
1696 }
1697
1698 }
1699
1700 /****************************************************************************
1701 Subject: To get the Post LDPC BER
1702 Function: INTERN_DVBT2_GetPostLdpcBer
1703 Parmeter: Quility
1704 Return: E_RESULT_SUCCESS
1705 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1706 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1707 We will not read the Period, and have the "/256/8"
1708 *****************************************************************************/
INTERN_DVBT2_GetPostLdpcBer(float * ber)1709 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber)
1710 {
1711 MS_BOOL status = true;
1712 MS_U8 reg=0;
1713 MS_U16 BitErrPeriod;
1714 MS_U32 BitErr;
1715 MS_U16 FecType = 0;
1716
1717 /////////// Post-Viterbi BER /////////////
1718
1719 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1720 {
1721 *ber = (float)-1.0;
1722 return false;
1723 }
1724
1725 /////////// Data BER /////////////
1726 // bank 0x33 0x02 [0] freeze
1727 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1728
1729 // bank 0x33 0x12 Data BER Window[15:0]
1730 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1731 BitErrPeriod = reg;
1732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1733 BitErrPeriod = (BitErrPeriod << 8) | reg;
1734
1735 // bank 0x33 0x34 Data BER count[15:0]
1736 // bank 0x33 0x35 Data BER count[31:16]
1737 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1738 BitErr = reg;
1739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1740 BitErr = (BitErr << 8) | reg;
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1742 BitErr = (BitErr << 8) | reg;
1743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1744 BitErr = (BitErr << 8) | reg;
1745
1746 // bank 0x33 0x02 [0] freeze
1747 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1748
1749 if (BitErrPeriod == 0)
1750 //protect 0
1751 BitErrPeriod = 1;
1752
1753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1754 FecType = reg;
1755 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1756 FecType = (FecType << 8) | reg;
1757
1758 if (FecType & 0x0180)
1759 {
1760 if (BitErr == 0)
1761 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1762 else
1763 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1764 }
1765 else
1766 {
1767 if (BitErr == 0)
1768 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1769 else
1770 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1771 }
1772
1773 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1774
1775 if (status == FALSE)
1776 {
1777 printf("INTERN_DVBT2_GetPostLdpcBer Fail!\n");
1778 return FALSE;
1779 }
1780
1781 return status;
1782 }
1783
1784 /****************************************************************************
1785 Subject: To get the Pre LDPC BER
1786 Function: INTERN_DVBT2_GetPreLdpcBer
1787 Parmeter: ber
1788 Return: E_RESULT_SUCCESS
1789 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1790 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1791 We will not read the Period, and have the "/256/8"
1792 *****************************************************************************/
INTERN_DVBT2_GetPreLdpcBer(float * ber)1793 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber)
1794 {
1795 MS_U8 status = true;
1796 MS_U8 reg=0;
1797 MS_U16 BitErrPeriod;
1798 MS_U32 BitErr;
1799 MS_U16 FecType = 0;
1800
1801 /////////// Data BER /////////////
1802 // bank 0x33 0x02 [0] freeze
1803 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1804
1805 // bank 0x33 0x12 Data BER Window[15:0]
1806 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1807 BitErrPeriod = reg;
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1809 BitErrPeriod = (BitErrPeriod << 8) | reg;
1810
1811 // bank 0x33 0x34 Data BER count[15:0]
1812 // bank 0x33 0x35 Data BER count[31:16]
1813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1814 BitErr = reg;
1815 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1816 BitErr = (BitErr << 8) | reg;
1817 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1818 BitErr = (BitErr << 8) | reg;
1819 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1820 BitErr = (BitErr << 8) | reg;
1821
1822 // bank 0x33 0x02 [0] freeze
1823 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1824
1825 if (BitErrPeriod == 0)
1826 //protect 0
1827 BitErrPeriod = 1;
1828
1829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1830 FecType = reg;
1831 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1832 FecType = (FecType << 8) | reg;
1833
1834 if (FecType & 0x0180)
1835 {
1836 if (BitErr == 0)
1837 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1838 else
1839 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1840 }
1841 else
1842 {
1843 if (BitErr == 0)
1844 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1845 else
1846 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1847 }
1848
1849 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1850
1851 if (status == FALSE)
1852 {
1853 printf("INTERN_DVBT2_GetPreLdpcBer Fail!\n");
1854 return FALSE;
1855 }
1856
1857 return status;
1858 }
1859
1860 /****************************************************************************
1861 Subject: To get the Packet error
1862 Function: INTERN_DVBT2_GetPacketErr
1863 Parmeter: pktErr
1864 Return: E_RESULT_SUCCESS
1865 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1866 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1867 We will not read the Period, and have the "/256/8"
1868 *****************************************************************************/
INTERN_DVBT2_GetPacketErr(MS_U16 * u16PktErr)1869 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr)
1870 {
1871 MS_BOOL status = true;
1872 MS_U8 reg = 0;
1873 MS_U16 PktErr;
1874
1875 //freeze
1876 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01);
1877 //read packet error
1878 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5B, ®);
1879 PktErr = reg;
1880 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5A, ®);
1881 PktErr = (PktErr << 8) | reg;
1882
1883 *u16PktErr = PktErr;
1884 //release
1885 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00);
1886
1887 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PktErr = %d \n ", (int)PktErr));
1888
1889 *u16PktErr = PktErr;
1890
1891 return status;
1892 }
1893
1894 /****************************************************************************
1895 Subject: To get the DVBT2 parameter
1896 Function: INTERN_DVBT2_Get_L1_Info
1897 Parmeter: point to return parameter
1898 Return: TRUE
1899 FALSE
1900 Remark: The TPS parameters will be available after TPS lock
1901 *****************************************************************************/
INTERN_DVBT2_Get_L1_Parameter(MS_U16 * pu16L1_parameter,DMD_DVBT2_SIGNAL_INFO eSignalType)1902 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType)
1903 {
1904 MS_U8 u8Data = 0;
1905 MS_U16 FecType = 0;
1906 MS_U16 u16Data = 0;
1907 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
1908 {
1909 if (eSignalType == T2_MODUL_MODE)
1910 {
1911 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1912 return FALSE;
1913
1914 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(5) | BIT(4) | BIT(3))) >> 3;
1915 }
1916 else if (eSignalType == T2_FFT_VALUE)
1917 {
1918 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1919 {
1920 return FALSE;
1921 }
1922 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1923 }
1924 else if (eSignalType == T2_GUARD_INTERVAL)
1925 {
1926 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1927 {
1928 return FALSE;
1929 }
1930 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(6) | BIT(5) | BIT(4))) >> 4;
1931 }
1932 else if (eSignalType == T2_CODE_RATE)
1933 {
1934 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1935 {
1936 return FALSE;
1937 }
1938 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1939 }
1940 else if (eSignalType == T2_PREAMBLE)
1941 {
1942 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1943 {
1944 return FALSE;
1945 }
1946 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(4))) >> 4;
1947 }
1948 else if (eSignalType == T2_S1_SIGNALLING)
1949 {
1950 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1951 {
1952 return FALSE;
1953 }
1954 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(3) | BIT(2) | BIT(1))) >> 1;
1955 }
1956 else if (eSignalType == T2_PILOT_PATTERN)
1957 {
1958 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE)
1959 {
1960 return FALSE;
1961 }
1962 *pu16L1_parameter = (((MS_U16) u8Data) & 0x0F);
1963 }
1964 else if (eSignalType == T2_BW_EXT)
1965 {
1966 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1967 {
1968 return FALSE;
1969 }
1970 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(0)));
1971 }
1972 else if (eSignalType == T2_PAPR_REDUCTION)
1973 {
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2), &u8Data) == FALSE)
1975 {
1976 return FALSE;
1977 }
1978 *pu16L1_parameter = (((MS_U16) u8Data) & 0xF0) >> 4;
1979 }
1980 else if (eSignalType == T2_OFDM_SYMBOLS_PER_FRAME)
1981 {
1982 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2), &u8Data) == FALSE)
1983 {
1984 return FALSE;
1985 }
1986 *pu16L1_parameter = (MS_U16) u8Data;
1987 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2) + 1, &u8Data) == FALSE)
1988 {
1989 return FALSE;
1990 }
1991 *pu16L1_parameter |= (((MS_U16) u8Data) & 0x0F) << 8;
1992 }
1993 else if (eSignalType == T2_PLP_ROTATION)
1994 {
1995 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1996 {
1997 return FALSE;
1998 }
1999 *pu16L1_parameter = (((MS_U16) u8Data) & BIT(6)) >> 6;
2000 }
2001 else if (eSignalType == T2_PLP_FEC_TYPE)
2002 {
2003 //FEC Type[8:7]
2004 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8f, &u8Data) == FALSE) return FALSE;
2005 FecType = u8Data;
2006 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8e, &u8Data) == FALSE) return FALSE;
2007 FecType = (FecType << 8) | u8Data;
2008
2009 *pu16L1_parameter = (FecType & 0x0180) >> 7;
2010 }
2011 else if (eSignalType == T2_NUM_PLP)
2012 {
2013 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x42 * 2), &u8Data) == FALSE)
2014 {
2015 return FALSE;
2016 }
2017 *pu16L1_parameter = (MS_U16)u8Data;
2018 }
2019 else if (eSignalType == T2_PLP_TYPE)
2020 {
2021 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x45 * 2) + 1, &u8Data) == FALSE)
2022 {
2023 return FALSE;
2024 }
2025 *pu16L1_parameter = ((MS_U16) u8Data) & 0x07;
2026 }
2027 else if (eSignalType == T2_PLP_TIME_IL_TYPE)
2028 {
2029 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x48 * 2) + 1, &u8Data) == FALSE)
2030 {
2031 return FALSE;
2032 }
2033 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2034 }
2035 else if (eSignalType == T2_PLP_TIME_IL_LENGTH)
2036 {
2037 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x49 * 2) + 1, &u8Data) == FALSE)
2038 {
2039 return FALSE;
2040 }
2041 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2042 }
2043 else if (eSignalType == T2_DAT_ISSY)
2044 {
2045 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2046 {
2047 return FALSE;
2048 }
2049 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2050 }
2051 else if (eSignalType == T2_PLP_MODE)
2052 {
2053 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE)
2054 {
2055 return FALSE;
2056 }
2057 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE)
2058 {
2059 return FALSE;
2060 }
2061 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2062 {
2063 return FALSE;
2064 }
2065 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE)
2066 {
2067 return FALSE;
2068 }
2069 *pu16L1_parameter = ((MS_U16) u8Data) & 0x03;
2070 }
2071 else if (eSignalType == T2_L1_MODULATION)
2072 {
2073 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2) + 1, &u8Data) == FALSE)
2074 {
2075 return FALSE;
2076 }
2077 *pu16L1_parameter = ((MS_U16) u8Data) & 0x0F;
2078 }
2079 else if (eSignalType == T2_NUM_T2_FRAMES)
2080 {
2081 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3b * 2), &u8Data) == FALSE)
2082 {
2083 return FALSE;
2084 }
2085 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2086 }
2087 else if (eSignalType == T2_PLP_NUM_BLOCKS_MAX)
2088 {
2089 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2) + 1, &u8Data) == FALSE) return FALSE;
2090 u16Data = u8Data & 0x03;
2091 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2), &u8Data) == FALSE) return FALSE;
2092 u16Data = (u16Data << 8) | u8Data;
2093
2094 *pu16L1_parameter = u16Data;
2095 }
2096 else if (eSignalType == T2_FEF_ENABLE)
2097 {
2098
2099 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(0x00F1, &u8Data) == FALSE)
2100 {
2101 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2102 return FALSE;
2103 }
2104 *pu16L1_parameter = ((MS_U16) u8Data) & 0x01;
2105 }
2106 else
2107 {
2108 return FALSE;
2109 }
2110
2111 return TRUE;
2112
2113 }
2114
2115 return FALSE;
2116 }
2117
2118
2119 /****************************************************************************
2120 Subject: Read the signal to noise ratio (SNR)
2121 Function: INTERN_DVBT2_GetSNR
2122 Parmeter: None
2123 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2124 Remark:
2125 *****************************************************************************/
INTERN_DVBT2_GetSNR(void)2126 float INTERN_DVBT2_GetSNR (void)
2127 {
2128 MS_U8 status = true;
2129 MS_U8 reg=0, reg_frz=0;
2130 MS_U16 u16_snr100 = 0;
2131 float f_snr;
2132 MS_U8 u8_win = 0;
2133 MS_U8 u8_gi = 0;
2134
2135 // freeze
2136 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2137 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2138
2139 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2140 u16_snr100 = reg;
2141 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2142 u16_snr100 = (u16_snr100<<8)|reg;
2143
2144 // unfreeze
2145 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2146
2147 f_snr = (float)u16_snr100/100.0;
2148
2149 // snr cali
2150 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2151 u8_win = (reg>>2)&0x01;
2152
2153 if (u8_win == 1)
2154 {
2155 float snr_offset = 0.0;
2156 float snr_cali = 0.0;
2157
2158 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2159 u8_gi = (reg>>1)&0x07;
2160
2161 if (u8_gi == 0) snr_offset = 0.157;
2162 else if(u8_gi == 1) snr_offset = 0.317;
2163 else if(u8_gi == 2) snr_offset = 0.645;
2164 else if(u8_gi == 3) snr_offset = 1.335;
2165 else if(u8_gi == 4) snr_offset = 0.039;
2166 else if(u8_gi == 5) snr_offset = 0.771;
2167 else if(u8_gi == 6) snr_offset = 0.378;
2168
2169 snr_cali = f_snr - snr_offset;
2170 if (snr_cali > 0.0) f_snr = snr_cali;
2171 }
2172 //use Polynomial curve fitting to fix snr
2173 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2174 //f_snr = f_snr + snr_poly;
2175
2176 if (status == true)
2177 return f_snr;
2178 else
2179 return -1;
2180
2181 }
2182
INTERN_DVBT2_GetSignalStrength(MS_U16 * strength,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2183 MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength,const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2184 {
2185 MS_U8 status = true;
2186 float ch_power_db = 0.0f;
2187 float ch_power_ref = 11.0f;
2188 float ch_power_rel = 0.0f;
2189 //MS_U8 u8_index = 0;
2190 MS_U16 L1_info_qam, L1_info_cr;
2191 // MS_U8 demodState = 0;
2192
2193 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2194 {
2195 *strength = 0;
2196 return TRUE;
2197 }
2198 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2199
2200 // if (INTERN_DVBT2_Lock(COFDM_TPS_LOCK))
2201 //if (INTERN_DVBT2_Lock(COFDM_AGC_LOCK))
2202 /* Actually, it's more reasonable, that signal level depended on cable input power level
2203 * thougth the signal isn't dvb-t signal.
2204 */
2205
2206 // use pointer of IFAGC table to identify
2207 // case 1: RFAGC from SAR, IFAGC controlled by demod
2208 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2209 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2210 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
2211 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2212 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2213 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
2214 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
2215
2216
2217 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2218 printf("[dvbt2] QAM parameter retrieve failure\n");
2219
2220 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2221 printf("[dvbt2]code rate parameter retrieve failure\n");
2222
2223 /*
2224 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2225 {
2226 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
2227 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
2228 {
2229 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2230 break;
2231 }
2232 else
2233 {
2234 u8_index++;
2235 }
2236 }
2237 */
2238 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
2239
2240 // status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + (0x62*2), &demodState);
2241
2242 if (ch_power_ref > 10.0f)
2243 *strength = 0;
2244 else
2245 {
2246 // For Nordig's SSI test items
2247 if ( (L1_info_qam == 3) //256qam
2248 && (L1_info_cr > 0 && L1_info_cr < 4) // CR 3/5,2/3,3/4
2249 )
2250 {
2251 MS_U8 u8_x = L1_info_cr - 1;
2252 float f_ssi = 0.0;
2253
2254 if(ch_power_db >= -45)f_ssi = 100;
2255 else if (ch_power_db >= -50) f_ssi = fT2_SSI_formula[u8_x][0]*(ch_power_db + 50) + fT2_SSI_formula[u8_x][1];
2256 else if (ch_power_db >= -60) f_ssi = fT2_SSI_formula[u8_x][2]*(ch_power_db + 60) + fT2_SSI_formula[u8_x][3];
2257 else if (ch_power_db >= -70) f_ssi = fT2_SSI_formula[u8_x][4]*(ch_power_db + 70) + fT2_SSI_formula[u8_x][5];
2258 else if (ch_power_db >= -80) f_ssi = fT2_SSI_formula[u8_x][6]*(ch_power_db + 80) + fT2_SSI_formula[u8_x][7];
2259 else if (ch_power_db >= -95) f_ssi = fT2_SSI_formula[u8_x][8]*(ch_power_db + 95) + fT2_SSI_formula[u8_x][9];
2260 else if (ch_power_db >= -100) f_ssi = fT2_SSI_formula[u8_x][10]*(ch_power_db + 100) + fT2_SSI_formula[u8_x][11];
2261
2262 if (f_ssi > 100) *strength = 100;
2263 else if (f_ssi < 0) *strength = 0;
2264 else *strength = (MS_U16)(f_ssi+0.5);
2265
2266 DBG_GET_SIGNAL(printf(">>> SSI... RF_level=%d, f_ssi=%d, ssi=%d, cr=%d, mod=%d\n", (MS_S16)ch_power_db, (MS_S16)f_ssi, (MS_S16)(*strength), L1_info_cr, L1_info_qam));
2267 }
2268 else
2269 {
2270 ch_power_rel = ch_power_db - ch_power_ref;
2271 /*
2272 if (demodState != 0x09)
2273 {
2274 ch_power_rel = ch_power_db - (-50.0f);
2275 }
2276 else
2277 {
2278 ch_power_rel = ch_power_db - ch_power_ref;
2279 }
2280 */
2281 if ( ch_power_rel < -15.0f )
2282 {
2283 *strength = 0;
2284 }
2285 else if ( ch_power_rel < 0.0f )
2286 {
2287 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2288 }
2289 else if ( ch_power_rel < 20 )
2290 {
2291 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2292 }
2293 else if ( ch_power_rel < 35.0f )
2294 {
2295 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2296 }
2297 else
2298 {
2299 *strength = 100;
2300 }
2301 }
2302 }
2303
2304 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2305 {
2306 *strength = 0;
2307 return TRUE;
2308 }
2309
2310 DBG_GET_SIGNAL(printf(">>> ch_power_ref(dB) = %d , ch_power_db(dB) = %d, ch_power_rel(dB) = %d<<<\n", (MS_S16)ch_power_ref, (MS_S16)ch_power_db, (MS_S16)ch_power_rel));
2311 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %d , Score = %d<<<\n", (MS_S16)ch_power_db, *strength));
2312 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2313
2314 return status;
2315 }
2316
2317 /****************************************************************************
2318 Subject: To get the DVT Signal quility
2319 Function: INTERN_DVBT2_GetSignalQuality
2320 Parmeter: Quility
2321 Return: E_RESULT_SUCCESS
2322 E_RESULT_FAILURE
2323 Remark: Here we have 4 level range
2324 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
2325 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
2326 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
2327 <4>.4th Range => Quality <10
2328 *****************************************************************************/
INTERN_DVBT2_GetSignalQuality(MS_U16 * quality,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2329 MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2330 {
2331 // float ber_sqi, SQI;
2332 float fber;
2333 float cn_rec = 0;
2334 float cn_ref = 0;
2335 float cn_rel = 0;
2336 float fBerTH1[] = {1E-4, 1E-4*(1.0-DVBT2_BER_TH_HY), 1E-4*(1.0+DVBT2_BER_TH_HY), 1E-4};
2337 float fBerTH2[] = {3E-7, 3E-7, 3E-7*(1.0-DVBT2_BER_TH_HY), 3E-7*(1.0+DVBT2_BER_TH_HY)};
2338 float BER_SQI = (float)0.0;
2339 float SQI = (float)0.0;
2340 static MS_U8 u8SQIState = 0;
2341
2342 MS_U8 status = true;
2343 MS_U16 L1_info_qam = 0, L1_info_cr = 0, i = 0;
2344
2345 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2346
2347 if (TRUE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_LOCK) )
2348 {
2349 #if 1 // copy from msb1240
2350 if (fBerFilteredDVBT2 < 0.0)
2351 {
2352 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2353 {
2354 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2355 return FALSE;
2356 }
2357 fBerFilteredDVBT2 = fber;
2358 }
2359 else
2360 {
2361 fber = fBerFilteredDVBT2;
2362 }
2363
2364 if (fber > fBerTH1[u8SQIState])
2365 {
2366 BER_SQI = 0.0;
2367 u8SQIState = 1;
2368 }
2369 else if (fber >=fBerTH2[u8SQIState])
2370 {
2371 BER_SQI = 100.0/15;
2372 u8SQIState = 2;
2373 }
2374 else
2375 {
2376 BER_SQI = 100.0/6;
2377 u8SQIState = 3;
2378 }
2379
2380 cn_rec = INTERN_DVBT2_GetSNR();
2381 if (cn_rec < 0.0)
2382 return FALSE;
2383
2384 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2385 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2386 L1_info_qam = 0xff;
2387 L1_info_cr = 0xff;
2388
2389 cn_ref = (float)-1.0;
2390 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2391 printf("[dvbt2] QAM parameter retrieve failure\n");
2392
2393 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2394 printf("[dvbt2]code rate parameter retrieve failure\n");
2395
2396 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2397 {
2398 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2399 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2400 {
2401 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2402 break;
2403 }
2404 }
2405
2406 if (cn_ref < 0.0)
2407 {
2408 SQI = (float)0.0;
2409 printf("SQI is zero, 1\n");
2410 }
2411 else
2412 {
2413 // 0.7, snr offset
2414 cn_rel = cn_rec - cn_ref + 0.7f;
2415 if (cn_rel > 3.0)
2416 SQI = 100;
2417 else if (cn_rel >= -3)
2418 {
2419 SQI = (cn_rel+3)*BER_SQI;
2420 if (SQI > 100.0) SQI = 100.0;
2421 else if (SQI < 0.0) SQI = 0.0;
2422 }
2423 else
2424 {
2425 SQI = (float)0.0;
2426 printf("SQI is zero, 2\n");
2427 }
2428 }
2429
2430 *quality = (MS_U16)SQI;
2431 #else
2432 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2433 {
2434 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2435 }
2436 ///////// Get Pre-BCH (Post-LDPC) BER to determine BER_SQI //////////
2437 if(fLDPCBerFiltered<= 0.0)
2438 {
2439 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2440 {
2441 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2442 return FALSE;
2443 }
2444 fLDPCBerFiltered = fber;
2445 }
2446 else
2447 {
2448 fber = fLDPCBerFiltered;
2449 }
2450 /*
2451 if (fber > 1.0E-3)
2452 ber_sqi = 0.0;
2453 else if (fber > 8.5E-7)
2454 #ifdef MSOS_TYPE_LINUX
2455 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2456 #else
2457 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2458 #endif
2459 else
2460 ber_sqi = 100.0;
2461 */
2462 if (fber > 1E-4)
2463 ber_sqi = 0.0;
2464 else if (fber >= 1E-7)
2465 ber_sqi = 100.0 / 15;
2466 else
2467 ber_sqi = 100.0 / 6;
2468
2469 cn_rec = INTERN_DVBT2_GetSNR();
2470
2471 if (cn_rec == -1) //get SNR return fail
2472 status = false;
2473
2474 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2475 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2476 L1_info_qam = 0xff;
2477 L1_info_cr = 0xff;
2478
2479 cn_ref = (float)-1.0;
2480 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2481 printf("[dvbt2] QAM parameter retrieve failure\n");
2482
2483 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2484 printf("[dvbt2]code rate parameter retrieve failure\n");
2485
2486 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2487 {
2488 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2489 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2490 {
2491 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2492 break;
2493 }
2494 }
2495
2496 if (cn_ref == -1.0)
2497 SQI = (float)0.0;
2498 else
2499 {
2500 cn_rel = cn_rec - cn_ref;
2501 if (cn_rel > 3.0)
2502 SQI = 100;
2503 else if (cn_rel >= -3)
2504 {
2505 SQI = (cn_rel+3)*ber_sqi;
2506 if (SQI > 100.0) SQI = 100.0;
2507 else if (SQI < 0.0) SQI = 0.0;
2508 }
2509 else
2510 SQI = (float)0.0;
2511 }
2512
2513 // SQI patch, 256qam, R3/4 CN=20.8, SQI=0~13
2514 if ((L1_info_qam==_T2_256QAM) && (L1_info_cr==_T2_CR3Y4))
2515 {
2516 if ( (cn_rec > 20.6) && (cn_rec < 20.9))
2517 {
2518 if (SQI > 3) SQI -= 3;
2519 }
2520 else if ( (cn_rec >= 20.9) && (cn_rec < 21.2))
2521 {
2522 if (SQI > 9) SQI -= 9;
2523 }
2524 }
2525
2526 *quality = (MS_U16)SQI;
2527 #endif
2528 }
2529 else
2530 {
2531 *quality = 0;
2532 }
2533
2534 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
2535 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2536 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2537 return status;
2538 }
2539
2540 /****************************************************************************
2541 Subject: To get the DVBT Carrier Freq Offset
2542 Function: INTERN_DVBT2_Get_FreqOffset
2543 Parmeter: Frequency offset (in KHz), bandwidth
2544 Return: E_RESULT_SUCCESS
2545 E_RESULT_FAILURE
2546 Remark:
2547 *****************************************************************************/
INTERN_DVBT2_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2548 MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2549 {
2550 float N, FreqB;
2551 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2552 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2553 MS_U8 reg_frz=0, reg=0;
2554 MS_U8 status;
2555
2556 FreqB = (float)u8BW * 8 / 7;
2557
2558 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2559
2560 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2561
2562 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2563 RegCfoTd = reg;
2564
2565 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2566 RegCfoTd = (RegCfoTd << 8)|reg;
2567
2568 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2569 RegCfoTd = (RegCfoTd << 8)|reg;
2570
2571 FreqCfoTd = (float)RegCfoTd;
2572
2573 if (RegCfoTd & 0x800000)
2574 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2575
2576 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2577
2578 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2579
2580 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2581 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2582
2583 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2584
2585 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2586 RegCfoFd = reg;
2587
2588 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2589 RegCfoFd = (RegCfoFd << 8)|reg;
2590
2591 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2592 RegCfoFd = (RegCfoFd << 8)|reg;
2593
2594 FreqCfoFd = (float)RegCfoFd;
2595
2596 if (RegCfoFd & 0x800000)
2597 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2598
2599 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2600
2601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2602 RegIcfo = reg & 0x07;
2603
2604 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2605 RegIcfo = (RegIcfo << 8)|reg;
2606
2607 FreqIcfo = (float)RegIcfo;
2608
2609 if (RegIcfo & 0x400)
2610 FreqIcfo = FreqIcfo - (float)0x800;
2611
2612 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2613 reg = reg & 0x30;
2614
2615 switch (reg)
2616 {
2617 case 0x00: N = 2048; break;
2618 case 0x20: N = 4096; break;
2619 case 0x10:
2620 default: N = 8192; break;
2621 }
2622
2623 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2624 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2625 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2626 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2627 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2628 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2629 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2630 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2631 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2632 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2633
2634 if (status == TRUE)
2635 return TRUE;
2636 else
2637 return FALSE;
2638 }
2639
2640
INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)2641 void INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)
2642 {
2643
2644 bPowerOn = bPowerOn;
2645 }
2646
INTERN_DVBT2_Power_Save(void)2647 MS_BOOL INTERN_DVBT2_Power_Save(void)
2648 {
2649
2650 return TRUE;
2651 }
2652
INTERN_DVBT2_Version(MS_U16 * ver)2653 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver)
2654 {
2655
2656 MS_U8 status = true;
2657 MS_U8 tmp = 0;
2658 MS_U16 u16_INTERN_DVBT2_Version;
2659
2660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2661 u16_INTERN_DVBT2_Version = tmp;
2662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2663 u16_INTERN_DVBT2_Version = u16_INTERN_DVBT2_Version<<8|tmp;
2664 *ver = u16_INTERN_DVBT2_Version;
2665
2666 return status;
2667 }
2668
INTERN_DVBT2_Version_minor(MS_U8 * ver2)2669 MS_BOOL INTERN_DVBT2_Version_minor(MS_U8 *ver2)
2670 {
2671
2672 MS_U8 status = true;
2673
2674 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2675
2676 return status;
2677 }
2678
2679
INTERN_DVBT2_Show_Demod_Version(void)2680 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void)
2681 {
2682
2683 MS_BOOL status = true;
2684 MS_U16 u16_INTERN_DVBT2_Version = 0;
2685 MS_U8 u8_minor_ver = 0;
2686
2687 status &= INTERN_DVBT2_Version(&u16_INTERN_DVBT2_Version);
2688 status &= INTERN_DVBT2_Version_minor(&u8_minor_ver);
2689 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT2_Version,u8_minor_ver);
2690
2691 return status;
2692 }
2693
INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float write_value)2694 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
2695 {
2696 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
2697 return TRUE;
2698 /*
2699 MS_U8 u8_index = 0;
2700 MS_BOOL bRet = false;
2701
2702 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2703 {
2704 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2705 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2706 {
2707 dvbt2_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2708 bRet = true;
2709 break;
2710 }
2711 else
2712 {
2713 u8_index++;
2714 }
2715 }
2716 return bRet;
2717 */
2718 }
2719
INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float * read_value)2720 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
2721 {
2722 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
2723 return TRUE;
2724 /*
2725 MS_U8 u8_index = 0;
2726 MS_BOOL bRet = false;
2727
2728 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2729 {
2730 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2731 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2732 {
2733 *read_value = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2734 bRet = true;
2735 break;
2736 }
2737 else
2738 {
2739 u8_index++;
2740 }
2741 }
2742 return bRet;
2743 */
2744 }
2745
INTERN_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)2746 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
2747 {
2748 MS_BOOL status = TRUE;
2749 MS_U8 u8Data = 0;
2750 MS_U8 indx = 0;
2751
2752 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_GetPlpBitMap\n"));
2753
2754 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2755 if (u8Data != 0x30)
2756 {
2757 DBG_INTERN_DVBT2(printf("\n[INTERN_DVBT2_GetPlpBitMap] Check L1 NOT Ready !! E_DMD_T2_L1_FLAG = 0x%x\n", u8Data));
2758 return FALSE;
2759 }
2760 while (indx < 32)
2761 {
2762 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_PLP_ID_ARR + indx, &u8Data);
2763 u8PlpBitMap[indx] = u8Data;
2764 indx++;
2765 }
2766
2767 if (status)
2768 {
2769 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap data+++++++++++++++\n"));
2770 for (indx = 0; indx < 32; indx++)
2771 DBG_INTERN_DVBT2(printf("[%d] ", u8PlpBitMap[indx]));
2772 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap end+++++++++++++++\n"));
2773 }
2774 return status;
2775 }
2776
INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)2777 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
2778 {
2779 MS_BOOL status = TRUE;
2780 MS_U8 u8Data = 0;
2781 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2782 if (u8Data != 0x30)
2783 {
2784 printf(">>>dvbt2 L1 not ready yet\n");
2785 return FALSE;
2786 }
2787 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_DVBT2_LOCK_HIS, &u8Data);
2788
2789 if ((u8Data & BIT(7)) == 0x00)
2790 {
2791 printf(">>>dvbt2 is un-lock\n");
2792 return FALSE;
2793 }
2794 // assign PLP-ID value
2795 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x78) * 2, u8PlpID);
2796 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x01); // MEM_EN
2797 MsOS_DelayTask(1);
2798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x79) * 2, u8GroupID);
2799 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x00); // ~MEM_EN
2800
2801 return status;
2802 }
2803
INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID,MS_U8 u8GroupID)2804 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID)
2805 {
2806 MS_BOOL status = TRUE;
2807
2808 // assign Group-ID and PLP-ID value (must be written in order)
2809 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_GROUP_ID, u8GroupID);
2810 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
2811
2812 return status;
2813 }
2814
2815 #if (AUTO_TS_DATA_RATE)
INTERN_DVBT2_GetTsDivNum(MS_U8 * u8TSDivNum)2816 MS_BOOL INTERN_DVBT2_GetTsDivNum(MS_U8* u8TSDivNum)
2817 {
2818 int TS_DATA_RATE =0;
2819 MS_U8 u8_tmp =0;
2820
2821 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_3, &u8_tmp) == FALSE)
2822 {
2823 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2824 return FALSE;
2825 }
2826 //printf("[dvbt2] TS_DATA_RATE_3 = 0x%x \n\n", u8_tmp);
2827 TS_DATA_RATE = u8_tmp;
2828
2829 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_2, &u8_tmp) == FALSE)
2830 {
2831 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2832 return FALSE;
2833 }
2834 //printf("[dvbt2] TS_DATA_RATE_2 = 0x%x \n\n", u8_tmp);
2835 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
2836
2837 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_1, &u8_tmp) == FALSE)
2838 {
2839 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2840 return FALSE;
2841 }
2842 //printf("[dvbt2] TS_DATA_RATE_1 = 0x%x \n\n", u8_tmp);
2843 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
2844
2845 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DATA_RATE_0, &u8_tmp) == FALSE)
2846 {
2847 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2848 return FALSE;
2849 }
2850 //printf("[dvbt2] TS_DATA_RATE_0 = 0x%x \n\n", u8_tmp);
2851 TS_DATA_RATE = (TS_DATA_RATE<<8) |u8_tmp;
2852
2853 DBG_AUTO_TS_DATA_RATE(printf("[dvbt2] TS_DATA_RATE_total = 0x%x %d \n\n", TS_DATA_RATE, TS_DATA_RATE));
2854
2855
2856 u8_tmp=HAL_DMD_RIU_ReadByte(0x103301);
2857
2858 if((u8_tmp&0x01) == 0x00)// 172 MHz 172/2(N+1)
2859 {
2860 //*u8TSDivNum = (MS_U8)(floor (172000000.0/(2*(((TS_DATA_RATE*TS_DATA_RATE_RATIO)/8.0)))-1));
2861 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DIV_172, &u8_tmp) == FALSE)
2862 {
2863 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2864 return FALSE;
2865 }
2866 *u8TSDivNum = u8_tmp;
2867
2868 DBG_AUTO_TS_DATA_RATE(printf(" CLK Source: 172 MHz \n"));
2869 }
2870 else// 288 MHz 288/2(N+1)
2871 {
2872 //*u8TSDivNum = (MS_U8)(floor (288000000.0/(2*(((TS_DATA_RATE*TS_DATA_RATE_RATIO)/8.0)))-1));
2873 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_TS_DIV_288, &u8_tmp) == FALSE)
2874 {
2875 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2876 return FALSE;
2877 }
2878 *u8TSDivNum = u8_tmp;
2879
2880 DBG_AUTO_TS_DATA_RATE(printf(" CLK Source: 288 MHz \n"));
2881 }
2882
2883
2884 if (*u8TSDivNum > 0x1f)// 36 MHz/8 = 4.5 MHz
2885 *u8TSDivNum = 0x1f;
2886
2887 if (*u8TSDivNum < 0x0f)// 72 MHz/8 = 9 MHz
2888 *u8TSDivNum = 0x0f;
2889
2890 DBG_AUTO_TS_DATA_RATE(printf(">>>INTERN_DVBT2_GetTsDivNum = 0x%x<<<\n", *u8TSDivNum));
2891
2892 return TRUE;
2893 }
2894 #endif
2895
2896 #if (INTERN_DVBT2_INTERNAL_DEBUG == 1)
INTERN_DVBT2_get_demod_state(MS_U8 * state)2897 void INTERN_DVBT2_get_demod_state(MS_U8* state)
2898 {
2899 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2900 return;
2901 }
2902
INTERN_DVBT2_Show_ChannelLength(void)2903 MS_BOOL INTERN_DVBT2_Show_ChannelLength(void)
2904 {
2905 MS_U8 status = true;
2906 MS_U8 tmp = 0;
2907 MS_U16 len = 0;
2908 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2909 len = tmp;
2910 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2911 len = (len<<8)|tmp;
2912 printf("[dvbt]Hw_channel=%d\n",len);
2913 return status;
2914 }
2915
INTERN_DVBT2_Show_SW_ChannelLength(void)2916 MS_BOOL INTERN_DVBT2_Show_SW_ChannelLength(void)
2917 {
2918 MS_U8 status = true;
2919 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2920 MS_U16 sw_len = 0;
2921 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2922 sw_len = tmp;
2923 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2924 sw_len = (sw_len<<8)|tmp;
2925 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2926 peak_num = tmp;
2927 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2928 insideGI = tmp&0x01;
2929 stoptracking = (tmp&0x02)>>1;
2930 flag_short_echo = (tmp&0x0C)>>2;
2931 fsa_mode = (tmp&0x30)>>4;
2932
2933 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2934 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2935
2936 return status;
2937 }
2938
INTERN_DVBT2_Show_ACI_CI(void)2939 MS_BOOL INTERN_DVBT2_Show_ACI_CI(void)
2940 {
2941
2942 #define BIT4 0x10
2943 MS_U8 status = true;
2944 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2945
2946 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2947 digACI = (tmp&BIT4)>>4;
2948
2949 // get flag_CI
2950 // 0: No interference
2951 // 1: CCI
2952 // 2: in-band ACI
2953 // 3: N+1 ACI
2954 // flag_ci = (tmp&0xc0)>>6;
2955 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2956 flag_CI = (tmp&0xC0)>>6;
2957 td_coef = (tmp&0x0C)>>2;
2958
2959 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2960
2961 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2962
2963 return status;
2964 }
2965
INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)2966 MS_BOOL INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)
2967 {
2968 MS_U8 status = true;
2969 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2970 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2971 fd = tmp;
2972 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2973 ch_len = tmp;
2974 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2975 snr_sel = (tmp>>4)&0x03;
2976 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2977 pertone_num = tmp;
2978
2979 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2980
2981 return status;
2982 }
2983
INTERN_DVBT2_Get_CFO(void)2984 MS_BOOL INTERN_DVBT2_Get_CFO(void)
2985 {
2986
2987 float N = 0, FreqB = 0;
2988 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2989 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2990 MS_U8 reg_frz = 0, reg = 0;
2991 MS_U8 status = 0;
2992 MS_U8 u8BW = 8;
2993
2994 FreqB = (float)u8BW * 8 / 7;
2995
2996 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2997
2998 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2999
3000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
3001 RegCfoTd = reg;
3002
3003 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
3004 RegCfoTd = (RegCfoTd << 8)|reg;
3005
3006 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
3007 RegCfoTd = (RegCfoTd << 8)|reg;
3008
3009 FreqCfoTd = (float)RegCfoTd;
3010
3011 if (RegCfoTd & 0x800000)
3012 FreqCfoTd = FreqCfoTd - (float)0x1000000;
3013
3014 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
3015
3016 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
3017
3018 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
3019 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
3020
3021 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3022
3023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
3024 RegCfoFd = reg;
3025
3026 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
3027 RegCfoFd = (RegCfoFd << 8)|reg;
3028
3029 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
3030 RegCfoFd = (RegCfoFd << 8)|reg;
3031
3032 FreqCfoFd = (float)RegCfoFd;
3033
3034 if (RegCfoFd & 0x800000)
3035 FreqCfoFd = FreqCfoFd - (float)0x1000000;
3036
3037 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
3038
3039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
3040 RegIcfo = reg & 0x07;
3041
3042 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
3043 RegIcfo = (RegIcfo << 8)|reg;
3044
3045 FreqIcfo = (float)RegIcfo;
3046
3047 if (RegIcfo & 0x400)
3048 FreqIcfo = FreqIcfo - (float)0x800;
3049
3050 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
3051 reg = reg & 0x30;
3052
3053 switch (reg)
3054 {
3055 case 0x00: N = 2048; break;
3056 case 0x20: N = 4096; break;
3057 case 0x10:
3058 default: N = 8192; break;
3059 }
3060
3061 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
3062 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
3063 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
3064 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3065 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
3066
3067 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
3068
3069 return status;
3070
3071 }
INTERN_DVBT2_Get_SFO(void)3072 MS_BOOL INTERN_DVBT2_Get_SFO(void)
3073 {
3074 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
3075 MS_BOOL status = true;
3076 MS_U8 reg = 0;
3077 float FreqB = 9.143, FreqS = 45.473; //20.48
3078 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
3079 float sfo_value = 0;
3080
3081 // get Reg_TDP_SFO,
3082 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
3083 Reg_TDP_SFO = reg;
3084 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
3085 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3086 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
3087 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3088
3089 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3090
3091 // get Reg_FDP_SFO,
3092 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
3093 Reg_FDP_SFO = reg;
3094 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
3095 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
3097 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3098
3099 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3100
3101 // get Reg_FSA_SFO,
3102 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
3103 Reg_FSA_SFO = reg;
3104 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
3105 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3106 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
3107 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3108
3109 // get Reg_FSA_IN,
3110 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
3111 Reg_FSA_IN = reg;
3112 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
3113 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
3114 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
3115
3116 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
3117 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
3118
3119 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
3120 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
3121 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
3122
3123
3124 return status;
3125 }
3126
INTERN_DVBT2_Get_SYA_status(void)3127 void INTERN_DVBT2_Get_SYA_status(void)
3128 {
3129 MS_U8 status = true;
3130 MS_U8 sya_k = 0,reg = 0;
3131 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
3132
3133 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
3134 sya_k = reg;
3135
3136 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
3137 sya_th = reg;
3138 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
3139 sya_th = (sya_th<<8)|reg;
3140
3141 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
3142 sya_offset = reg;
3143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
3144 sya_offset = (sya_offset<<8)|reg;
3145
3146 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
3147 len_m = reg;
3148 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
3149 len_m = (len_m<<8)|reg;
3150
3151 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
3152 len_b = reg;
3153 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
3154 len_b = (len_b<<8)|reg;
3155
3156
3157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
3158 len_a = reg;
3159 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
3160 len_a = (len_a<<8)|reg;
3161
3162
3163 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
3164 tracking_reg = reg;
3165
3166
3167 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
3168 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
3169
3170 return;
3171 }
3172
INTERN_DVBT2_Get_cci_status(void)3173 void INTERN_DVBT2_Get_cci_status(void)
3174 {
3175 MS_U8 status = true;
3176 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
3177
3178 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
3179 cci_fsweep = reg;
3180
3181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
3182 cci_kp = reg;
3183
3184 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
3185
3186 return;
3187 }
3188
INTERN_DVBT2_Show_PRESFO_Info(void)3189 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void)
3190 {
3191 MS_U8 tmp = 0;
3192 MS_BOOL status = TRUE;
3193 printf("\n[SFO]");
3194 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
3195 printf("[%x]",tmp);
3196 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
3197 printf("[%x]",tmp);
3198 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
3199 printf("[%x]",tmp);
3200 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
3201 printf("[%x]",tmp);
3202 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
3203 printf("[%x]",tmp);
3204 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
3205 printf("[%x]",tmp);
3206 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
3207 printf("[%x]",tmp);
3208 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
3209 printf("[%x][End]",tmp);
3210
3211 return status;
3212 }
3213
INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 * locktime)3214 MS_BOOL INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 *locktime)
3215 {
3216 MS_BOOL status = true;
3217
3218 *locktime = 0xffff;
3219 printf("[dvbt]INTERN_DVBT2_Get_Lock_Time_Info not implement\n");
3220
3221 status = false;
3222 return status;
3223 }
3224
3225
INTERN_DVBT2_Show_Lock_Time_Info(void)3226 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void)
3227 {
3228 MS_U16 locktime = 0;
3229 MS_BOOL status = TRUE;
3230 status &= INTERN_DVBT2_Get_Lock_Time_Info(&locktime);
3231 printf("[DVBT]lock_time = %d ms\n",locktime);
3232 return status;
3233 }
3234
INTERN_DVBT2_Show_BER_Info(void)3235 MS_BOOL INTERN_DVBT2_Show_BER_Info(void)
3236 {
3237 MS_U8 tmp = 0;
3238 MS_BOOL status = TRUE;
3239 printf("\n[BER]");
3240 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
3241 printf("[%x,",tmp);
3242 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
3243 printf("%x]",tmp);
3244 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
3245 printf("[%x,",tmp);
3246 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
3247 printf("%x]",tmp);
3248 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
3249 printf("[%x,",tmp);
3250 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
3251 printf("%x][End]",tmp);
3252
3253 return status;
3254
3255 }
3256
3257
INTERN_DVBT2_Show_AGC_Info(void)3258 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void)
3259 {
3260 MS_U8 tmp = 0;
3261 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3262 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3263 MS_U16 if_agc_err = 0;
3264 MS_BOOL status = TRUE;
3265 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
3266
3267 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
3268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
3269 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
3270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
3271 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
3272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3273
3274
3275 // select IF gain to read
3276 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3277 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3278
3279 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3280 if_agc_gain = tmp;
3281 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3282 if_agc_gain = (if_agc_gain<<8)|tmp;
3283
3284
3285 // select d1 gain to read.
3286 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3287 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3288
3289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3290 d1_gain = tmp;
3291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3292 d1_gain = (d1_gain<<8)|tmp;
3293
3294 // select d2 gain to read.
3295 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3296 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3297
3298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3299 d2_gain = tmp;
3300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3301 d2_gain = (d2_gain<<8)|tmp;
3302
3303 // select IF gain err to read
3304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3305 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3306
3307 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3308 if_agc_err = tmp;
3309 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3310 if_agc_err = (if_agc_err<<8)|tmp;
3311
3312 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3314 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3315
3316
3317
3318 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3319 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3320
3321 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3322 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3323
3324 return status;
3325
3326 }
3327
INTERN_DVBT2_Show_WIN_Info(void)3328 MS_BOOL INTERN_DVBT2_Show_WIN_Info(void)
3329 {
3330 MS_U8 tmp = 0;
3331 MS_U8 trigger = 0;
3332 MS_U16 win_len = 0;
3333
3334 MS_BOOL status = TRUE;
3335
3336 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3337 win_len = tmp;
3338 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3339 win_len = (win_len<<8)|tmp;
3340
3341 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3342
3343 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3344
3345 return status;
3346 }
3347
INTERN_DVBT2_Show_td_coeff(void)3348 void INTERN_DVBT2_Show_td_coeff(void)
3349 {
3350 MS_U8 status = true;
3351 MS_U8 w1 = 0,w2 = 0,reg = 0;
3352
3353 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3354 w1 = reg;
3355
3356 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3357 w2 = reg;
3358
3359 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3360
3361 return;
3362 }
3363
3364 /********************************************************
3365 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM
3366 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
3367 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256
3368 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE
3369 *Preamble(b12) : 0~1 => mixed, not_mixed
3370 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved
3371 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8
3372 *BW_Extend(b19) : 0~1 => normal, extension
3373 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved
3374 ********************************/
INTERN_DVBT2_Show_Modulation_info(void)3375 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void)
3376 {
3377 MS_BOOL bRet = TRUE;
3378 MS_U16 u16Data = 0;
3379
3380 char* cConStr[] = {"qpsk", "16qam", "64qam", "256qam"};
3381 char* cCRStr[] = {"1_2", "3_5", "2_3", "3_4", "4_5", "5_6"};
3382 char* cGIStr[] = {"1_32", "1_16", "1_8", "1_4", "1_128", "19_128", "19_256"};
3383 char* cFFTStr[] = {"2k", "8k", "4k", "1k", "16k", "32k", "8k", "32k"};
3384 char* cPreAStr[] = {"mixed", "not_mixed"};
3385 char* cS1SStr[] = {"t2_siso", "t2_miso", "non_t2", "reserved"};
3386 char* cPPSStr[] = {"PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", "PP8", "reserved"};
3387 char* cBWStr[] = {"normal", "extension"};
3388 char* cPAPRStr[] = {"none", "ace", "tr", "tr_and_ace", "reserved"};
3389
3390 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
3391 {
3392
3393 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_MODUL_MODE) == FALSE)
3394 {
3395 printf("T2_MODUL_MODE Error!\n");
3396 bRet = FALSE;
3397 }
3398 u16Data &= 0x07;
3399 //*L1_Info = (MS_U64)(u16Data);
3400 printf("T2 Constellation:%s\n", cConStr[u16Data]);
3401
3402 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_CODE_RATE) == FALSE)
3403 {
3404 printf(("T2_CODE_RATE Error!\n"));
3405 bRet = FALSE;
3406 }
3407 u16Data &= 0x07;
3408 //*L1_Info |= (MS_U64)(u16Data << 3);
3409 printf("T2 Code Rate:%s\n", cCRStr[u16Data]);
3410
3411 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_GUARD_INTERVAL) == FALSE)
3412 {
3413 printf("T2_GUARD_INTERVAL Error!\n");
3414 bRet = FALSE;
3415 }
3416 u16Data &= 0x07;
3417 //*L1_Info |= (MS_U64)(u16Data << 6);
3418 printf("T2 GI:%s\n", cGIStr[u16Data]);
3419
3420 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_FFT_VALUE) == FALSE)
3421 {
3422 printf("T2_FFT_VALUE Error!\n");
3423 bRet = FALSE;
3424 }
3425 u16Data &= 0x07;
3426 //*L1_Info |= (MS_U64)(u16Data << 9);
3427 printf("T2 FFT:%s\n", cFFTStr[u16Data]);
3428
3429 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PREAMBLE) == FALSE)
3430 {
3431 printf("T2_PREAMBLE Error!\n");
3432 bRet = FALSE;
3433 }
3434 u16Data &= 0x01;
3435 //*L1_Info |= (MS_U64)(u16Data << 12);
3436 printf("Preamble:%s\n", cPreAStr[u16Data]);
3437
3438 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_S1_SIGNALLING) == FALSE)
3439 {
3440 printf("T2_S1_SIGNALLING Error!\n");
3441 bRet = FALSE;
3442 }
3443 u16Data &= 0x03;
3444 if (u16Data > 2)
3445 u16Data = 3;
3446 //*L1_Info |= (MS_U64)(u16Data << 13);
3447 printf("S1 Signalling:%s\n", cS1SStr[u16Data]);
3448
3449 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PILOT_PATTERN) == FALSE)
3450 {
3451 printf("T2_PILOT_PATTERN Error!\n");
3452 bRet = FALSE;
3453 }
3454 u16Data &= 0x0F;
3455 if (u16Data > 7)
3456 u16Data = 8;
3457 //*L1_Info |= (MS_U64)(u16Data << 15);
3458 printf("PilotPattern:%s\n", cPPSStr[u16Data]);
3459
3460 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_BW_EXT) == FALSE)
3461 {
3462 printf("T2_BW_EXT Error!\n");
3463 bRet = FALSE;
3464 }
3465 u16Data &= 0x01;
3466 //*L1_Info |= (MS_U64)(u16Data << 19);
3467 printf("BW EXT:%s\n", cBWStr[u16Data]);
3468
3469 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PAPR_REDUCTION) == FALSE)
3470 {
3471 printf("T2_PAPR_REDUCTION Error!\n");
3472 bRet = FALSE;
3473 }
3474 u16Data &= 0x07;
3475 if (u16Data > 3)
3476 u16Data = 4;
3477 //*L1_Info |= (MS_U64)(u16Data << 20);
3478 printf("T2 PAPR:%s\n", cPAPRStr[u16Data]);
3479
3480 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_OFDM_SYMBOLS_PER_FRAME) == FALSE)
3481 {
3482 printf("T2_OFDM_SYMBOLS_PER_FRAME Error!\n");
3483 bRet = FALSE;
3484 }
3485 u16Data &= 0xFFF;
3486 //*L1_Info |= (MS_U64)(u16Data << 23);
3487 printf("T2 OFDM Symbols:%u\n", u16Data);
3488 }
3489 else
3490 {
3491 printf("INVALID\n");
3492 return FALSE;
3493 }
3494
3495 return bRet;
3496
3497 }
3498
3499
INTERN_DVBT2_Show_BER_PacketErr(void)3500 void INTERN_DVBT2_Show_BER_PacketErr(void)
3501 {
3502 float f_ber = 0;
3503 MS_U16 packetErr = 0;
3504 INTERN_DVBT2_GetPostLdpcBer(&f_ber);
3505 INTERN_DVBT2_GetPacketErr(&packetErr);
3506
3507 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3508 return;
3509 }
3510
INTERN_DVBT2_Show_Lock_Info(void)3511 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void)
3512 {
3513
3514 printf("[dvbt]INTERN_DVBT2_Show_Lock_Info not implement!!!\n");
3515 return false;
3516 }
3517
3518
INTERN_DVBT2_Show_Demod_Info(void)3519 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void)
3520 {
3521 MS_U8 demod_state = 0;
3522 MS_BOOL status = true;
3523 static MS_U8 counter = 0;
3524
3525 INTERN_DVBT2_get_demod_state(&demod_state);
3526
3527 printf("==========[dvbt]state=%d\n",demod_state);
3528 if (demod_state < 5)
3529 {
3530 INTERN_DVBT2_Show_Demod_Version();
3531 INTERN_DVBT2_Show_AGC_Info();
3532 INTERN_DVBT2_Show_ACI_CI();
3533 }
3534 else if(demod_state < 8)
3535 {
3536 INTERN_DVBT2_Show_Demod_Version();
3537 INTERN_DVBT2_Show_AGC_Info();
3538 INTERN_DVBT2_Show_ACI_CI();
3539 INTERN_DVBT2_Show_ChannelLength();
3540 INTERN_DVBT2_Get_CFO();
3541 INTERN_DVBT2_Get_SFO();
3542 INTERN_DVBT2_Show_td_coeff();
3543 }
3544 else if(demod_state < 11)
3545 {
3546 INTERN_DVBT2_Show_Demod_Version();
3547 INTERN_DVBT2_Show_AGC_Info();
3548 INTERN_DVBT2_Show_ACI_CI();
3549 INTERN_DVBT2_Show_ChannelLength();
3550 INTERN_DVBT2_Get_CFO();
3551 INTERN_DVBT2_Get_SFO();
3552 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3553 INTERN_DVBT2_Get_SYA_status();
3554 INTERN_DVBT2_Show_td_coeff();
3555 }
3556 else if((demod_state == 11) && ((counter%4) == 0))
3557 {
3558 INTERN_DVBT2_Show_Demod_Version();
3559 INTERN_DVBT2_Show_AGC_Info();
3560 INTERN_DVBT2_Show_ACI_CI();
3561 INTERN_DVBT2_Show_ChannelLength();
3562 INTERN_DVBT2_Get_CFO();
3563 INTERN_DVBT2_Get_SFO();
3564 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3565 INTERN_DVBT2_Get_SYA_status();
3566 INTERN_DVBT2_Show_td_coeff();
3567 INTERN_DVBT2_Show_Modulation_info();
3568 INTERN_DVBT2_Show_BER_PacketErr();
3569 }
3570 else
3571 status = false;
3572
3573 printf("===========================\n");
3574 counter++;
3575
3576 return status;
3577 }
3578 #endif
3579
3580