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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include <math.h>
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 //#include "apiPWS.h"
109
110 #include "MsTypes.h"
111 #include "drvBDMA.h"
112 //#include "drvIIC.h"
113 //#include "msAPI_Tuner.h"
114 //#include "msAPI_MIU.h"
115 //#include "BinInfo.h"
116 //#include "halVif.h"
117 #include "drvDMD_INTERN_DVBC.h"
118 #include "halDMD_INTERN_DVBC.h"
119 #include "halDMD_INTERN_common.h"
120 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
121 #include "InfoBlock.h"
122 #endif
123 #include "drvMMIO.h"
124 //#include "TDAG4D01A_SSI_DVBT.c"
125 #include "drvDMD_VD_MBX.h"
126 #include "ULog.h"
127 #define TEST_EMBEDED_DEMOD 0
128 //U8 load_data_variable=1;
129 //-----------------------------------------------------------------------
130 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
131
132 #define TDE_REG_BASE 0x2400UL
133 #define INNC_REG_BASE 0x2600UL
134 #define EQE_REG_BASE 0x2c00UL // P2= 1; 0x11c00 -> 0x1c00
135 #define EQE2_REG_BASE 0x9c00UL
136 #define MBX_REG_BASE 0x2F00UL
137
138 #ifdef MS_DEBUG
139 #define DBG_INTERN_DVBC(x) x
140 #define DBG_GET_SIGNAL_DVBC(x) x
141 #define DBG_INTERN_DVBC_TIME(x) x
142 #define DBG_INTERN_DVBC_LOCK(x) x
143 #define INTERN_DVBC_INTERNAL_DEBUG 0
144 #else
145 #define DBG_INTERN_DVBC(x) //x
146 #define DBG_GET_SIGNAL_DVBC(x) //x
147 #define DBG_INTERN_DVBC_TIME(x) //x
148 #define DBG_INTERN_DVBC_LOCK(x) //x
149 #define INTERN_DVBC_INTERNAL_DEBUG 0
150 #endif
151 #define DBG_DUMP_LOAD_DSP_TIME 0
152
153
154 #define SIGNAL_LEVEL_OFFSET 0.00f
155 #define TAKEOVERPOINT -60.0f
156 #define TAKEOVERRANGE 0.5f
157 #define LOG10_OFFSET -0.21f
158 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
159 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
160
161 #define TUNER_IF 36167
162
163 #define TS_SER_C 0x00 //0: parallel 1:serial
164
165 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
166 #define TS_INV_C 0x01
167 #else
168 #define TS_INV_C 0x00
169 #endif
170
171 #define DVBC_FS 45474 //24000
172 #define CFG_ZIF 0x00 //For ZIF ,FC=0
173 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
174 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
175 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
176 #define FS_L_C (DVBC_FS&0xFF)
177 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
178 #define IQ_SWAP_C 0x00
179 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
180 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
181 // Symbol Rate: 6875 = 0x1ADB
182 // Symbol Rate: 6900 = 0x1AF4
183 // Symbol Rate: 7000 = 0x1B58
184 // Symbol Rate: 4000 = 0x0FA0
185 // Symbol Rate: 6125 = 0x17ED
186 #define SR0_H 0x1A
187 #define SR0_L 0xF4 //6900
188 #define SR1_H 0x1B
189 #define SR1_L 0x58 //7000
190 #define SR2_H 0x17
191 #define SR2_L 0xED //6125
192 #define SR3_H 0x0F
193 #define SR3_L 0xA0 //4000
194 #define SR4_H 0x1B
195 #define SR4_L 0x26 //6950
196 #define SR5_H 0x1A //0xDB
197 #define SR5_L 0xDB //0x1A //6875
198 #define SR6_H 0x1C
199 #define SR6_L 0x20 //7200
200 #define SR7_H 0x1C
201 #define SR7_L 0x52 //7250
202 #define SR8_H 0x0B
203 #define SR8_L 0xB8 //3000
204 #define SR9_H 0x03
205 #define SR9_L 0xE8 //1000
206 #define SR10_H 0x07
207 #define SR10_L 0xD0 //2000
208 #define SR11_H 0x00
209 #define SR11_L 0x00 //0000
210
211
212 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
213
214 // SAR dependent
215 #define NO_SIGNAL_TH_A 0xA3
216 // Tuner dependent
217 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
218 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
219 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
220 #define NO_SIGNAL_TH_C_H 0xff //0x00
221 #define DAGC1_REF 0x70
222 #define DAGC2_REF 0x30
223 #define AGC_REF_L 0x00
224 #define AGC_REF_H 0x06
225
226 #define INTERN_AUTO_SR_C 1
227 #define INTERN_AUTO_QAM_C 1
228
229 #define ATV_DET_EN 1
230
231 #if 0
232 MS_U8 INTERN_DVBC_DSPREG[] =
233 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
234 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
235 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
236 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
237 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
238 };
239 #else
240 MS_U8 INTERN_DVBC_DSPREG[] =
241 {
242 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
243 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
244 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
245 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
246 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
247 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
248 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
249 };
250 #endif
251 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
252
253 //-----------------------------------------------------------------------
254 /****************************************************************
255 *Local Variables *
256 ****************************************************************/
257
258 //static MS_BOOL TPSLock = 0;
259 static MS_U32 u32ChkScanTimeStartDVBC = 0;
260 static MS_U8 g_dvbc_lock = 0;
261 static float intern_dvb_c_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
262
263 //Global Variables
264 S_CMDPKTREG gsCmdPacketDVBC;
265 //MS_U8 gCalIdacCh0, gCalIdacCh1;
266 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
267 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
268 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
269 MS_U8 INTERN_DVBC_table[] = {
270 #include "fwDMD_INTERN_DVBC.dat"
271 };
272
273 #endif
274
275 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
276 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
277 // MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
278 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
279 // MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff);
280 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
281 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
282 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
283
284 #if (INTERN_DVBC_INTERNAL_DEBUG)
285 void INTERN_DVBC_info(void);
286 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
287 #endif
288
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)289 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
290 {
291 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
292 MS_U8 status = TRUE;
293 MS_U16 u16DspAddr = 0;
294
295 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init\n");
296
297 #if 0//def MS_DEBUG
298 {
299 MS_U8 u8buffer[256];
300 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Reset\n");
301 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
302 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
303
304 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
305 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
306 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
307 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
308 ULOGD("DEMOD","%x ", u8buffer[idx]);
309 ULOGD("DEMOD","\n");
310
311 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Value\n");
312 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
313 ULOGD("DEMOD","%x ", INTERN_DVBC_DSPREG[idx]);
314 ULOGD("DEMOD","\n");
315 }
316 #endif
317
318 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
319 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
320
321 // readback to confirm.
322 #ifdef MS_DEBUG
323 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
324 {
325 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
326 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
327 {
328 ULOGD("DEMOD","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
329 }
330 }
331 #endif
332
333 if (u8DVBC_DSPReg != NULL)
334 {
335 if (1 == u8DVBC_DSPReg[0])
336 {
337 u8DVBC_DSPReg+=2;
338 for (idx = 0; idx<u8Size; idx++)
339 {
340 u16DspAddr = *u8DVBC_DSPReg;
341 u8DVBC_DSPReg++;
342 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
343 u8DVBC_DSPReg++;
344 u8Mask = *u8DVBC_DSPReg;
345 u8DVBC_DSPReg++;
346 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
347 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
348 u8DVBC_DSPReg++;
349 ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
350 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
351 }
352 }
353 else
354 {
355 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
356 }
357 }
358
359 #if 0//def MS_DEBUG
360 {
361 MS_U8 u8buffer[256];
362 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
363 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
364 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack\n");
365 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
366 ULOGD("DEMOD","%x ", u8buffer[idx]);
367 ULOGD("DEMOD","\n");
368 }
369 #endif
370
371 #if 0//def MS_DEBUG
372 {
373 MS_U8 u8buffer[256];
374 for (idx = 0; idx<128; idx++)
375 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
376 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
377 for (idx = 0; idx<128; idx++)
378 {
379 ULOGD("DEMOD","%x ", u8buffer[idx]);
380 if ((idx & 0xF) == 0xF) ULOGD("DEMOD","\n");
381 }
382 ULOGD("DEMOD","\n");
383 }
384 #endif
385 return status;
386 }
387
388 /***********************************************************************************
389 Subject: Command Packet Interface
390 Function: INTERN_DVBC_Cmd_Packet_Send
391 Parmeter:
392 Return: MS_BOOL
393 Remark:
394 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)395 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
396 {
397
398 return TRUE;
399
400 }
401
402
403 /***********************************************************************************
404 Subject: Command Packet Interface
405 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
406 Parmeter:
407 Return: MS_BOOL
408 Remark:
409 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)410 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
411 {
412 return TRUE;
413 }
414
415 /***********************************************************************************
416 Subject: SoftStop
417 Function: INTERN_DVBC_SoftStop
418 Parmeter:
419 Return: MS_BOOL
420 Remark:
421 ************************************************************************************/
422
INTERN_DVBC_SoftStop(void)423 MS_BOOL INTERN_DVBC_SoftStop ( void )
424 {
425 #if 1
426 MS_U16 u8WaitCnt=0;
427
428 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
429 {
430 ULOGD("DEMOD",">> MB Busy!\n");
431 return FALSE;
432 }
433
434 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
435
436 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
437 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
438
439 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
440 {
441 #if TEST_EMBEDED_DEMOD
442 MsOS_DelayTask(1); // << Ken 20090629
443 #endif
444 if (u8WaitCnt++ >= 0x7FFF)
445 {
446 ULOGD("DEMOD",">> DVBT SoftStop Fail!\n");
447 return FALSE;
448 }
449 }
450
451 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
452 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
453 #endif
454 return TRUE;
455 }
456
457
458 /***********************************************************************************
459 Subject: Reset
460 Function: INTERN_DVBC_Reset
461 Parmeter:
462 Return: MS_BOOL
463 Remark:
464 ************************************************************************************/
465 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)466 MS_BOOL INTERN_DVBC_Reset ( void )
467 {
468 ULOGD("DEMOD"," @INTERN_DVBC_reset\n");
469
470 //ULOGD("DEMOD","INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime());
471
472 //INTERN_DVBC_SoftStop();
473
474
475 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
476 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
477 MsOS_DelayTask(5);
478 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
479 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
480 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
481 MsOS_DelayTask(5);
482
483 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
484 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
485
486 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
487 g_dvbc_lock = 0;
488
489 return TRUE;
490 }
491
492 /***********************************************************************************
493 Subject: Exit
494 Function: INTERN_DVBC_Exit
495 Parmeter:
496 Return: MS_BOOL
497 Remark:
498 ************************************************************************************/
INTERN_DVBC_Exit(void)499 MS_BOOL INTERN_DVBC_Exit ( void )
500 {
501
502 INTERN_DVBC_SoftStop();
503
504 return TRUE;
505 }
506
507 /***********************************************************************************
508 Subject: Load DSP code to chip
509 Function: INTERN_DVBC_LoadDSPCode
510 Parmeter:
511 Return: MS_BOOL
512 Remark:
513 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)514 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
515 {
516 MS_U8 udata = 0x00;
517 MS_U16 i;
518 MS_U16 fail_cnt=0;
519
520 #if (DBG_DUMP_LOAD_DSP_TIME==1)
521 MS_U32 u32Time;
522 #endif
523
524
525 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
526 BININFO BinInfo;
527 MS_BOOL bResult;
528 MS_U32 u32GEAddr;
529 MS_U8 Data;
530 MS_S8 op;
531 MS_U32 srcaddr;
532 MS_U32 len;
533 MS_U32 SizeBy4K;
534 MS_U16 u16Counter=0;
535 MS_U8 *pU8Data;
536 #endif
537
538
539
540 // MDrv_Sys_DisableWatchDog();
541
542
543 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
544 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
545 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
546 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
547 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
548 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
549
550 //// Load code thru VDMCU_IF ////
551 ULOGD("DEMOD",">Load Code.....\n");
552 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
553 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
554 {
555 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
556 }
557 #else
558 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
559 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
560 if ( bResult != PASS )
561 {
562 return FALSE;
563 }
564 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
565
566 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
567 InfoBlock_Flash_2_Checking_Start(&BinInfo);
568 #endif
569
570 #if OBA2
571 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
572 #else
573 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
574 #endif
575
576 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
577 InfoBlock_Flash_2_Checking_End(&BinInfo);
578 #endif
579
580 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
581 SizeBy4K=BinInfo.B_Len/0x1000;
582 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
583
584 #if (DBG_DUMP_LOAD_DSP_TIME==1)
585 u32Time = msAPI_Timer_GetTime0();
586 #endif
587
588 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
589
590 for (i=0;i<=SizeBy4K;i++)
591 {
592 if(i==SizeBy4K)
593 len=BinInfo.B_Len%0x1000;
594 else
595 len=0x1000;
596
597 srcaddr = u32GEAddr+(0x1000*i);
598 //ULOGD("DEMOD","\t i = %08X\n", i);
599 //ULOGD("DEMOD","\t len = %08X\n", len);
600 op = 1;
601 u16Counter = 0 ;
602 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
603 while(len--)
604 {
605 u16Counter ++ ;
606 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
607 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
608 #if OBA2
609 pU8Data = (MS_U8 *)(srcaddr);
610 #else
611 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
612 #endif
613 Data = *pU8Data;
614
615 #if 0
616 if(u16Counter < 0x100)
617 ULOGD("DEMOD","0x%bx,", Data);
618 #endif
619 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
620
621 srcaddr += op;
622 }
623 // ULOGD("DEMOD","\n\n\n");
624 }
625
626 #if (DBG_DUMP_LOAD_DSP_TIME==1)
627 ULOGD("DEMOD","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
628 #endif
629
630 #endif
631
632 //// Content verification ////
633 ULOGD("DEMOD",">Verify Code...\n");
634
635 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
636 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
637
638 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
639 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
640 {
641 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
642 if (udata != INTERN_DVBC_table[i])
643 {
644 ULOGD("DEMOD",">fail add = 0x%x\n", i);
645 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBC_table[i]);
646 ULOGD("DEMOD",">data = 0x%x\n", udata);
647
648 if (fail_cnt > 10)
649 {
650 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
651 return false;
652 }
653 fail_cnt++;
654 }
655 }
656 #else
657 for (i=0;i<=SizeBy4K;i++)
658 {
659 if(i==SizeBy4K)
660 len=BinInfo.B_Len%0x1000;
661 else
662 len=0x1000;
663
664 srcaddr = u32GEAddr+(0x1000*i);
665 //ULOGD("DEMOD","\t i = %08LX\n", i);
666 //ULOGD("DEMOD","\t len = %08LX\n", len);
667 op = 1;
668 u16Counter = 0 ;
669 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
670 while(len--)
671 {
672 u16Counter ++ ;
673 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
674 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
675 #if OBA2
676 pU8Data = (MS_U8 *)(srcaddr);
677 #else
678 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
679 #endif
680 Data = *pU8Data;
681
682 #if 0
683 if(u16Counter < 0x100)
684 ULOGD("DEMOD","0x%bx,", Data);
685 #endif
686 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
687 if (udata != Data)
688 {
689 ULOGD("DEMOD",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
690 ULOGD("DEMOD",">code = 0x%x\n", Data);
691 ULOGD("DEMOD",">data = 0x%x\n", udata);
692
693 if (fail_cnt++ > 10)
694 {
695 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
696 return false;
697 }
698 }
699
700 srcaddr += op;
701 }
702 // ULOGD("DEMOD","\n\n\n");
703 }
704 #endif
705
706 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
707 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
708 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
709 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
710
711 ULOGD("DEMOD",">DSP Loadcode done.");
712 //while(load_data_variable);
713
714
715
716 return TRUE;
717 }
718
719 /***********************************************************************************
720 Subject: DVB-T CLKGEN initialized function
721 Function: INTERN_DVBC_Power_On_Initialization
722 Parmeter:
723 Return: MS_BOOL
724 Remark:
725 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)726 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
727 {
728 // MS_U8 temp_val;
729
730 HAL_DMD_RIU_WriteByte(0x103c0e, 0x00); //mux from DMD MCU to HK.
731 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
732 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
733
734 // CLK_DMDMCU clock setting
735 // [0] disable clock
736 // [1] invert clock
737 // [4:2]
738 // 000:170 MHz(MPLL_DIV_BUf)
739 // 001:160MHz
740 // 010:144MHz
741 // 011:123MHz
742 // 100:108MHz
743 // 101:mem_clcok
744 // 110:mem_clock div 2
745 // 111:select XTAL
746 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
747 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
748
749 // set parallet ts clock
750 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
751 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
752 // wriu 0x103301 0x06
753 // wriu 0x103300 0x19
754
755
756 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
757 HAL_DMD_RIU_WriteByte(0x103301,0x07);
758 HAL_DMD_RIU_WriteByte(0x103300,0x13);
759
760 // enable atsc, DVBTC ts clock
761 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
762 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
763 // wriu 0x103309 0x00
764 // wriu 0x103308 0x00
765
766 HAL_DMD_RIU_WriteByte(0x103309,0x00);
767 HAL_DMD_RIU_WriteByte(0x103308,0x00);
768
769 // enable dvbc adc clock
770 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
771 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
772 // wriu 0x103315 0x00
773 // wriu 0x103314 0x00
774
775 HAL_DMD_RIU_WriteByte(0x103315,0x00);
776 HAL_DMD_RIU_WriteByte(0x103314,0x00);
777
778 // Reset TS divider
779 HAL_DMD_RIU_WriteByte(0x103302,0x01);
780 HAL_DMD_RIU_WriteByte(0x103302,0x00);
781
782 HAL_DMD_RIU_WriteByte(0x152929,0x00);
783 HAL_DMD_RIU_WriteByte(0x152928,0x04);
784
785 HAL_DMD_RIU_WriteByte(0x152903,0x04);
786 HAL_DMD_RIU_WriteByte(0x152902,0x04);
787
788 HAL_DMD_RIU_WriteByte(0x152905,0x00);
789 HAL_DMD_RIU_WriteByte(0x152904,0x00);
790
791 HAL_DMD_RIU_WriteByte(0x152907,0x04);
792 HAL_DMD_RIU_WriteByte(0x152906,0x00);
793
794 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
795 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
796
797
798 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
799 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
800
801 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
802 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
803
804 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
805 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
806
807 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
808 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
809
810 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
811 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
812
813 HAL_DMD_RIU_WriteByte(0x111f69,0x88);
814 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
815
816 HAL_DMD_RIU_WriteByte(0x111f6b,0x01);
817 HAL_DMD_RIU_WriteByte(0x111f6a,0x11);
818
819 HAL_DMD_RIU_WriteByte(0x152923,0x00);
820 HAL_DMD_RIU_WriteByte(0x152922,0x44);
821
822 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
823 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
824
825 HAL_DMD_RIU_WriteByte(0x15296d,0x00);
826 HAL_DMD_RIU_WriteByte(0x15296c,0x81);
827
828 HAL_DMD_RIU_WriteByte(0x152971,0x1c);
829 HAL_DMD_RIU_WriteByte(0x152970,0xc1);
830
831 HAL_DMD_RIU_WriteByte(0x152977,0x08);
832 HAL_DMD_RIU_WriteByte(0x152976,0x08);
833
834 HAL_DMD_RIU_WriteByte(0x152981,0x00);
835 HAL_DMD_RIU_WriteByte(0x152980,0x00);
836
837 HAL_DMD_RIU_WriteByte(0x152983,0x00);
838 HAL_DMD_RIU_WriteByte(0x152982,0x00);
839
840 HAL_DMD_RIU_WriteByte(0x152985,0x00);
841 HAL_DMD_RIU_WriteByte(0x152984,0x00);
842
843 HAL_DMD_RIU_WriteByte(0x152987,0x00);
844 HAL_DMD_RIU_WriteByte(0x152986,0x00);
845
846 HAL_DMD_RIU_WriteByte(0x111feb,0x18);
847 HAL_DMD_RIU_WriteByte(0x111fea,0x14);
848
849 HAL_DMD_RIU_WriteByte(0x111f74,0x10);
850
851 HAL_DMD_RIU_WriteByte(0x111f77,0x01);
852
853 HAL_DMD_RIU_WriteByte(0x111f79,0x41);
854 HAL_DMD_RIU_WriteByte(0x111f78,0x10);
855
856 HAL_DMD_RIU_WriteByte(0x111fe0,0x08);
857
858 HAL_DMD_RIU_WriteByte(0x111fe3,0x08);
859 HAL_DMD_RIU_WriteByte(0x111fe2,0x10);
860
861 HAL_DMD_RIU_WriteByte(0x111ff0,0x08);
862
863 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
864
865 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
866
867 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
868 }
869
870
871 /***********************************************************************************
872 Subject: Power on initialized function
873 Function: INTERN_DVBC_Power_On_Initialization
874 Parmeter:
875 Return: MS_BOOL
876 Remark:
877 ************************************************************************************/
878
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)879 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
880 {
881 MS_U8 status = true;
882 ULOGD("DEMOD","INTERN_DVBC_Power_On_Initialization\n");
883
884 #if defined(PWS_ENABLE)
885 Mapi_PWS_Stop_VDMCU();
886 #endif
887
888 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
889 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
890 //// Firmware download //////////
891 ULOGD("DEMOD","INTERN_DVBC Load DSP...\n");
892 //MsOS_DelayTask(100);
893
894
895 {
896 if (INTERN_DVBC_LoadDSPCode() == FALSE)
897 {
898 ULOGD("DEMOD","DVB-C Load DSP Code Fail\n");
899 return FALSE;
900 }
901 else
902 {
903 ULOGD("DEMOD","DVB-C Load DSP Code OK\n");
904 }
905 }
906
907 status &= INTERN_DVBC_Reset();
908
909 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
910
911 return status;
912 }
913
914 /************************************************************************************************
915 Subject: Driving control
916 Function: INTERN_DVBC_Driving_Control
917 Parmeter: bInversionEnable : TRUE For High
918 Return: void
919 Remark:
920 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)921 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
922 {
923 MS_U8 u8Temp;
924
925 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
926
927 if (bEnable)
928 {
929 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
930 }
931 else
932 {
933 u8Temp = u8Temp & (~0x01);
934 }
935
936 ULOGD("DEMOD","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp);
937 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
938 }
939 /************************************************************************************************
940 Subject: Clk Inversion control
941 Function: INTERN_DVBC_Clk_Inversion_Control
942 Parmeter: bInversionEnable : TRUE For Inversion Action
943 Return: void
944 Remark:
945 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)946 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
947 {
948 MS_U8 u8Temp;
949
950 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
951
952 if (bInversionEnable)
953 {
954 u8Temp = u8Temp | 0x02; //bit 9: clk inv
955 }
956 else
957 {
958 u8Temp = u8Temp & (~0x02);
959 }
960
961 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
962 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
963 }
964 /************************************************************************************************
965 Subject: Transport stream serial/parallel control
966 Function: INTERN_DVBC_Serial_Control
967 Parmeter: bEnable : TRUE For serial
968 Return: MS_BOOL :
969 Remark:
970 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)971 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
972 {
973 MS_U8 status = true;
974 return status;
975
976
977 }
978
979 /************************************************************************************************
980 Subject: TS1 output control
981 Function: INTERN_DVBC_PAD_TS1_Enable
982 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
983 Return: void
984 Remark:
985 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)986 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
987 {
988 ULOGD("DEMOD"," @INTERN_DVBC_TS1_Enable... \n");
989
990 if(flag) // PAD_TS1 Enable TS CLK PAD
991 {
992 //ULOGD("DEMOD","=== TS1_Enable ===\n");
993 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
994 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
995 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
996 }
997 else // PAD_TS1 Disable TS CLK PAD
998 {
999 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1000 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1001 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1002 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1003 }
1004 }
1005
1006 /************************************************************************************************
1007 Subject: channel change config
1008 Function: INTERN_DVBC_Config
1009 Parmeter: BW: bandwidth
1010 Return: MS_BOOL :
1011 Remark:
1012 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1013 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1014 {
1015
1016 MS_U8 status = true;
1017 MS_U8 reg_symrate_l, reg_symrate_h;
1018 //MS_U16 u16Fc = 0;
1019 // force
1020 // u16SymbolRate = 0;
1021 // eQamMode = DMD_DVBC_QAMAUTO;
1022
1023 pu16_symbol_rate_list = pu16_symbol_rate_list;
1024 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1025
1026 //ULOGD("DEMOD"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk);
1027 //ULOGD("DEMOD","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime());
1028
1029 if (u8TSClk == 0xFF) u8TSClk=0x13;
1030
1031 /*
1032 switch(u32IFFreq)
1033 {
1034 case 36125:
1035 case 36167:
1036 case 36000:
1037 case 6000:
1038 case 4560:
1039 //u16Fc = DVBC_FS - u32IFFreq;
1040 DBG_INTERN_DVBC(ULOGD("DEMOD","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1041 break;
1042 case 44000:
1043 default:
1044 ULOGD("DEMOD","IF frequency not supported\n");
1045 status = false;
1046 break;
1047 }
1048 */
1049
1050 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1051 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1052
1053 status &= INTERN_DVBC_Reset();
1054
1055 if (eQamMode == DMD_DVBC_QAMAUTO)
1056 {
1057 ULOGD("DEMOD","DMD_DVBC_QAMAUTO\n");
1058 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1059 // give default value.
1060 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1061 }
1062 else
1063 {
1064 ULOGD("DEMOD","DMD_DVBC_QAM %d\n", eQamMode);
1065 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1066 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1067 }
1068 // auto symbol rate enable/disable
1069 if (u16SymbolRate == 0)
1070 {
1071 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1072 }
1073 else
1074 {
1075 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1076 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1077 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1078 }
1079 // TS mode
1080 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1081
1082 // IQ Swap
1083 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1084
1085 // Fc
1086 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1087 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1088 // Lif
1089 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1090 // Fif
1091 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1092 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1093
1094 //// INTERN_DVBC system init: DVB-C //////////
1095 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1096
1097 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1098 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1099
1100 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1101 INTERN_DVBC_Show_Demod_Version();
1102 #endif
1103
1104 return status;
1105 }
1106 /************************************************************************************************
1107 Subject: enable hw to lock channel
1108 Function: INTERN_DVBC_Active
1109 Parmeter: bEnable
1110 Return: MS_BOOL
1111 Remark:
1112 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1113 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1114 {
1115 MS_U8 status = true;
1116
1117 ULOGD("DEMOD"," @INTERN_DVBC_active\n");
1118
1119 //// INTERN_DVBC Finite State Machine on/off //////////
1120 #if 0
1121 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1122
1123 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1124 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1125 #else
1126 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1127 #endif
1128
1129 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1130 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1131 return status;
1132 }
1133
1134 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBC_Adaptive_TS_CLK(void)1135 MS_BOOL INTERN_DVBC_Adaptive_TS_CLK(void)
1136 {
1137 MS_U8 u8_ts_clk=0x00;
1138 MS_U8 TS_Clock_Temp;
1139 MS_U8 CLK_source=0;
1140
1141 u8_ts_clk = HAL_DMD_RIU_ReadByte(MBRegBase+0x15);
1142
1143 CLK_source=(u8_ts_clk>>6);
1144 u8_ts_clk=u8_ts_clk&0x1F;
1145
1146 //reg_atsc_dvb_div_reset =1 ; CLKGEN1
1147 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1148 TS_Clock_Temp=TS_Clock_Temp|0x01;
1149 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1150
1151 //set TS clock source div 5
1152 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1);
1153 if (CLK_source==0)
1154 TS_Clock_Temp &=(~0x01);
1155 else
1156 TS_Clock_Temp |= (0x01);
1157
1158 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp);
1159
1160 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
1161 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1162 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_ts_clk ;
1163 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp);
1164
1165
1166 //reg_atsc_dvb_div_reset =0
1167 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02);
1168 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
1169 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
1170
1171 // set ts FIFO
1172 // reg_RS_BACKEND
1173 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
1174 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ;
1175
1176 // enable ts
1177 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ;
1178 TS_Clock_Temp=TS_Clock_Temp|0x01;
1179 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ;
1180
1181 //debug: re-check ts clock
1182 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN);
1183 TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
1184
1185 return TRUE;
1186 }
1187
1188
1189
1190
1191
1192
1193
INTERN_DVBC_Locked_Task(void)1194 MS_BOOL INTERN_DVBC_Locked_Task(void)
1195 {
1196 INTERN_DVBC_Adaptive_TS_CLK();
1197
1198 //extension task
1199 {
1200
1201 }
1202
1203 return TRUE;
1204
1205 }
1206
1207 #endif
1208
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)1209 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1210 {
1211 MS_U16 u16Address = 0;
1212 MS_U8 cData = 0;
1213 MS_U8 cBitMask = 0;
1214 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1215 MS_U8 unlock_indicator=0;
1216 #endif
1217 if (fCurrRFPowerDbm < 100.0f)
1218 {
1219 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1220 {
1221 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1222 if (cData > 5)
1223 {
1224 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1225 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1226 }
1227 else
1228 {
1229 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
1230 {
1231 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1232 }
1233 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1234 {
1235 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1236 #ifdef MS_DEBUG
1237 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1238 #endif
1239 return TRUE;
1240 }
1241 }
1242 #ifdef MS_DEBUG
1243 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1244 #endif
1245 }
1246 }
1247
1248 {
1249 switch( eType )
1250 {
1251 case DMD_DVBC_GETLOCK_FEC_LOCK:
1252 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1253 #if (INTERN_DVBC_INTERNAL_DEBUG)
1254 INTERN_DVBC_info();
1255 #endif
1256 ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData);
1257 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1258 MDrv_SYS_DMD_VD_MBX_ReadReg(MBX_REG_BASE + 0x16, &unlock_indicator);
1259 #endif
1260 if (cData == 0x0C)
1261 {
1262
1263 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1264 if(g_dvbc_lock == 0 || unlock_indicator==0x01)
1265 #else
1266 if(g_dvbc_lock == 0)
1267 #endif
1268 {
1269
1270 g_dvbc_lock = 1;
1271 ULOGD("DEMOD","[T12][DVBC]lock++++\n");
1272
1273 #ifdef SUPPORT_ADAPTIVE_TS_CLK
1274 ULOGD("DEMOD","===================================================================\n");
1275 ULOGD("DEMOD","Support adaptive TS CLK in polling mode! \n");
1276 ULOGD("DEMOD","===================================================================\n");
1277 INTERN_DVBC_Locked_Task();
1278 MDrv_SYS_DMD_VD_MBX_WriteReg(MBX_REG_BASE + 0x16, 0x00);
1279 #endif
1280
1281 }
1282 return TRUE;
1283 }
1284 else
1285 {
1286 if(g_dvbc_lock == 1)
1287 {
1288 g_dvbc_lock = 0;
1289 ULOGD("DEMOD","[T12][DVBC]unlock----\n");
1290 }
1291 return FALSE;
1292 }
1293 break;
1294
1295 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1296 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1297 cBitMask = BIT(1);
1298 break;
1299
1300 case DMD_DVBC_GETLOCK_DCR_LOCK:
1301 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1302 cBitMask = BIT(0);
1303 break;
1304
1305 case DMD_DVBC_GETLOCK_AGC_LOCK:
1306 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1307 cBitMask = BIT(0);
1308 break;
1309
1310 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1311 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1312 cBitMask = BIT(2)|BIT(3)|BIT(4);
1313 #ifdef MS_DEBUG
1314 {
1315 MS_U8 reg_frz=0, FSM=0;
1316 MS_U16 u16Timer=0;
1317 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1318 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1319 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1320 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1321 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1322 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1323 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1324 u16Timer=(u16Timer<<8)+reg_frz;
1325 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1326 u16Timer=(u16Timer<<8)+reg_frz;
1327 ULOGD("DEMOD","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1328 }
1329 #endif
1330 break;
1331
1332 case DMD_DVBC_GETLOCK_ATV_DETECT:
1333 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1334 cBitMask = BIT(1); // check atv
1335 break;
1336
1337 case DMD_DVBC_GETLOCK_TR_LOCK:
1338 #if 0 // 20111108 temporarily solution
1339 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1340 cBitMask = BIT(4);
1341 break;
1342 #endif
1343 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1344 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1345 cBitMask = BIT(4);
1346 break;
1347
1348 default:
1349 return FALSE;
1350 }
1351
1352 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1353 return FALSE;
1354
1355 if ((cData & cBitMask) != 0)
1356 {
1357 return TRUE;
1358 }
1359
1360 return FALSE;
1361 }
1362
1363 return FALSE;
1364 }
1365
1366
1367 /****************************************************************************
1368 Subject: To get the Post viterbi BER
1369 Function: INTERN_DVBC_GetPostViterbiBer
1370 Parmeter: Quility
1371 Return: E_RESULT_SUCCESS
1372 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1373 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1374 We will not read the Period, and have the "/256/8"
1375 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1376 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber)
1377 {
1378 MS_BOOL status = true;
1379 MS_U8 reg = 0, reg_frz = 0;
1380 MS_U16 BitErrPeriod;
1381 MS_U32 BitErr;
1382 MS_U16 PktErr;
1383
1384 /////////// Post-Viterbi BER /////////////
1385
1386 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1387 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1388 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1389
1390 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1391 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1392 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1393 BitErrPeriod = reg;
1394
1395 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1396 BitErrPeriod = (BitErrPeriod << 8)|reg;
1397
1398 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1399 // 0x6b [15:8] reg_bit_err_num_15_8
1400 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1401 // 0x6d [15:8] reg_bit_err_num_31_24
1402 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1403 BitErr = reg;
1404
1405 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1406 BitErr = (BitErr << 8)|reg;
1407
1408 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1409 BitErr = (BitErr << 8)|reg;
1410
1411 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1412 BitErr = (BitErr << 8)|reg;
1413
1414 INTERN_DVBC_GetPacketErr(&PktErr);
1415
1416 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1417 reg_frz=reg_frz&(~0x03);
1418 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1419
1420 if (BitErrPeriod == 0 ) //protect 0
1421 BitErrPeriod = 1;
1422
1423 if (BitErr <=0 )
1424 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1425 else
1426 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1427
1428 ULOGD("DEMOD","INTERN_DVBC PostVitBER = %8.3e \n ", *ber);
1429
1430 return status;
1431 }
1432
1433
1434 /****************************************************************************
1435 Subject: To get the Packet error
1436 Function: INTERN_DVBC_GetPacketErr
1437 Parmeter: pktErr
1438 Return: E_RESULT_SUCCESS
1439 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1440 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1441 We will not read the Period, and have the "/256/8"
1442 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1443 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1444 {
1445 MS_BOOL status = true;
1446 MS_U8 reg = 0, reg_frz = 0;
1447 MS_U16 PktErr;
1448
1449 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1450 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1451 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1452
1453 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1454 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1455 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1456 PktErr = reg;
1457
1458 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1459 PktErr = (PktErr << 8)|reg;
1460
1461 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1462 reg_frz=reg_frz&(~0x03);
1463 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1464
1465 ULOGD("DEMOD","INTERN_DVBC PktErr = %d \n ", (int)PktErr);
1466
1467 *pktErr = PktErr;
1468
1469 return status;
1470 }
1471
1472 /****************************************************************************
1473 Subject: Read the signal to noise ratio (SNR)
1474 Function: INTERN_DVBC_GetSNR
1475 Parmeter: None
1476 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1477 Remark:
1478 *****************************************************************************/
INTERN_DVBC_GetSNR(float * f_snr)1479 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr)
1480 {
1481 MS_BOOL status = true;
1482 MS_U8 u8Data = 0, reg_frz = 0;
1483 // MS_U8 freeze = 0;
1484 MS_U16 noisepower = 0;
1485
1486 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1487 {
1488 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1489 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1490 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1491
1492 // read vk
1493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1494 noisepower = u8Data;
1495 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1496 noisepower = (noisepower<<8)|u8Data;
1497
1498 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1499 reg_frz=reg_frz&(~0x01);
1500 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1501
1502 if(noisepower == 0x0000)
1503 noisepower = 0x0001;
1504
1505 #ifdef MSOS_TYPE_LINUX
1506 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1507 #else
1508 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1509 #endif
1510
1511 }
1512 else
1513 {
1514 *f_snr = 0.0f;
1515 }
1516 return status;
1517
1518
1519 }
1520
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1521 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1522 {
1523 MS_BOOL status = true;
1524 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1525 DMD_DVBC_MODULATION_TYPE Qam_mode;
1526
1527 //ULOGD("DEMOD","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi));
1528
1529 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1530 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1531 /* Actually, it's more reasonable, that signal level depended on cable input power level
1532 * thougth the signal isn't dvb-t signal.
1533 */
1534 // use pointer of IFAGC table to identify
1535 // case 1: RFAGC from SAR, IFAGC controlled by demod
1536 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1537 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1538 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1539 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1540 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1541 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
1542 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
1543
1544 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1545
1546 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
1547 {
1548 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
1549 }
1550 else
1551 {
1552 ch_power_db_rel = -100.0f;
1553 }
1554
1555 if(ch_power_db_rel <= -85.0f)
1556 {*strength = 0;}
1557 else if (ch_power_db_rel <= -80.0f)
1558 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
1559 else if (ch_power_db_rel <= -75.0f)
1560 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
1561 else if (ch_power_db_rel <= -70.0f)
1562 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
1563 else if (ch_power_db_rel <= -65.0f)
1564 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
1565 else if (ch_power_db_rel <= -55.0f)
1566 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
1567 else if (ch_power_db_rel <= -45.0f)
1568 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
1569 else
1570 {*strength = 100;}
1571
1572 ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength);
1573 ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength);
1574
1575 return status;
1576 }
1577
1578 /****************************************************************************
1579 Subject: To get the DVT Signal quility
1580 Function: INTERN_DVBC_GetSignalQuality
1581 Parmeter: Quility
1582 Return: E_RESULT_SUCCESS
1583 E_RESULT_FAILURE
1584 Remark: Here we have 4 level range
1585 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1586 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1587 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1588 <4>.4th Range => Quality <10
1589 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(MS_U16 * quality,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1590 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1591 {
1592
1593 float fber;
1594 float log_ber;
1595 MS_BOOL status = true;
1596 DMD_DVBC_MODULATION_TYPE Qam_mode;
1597 float f_snr;
1598
1599 fRFPowerDbm = fRFPowerDbm;
1600 status &= INTERN_DVBC_GetSNR(&f_snr);
1601 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
1602 {
1603 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
1604 {
1605 ULOGD("DEMOD","\nGetPostViterbiBer Fail!");
1606 return FALSE;
1607 }
1608
1609 // log_ber = log10(fber)
1610 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
1611
1612 ULOGD("DEMOD","\nLog(BER) = %f",log_ber);
1613 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1614 if (Qam_mode == DMD_DVBC_QAM16)
1615 {
1616 if(log_ber <= (-5.5f))
1617 *quality = 100;
1618 else if(log_ber <= (-5.1f))
1619 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
1620 else if(log_ber <= (-4.9f))
1621 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1622 else if(log_ber <= (-4.5f))
1623 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
1624 else if(log_ber <= (-3.7f))
1625 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
1626 else if(log_ber <= (-3.2f))
1627 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1628 else if(log_ber <= (-2.9f))
1629 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1630 else if(log_ber <= (-2.5f))
1631 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
1632 else if(log_ber <= (-2.2f))
1633 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
1634 else if(log_ber <= (-2.0f))
1635 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1636 else
1637 *quality = 0;
1638 }
1639 else if (Qam_mode == DMD_DVBC_QAM32)
1640 {
1641 if(log_ber <= (-5.0f))
1642 *quality = 100;
1643 else if(log_ber <= (-4.7f))
1644 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
1645 else if(log_ber <= (-4.5f))
1646 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
1647 else if(log_ber <= (-3.8f))
1648 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
1649 else if(log_ber <= (-3.5f))
1650 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
1651 else if(log_ber <= (-3.0f))
1652 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
1653 else if(log_ber <= (-2.7f))
1654 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
1655 else if(log_ber <= (-2.4f))
1656 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1657 else if(log_ber <= (-2.2f))
1658 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1659 else if(log_ber <= (-2.0f))
1660 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
1661 else
1662 *quality = 0;
1663 }
1664 else if (Qam_mode == DMD_DVBC_QAM64)
1665 {
1666 if(log_ber <= (-5.4f))
1667 *quality = 100;
1668 else if(log_ber <= (-5.1f))
1669 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
1670 else if(log_ber <= (-4.9f))
1671 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1672 else if(log_ber <= (-4.3f))
1673 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
1674 else if(log_ber <= (-3.7f))
1675 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
1676 else if(log_ber <= (-3.2f))
1677 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
1678 else if(log_ber <= (-2.9f))
1679 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
1680 else if(log_ber <= (-2.4f))
1681 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
1682 else if(log_ber <= (-2.2f))
1683 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
1684 else if(log_ber <= (-2.05f))
1685 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
1686 else
1687 *quality = 0;
1688 }
1689 else if (Qam_mode == DMD_DVBC_QAM128)
1690 {
1691 if(log_ber <= (-5.1f))
1692 *quality = 100;
1693 else if(log_ber <= (-4.9f))
1694 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
1695 else if(log_ber <= (-4.7f))
1696 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
1697 else if(log_ber <= (-4.1f))
1698 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
1699 else if(log_ber <= (-3.5f))
1700 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
1701 else if(log_ber <= (-3.1f))
1702 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1703 else if(log_ber <= (-2.7f))
1704 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1705 else if(log_ber <= (-2.5f))
1706 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
1707 else if(log_ber <= (-2.06f))
1708 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
1709 //else if(log_ber <= (-2.05))
1710 else
1711 {
1712 if (f_snr >= 27.2f)
1713 *quality = 20;
1714 else if (f_snr >= 25.1f)
1715 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
1716 else
1717 *quality = 0;
1718 }
1719 }
1720 else //256QAM
1721 {
1722 if(log_ber <= (-4.8f))
1723 *quality = 100;
1724 else if(log_ber <= (-4.6f))
1725 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
1726 else if(log_ber <= (-4.4f))
1727 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
1728 else if(log_ber <= (-4.0f))
1729 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
1730 else if(log_ber <= (-3.5f))
1731 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
1732 else if(log_ber <= (-3.1f))
1733 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
1734 else if(log_ber <= (-2.7f))
1735 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
1736 else if(log_ber <= (-2.4f))
1737 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
1738 else if(log_ber <= (-2.06f))
1739 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
1740 //else if(log_ber <= (-2.05))
1741 else
1742 {
1743 if (f_snr >= 29.6f)
1744 *quality = 20;
1745 else if (f_snr >= 27.3f)
1746 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
1747 else
1748 *quality = 0;
1749 }
1750 }
1751 }
1752 else
1753 {
1754 *quality = 0;
1755 }
1756
1757 //DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
1758 ULOGD("DEMOD","BER = %8.3e\n", fber);
1759 ULOGD("DEMOD","Signal Quility = %d\n", *quality);
1760 return TRUE;
1761 }
1762
1763 /****************************************************************************
1764 Subject: To get the Cell ID
1765 Function: INTERN_DVBC_Get_CELL_ID
1766 Parmeter: point to return parameter cell_id
1767
1768 Return: TRUE
1769 FALSE
1770 Remark:
1771 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)1772 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
1773 {
1774 MS_BOOL status = true;
1775 MS_U8 value1 = 0;
1776 MS_U8 value2 = 0;
1777
1778 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
1779 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
1780
1781 *cell_id = ((MS_U16)value1<<8)|value2;
1782 return status;
1783 }
1784
1785 /****************************************************************************
1786 Subject: To get the DVBC Carrier Freq Offset
1787 Function: INTERN_DVBC_Get_FreqOffset
1788 Parmeter: Frequency offset (in KHz), bandwidth
1789 Return: E_RESULT_SUCCESS
1790 E_RESULT_FAILURE
1791 Remark:
1792 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)1793 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
1794 {
1795 MS_U16 FreqB, config_Fc=0;
1796 float FreqCfo_offset,f_Fc;
1797 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
1798 MS_U8 reg_frz = 0, reg = 0;
1799 MS_BOOL status = TRUE;
1800
1801 // no use.
1802 u8BW = u8BW;
1803
1804 ULOGD("DEMOD","INTERN_DVBC_Get_FreqOffset\n");
1805
1806 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1807 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1808 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1809
1810 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
1811 RegCfo_offset = reg;
1812 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
1813 RegCfo_offset = (RegCfo_offset<<8)|reg;
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
1815 RegCfo_offset = (RegCfo_offset<<8)|reg;
1816 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
1817 RegCfo_offset = (RegCfo_offset<<8)|reg;
1818
1819 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1820 reg_frz=reg_frz&(~0x01);
1821 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1822
1823 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
1824 Reg_Fc_over_Fs = reg;
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
1826 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
1827 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
1828 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
1829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
1830 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
1831
1832 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
1833 config_Fc = reg;
1834 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
1835 config_Fc = (config_Fc<<8)|reg;
1836
1837 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
1838
1839 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
1840
1841 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
1842
1843 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
1844
1845 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
1846 //ULOGD("DEMOD","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
1847 // FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc);
1848
1849 *pFreqOff = FreqCfo_offset;
1850
1851 return status;
1852 }
1853
1854
1855
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)1856 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
1857 {
1858
1859 bPowerOn = bPowerOn;
1860 }
1861
INTERN_DVBC_Power_Save(void)1862 MS_BOOL INTERN_DVBC_Power_Save(void)
1863 {
1864
1865 return TRUE;
1866 }
1867
1868 /****************************************************************************
1869 Subject: To get the current modulation type at the DVB-C Demod
1870 Function: INTERN_DVBC_GetCurrentModulationType
1871 Parmeter: pointer for return QAM type
1872
1873 Return: TRUE
1874 FALSE
1875 Remark:
1876 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)1877 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
1878 {
1879 MS_U8 u8Data=0;
1880
1881 ULOGD("DEMOD","INTERN_DVBC_GetCurrentModulationType\n");
1882
1883
1884 MDrv_SYS_DMD_VD_MBX_ReadReg(0x9cc4, &u8Data);
1885
1886
1887 // ULOGD("DEMOD","@@@@@@ 0x9cc4 pQAMMode = %d \n",u8Data&0x07);
1888
1889 switch(u8Data&0x07)
1890 {
1891 case 0:
1892 *pQAMMode = DMD_DVBC_QAM16;
1893 ULOGD("DEMOD","[dvbc]QAM=16\n");
1894 return TRUE;
1895 break;
1896 case 1:
1897 *pQAMMode = DMD_DVBC_QAM32;
1898 ULOGD("DEMOD","[dvbc]QAM=32\n");
1899 return TRUE;
1900 break;
1901 case 2:
1902 *pQAMMode = DMD_DVBC_QAM64;
1903 ULOGD("DEMOD","[dvbc]QAM=64\n");
1904 return TRUE;
1905 break;
1906 case 3:
1907 *pQAMMode = DMD_DVBC_QAM128;
1908 ULOGD("DEMOD","[dvbc]QAM=128\n");
1909 return TRUE;
1910 break;
1911 case 4:
1912 *pQAMMode = DMD_DVBC_QAM256;
1913 ULOGD("DEMOD","[dvbc]QAM=256\n");
1914 return TRUE;
1915 break;
1916 default:
1917 *pQAMMode = DMD_DVBC_QAMAUTO;
1918 ULOGD("DEMOD","[dvbc]QAM=invalid\n");
1919 return FALSE;
1920 }
1921 }
1922
1923 /****************************************************************************
1924 Subject: To get the current symbol rate at the DVB-C Demod
1925 Function: INTERN_DVBC_GetCurrentSymbolRate
1926 Parmeter: pointer pData for return Symbolrate
1927
1928 Return: TRUE
1929 FALSE
1930 Remark:
1931 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)1932 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
1933 {
1934 MS_U8 tmp = 0;
1935 MS_U16 u16SymbolRateTmp = 0;
1936
1937 // intp
1938 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d2, &tmp);
1939 u16SymbolRateTmp = tmp;
1940 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d1, &tmp);
1941 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
1942
1943 if (abs(u16SymbolRateTmp-6900)<2)
1944 {
1945 u16SymbolRateTmp=6900;
1946 }
1947
1948 if (abs(u16SymbolRateTmp-6875)<2)
1949 {
1950 u16SymbolRateTmp=6875;
1951 }
1952
1953 *u16SymbolRate = u16SymbolRateTmp;
1954
1955 ULOGD("DEMOD","[dvbc]SR=%d\n",*u16SymbolRate);
1956
1957 return TRUE;
1958 }
1959
1960
1961 /****************************************************************************
1962 Subject: To get the current symbol rate offset at the DVB-C Demod
1963 Function: INTERN_DVBC_GetCurrentSymbolRate
1964 Parmeter: pointer pData for return Symbolrate offset
1965
1966 Return: TRUE
1967 FALSE
1968 Remark:
1969 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)1970 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
1971 {
1972 MS_U8 u8Data = 0, reg_frz = 0;
1973 MS_U32 u32Data = 0;
1974 // MS_S32 s32Data = 0;
1975 MS_BOOL status = TRUE;
1976 MS_U16 u16SymbolRate = 0;
1977 float f_symb_offset = 0.0f;
1978
1979
1980
1981 // bank 26 0x03 [7] reg_bit_err_num_freeze
1982 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
1983 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
1984
1985 // sel, SFO debug output.
1986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
1987 u32Data = u8Data;
1988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
1989 u32Data = (u32Data<<8)|u8Data;
1990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
1991 u32Data = (u32Data<<8)|u8Data;
1992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
1993 u32Data = (u32Data<<8)|u8Data;
1994
1995 // bank 26 0x03 [7] reg_bit_err_num_freeze
1996 reg_frz=reg_frz&(~0x80);
1997 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
1998 // s32Data = (MS_S32)(u32Data<<8);
1999
2000 ULOGD("DEMOD","[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2001
2002 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2003
2004 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2005 f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2006
2007 *pData = (MS_U16)(f_symb_offset + 0.5f);
2008
2009 ULOGD("DEMOD","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset);
2010
2011 return status;
2012 }
2013
INTERN_DVBC_Version(MS_U16 * ver)2014 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2015 {
2016
2017 MS_U8 status = true;
2018 MS_U8 tmp = 0;
2019 MS_U16 u16_INTERN_DVBC_Version;
2020
2021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2022 u16_INTERN_DVBC_Version = tmp;
2023 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2024 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2025 *ver = u16_INTERN_DVBC_Version;
2026
2027 return status;
2028 }
2029
2030
INTERN_DVBC_Show_Demod_Version(void)2031 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2032 {
2033
2034 MS_BOOL status = true;
2035 MS_U16 u16_INTERN_DVBC_Version;
2036
2037 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2038
2039 ULOGD("DEMOD","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2040
2041 return status;
2042 }
2043
2044
2045
2046 #if (INTERN_DVBC_INTERNAL_DEBUG)
2047
INTERN_DVBC_Show_AGC_Info(void)2048 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2049 {
2050 MS_U8 tmp = 0;
2051 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2052 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2053 MS_U16 if_agc_err = 0;
2054 MS_BOOL status = TRUE;
2055
2056 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2057 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2058 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2059 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2060 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2061 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2062
2063
2064 // select IF gain to read
2065 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2066 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2067
2068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2069 if_agc_gain = tmp;
2070 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2071 if_agc_gain = (if_agc_gain<<8)|tmp;
2072
2073
2074 // select d1 gain to read.
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2076 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2077
2078 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2079 d1_gain = tmp;
2080 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2081 d1_gain = (d1_gain<<8)|tmp;
2082
2083 // select d2 gain to read.
2084 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2085 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2086
2087 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2088 d2_gain = tmp;
2089 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2090 d2_gain = (d2_gain<<8)|tmp;
2091
2092 // select IF gain err to read
2093 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2094 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2095
2096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2097 if_agc_err = tmp;
2098 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2099 if_agc_err = (if_agc_err<<8)|tmp;
2100
2101 ULOGD("DEMOD","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2102 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2103
2104 ULOGD("DEMOD","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2105
2106 return status;
2107 }
2108
INTERN_DVBC_info(void)2109 void INTERN_DVBC_info(void)
2110 {
2111 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2112 MS_U8 qam,tmp = 0;
2113 MS_U8 fft_u8 = 0;
2114 MS_U16 fft_u16bw = 0;
2115 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2116 float f_snr = 0,f_freq = 0;
2117 DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2118 MS_U16 f_start = 0,f_end = 0;
2119 MS_U8 s0_count = 0;
2120 MS_U8 sc4 = 0,sc3 = 0;
2121 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2122 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2123 MS_U16 count = 0;
2124 MS_U16 fb_i_1,fb_q_1;
2125 MS_U8 e0,e1,e2,e3;
2126 MS_S16 reg_freq;
2127 float freq,mag;
2128
2129
2130
2131 INTERN_DVBC_Version(&version);
2132
2133 // fb_fs
2134 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2135 fb_fs = tmp;
2136 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2137 fb_fs = (fb_fs<<8)|tmp;
2138 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2139 fb_fs = (fb_fs<<8)|tmp;
2140 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2141 fb_fs = (fb_fs<<8)|tmp;
2142 // fc_fs
2143 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2144 fc_fs = tmp;
2145 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2146 fc_fs = (fc_fs<<8)|tmp;
2147 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2148 fc_fs = (fc_fs<<8)|tmp;
2149 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2150 fc_fs = (fc_fs<<8)|tmp;
2151 // crv
2152 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2153 crv = tmp;
2154 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2155 crv = (crv<<8)|tmp;
2156 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2157 crv = (crv<<8)|tmp;
2158 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2159 crv = (crv<<8)|tmp;
2160 // tr_error
2161 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2162 tr_error = tmp;
2163 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2164 tr_error = (tr_error<<8)|tmp;
2165 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2166 tr_error = (tr_error<<8)|tmp;
2167
2168 // intp
2169 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2170 intp = tmp;
2171 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2172 intp = (intp<<8)|tmp;
2173 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2174 intp = (intp<<8)|tmp;
2175 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2176 intp = (intp<<8)|tmp;
2177
2178 // fft info
2179 // intp
2180 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2181 fft_u16bw = tmp;
2182 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2183 fft_u16bw = (fft_u16bw<<8)|tmp;
2184 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2185 fft_u8 = tmp;
2186
2187
2188 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2189 qam = tmp;
2190
2191 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2192 f_start = tmp;
2193 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2194 f_start = (f_start<<8)|tmp;
2195 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2196 f_end = tmp;
2197 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2198 f_end = (f_end<<8)|tmp;
2199 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2200 s0_count = tmp;
2201
2202 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2203 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2204
2205 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2206 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2207 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2208 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2209 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2210 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2211 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2212
2213
2214 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2215
2216 count = 0x400;
2217 while(count--);
2218
2219 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2220 aci_e0 = tmp&0x0f;
2221 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2222 aci_e0 = aci_e0<<8|tmp;
2223
2224 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2225
2226 count = 0x400;
2227 while(count--);
2228
2229
2230 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2231 aci_e1 = tmp&0x0f;
2232 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2233 aci_e1 = aci_e1<<8|tmp;
2234
2235 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2236
2237 count = 0x400;
2238 while(count--);
2239
2240 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2241 aci_e2 = tmp&0x0f;
2242 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2243 aci_e2 = aci_e2<<8|tmp;
2244
2245 // read aci coef
2246 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2247
2248 count = 0x400;
2249 while(count--);
2250
2251 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2252 aci_e3 = tmp&0x0f;
2253 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2254 aci_e3 = aci_e3<<8|tmp;
2255
2256 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2257 fb_i_1 = tmp;
2258 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2259 fb_i_1 = fb_i_1<<8|tmp;
2260
2261 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2262 fb_q_1 = tmp;
2263 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2264 fb_q_1 = fb_q_1<<8|tmp;
2265
2266
2267 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2268 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2269 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2270 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2271
2272 reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2273 freq = (float)reg_freq*45473.0/65536.0;
2274 mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2275
2276
2277 INTERN_DVBC_GetPacketErr(&packetErr);
2278 INTERN_DVBC_GetSNR(&f_snr);
2279 INTERN_DVBC_Show_AGC_Info();
2280 INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2281 INTERN_DVBC_Get_FreqOffset(&f_freq,8);
2282 INTERN_DVBC_GetCurrentSymbolRate(&symb_rate);
2283 INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2284 INTERN_DVBC_GetCurrentModulationType(&QAMMode);
2285
2286 ULOGD("DEMOD","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2287 ULOGD("DEMOD","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2288 ULOGD("DEMOD","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2289 ULOGD("DEMOD","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2290 ULOGD("DEMOD","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2291 ULOGD("DEMOD","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2292 return;
2293 }
2294
2295
2296 #endif
2297
2298 /***********************************************************************************
2299 Subject: read register
2300 Function: MDrv_1210_IIC_Bypass_Mode
2301 Parmeter:
2302 Return:
2303 Remark:
2304 ************************************************************************************/
2305 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2306 //{
2307 // UNUSED(enable);
2308 // if (enable)
2309 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2310 // else
2311 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2312 //}
2313